CN1883141A - Dual phase pulse modulation system - Google Patents
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- CN1883141A CN1883141A CN 200480033586 CN200480033586A CN1883141A CN 1883141 A CN1883141 A CN 1883141A CN 200480033586 CN200480033586 CN 200480033586 CN 200480033586 A CN200480033586 A CN 200480033586A CN 1883141 A CN1883141 A CN 1883141A
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Abstract
A system configured to transmit and receive data signals over a data link in serial fashion using dual phase pulse modulation (DPPM) is described. The data link may be, for example, a one or two wire unshielded twisted pair (UTP) cable. An exemplary system includes a configurable interface (301) able to accept parallel data from an external source, such as a microprocessor or an imaging device. The interface (301) is externally programmable for a particular data format. An encoder is coupled to the configurable interface (301) and converts parallel data into serial output data, the serial output data having high and low data pulses with each of the high and low data pulses encoded to have one of 2<M> distinct data pulse widths. The system further includes a decoder (303) coupled to the configurable interface (301), which is able to convert the serial input data into parallel data.
Description
Technical field
Generally speaking, the present invention relates to stride the programmable format of the input and output data in the transfer of data of the link that uses the dual phase pulse modulation Code And Decode.Particularly, the present invention is a kind of dual phase pulse modulation system able to programme that is used for sending and receiving by the physical data with minimum power utilization microprocessor and/or image compatible data.
Background technology
Dissimilar signals of communication is classified according to certain essential characteristics such as certain combination that such as signal carrier whether are amplitude modulation(PAM), angle modulated, pulse modulation or these modulation types usually.In pulse-modulated signal, may in amplitude, duration (width), position (phase place), repetition rate (at interval) or its any combination, modulate by paired pulses equally.The individual channel or a plurality of channel that have simulation, quantification or the digital information of modulated carrier, and it is multiplexed to have various forms of information.Information can be represented the data of audio sound, video image, measurement, alphanumeric character and symbol, other kind or these certain combination.
Pulse duration modulation (PDM) is also referred to as pulse-width modulation (PWM), and it is a kind of modulation of pulse carrier, and wherein the rising edge of the value of the information signal of modulated carrier by changing pulse, trailing edge or both produce the pulse of proportional duration.Usually in PDM, pulse distance or interval keep constant.Pulse distance (or at interval) modulation is a kind of frequency modulation form, and wherein modulate according to the value of information at spacing between the pulse or interval.Usually, pulse duration or width keep constant in this modulation type.Pulse position modulation (PPM) is a kind of pulse modulation of pulse carrier, and wherein the value of information changes the time location of pulse with respect to the unmodulated time of origin of pulse.These are different with the pulse distance modulation, because PPM requires reference clock to judge the relative phase or the position of pulse exactly usually.
" keying " is any type of digital modulation, and wherein signal is to form by between discrete value any feature of carrier wave being modulated.The ON/OFF keying is the binary form with amplitude shift keying of two discrete states, and one of them state is the existence of energy in the keying interval, and another state is not existing of this energy.Information can be represented (for example, the point in the Morse code telegram and draw) by the duration of one of state.
Yet, common amplitude state or represent information encoded to the transformation of another state itself from a state.Have various possible encoding schemes (for example, one pole, polarity, bipolar, make zero, normalizing, non-return-to-zero).For example, non-return-to-zero (NRZ) is a kind of like this modulating mode, has encoded in signal wherein that signal need not to make zero after each data element, and makes zero and normalizing is such modulating mode, wherein signal make zero (or) after each data element of having encoded.
Frequency shift keying (FSK) is a kind of like this frequency modulation of form, and wherein the modulated output signal is shifted between two or more discrete preset frequencies according to the value of information.In Multiple Frequency Shift Keying, the group of n data bit is by 2
nIndividual discrete frequency is encoded.Phase shift keying (PSK) is a kind of like this phase modulated, and wherein modulation intelligence is shifted the instantaneous phase of modulated signal between predetermined discrete phase value.Differential phase keying (DPSK) (DPSK) is a kind of like this PSK of form, and wherein the fixed phase of given keying interval is the signal phase in the last keying interval.FSK and PSK modulation are usually directed to the continuous wave carrier wave and non-pulse.
Multidigit or N unit (ternary, quaternary, eight yuan etc.) encoding scheme has such modulated signal, wherein above information bit of each signal conditioning (amplitude, frequency, phase place) expression.MFSK is an example, but PSK or DPSK may also have phase place discrete more than two, for example, and 4 phase places of expression dibit.Each of various forms of modulation has its oneself one group of merits and demerits with respect to the concrete application of using it.Some factor that will consider when selecting specific modulation format comprises the possibility that bandwidth, power consumption requirement and signal propagation errors and raw information are recovered.For numerical data, importantly whether needing independent clock signal or modulated signal is self clock.The relative simplicity of modulation and demodulation equipment or circuit or complexity also can be judgement factors.Seek low-power consumption is used for the transmission line of capacitive load especially.Usually, between elementary cell and remote unit, transmit data.For example, these data can adopt at basic or master site and long-range or from the video that transmits between the position or the form of view data.These data need transmit to avoid above-mentioned capacitive load effect with low-power.Transmit these data with serial mode and allow (for example) transmission on existing data lines such as unshielded twisted pair data wires such as (UTP), if but suitably to encode, serial transfer may be slowly.Therefore, be favourable to the efficient parallel of serial data coding.In addition, expectation advocate peace and have reverse functions from the position (that is, and main transformer be from, vice versa) ability.
Summary of the invention
The present invention is a kind of system of transmitting and receive data by data link of being configured to.This data link can be, for example a line or two wires unshielded twisted pair (UTP) cable.An example system comprises configurable interface, and this interface can be accepted from the parallel data such as external sources such as microprocessor or imaging devices.(perhaps, parallel data can from receiving) with the integrated source of this interface circuit.This interface can be to the outside programming of specific data format.One encoder is coupled to configurable interface, and converts parallel data to will send by data link serial output data; This serial output data has high and low data pulse, and each of wherein high and low data pulse all is encoded into has 2
MIn the individual different data pulse widths one.This system also comprises the decoder that is coupled to this configurable interface, and this decoder can convert parallel data to by the serial input data that data link receives.In addition, parallel data can be output to external circuit then.
The present invention also is a kind of method that is used for the parallel image data transaction is become serial data signal.An illustrative methods comprises reception parallel image data, peels off any pixel clock (because need not to send independent clock signal) and the parallel image data transaction is become serial data signal from the parallel image data.Serial data signal has high and low data pulse.Each of high and low data pulse is encoded into has 2
MIn the individual data pulsewidth one.
The present invention also can be used as a kind of method that is used for the paralleling microprocessor data transaction is become serial data signal.An illustrative methods comprises reception paralleling microprocessor data, peels off any clock signal from this microprocessor data, peel off any chip selection data and the paralleling microprocessor data transaction is become serial data signal from this microprocessor data.Serial microprocessor data has high and low data pulse.Each of high and low data pulse is encoded into has 2
MIn the individual different data pulse widths one.
The accompanying drawing summary
Fig. 1 is according to one exemplary embodiment of the present invention, and the diagram (signal value and time relation) by one group of exemplary pulse in various pulse durations of dual phase pulse modulation (DPPM) coding is used to represent one group of corresponding dibit data symbols.
Fig. 2 A and 2B are the diagrams that is used for the DPPM pulse train of one group of example data according to one exemplary embodiment of the present invention, show the transmission of the pulses of a series of 9 high 9 low trends in single 100 nanoseconds (nsec) system clock cycles.
Fig. 3 A is the block diagram of an exemplary application that is used to send and receive the DPPM of microprocessor data.
Fig. 3 B is the block diagram of an exemplary application that is used to send and receive the DPPM of view data.
Fig. 4 is used to prepare based on the signal of the image diagrammatic flow for an illustrative methods that sends via DPPM according to the present invention.
Realize best mode of the present invention
DPPM is that a kind of digital coding that will reside in the digital circuit with binary ciruit state (1 and 0) form is its duration or the height that replaces of 2 (or a plurality of) data bit of each pulse of width means and method of low signal pulses string separately.The exemplary embodiment of Fig. 1 has used 2 to be used for coding.The position is to using one group of distinct pulse widths of representing the dibit symbol value that each is possible to encode, such as:
The 00=4ns pulse
The 01=6ns pulse
The 10=8ns pulse
The 11=10na pulse
To 4,6,8 and the selection of 10ns pulsewidth be arbitrarily, 4,5,6 and 7 or some other pulsewidth too, as long as the decoding circuit of the receiving terminal that the DPPM signal transmits can correctly be distinguished from each other different pulsewidths.The figure place that decoding circuit (and intrinsic noise source, degradation of signals and temperature/voltage variation in the communication environments) also can be encoded to each pulse has been set up physical constraints, and 3 needs of every pulse are correctly differentiated 8 (that is, 2
3) possible pulsewidth, and 4 needs of every pulse are correctly differentiated 16 (that is, 2
4) possible pulsewidth.Data rate can be considered to the figure place of per second coding, and it depends on the umber of pulse and the system clock frequency of each system clock.
" quarter-phase " information that refers to is moved towards pulse as height and is hanged down and move towards the fact that pulse sends.Most of pulse width modulating schemes only change the width that height moves towards pulse, have therefore in fact modulated a duty ratio.DPPM modulates the high and low width that moves towards pulse independently, the different hyte of having encoded in the height in each " cycle " and lower part.Therefore, clock cycle and duty ratio are not effective notions for the DPPM pulse train that is generated.DPPM is " unclocked " in essence, this means that data can decode for the width that changes each time by detecting pulsion phase simply.This means to need not, also needn't from data, encode and recovered clock with the data tranmitting data register.This is a major advantage when the time-critical burst pulse string that sends between the different chips, introduces and regularly changes and necessity of the clock of the chance of error because this has eliminated dirigibility.Unique clock considers it is the fact that sends several pulses " cycle " in each system clock cycle.
For example, Fig. 2 A and 2B show in the 100nsec system clock cycle example of the DPPM pulse train of the height that replaces that sends 18 data bit (being organized as 9 dibits herein) and low pulse (5 high impulses and 4 low pulses).These 18 can form for example 16 bit data word, have added two error correction bits after this data word.Thus, can in each system clock cycle, send a data word.
Because information is to send simultaneously in the height of pulse train and low pulse, therefore in the present embodiment, DPPM is non-return-to-zero (or non-normalizing) modulation scheme in essence.Yet the pulse train that is included in the system clock cycle may be the end of each such sequence make zero (or one).Indicated in the example as Fig. 2 A and 2B, the multidigit code element number in the word represented by the odd number pulse, allows a final code element pulse in the end back in the sequence to have make zero (or normalizing) when changing thus.In addition,, then can insert an extra pulse, and ignore this pulse by decoder and return with pressure by encoder if the figure place of being transmitted causes non-return-to-zero (or one's) situation.Yet this extra pulse has consumed the secondary power that does not send any real data.
Thus, the DPPM method is with M data bit, and (that is, group M=2) is expressed as the signal pulse of specified width, which width such as dibit.2
MEach of individual possible data value is corresponding to aforesaid 2
MOne of individual different pulsewidth, and the group of a continuous M data bit is by alternately representing (for example, under the situation of M=2, each high signal and each low signal are represented a dibit) for high and low signal pulse.Conversion between the signal pulse of signal encoding and the decoding circuit execution data position and the information content is represented.
For being signal pulse with data-bit encoding, the data word that is received at first is subdivided into the ordered sequence of the group of M data bit, then, each group in the sequence is converted into its corresponding signal pulse to be represented, has produced the height and the low signal pulses of a series of expression data thus.The execution data word is to specify the signal pulse transitions time to a kind of mode of the conversion of signal pulse, its each corresponding to the last fringe time that increases progressively by current group specified pulse width corresponding to M data bit, produce signal pulse transitions at the fringe time place of these appointments then.U.S.'s publication application of awaiting the reply jointly of " Dual Phase Pulse Modulation EncoderImplementation (dual phase pulse modulation encoder realization) " that example encoder hardware was submitted in xx day in April, 2004, by name 2004xxxxxxx number is (based on U.S. Provisional Patent Application the 60/510th, No. 738) in have a detailed description, this application all is incorporated into this by reference.
For the DPPM signal decoding is returned data, determine each pulsewidth high and low signal pulses, then they are reassembled into data word.Carry out that a kind of method of this conversion was submitted in xx day in April, 2004, U.S.'s publication application of " DualPhase Pulse Modulation Decoder Implementation (realization of dual phase pulse modulation decoder) " by name 2004xxxxxxx number (based on U.S. Provisional Patent Application the 60/509th, No. 487) in have a detailed description, this application all is incorporated into this by reference.
The present invention allows from microprocessor or is programmable based on the data format of the system of image.The transmission that data are striden electric wire or cable is a dual phase pulse modulation, and therefore need not clock pulse is sent to receiving system.
In one exemplary embodiment, the present invention is made of the semiconductor circuit that is manufactured on the chip, and also comprises transmitter and acceptor circuit except that the encoder circuit.
The present invention allows circuit to be programmed to transmitter or receiver.
Circuit can be for example only sending (that is, main) and (that is, the from) system that receives uses one or two physical data lines in physical data transmission microprocessor of 16 bit data and control signal, or 8 bit image data and sync bits.Data are to use dual phase pulse modulation to encode, and are decoded by receiving circuit then.
Each circuit can be programmed to transmitter (TX) or receiver (RX) by outside programming signal.In addition, each circuit can be programmed to receive microprocessor or based on the data of image by another external signal.In this example, the single dibit that can be used as according to table 1 of external signal sends.
Signal (dibit) pattern TX/RX
00 microprocessor RX
01 microprocessor TX
10 based on image RX
11 based on image TX
Table 1
One group of signal that send in microprocessor model in one example, is that 16 data bit, address bit, two chips are selected and microprocessor clock.Therefore, this example has 20.Can revise signal, make that the sum of data bit and address bit is 17 address/data positions (having eliminated any unnecessary chip selects and the microprocessor clock pulse), need 9 dibits to send thus as DPPM pulse train.
System of the present invention is highly configurable, thereby allows this system and multiple microprocessor and join based on the interface of image.This configuration allows each polarity based on the signal of image of counter-rotating.It also allows to revise the form of microprocessor signals to eliminate unnecessary position.
In an exemplary microprocessor mode, microprocessor/image interface piece converts 20 microprocessor signals to 18 words that will send.When in microprocessor model, this interface is selected by two chips and microprocessor clock is decoded into 1 data bit.Which chip this indicates select in essence is movable.If it is movable that the neither one chip is selected,, does not then stride link and send any data if perhaps there is not microprocessor clock.This causes power consumption lower on the link.In receiving element, regenerate microprocessor clock and two chips and select, wherein regularly must with the external interface compatibility.System clock is used to create essential timing.Control signal is encoded, make on receiving system, to regenerate information.This coded data allows data are regenerated another kind of form into receiving system, thereby allows in the data format modification that does not have under the situation of adjunct circuit.
One group of exemplary signal that will send in the pattern based on image is 8 data bit, horizontal synchronization, vertical synchronization and pixel clocks, 11 altogether.In a certain embodiments, based on the twice work of the interface of image with system clock frequency.In this exemplary pattern based on image, this interface is concatenated into 18 words that will send (that is, two 8 bit data word and a level and a vertical synchronizing signal) with 2 11 bit image blocks.Do not send pixel clock, but can use the system clock in the receiving element to come the remarked pixel clock.18 bit data use dual phase pulse modulation to encode on transmitting element.On receiving element, 18 parallel-by-bit data are returned in the dual phase pulse modulation data decode.
With reference to figure 3A, an exemplary application that is used to send and receive the DPPM system of microprocessor data comprises basic DPPM circuit 301 and long-range DPPM circuit 303.Herein, the said external programming signal is sent to basic circuit 301 and remote circuit 303 to dispose each circuit; Basic circuit 301 is configured to microprocessor master transtation mission circuit, and remote circuit 303 is configured to microprocessor from receiving circuit.In case on the wide parallel data bus line of m, receive parallel data signal, just peel off unnecessary data (for example, clock signal), and the DPPM circuit converts the parallel data string to and above-mentionedly has 2
MThe serial data pulse stream of individual distinct pulse widths.
Be used to send and receive the block diagram of an exemplary application of the DPPM system of view data, promptly Fig. 3 B comprises basic DPPM circuit 305, long-range DPPM circuit 307 and such as imaging devices 309 such as imaging video cameras.As above-mentioned microcontroller circuit, outside programming signal is sent to basic circuit 305 and remote circuit 307 to dispose each circuit; Basic circuit 305 is configured to the main transtation mission circuit based on image, and remote circuit 307 be configured to based on image from receiving circuit.Fig. 4 has described according to the present invention and has been used to prepare for the illustrative methods 400 based on the signal of image that sends via DPPM.
With reference to figure 4, initial word counter index j is set as 0 (401).The parallel image data are submitted to basic circuit 305 (Fig. 3) from imaging device 309 on the wide parallel route of n.For this example, n carries 8 words.Determine whether (405) exist pixel clock.If find pixel clock, then peel off this clock (407).Determine then whether (409) exist vertical and/or horizontal synchronization (" sync ") signal (as mentioned above, the DPPM of each transmission string only needs single vertical and horizontal-drive signal to the data word of each serial connection).If there are one or more synchronizing signals, then they are stripped from (411), and increase progressively word counter index (413).Determine whether (415) word counter equals " 2 ".If not, then submit another image word to, and repeating step 403-415.In case word counter index j equals " 2 ", then be connected in series two image words (417).The single vertical and single horizontal-drive signal of data supplementing (419) to serial connection.Parallel data is converted (421) then and becomes serial D PPM data flow described herein.
Although the present invention describes according to concrete exemplary embodiment, those skilled in the art will readily recognize that, can imagine the replacement form of DPPM system and method, and these still within the scope of the present invention.For example, with reference to the dibit (that is, M equals " 2 ") that sends.Although M is integer normally, M can easily be the integer greater than 2.In addition, exemplary DPPM system is according to sending and receive microprocessor and describing based on the data of image.Yet those skilled in the art can easily conceive the data that can easily be adapted to other type of DPPM system and form.Therefore, scope of the present invention should only be limited by appended claims.
Claims (27)
1. electronic circuit that is configured to send by data link data-signal comprises:
Configurable interface, it is configured to accept the data from external source, and described interface can carry out the outside programming to specific data format; And
Be coupled to the encoder of described configurable interface, it is configured to convert parallel data to serial output data, and described serial output data has high and low data pulse, and each of described height and low data pulse is encoded into has 2
MIn the individual different data pulse widths one, wherein M is the integer more than or equal to 1.
2. the system as claimed in claim 1 is characterized in that, described external source is a microcontroller.
3. the system as claimed in claim 1 is characterized in that, described external source is an imaging device.
4. the system as claimed in claim 1 is characterized in that, described configurable interface is configured to accept microprocessor data.
5. the system as claimed in claim 1 is characterized in that, described configurable interface is configured to accept the data based on image.
6. the system as claimed in claim 1 is characterized in that, the value of M is 2.
7. system that is configured to receive by data link data-signal comprises:
Configurable interface, it is configured to accept serial data by the serial data input, and described interface can carry out the outside programming to format; And
Be coupled to the decoder of the output of described interface, described decoder is configured to receive corresponding to signal M bit data hyte, that be made of the height that replaces and the low signal pulses of specified width, which width, and each high and low data pulse has 2
MIn the individual different pieces of information pulsewidth one, wherein M is the integer more than or equal to 1, described decoder also is configured to convert described serial data to parallel data.
8. system as claimed in claim 7 is characterized in that described external source is a microcontroller.
9. system as claimed in claim 7 is characterized in that described external source is an imaging device.
10. system as claimed in claim 7 is characterized in that described configurable interface is configured to accept microprocessor data.
11. system as claimed in claim 7 is characterized in that, described programmable interface is configured to accept the data based on image.
12. system as claimed in claim 7 is characterized in that, the value of M is 2.
13. one kind is configured to comprise by the transmit and receive data system of signal of data link:
Configurable interface, it is configured to accept the parallel data from external source, and described interface can carry out the outside programming to format;
Be coupled to the encoder of described configurable interface, it is configured to convert parallel data to serial output data, and described serial output data has high and low data pulse, and each height and low data pulse are encoded into has 2
MIn the individual different pieces of information pulsewidth one, wherein M is the integer more than or equal to 1; And
Be coupled to the decoder of described configurable interface, it is configured to convert described serial output data to parallel data.
14. system as claimed in claim 13 is characterized in that, described external source is a microcontroller.
15. system as claimed in claim 13 is characterized in that, described external source is an imaging device.
16. system as claimed in claim 13 is characterized in that, described configurable interface is configured to accept microprocessor data.
17. system as claimed in claim 13 is characterized in that, described configurable interface is configured to accept the data based on image.
18. system as claimed in claim 13 is characterized in that, the value of M is 2.
19. a method that is used for the parallel image data transaction is become serial image data comprises:
Receive the parallel image data;
From described parallel image data, peel off any pixel clock; And
Described parallel image data transaction is become serial data, and described serial data has high and low data pulse, and each height and low data pulse are encoded into has 2
MIn the individual different data pulse widths one, wherein M is the integer more than or equal to 1.
20. method as claimed in claim 19 is characterized in that, also comprises from described parallel image data peeling off any synchronizing signal.
21. method as claimed in claim 20 is characterized in that, also comprises the two or more parallel image data words of serial connection, any synchronizing signal be stripped from described word.
22. method as claimed in claim 21 is characterized in that, also comprises to the view data that is connected in series appending single horizontal-drive signal and single vertical synchronizing signal.
23. method as claimed in claim 19 is characterized in that, the value of M is 2.
24. a method that is used for the paralleling microprocessor data transaction is become serial microprocessor data comprises:
Receive the paralleling microprocessor data;
From described microprocessor data, peel off any clock signal;
From described microprocessor data, peel off any chip and select data; And
Described paralleling microprocessor data transaction is become serial data, and described serial data has high and low data pulse, and each height and low data pulse are encoded into has 2
MIn the individual different pieces of information pulsewidth one, wherein M is the integer more than or equal to 1.
25. method as claimed in claim 24 is characterized in that, the value of M is 2.
26. a method that is used for parallel data signal is converted to serial data signal comprises:
Receive parallel data; And
Convert described parallel data to serial data, described serial data has high and low data pulse, and each height and low data pulse are encoded into has 2
MIn the individual different pieces of information pulsewidth one.
27. method as claimed in claim 24 is characterized in that, the value of M is 2.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US51074003P | 2003-10-10 | 2003-10-10 | |
| US60/509,487 | 2003-10-10 | ||
| US60/510,740 | 2003-10-10 |
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| CN1883141A true CN1883141A (en) | 2006-12-20 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9215410B2 (en) | 2013-07-08 | 2015-12-15 | Fermax Design & Development, S.L.U. | Two-wire multichannel video door system |
| CN113822258A (en) * | 2021-11-24 | 2021-12-21 | 山东省计量科学研究院 | Cable length metering method and device and storage medium |
-
2004
- 2004-10-08 CN CN 200480033586 patent/CN1883141A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9215410B2 (en) | 2013-07-08 | 2015-12-15 | Fermax Design & Development, S.L.U. | Two-wire multichannel video door system |
| CN113822258A (en) * | 2021-11-24 | 2021-12-21 | 山东省计量科学研究院 | Cable length metering method and device and storage medium |
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