CN1877553A - Bus system - Google Patents
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- CN1877553A CN1877553A CN 200510026486 CN200510026486A CN1877553A CN 1877553 A CN1877553 A CN 1877553A CN 200510026486 CN200510026486 CN 200510026486 CN 200510026486 A CN200510026486 A CN 200510026486A CN 1877553 A CN1877553 A CN 1877553A
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Abstract
Disclosed is a general bus system which can transmit distributed data between different general bus equipments. The inventive general bus system comprises a plurality of general bus node units, each of them corresponds to one general device; a general bus ring for connecting the said plural general bus nodes together. The general bus system is a ring type structure, and the general bus allows the concurrency of data transmission among plural nodes to promote transmission efficiency and band width of general bus.
Description
Technical field
The present invention relates to a kind of bus system, relate in particular to a kind of bus system that can between a plurality of bus apparatus, carry out the distributed data transmission that is applied to system-on-a-chip.
Background technology
System-on-a-chip is to concentrate design on chip piece the armamentarium of electronic system, by certain coordination system each equipment in the system is carried out cooperation management, realizes to reach system-level function.System-on-a-chip generally has characteristic of simple structure, the design process of system-on-a-chip is also simplified and accelerated to silicon intellectual property nuclear multiplex technique simultaneously, both can increase and decrease applied function module easily, and can make upgrading and modification become more easy again according to real needs.
The comprehensive realization of reaching sophisticated functions on chip piece in the system-on-a-chip, usually comprise a plurality of equipment that need receiving and transmitting signal to each other, for avoiding the equipment while contention bus of a plurality of transmission signals, perhaps send a signal to identical target device simultaneously and produce conflict, bus system will be between each equipment on the bus allocate communications resource.In order to adapt with system architecture, the communication between inner each subsystem of system-on-a-chip tends to be provided with the chip system bus.The chip system bus then adopts standard interface based on certain computer bus agreement for each equipment that is connected on the bus, and this bus system itself has also constituted a modularization ingredient in the total system.This modular design mode has further improved the extensibility of system, and the deep sub-micron technique that technology adopted of system-on-a-chip realization has simultaneously also further promoted the raising of the integrated level of system-on-a-chip.On the System on Chip/SoC of this Highgrade integration, the real-time Communication for Power of each equipment becomes the problem that needs are paid close attention in the how assurance system.A large amount of distributed embedded dynamic RAM (Embedded Dynamic Random Access Memory are especially arranged in chip; EDRAM) or single tube static random-access memory (Static Random Access Memory; SRAM) occasion, each main equipment in the system allows accessing storage device continually, and can carry out data transfer by memory device.For reaching more real-time high-efficiency accessing, requirement has been proposed for the concurrent access of each equipment in the system.
Fig. 1 is a kind of logic bus structural drawing of existing system-on-a-chip.Bus apparatus 1-6 is connected with bus 10 respectively, and transmits signal by bus.When the equipment on each bus need send signal, propose bus to moderator 18 and use request, decide the current equipment that takies bus by moderator at last.In the bus architecture of this class, the arbitration of moderator 18 at a time only allows a main equipment to take bus and transmits signal, that is to say, arbitrary moment can only have a main equipment to meet with a response and take the bus Data transmission, other main equipments just may take bus and carry out the signal transmission if needing to send signal also need wait for after the current main equipment that takies bus discharges bus.Simultaneously, in this bus architecture, all data transmit all to be needed at first could arrive target device through moderator, thereby has also limited the raising of bus frequency.
Summary of the invention
The objective of the invention is to overcome the defective of prior art, a kind of bus system of novelty is provided, particularly a kind ofly carry out that distributed data transmits and allow a plurality of main equipments on the bus to transmit the bus system of data simultaneously to a plurality of slave units.
According to bus system of the present invention, to transmit in order between a plurality of bus apparatus, to carry out distributed data, it comprises:
A plurality of bus nodes unit, each bus node unit corresponds respectively to each bus apparatus;
Bus ring is in order to link together described a plurality of bus nodes unit circlewise.
Wherein, described bus node unit comprises:
Receive queue unit, in order to receive and buffer memory from the data of a last bus node unit;
The transmit queue unit, the data of coming self-corresponding bus apparatus in order to buffer memory;
The ring control module, control described reception queue unit reception and buffer memory and deliver to corresponding bus apparatus processing, control described transmit queue unit caches and come the data of self-corresponding bus apparatus and these data are sent to next bus node unit from the data of a last bus node unit and with these data.
Wherein, described bus node unit also comprises the queue unit of passing by on one's way that is sent to the data of next bus node unit in order to buffer memory by a last bus node unit.
Wherein, described bus ring is the bidirectional bus ring, and it comprises at least two unidirectional rings of up time needle ring and inverse time needle ring.
Wherein, described ring control module comprises:
Receive control module, receive by described bus ring and to comprise command field, address field and data field at interior token signal by what a last bus node unit sent, and according to the reception queue unit of the current bus node of this token signal controlling unit or the queue unit of passing by on one's way receives and buffer memory from the data of a last bus node unit;
Sending controling unit receives the transmit queue unit of current bus node unit or the described token signal of the queue unit of passing by on one's way, and sends to described bus ring according to the data in this token signal controlling described transmit queue unit or the queue unit of passing by on one's way.
Wherein, described bus node unit comprises at least one the busy condition module corresponding at least one unidirectional ring of described bus ring.
Wherein, described busy condition module comprises:
At least one latch register is in order to latch the data in pass by on one's way in the current bus node unit queue unit or the transmit queue unit;
The busy condition machine, full or receive the full busy status signal of queue unit in order to receive the queue unit of passing by on one's way that next bus node unit sends, control described latch register and latch data in pass by on one's way in the current bus node unit queue unit or the transmit queue unit.
Wherein, described reception queue unit, transmit queue unit and the queue unit of passing by on one's way are made up of impact damper.
Wherein, in a plurality of bus apparatus corresponding to a plurality of bus nodes unit, the bus apparatus that access probability is bigger is arranged on the bus ring on the position adjacent each other.
In the bus system of the present invention, the bus node unit can carry out data transfer each other by bus ring, thereby reaches the data transfer between the bus apparatus.When a certain bus node unit as source node when other bus node unit as destination node send data, data to be sent send by the bus apparatus of source node earlier and buffer memory to the transmit queue unit of source node, under the control of the ring control module of source node, send to other node units again by bus ring.When a certain bus node unit receives from as the data of other bus node unit of source node the time as destination node, under the control of the ring control module of this destination node, data elder generation buffer memory to be received is received data and is carried out respective handling by bus apparatus again to the reception queue unit of this destination node.Transmit in the process of data to destination node at source node on the bus, bus node unit between source node and the destination node is as the passing node unit, the data that transmit then are buffered in the queue unit of passing by on one's way of each passing node unit in succession, transmit in the mode of relay.
And bus ring comprises up time needle ring and inverse time needle ring, can carry out bi-directional data and transmit.
And on bus ring, the bus apparatus that access probability is bigger is arranged on contiguous position each other.
And this bus system is loop configuration, allows the data transfer of a plurality of nodes concurrent in the bus, thereby improved the transmission efficiency of bus, also correspondingly increased bus width.
Description of drawings
The following drawings is the aid illustration to exemplary embodiment of the present, to the elaboration of the embodiment of the invention, be to disclose feature of the present invention place, but do not limit the present invention in conjunction with the following drawings for further, same-sign is represented respective element or step among the embodiment among the figure, wherein:
Fig. 1 is the bus structure synoptic diagram of a kind of system-on-a-chip of the prior art.
Fig. 2 is the structured flowchart of a kind of bus system in one embodiment of the present of invention.
Fig. 3 is the inner structure block diagram of a bus node unit in the bus system of the present invention.
Fig. 4 is the composition synoptic diagram of token between the bus node unit in one embodiment of the present of invention.
Fig. 5 is the structural representation of ring control module in the bus node of the present invention unit.
Fig. 6 is the fundamental diagram of ring control module in the bus node of the present invention unit, and it has comprised a busy condition module.
Fig. 7 is the logical organization synoptic diagram of the busy condition machine in the busy condition module shown in Fig. 6.
Embodiment
Embodiment shown in Figure 2 is that example illustrates bus system of the present invention with the bus system that comprises 6 bus apparatus 11 to 16.Bus apparatus can be CPU, demoder and other special IC module (ASIC) or storer, as SDRAM, FLASH etc.
Referring to Fig. 2, bus system of the present invention comprises the bus ring 20 of a loop configuration, has a plurality of bus apparatus to be connected on the bus ring 20 by each self-corresponding bus node unit (also abbreviating bus node as) 21 to 26 respectively.Bus ring 20 is a two-way ring for example, comprises up time needle ring and inverse time needle ring.On the bus ring, bus apparatus 11 to 16 can transmit signal by each self-corresponding bus node unit 21 to 26 two-wayly.Up time needle ring and inverse time needle ring can be set to separate physically, and like this, two adjacent bus apparatus can carry out the bi-directional of data each other simultaneously.
In one embodiment of the invention, bus apparatus neighbouring relations are to each other also followed certain rule, and promptly in the bus ring 20, the bigger equipment of access probability is arranged on close position each other.For example, bus apparatus 11 and bus apparatus 13 need be to bus apparatus 12 read/write data, bus apparatus 14 also needs to bus apparatus 13 read/write data, and bus apparatus 11 is compared the visit of 14 pairs of bus apparatus 12 of bus apparatus with bus apparatus 13 more frequent, so bus apparatus 11 and bus apparatus 13 are arranged on the adjacent both sides of bus apparatus 12 in the bus ring, and bus apparatus 14 can be provided with far from bus apparatus 12.In addition, bus apparatus 11 need be to bus apparatus 15 and 16 read/write data, comparatively speaking, bus apparatus 11 for the access probability of bus apparatus 16 greater than access probability to bus apparatus 15, therefore, bus apparatus 16 is arranged at bus apparatus 11 adjacent position, and bus apparatus 15 can be provided with far slightly from bus apparatus 11.
In the bus ring 20, the data transfer operation between each bus apparatus adopts distributed carrying out.For example, transmit data from bus apparatus 11 and give bus apparatus 14, when data in bus ring 20 when the up time needle ring transmits, its data transmission route is:
Bus node unit, bus node unit, bus node unit 11---〉12---〉13---〉bus node unit 14.At this moment, bus node unit 11 is as source node unit, and bus node unit 14 is as the destination node unit.And for bus node unit 11 and 14, bus node unit 12 and 13 is the passing node unit.On the other hand, as bus node unit 12 being regarded as current bus node unit, then bus node unit 11 is its a last bus node unit, and bus node unit 13 is its next bus node unit.
And at synchronization, the data between bus apparatus 15 and the bus apparatus 16 transmit the influence that is not subjected to the data transfer operation between bus apparatus 11 and the bus apparatus 14.
Like this, at synchronization, allow a plurality of bus apparatus in the bus ring 20 and carrying out data transfer operation, thereby the transmission bandwidth of bus ring is greatly improved.
Fig. 3 has exemplarily represented the inner structure of each bus node unit 21 to 26 on the bus ring 20.
Each bus node unit comprises reception queue unit 231, transmit queue unit 232, the queue unit of passing by on one's way 233 and ring control module 235.Reception queue unit 231, transmit queue unit 232, the queue unit of passing by on one's way 233 for example are made up of impact damper, and it can be data cached, as register or static RAM, dynamic RAM etc.Carry out buffer memory with the FIFO form in the present embodiment.It is data cached in the process of bus node unit reception data, transmission data respectively to receive queue unit 231, transmit queue unit 232.Neither send the source node of data, is not again the destination node that receives data when the bus node unit, and during just as the passing node in the data conveyance path configured, carries out buffer memory by the mistake circuit-switched data of the 233 pairs of transmission of queue unit of passing by on one's way.
Utilize token on bus ring, to carry out the signal transmission between the bus node unit.In one embodiment of the invention, when sending order between the bus apparatus, all orders, address and data-signal all send simultaneously.Token is divided into three ingredients: command field, address field and data field.
Fig. 4 is the composition synoptic diagram of used token between the bus node unit in the one embodiment of the invention.As shown in Figure 4, the transmission command signal ONCmd and the IPCmd that comprise output next node and the last node of input in the command field 41 wherein.For the data that adopt burst form to send, the burst command signal ONBurst and the IPBurst of output next node and the last node of input can be arranged in the command field 41.The destination node number ONDstnum and the IPDstnum that comprise output next node and the last node of input in the address field 42; The purpose transport address ONAddr and the IPAddr of output next node and the last node of input; The source node number ONSrcnum and the IPSrcnum of output next node and the last node of input.Then comprise the data of exporting next node and data ONData and the IPData that imports a last node in the data field 43 at least.Command field 41 can also comprise output busy status signal OPBusy that exports a last node and the input busy status signal INBusy that imports next node.Output busy status signal OPBusy and input busy status signal INBusy will be further described below.
A certain bus node unit as source node when other bus node unit send data, data to be sent are delivered to the transmit queue unit of source node and buffer memory from the pairing bus apparatus of source node earlier, send to other node units by bus ring again under the control of the ring control module of source node.When a certain bus node unit receives data from other bus node unit as destination node, data to be received elder generation buffer memory is to the reception queue unit of this destination node, and pairing bus apparatus receives and is buffered in the data that receive in the queue unit by this destination node under the control of the ring control module of destination node again.Transmit in the process of data to destination node at source node on the bus ring, if as also having other bus node unit between the bus node unit of source node and the bus node unit as destination node, then the latter is as passing node, data in the transmission are buffered in the queue unit of passing by on one's way of each passing node in succession, transmit in the mode of relay.
Fig. 5 is the structured flowchart of ring control module 235, and Fig. 6 is the fundamental diagram of ring control module 235.Ring control module 235 comprises reception control module 2351 and sending controling unit 2352, respectively the reception and the transmission of the data of control bus node unit.Can see that in conjunction with Fig. 5 and Fig. 6 reception control module 2351 receives by a last token signal that the bus node unit sends by the up time needle ring 201 or the inverse time needle ring 202 of bus ring 20, and whether the destination node that judgment data sends is present node.If destination node is a present node, then receive data and buffer memory by receiving queue unit 231.If destination node is not a present node, present node is just as passing node, and then the queue unit 233 of passing by on one's way by present node receives data and buffer memory.
Sending controling unit 2352 receives the transmit queue unit 232 of bus node unit and the token signal of queue unit 233 of passing by on one's way, and judges that data to be sent are from transmit queue unit 232 or from the queue unit 233 of passing by on one's way.Sending controling unit 2352 adopts predetermined algorithm to select the preferential data that send, and personnel know as the present technique field, and daisy chain algorithm, priority is algorithm or fair round-robin algorithm etc. fixedly.Adopt fair round-robin algorithm to describe in the present embodiment.When competition appearred in the bus request of the transmit queue unit in the sending controling unit 2,352 232 and the queue unit 233 of passing by on one's way, sending controling unit 2352 was selected the data of the transmit queue unit 232 and the queue unit 233 of passing by on one's way by turns according to fair round-robin algorithm.Sending controling unit 2352 also needs to judge up time needle ring 201 or the inverse time needle ring 202 that data to be sent are given bus ring 20 according to token signal simultaneously, then sends data to corresponding unidirectional ring by token signal when output data.
With reference to Fig. 6, sending controling unit 2352 is provided with a busy condition module 60 respectively corresponding to each unidirectional ring (up time needle ring 201 or inverse time needle ring 202).Each busy condition module 60 of up time needle ring 201 and inverse time needle ring 202 is provided with at least one busy condition machine in the present embodiment.Match with the busy condition machine, be provided with two corresponding busy status signal: OPBUSY and INBUSY in the command field of token.Wherein, OPBUSY is an output signal, is to export on it node by present node to show that present node is in busy condition; INBUSY is an input signal, is to be input to present node by next node to show that next node is in busy condition.
Be in busy condition at present node, in the time of can not receiving the data from a last node, present node sends busy status signal OPBUSY and gives a last node, makes a node latch data; Need if next node is in busy condition, can not receive data when next node sends data at present node, then the busy condition module 60 of present node can receive busy status signal INBUSY, and latchs data.
Be provided with at least one latch register in each busy condition module 60 and come latch data.Be provided with two latch registers 604 and 605 in the present embodiment, be called first latch register and second latch register, the two is respectively by busy condition machine 601 and 602 controls.
Fig. 7 is the logical organization synoptic diagram of busy condition machine.Referring to Fig. 7, the busy condition machine has two states: input busy condition (INBUSY) and idle condition (IDLE).The busy condition machine is IDLE generally speaking, and when following two kinds of situations occurring, the busy condition machine changes the input busy condition over to:
1) when next node be passing node, and the busy condition machine receives the full busy status signal INBUSY of queue unit that passes by on one's way that next node sends, at this moment, first latch register or second latch register can latch pass by on one's way data in the queue unit of present node; Perhaps
2) when next node be destination node, and the busy condition machine receives the full busy status signal INBUSY of reception queue unit that next node sends, at this moment, first latch register or second latch register can latch the data in the present node transmit queue unit.
Busy condition machine 601,602 is controlled the action of latching of its latch registers 603,604, makes token keep stable.Latch register for example can realize that as d type flip flop or rest-set flip-flop, busy status signal INBUSY sends into the control end control of trigger and latchs action with trigger.
In each unidirectional ring, for example in the up time needle ring 201 or inverse time needle ring 202 of present embodiment, mainly have two kinds of situations and can produce busy status signal OPBUSY.First kind of situation be, when the reception queue unit of present node when full, it is that destination node needs the reception queue unit of present node to receive the request signal of data with the present node that present node receives one simultaneously; Second kind of situation be, when two latch registers of present node all have data transmitting, promptly all be the unlatching state, receives a request signal that the data demand transmission of passing by on one's way is arranged simultaneously again.Under these two kinds of situations, the reception control module of present node will send the OPBUSY signal to a last node.When above-mentioned these the two kinds of situations of present node appearance, present node can be exported the OPBUSY signal and give a last node, and after the OPBUSY signal was input to a node, for a last node, the signal that receives was the INBUSY signal.
After sending controling unit is chosen data to be sent according to fair round-robin algorithm, will send request signal to the next bus node on the bus ring.Here, when the next bus node unit of sending controling unit output was destination node, whether its reception queue unit of next bus node unit judges was full; The next bus node unit of sending controling unit output is during as passing node, and whether next two latch register of bus node unit judges all is the unlatching state.If the reception queue unit of next node or the queue unit of passing by on one's way are full state, then feed back a busy status signal OPBUSY and give present node.After present node received the signal that a node sends, the confidential busy status signal INBUSY that comes according to feedback of the busy condition of present node maked decision, and makes the data temporary cache in present node, and does not carry out next step transmission.When the busy condition in next bus node unit finished, the busy condition machine of present node was transformed into idle condition, allowed data in buffer in the reception queue unit or the queue unit of passing by on one's way in the present node is sent to next bus node unit.
When the present node unit is as the data of source node in its next node output transmit queue unit, present node also can be exported data in the queue unit of passing by on one's way, the parallel transfer of so further having reached the unidirectional loop data of present node simultaneously as passing node.For each unidirectional ring of present embodiment, can realize the parallel transfer of data.And carrying out data when transmitting simultaneously when the transmit queue unit of present node and the queue unit of passing by on one's way, if it need be the request signal that passing node transmits data with the present node that the last node on the unidirectional in the same way ring sends, then the reception control module of present node can feed back the OPBUSY signal to a last node, the data of a node are latched, and can not lose, thereby make the token of a node keep stable.
In other embodiments of the invention, more queue unit of independently passing by on one's way can be set on the bus node unit, and correspondingly increase the quantity of latch register, also allow the more parallel transfer of multichannel data.
Present embodiment is just in order further more clearly to describe the present invention, but not limitation of the present invention.Be to be understood that the present invention is not limited to the elaboration that the foregoing description is done, anyly all should be encompassed within the spirit and scope of claim of the present invention based on modification of the present invention and equivalent of the present invention.
Claims (9)
1. one kind in order to carry out the bus system that distributed data transmits between a plurality of bus apparatus, it is characterized in that comprising:
A plurality of bus nodes unit, each bus node unit corresponds respectively to each bus apparatus;
Bus ring is in order to link together described a plurality of bus nodes unit circlewise.
2. bus system as claimed in claim 1 is characterized in that, described bus node unit comprises:
Receive queue unit, in order to receive and buffer memory from the data of a last bus node unit;
The transmit queue unit, the data of coming self-corresponding bus apparatus in order to buffer memory;
The ring control module, control described reception queue unit reception and buffer memory and deliver to corresponding bus apparatus processing, and control described transmit queue unit caches and come the data of self-corresponding bus apparatus and these data are sent to next bus node unit from the data of a last bus node unit and with these data.
3. bus system as claimed in claim 2 is characterized in that, described bus node unit also comprises the queue unit of passing by on one's way that is sent to the data of next bus node unit in order to buffer memory by a last bus node unit.
4. bus system as claimed in claim 1 is characterized in that, described bus ring is the bidirectional bus ring, and it comprises at least two unidirectional rings of up time needle ring and inverse time needle ring.
5. bus system as claimed in claim 3 is characterized in that, described ring control module comprises:
Receive control module, receive by described bus ring and to comprise command field, address field and data field at interior token signal by what a last bus node unit sent, and according to the reception queue unit of the current bus node of this token signal controlling unit or the queue unit of passing by on one's way receives and buffer memory from the data of a last bus node unit;
Sending controling unit receives the transmit queue unit of current bus node unit or the described token signal of the queue unit of passing by on one's way, and sends to described bus ring according to the data in this token signal controlling described transmit queue unit or the queue unit of passing by on one's way.
6. bus system as claimed in claim 4 is characterized in that, described bus node unit comprises at least one the busy condition module corresponding at least one unidirectional ring of described bus ring.
7. bus system as claimed in claim 6 is characterized in that, described busy condition module comprises:
At least one latch register is in order to latch the data in pass by on one's way in the current bus node unit queue unit or the transmit queue unit;
The busy condition machine, full or receive the full busy status signal of queue unit in order to receive the queue unit of passing by on one's way that next bus node unit sends, control described latch register and latch data in pass by on one's way in the current bus node unit queue unit or the transmit queue unit.
8. bus system as claimed in claim 3 is characterized in that, described reception queue unit, transmit queue unit and the queue unit of passing by on one's way are made up of impact damper.
9. as the arbitrary described bus system of claim 1 to 8, it is characterized in that in a plurality of bus apparatus corresponding to a plurality of bus nodes unit, the bus apparatus that access probability is bigger is arranged on the bus ring on the position adjacent each other.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005100264867A CN100447769C (en) | 2005-06-06 | 2005-06-06 | Bus system |
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| CNB2005100264867A CN100447769C (en) | 2005-06-06 | 2005-06-06 | Bus system |
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| CN1877553A true CN1877553A (en) | 2006-12-13 |
| CN100447769C CN100447769C (en) | 2008-12-31 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8514953B2 (en) | 2007-11-06 | 2013-08-20 | Qualcomm Incorporated | Delta writing scheme for MIMO signal paths |
| CN103164380B (en) * | 2011-12-06 | 2017-04-12 | 费斯托股份有限两合公司 | Bus node and control system |
| CN111026699A (en) * | 2019-12-05 | 2020-04-17 | 苏州雄立科技有限公司 | Multi-core network communication method, device and system based on ring bus |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5555540A (en) * | 1995-02-17 | 1996-09-10 | Sun Microsystems, Inc. | ASIC bus structure |
| DE19844185C2 (en) * | 1998-09-28 | 2002-01-03 | Danfoss As | bus line |
| US6718421B1 (en) * | 2001-06-19 | 2004-04-06 | Webtv Networks, Inc. | Interconnect bus |
| GB2377138A (en) * | 2001-06-28 | 2002-12-31 | Ericsson Telefon Ab L M | Ring Bus Structure For System On Chip Integrated Circuits |
| KR100477641B1 (en) * | 2002-01-15 | 2005-03-23 | 삼성전자주식회사 | Bus system and path decision method therefor |
| CN1286038C (en) * | 2003-10-17 | 2006-11-22 | 中兴通讯股份有限公司 | Dual-ring quene-based, non-interrupt PCI communication method |
-
2005
- 2005-06-06 CN CNB2005100264867A patent/CN100447769C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8514953B2 (en) | 2007-11-06 | 2013-08-20 | Qualcomm Incorporated | Delta writing scheme for MIMO signal paths |
| CN101843004B (en) * | 2007-11-06 | 2016-08-03 | 高通股份有限公司 | The increment wiring method in MIMO signal path and equipment |
| CN103164380B (en) * | 2011-12-06 | 2017-04-12 | 费斯托股份有限两合公司 | Bus node and control system |
| CN111026699A (en) * | 2019-12-05 | 2020-04-17 | 苏州雄立科技有限公司 | Multi-core network communication method, device and system based on ring bus |
| CN111026699B (en) * | 2019-12-05 | 2024-02-06 | 苏州雄立科技有限公司 | Multi-core network communication method, device and system based on ring bus |
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| CN100447769C (en) | 2008-12-31 |
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