CN1877480A - Light Load Control Circuit for Buck-Boost Voltage Converter - Google Patents

Abstract

The present invention discloses a light load control circuit, which enables the switching circuit of a step-up/down voltage converter to alternately operate in multiple phase cycles and sleep periods. Each phase cycle has a rising phase, a falling phase, and a maintaining phase. In the rising phase, the switching circuit system is operated to increase the inductor current. In the falling phase, the switching circuit system is operated to decrease the inductor current. In the maintaining phase, the switching circuit system is operated to maintain the inductor current almost fixed. During the sleep period, the two ends of the inductor are prevented from being coupled to any two of the input voltage, the output voltage, and the ground potential.

Description

Light Load Control Circuit for Buck-Boost Voltage Converter

technical field

The invention relates to a DC/DC voltage converter, in particular to a light load control circuit of a lifting voltage converter.

current technology

Figure 1 shows the circuit diagram of an existing buck-boost voltage converter. Referring to FIG. 1 , the conventional up-down voltage converter includes a synchronous switching circuit 10 , a up-down control circuit 11 , a driving circuit 12 , and a light load control circuit 13 .

The up-down control circuit 11 generates a voltage conversion control signal VCS based on the feedback of the output voltage V _out . In response to the voltage conversion control signal VCS, the driving circuit 12 generates four driving signals D1 to D4 for driving the switching units S1 to S4 respectively. By properly controlling the conduction and/or non-conduction of the switching units S1 to S4, and the ratio of the conduction time or non-conduction time, the input voltage V _in can be effectively converted into the output voltage V _out , wherein the input voltage V _in Can be greater than, equal to, or less than the output voltage V _out . There are many types of lifting control circuits 11 in the prior art, such as the circuits and methods disclosed in technical documents such as US Pat. No. 6,166,527 and US Pat. No. 6,788,033.

When the load current I _out required by the load 50 is small, in order to improve the voltage conversion efficiency, the existing buck-boost voltage converter will enter the light load mode of operation. In the operation of the light load mode, the driving circuit 12 no longer responds to the voltage conversion control signal VCS of the lifting control circuit 11 , but is changed to be controlled by the light load control circuit 13 . For example, Figures 3 and 4 on page 10 of the LT3438 "Micropower Synchronous Buck-Boost DC/DC Converter" product specification (Datasheet) published by Linear Technology in October 2001 disclose the existing lightweight load pattern.

Figure 2(A) shows the timing diagram of the inductor current I _L in the existing light load mode. Referring to FIG. 2(A), the existing light load mode includes a rising phase and a falling phase. During the rising phase, ie from time t1 to t2, the inductor current _IL rises linearly from zero to a predetermined peak value I _pk . During the falling phase, ie from time t2 to t3, the inductor current _IL drops linearly from the peak value _Ipk to zero.

FIG. 2(B) shows a schematic diagram of the operation state of the synchronous switching circuit 10 in the rising phase. Referring to FIG. 2(B), the switching units S1 and S4 are both turned on and the switching units S2 and S3 are not turned on, so that the first end La of the inductor L is coupled to the input voltage _Vin and the second end Lb is coupled to the ground potential. Therefore, the inductor current _IL increases linearly at a rate of (V _in /L).

FIG. 2(C) shows a schematic diagram of the operation state of the synchronous switching circuit 10 in the falling phase. Referring to FIG. 2(C), the switching units S1 and S4 are both turned on and the switching units S2 and S3 are both turned on, so that the first end La of the inductor L is coupled to the ground potential and the second end Lb is coupled to the output voltage V _out . Therefore, the inductor current _IL decreases linearly at a rate of (V _out /L).

In the existing light load mode, the maximum average value of the load current that can be provided can be calculated by the following equation (1):

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; ave</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; max</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; pk</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

If the load current I _out exceeds the maximum light-load average output current I _{out_ave(max)} represented by equation (1), the existing buck-boost voltage converter will leave the light-load mode and its operation will return to the buck-boost control circuit 11 under control.

As mentioned above, regardless of whether the input voltage V _in is greater than, equal to, or less than the output voltage V _out , the buck-boost voltage converter can convert the input voltage V _in into a predetermined output voltage V _out . That is, the buck-boost voltage converter can be applied to a wide range of input voltages V _in . However, the change of the input voltage V _in will affect the maximum light-load average output current I _{out_ave(max)} in the light-load mode. Specifically, considering the partial differential operation of equation (1) with respect to the input voltage V _in , the following equation (2) can be obtained:

$<span\; class="notranslate">\; (</span>\frac{<span\; class="notranslate">\; \&PartialD;</span>}{{<span\; class="notranslate">\; \&PartialD;</span>\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; ave</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; max</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; pk</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}}{{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

Since Equation (2) is a function of the input voltage V _in , for different input voltages V _in , the light load control circuit 13 causes the buck-boost voltage converter to leave the light load under different maximum light load average output current I _{out_ave(max).} load pattern.

However, what is desired is a light load control circuit that can stably control the initiation and termination of the light load mode of the buck-boost converter for a wide range of input voltage V _in .

Contents of the invention

In view of the aforementioned problems, an object of the present invention is to provide a light load control circuit that can stably control the start and end of the light load mode of the buck-boost converter for a wide range of input voltages.

Another object of the present invention is to provide a light load control circuit that can effectively reduce the impact of input voltage changes on the maximum light load average output current.

According to an aspect of the present invention, a light load control circuit is provided for controlling a switching circuit of a buck-boost voltage converter. The switching circuit has an input switching unit and an output switching unit. The input switching unit selectively couples the first end of the inductor to the input voltage and the ground potential. The output switching unit selectively couples the second end of the inductor to the output voltage and the ground potential.

The light load control circuit has a stage control unit and a sleep control unit. The phase control unit makes the switching circuit operate in multiple phase cycles. Each phase cycle has an ascending phase, a descending phase, and a sustaining phase. During the ramp-up phase, the switching circuit operates to ramp up the inductor current flowing through the inductor. Alternatively, the switching circuit is operative to cause a potential difference across the first end and the second end of the inductor to have the first polarity. During the ramp-down phase, the switching circuit operates to ramp down the inductor current. Alternatively, the switching circuit is operative to cause the potential difference across the first end and the second end of the inductor to have the second polarity. The second polarity is opposite to the first polarity. During the sustain phase, the switching circuit operates to maintain the inductor current nearly constant. Alternatively, the switching circuit is operated such that the potential difference across the first terminal and the second terminal of the inductor is substantially zero.

After the output voltage reaches a predetermined sleep reference voltage, the sleep control unit makes the switching circuit operate during sleep to prevent the first end and the second end of the inductor from being coupled to any two of the input voltage, the output voltage, and the ground potential, respectively. . During the sleep period, the supply of load current is achieved solely by discharging the output capacitor.

The rate of change of the maximum light load average output current due to the output voltage is suppressed by the maintenance phase operation provided by the light load control circuit. Therefore, for a wide range of input voltages, the light load control circuit according to the present invention can stably control the startup and termination of the light load mode of the buck-boost voltage converter.

Description of drawings

Figure 1 shows a circuit diagram of an existing boost-boost voltage converter;

Figure 2(A) shows the timing diagram of the inductor current in the existing light load mode;

FIG. 2(B) shows a schematic diagram of the operating state of the synchronous switching circuit in the rising phase;

FIG. 2(C) shows a schematic diagram of the operating state of the synchronous switching circuit in the falling phase;

FIG. 3 shows a circuit diagram of a boost voltage converter according to a first embodiment of the present invention;

4 shows a timing diagram of the feedback voltage signal and the inductor current in the light load mode according to the first embodiment of the present invention;

FIG. 5(A) shows a schematic diagram of the operating state of the synchronous switching circuit in the rising phase;

Fig. 5 (B) shows the schematic diagram of the operating state of the synchronous switching circuit in the falling phase;

FIG. 5(C) shows a schematic diagram of the operating state of the synchronous switching circuit in the maintenance phase;

FIG. 5(D) shows a schematic diagram of six operating states of the synchronous switching circuit during sleep;

FIG. 6 shows a detailed circuit diagram of the sustain time control unit according to the first embodiment of the present invention;

FIG. 7(A) shows a circuit diagram of a light load control circuit according to a second embodiment of the present invention;

FIG. 7(B) shows a timing diagram of the inductor current in the light load mode according to the second embodiment of the present invention;

FIG. 8(A) shows a circuit diagram of a light load control circuit according to a third embodiment of the present invention; and

FIG. 8(B) shows a timing diagram of the inductor current in the light load mode according to the third embodiment of the present invention.

Description of main component symbols

10, 30 Synchronous switching circuit 11, 31 Lifting control circuit

12, 32 Drive circuit 13, 33, 73, 83 Light load control circuit

34 Voltage Feedback Circuit 35 Starting Unit

36, 76, 86 stage control unit 36-1, 36-2 current comparator

36-3, 76-3, 86-3 maintenance time control unit

37 Sleep control unit 50 Load

AT, AT1, AT2 trigger terminal AO, AO1, AO2 output terminal

B _m buffer inverter C _out output capacitance

C _m capacitance CP _m voltage comparator

D1～D4 Drive Signal L L Inductance

La, La Both ends of the inductor I _L inductor current

I _out load current I _pk peak current

I _bm valley current I _th critical current

I _m charging current S1～S4 switching unit

S _m NMOS transistor T _m sustain time

V _in input voltage V _out output voltage

V _fb voltage feedback signal V _th threshold voltage

V _m sustain time reference voltage V _slp sleep reference voltage

V _hys hysteresis voltage VCS voltage switching control signal

LM Light load start signal LX Light load termination signal

RX Rising stop signal FX Falling stop signal

MX, MX1, MX2 maintain termination signal

SLP sleep signal

Detailed ways

The foregoing and other objects, features, and advantages of the present invention will be more apparent from the following description and accompanying drawings. Preferred embodiments according to the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 3 shows a circuit diagram of a buck-boost voltage converter according to a first embodiment of the invention. The buck-boost voltage converter is used to convert the input voltage V _in to an output voltage V _out , wherein the input voltage V _in can be greater than, equal to, or less than the output voltage V _out . Referring to FIG. 3 , the boost voltage converter includes a synchronous switching circuit 30 , a boost control circuit 31 , a drive circuit 32 , a light load control circuit 33 , and a voltage feedback circuit 34 .

The synchronous switching circuit 30 has an input switching unit and an output switching unit. Specifically, the input switching unit is composed of the first switching unit S1 and the second switching unit S2, and the output switching unit is composed of the third switching unit S3 and the fourth switching unit S4. The first switching unit S1 is disposed between the input voltage _Vin and the first end La of the inductor L. As shown in FIG. The second switching unit S2 is disposed between the first end La of the inductor L and the ground potential. The third switching unit S3 is disposed between the second end Lb of the inductor L and the output voltage V _out . The fourth switching unit S4 is disposed between the second end Lb of the inductor L and the ground potential.

The voltage feedback circuit 34 is coupled to the synchronous switching circuit 30 for generating a voltage feedback signal V _fb representing the output voltage V _out . For example, the voltage feedback circuit 34 is implemented by a voltage divider formed by a plurality of series resistors.

In response to the voltage feedback signal V _fb , the up-down control circuit 31 generates a voltage conversion control signal VCS for determining the conduction or non-conduction of the switching units S1 to S4 of the synchronous switching circuit 30 , and their conduction time and non-conduction time. The voltage conversion control signal VCS includes a plurality of independent or interrelated sub-signals for controlling the switching units S1 to S4 respectively. The voltage conversion control signal VCS forms four driving signals D1 to D4 through the driving circuit 32 to drive the switching units S1 to S4 respectively. By properly controlling the conduction and/or non-conduction of the switching units S1 to S4, and the ratio of the conduction time to the non-conduction time, the input voltage V _in can be effectively converted into the output voltage V _out regardless of the input voltage V _in greater than, equal to, or less than the output voltage V _out . Since the lifting control circuit 31 is well known to those skilled in the art, it will not be repeated here. Please note that the present invention mainly relates to the light-load control circuit 33, and the light-load control circuit 33 according to the present invention can be applied to all currently known or future-developed buck-boost voltage converters, rather than being limited to a few specific buck-boost converters. Formula control circuit 31.

When the load current I _out required by the load 50 is small, in order to improve the voltage conversion efficiency, the buck-boost voltage converter according to the present invention will enter into a light load mode of operation. In the operation of the light load mode, the driving circuit 32 no longer responds to the voltage conversion control signal VCS generated by the lifting control circuit 31 , but is changed to be controlled by the light load control circuit 33 . Specifically, the light load control circuit 33 includes a startup unit 35 , a stage control unit 36 , a sleep control unit 37 , and a termination unit 38 .

The starting unit 35 is used for detecting the inductor current I _L and is triggered to generate a light load starting signal LM when the inductor current I _L is lower than a predetermined critical current I _th . In response to the light load enable signal LM, the driving circuit 32 is then switched to be controlled by the light load control circuit 33 so as to operate in a light load mode with higher efficiency. For example, the start-up unit 35 can be implemented by a current comparator to compare the inductor current I _L with the critical current I _th , so that when the inductor current I _L is lower than the critical current I _th , the current comparator is triggered to generate light Load enable signal LM.

The phase control unit 36 is used to make the synchronous switching circuit 30 operate in a plurality of phase cycles, wherein each phase cycle has a rising phase, a falling phase, and a maintaining phase. As shown in FIG. 4 , during the rising phase, that is, from time t1 to t2 , the inductor current _IL increases linearly from a predetermined valley value I _bm to a predetermined peak value I _pk . In the falling phase, ie from time t2 to t3, the inductor current I _L linearly decreases from the peak value I _pk to the valley value I _bm . In the maintaining phase, that is, from time t3 to t4, the inductor current _IL is maintained at a nearly constant state, that is, at the valley value I _bm at time t3.

The phase control unit 36 is provided with a current comparator 36-1 for comparing the inductor current I _L with a predetermined peak current I _pk . When the inductor current I _L rises linearly to reach the peak current I _pk , the current comparator 36 - 1 is triggered to generate a rising end signal RX, so that the driving circuit 32 terminates the rising phase operation of the synchronous switching circuit 30 .

The phase control unit 36 is also provided with another current comparator 36-2 for comparing the inductor current I _L with a predetermined valley current I _bm . When the inductor current I _L drops linearly to reach the valley current I _bm , the current comparator 36 - 2 is triggered to generate the falling termination signal FX, so that the driving circuit 32 terminates the falling phase operation of the synchronous switching circuit 30 . For example, the valley current I _bm can be set to zero.

The phase control unit 36 is also provided with a maintenance time control unit 36-3 for determining the length of the maintenance time T _m occupied by the maintenance phase. The hold time control unit 36-3 has a trigger terminal AT and an output terminal AO. When the trigger terminal AT receives the falling end signal FX, the sustain time control unit 36-3 starts to count the time. Once the predetermined sustain time T _m elapses, the output terminal AO of the sustain time control unit 36 - 3 generates a sustain termination signal MX, so that the driving circuit 32 terminates the sustain phase operation of the synchronous switching circuit 30 .

As shown in FIG. 5(A), in the rising phase, both the switching units S1 and S4 are turned on and neither the switching units S2 nor S3 are turned on, so that the first end La of the inductor L is coupled to the input voltage Vin and the second end La is coupled to the input voltage _Vin . Terminal Lb is coupled to ground potential. Therefore, the inductor current _IL increases linearly at a rate of (V _in /L).

As shown in FIG. 5(B), in the falling phase, the switching units S1 and S4 are both conducting and the switching units S2 and S3 are both conducting, so that the first end La of the inductor L is coupled to the ground potential and the second end Lb coupled to the output voltage V _out . Therefore, the inductor current _IL decreases linearly at a rate of (V _out /L).

As shown in FIG. 5(C), in the maintenance phase, the switching units S1 and S3 are both turned on and the switching units S2 and S4 are both turned on, so that both the first end La and the second end Lb of the inductor L are coupled to the ground potential. Since the potential difference between the first end La and the second end Lb of the inductor L is zero, the inductor current _IL freely flows in a closed loop and maintains an almost fixed state (if the inductor L and the switching unit S2 and S4 has a resistivity).

Referring back to FIGS. 3 and 4 , in the aforementioned multiple stages of operation, when the voltage feedback signal V _fb reaches the predetermined sleep reference voltage V _slp , the sleep control unit 37 is triggered to generate the sleep signal SLP. In response to the sleep signal SLP, the driving circuit 32 makes the switching circuit operate during the sleep period to prevent the first end La and the second end Lb of the inductor L from being coupled to any two of the input voltage V _in , the output voltage V _out , and the ground potential, respectively. indivual.

For example, as shown in FIG. 5(D), the synchronous switching circuit 30 can be in any one of six operating states during the sleep period. As for Example 1, the first switch unit S1 is turned on and the second to fourth switch units S2 to S4 are all turned on, so that the first end La of the inductor L is coupled to the input voltage _Vin , and the second end La of the inductor L The terminal Lb is in a floating state. As for Example 2, the second switching unit S2 is turned on while the first, third, and fourth switching units S1, S3, and S4 are not turned on, so that the first end La of the inductor L is coupled to the ground potential, and The second terminal Lb of the inductor L is in a floating state. As for Example 3, the third switching unit S3 is turned on while the first, second, and fourth switching units S1, S2, and S4 are not turned on, so that the first end La of the inductor L is in a floating state, and The second end Lb of the inductor L is coupled to the output voltage V _out . As for Example 4, the fourth switching unit S4 is turned on and the first to third switching units S1 to S3 are not turned on, so that the first terminal La of the inductor L is in a floating state, and the second terminal Lb of the inductor L is in a floating state. Coupled to ground potential. As for Example 5, both the second and fourth switching units S2 and S4 are turned on, while the first and third switching units S1 and S3 are not turned on, so that both the first terminal La and the second terminal Lb of the inductor L are coupled to ground potential. As for example 6, none of the first to fourth switching units S1 to S4 are turned on, so that both the first terminal La and the second terminal Lb of the inductor L are in a floating state.

During the sleep period, the supply of the load current I _out takes place solely by means of the discharge of the output capacitor C _out . Since the load current I _out required by the light load mode is extremely small, the discharge of the output capacitor C _out will not cause a sharp change in the output voltage V _out . For example, the sleep control unit 37 is implemented by a voltage comparator with hysteresis effect. After the start of the sleep period (such as time t5 of FIG. 4 ), once the voltage feedback signal V _fb drops from the sleep reference voltage V _slp by a predetermined hysteresis voltage V _hys (such as the time t5 of FIG. 4 ) due to the discharge of the output capacitor C _out time t6), the sleep period is terminated and the stage cycle controlled by the stage control unit 36 is resumed.

In the light load mode, when the maximum light load average output current I _{out_ave(max)} still cannot meet the requirement of the actual load current I _out , the termination unit 38 generates a light load termination signal LX. In response to the light load termination signal LX, the driving circuit 32 is immediately switched to be controlled by the up-down control circuit 31, and returns to the normal up-down voltage conversion operation. For example, the termination unit 38 is implemented by a voltage comparator for comparing the voltage feedback signal V _fb with a predetermined threshold voltage V _th . When the maximum light-load average output current I _{out_ave(max)} still cannot meet the demand of the actual load current I _out , the voltage feedback signal V _fb will gradually decrease. Therefore, a threshold voltage V _th can be properly set so that when the voltage feedback signal V _fb drops below the threshold voltage V _th , the voltage comparator of the termination unit 38 is triggered to generate the light load termination signal LX. It should be noted that the threshold voltage V _th must be set to be smaller than the sleep reference voltage V _slp minus the hysteresis voltage V _hys .

In the stage cycle consisting of the rising stage, the falling stage, and the maintaining stage according to the present invention, assuming that the valley current _Ibm is set to zero, the maximum light-load average output current _{Iout_ave(max)} that can be provided It can be calculated by the following equation (3):

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; ave</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; max</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; pk</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}{<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; pk</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

As mentioned above, no matter whether the input voltage V _in is greater than, equal to, or less than the output voltage V _out , the buck-boost voltage converter can convert the input voltage V _in into a predetermined output voltage V _out . That is, the buck-boost voltage converter can be applied to a wide range of input voltages V _in . However, the change of the input voltage V _in will affect the maximum light-load average output current I _{out_ave(max)} in the light-load mode. Specifically, considering the partial differential operation of equation (3) with respect to the input voltage V _in , the following equation (4) can be obtained:

$<span\; class="notranslate">\; (</span>\frac{<span\; class="notranslate">\; \&PartialD;</span>}{{<span\; class="notranslate">\; \&PartialD;</span>\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; ave</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; max</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; pk</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}}{{<span\; class="notranslate">\; (</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}{<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; pk</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

Comparing Equation (2) with Equation (4), it can be seen that in the light load mode according to the present invention, the rate of change of the maximum light load average output current I _{out_ave(max)} decreases due to the existence of the maintenance time T _m . In other words, the maintenance phase according to the present invention effectively achieves the effect of enhancing the stability of the maximum light-load average output current I _{out_ave(max)} . For a wide range of input voltages _Vin , the light load control circuit 33 according to the first embodiment of the present invention can stably control the startup and termination of the light load mode of the buck-boost voltage converter.

Please note that in the present invention, the maintenance time T _m is not limited to a fixed value but can also be implemented by a controllable variable value. Now assume that the hold time T _m is set proportional to the input voltage V _in , namely:

T _m =k·V _in (5)

Where k is a proportional constant, then the maximum light-load average output current _{Iout_ave(max)} according to the present invention can be calculated by the following equation (6):

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; ave</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; max</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; pk</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}}{<span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; k</span>}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; pk</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

Therefore, considering the partial differential operation of equation (6) with respect to the input voltage V _in , the following equation (7) can be obtained:

$<span\; class="notranslate">\; (</span>\frac{<span\; class="notranslate">\; \&PartialD;</span>}{{<span\; class="notranslate">\; \&PartialD;</span>\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}<span\; class="notranslate">\; \_</span>\mathrm{<span\; class="notranslate">\; ave</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; max</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; pk</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; k</span>}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; pk</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{<span\; class="notranslate">\; (</span><span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; k</span>}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; pk</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span>$

It can be known from equation (7) that when the input voltage V _in satisfies the following equation (8):

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}<span\; class="notranslate">\; =</span>\sqrt{\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; pk</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; L</span>}}{\mathrm{<span\; class="notranslate">\; k</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; )</span>$

The maximum light-load average output current I _{out_ave(max)} will not be affected by changes in the input voltage V _in . Therefore, properly selecting the proportionality constant k so that the value of equation (8) is at the middle point of the operating range of the input voltage _Vin can effectively reduce the impact of the variation of the input voltage _Vin on the maximum light-load average output current I _{out_ave(max)} impact.

FIG. 6 shows a detailed circuit diagram of the sustain time control unit 36-3 according to the first embodiment of the present invention. Referring to FIG. 6 , the sustain time control unit 36-3 may include a voltage comparator CP _m , a current source I _m , a capacitor C _m , an NMOS transistor S _m , and a buffer inverter B _m . The gate of the NMOS transistor S _m serves as the trigger terminal AT of the sustain time control unit 36 - 3 for receiving the falling termination signal FX via the buffer inverter B _m . The output terminal of the voltage comparator CP _m serves as the output terminal AO of the sustain time control unit 36-3 for providing the sustain termination signal MX. At the end of the falling phase, that is, when the inductor current I _L drops to the valley current I _bm , the falling termination signal FX changes from a low level to a high level. Therefore, the NMOS transistor S _m turns from a conducting state to a non-conducting state, so that the current source _Im begins to charge the capacitor C _m . Once the potential difference across the capacitor C _m increases linearly beyond the predetermined sustain time reference voltage V _m , the voltage comparator CP _m is triggered to make the sustain termination signal MX transition from low to high. Therefore, the length of the maintenance time T _m can be determined by the maintenance time control unit 36-3.

FIG. 7(A) shows a circuit diagram of a light load control circuit 73 according to a second embodiment of the present invention. The second embodiment is different from the first embodiment in that the sustaining time control unit 76 - 3 of the second embodiment is triggered by the rising end signal RX to start calculating the sustaining time T _m . Therefore, in the light load mode of the second embodiment, the sustain phase occurs successively after the ramp-up phase. Referring to FIG. 7(B), in the rising phase, that is, from time t1 to t2, the inductor current _IL increases linearly from the valley value I _bm to the peak value I _pk . In the maintaining phase, ie from time t2 to t3, the inductor current _IL is maintained at a nearly constant state, ie at the peak value I _pk at time t2. In the falling phase, ie from time t3 to t4, the inductor current I _L linearly decreases from the peak value I _pk to the valley value I _bm .

FIG. 8(A) shows a circuit diagram of a light load control circuit 83 according to a third embodiment of the present invention. The third embodiment is different from the first embodiment in that the hold time control unit 86 - 3 of the third embodiment has a first trigger terminal AT1 and a second trigger terminal AT2 as well as a first output terminal AO1 and a second output terminal AO2 . The first trigger terminal AT1 is triggered by the rising termination signal RX, and starts to count the first sustaining time T _m1 . After the first sustaining time T _m1 elapses, the first output terminal AO1 outputs a first sustaining end signal MX1 . Therefore, in the light load mode of the third embodiment, the first sustain phase occurs after the ramp-up phase. The second trigger terminal AT2 is triggered by the falling termination signal FX, and starts to count the second sustaining time T _m2 . After the second sustain time T _m2 elapses, the second output terminal AO2 outputs the second sustain termination signal MX2 . Therefore, in the light load mode of the third embodiment, the second sustaining phase occurs following the ramping down phase.

Referring to FIG. 8(B), in the rising phase, that is, from time t1 to t2, the inductor current _IL increases linearly from the valley value I _bm to the peak value I _pk . In the first sustaining phase, ie from time t2 to t3, the inductor current _IL is maintained at a nearly constant state, ie at the peak value I _pk at time t2. In the falling phase, ie from time t3 to t4, the inductor current I _L linearly decreases from the peak value I _pk to the valley value I _bm . In the second maintaining phase, ie from time t4 to t5, the inductor current _IL is maintained at a nearly constant state, ie at the valley value I _bm at time t4.

While the present invention has been described by way of illustration of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and similar arrangements apparent to those skilled in the art. Accordingly, the scope of the full claims shall be construed in the broadest way to encompass all such modifications and similar configurations.

Claims (15)

1. A light load control circuit for controlling a switching circuit having an input switching unit for selectively coupling a first end of an inductor to an input voltage and a ground potential; and an output switching unit for For selectively coupling the second end of the inductor to an output voltage and the ground potential, the light load control circuit includes: a stage control unit for making the switching circuit operate in a plurality of stage cycles, each of the plurality of stage cycles having: In the rising stage, the inductor current flowing through the inductor rises; Falling phase, causing the inductor current to drop; and sustain phase, so that the inductor current remains nearly constant, and A sleep control unit, configured to make the switching circuit operate during a sleep period after the output voltage reaches a predetermined sleep reference voltage, so as to prevent the first terminal and the second terminal from being coupled to the input voltage, the output voltage and the Any two of this ground potential. 2. The light load control circuit according to claim 1, wherein: the falling phase occurs after the rising phase, and The maintenance phase occurs after the descent phase. 3. The light load control circuit according to claim 1, wherein: The sustain phase occurs after the ramp phase, and The descent phase occurs after the maintenance phase. 4. The light load control circuit according to claim 1, wherein: The maintenance phase is divided into a first maintenance phase and a second maintenance phase such that: the first maintenance phase occurs after the ramp-up phase; the decline phase occurs after the first maintenance phase; and The second maintenance phase occurs after the descent phase. 5. The light load control circuit according to claim 1, wherein: The duration of the sustain phase is proportional to the input voltage. 6. The light load control circuit according to claim 1, wherein: In the rising phase, the input switching unit couples the first terminal to the input voltage, and the output switching unit couples the second terminal to the ground potential. 7. The light load control circuit according to claim 1, wherein: In the falling phase, the input switching unit couples the first terminal to the ground potential, and the output switching unit couples the second terminal to the output voltage. 8. The light load control circuit according to claim 1, wherein: In the maintaining phase, the input switching unit couples the first terminal to the ground potential, and the output switching unit couples the second terminal to the ground potential. 9. A light load control circuit for controlling a switching circuit, the switching circuit has an input switching unit for selectively coupling a first end of an inductor to an input voltage and a ground potential, and an output switching unit A unit for selectively coupling a second end of the inductor to an output voltage and the ground potential, the light load control circuit includes: A stage control unit for making the switching circuit operate in a plurality of stage cycles, each of the plurality of stage cycles has: a first stage, making a potential difference across the first terminal and the second terminal have a first polarity; a second stage of imparting a second polarity to the potential difference across the first terminal and the second terminal, the second polarity being opposite to the first polarity; and a third stage, making the potential difference across the first terminal and the second terminal substantially zero, and The sleep control unit is used to make the switching circuit operate in a sleep period after the output voltage reaches a predetermined sleep reference voltage, so as to prevent the first terminal and the second terminal from being coupled to the input voltage, the output voltage and the Any two of this ground potential. 10. The light load control circuit according to claim 9, wherein: During the sleep period, the input switching unit couples the first terminal to the input voltage, and the output switching unit keeps the second terminal in a floating state. 11. The light load control circuit according to claim 9, wherein: During the sleep period, the input switching unit couples the first terminal to the ground potential, and the output switching unit keeps the second terminal in a floating state. 12. The light load control circuit according to claim 9, wherein: During the sleep period, the input switching unit keeps the first terminal in a floating state, and the output switching unit couples the second terminal to the output voltage. 13. The light load control circuit according to claim 9, wherein: During the sleep period, the input switching unit keeps the first terminal in a floating state, and the output switching unit couples the second terminal to the ground potential. 14. The light load control circuit according to claim 9, wherein: During the sleep period, the input switching unit couples the first terminal to the ground potential, and the output switching unit couples the second terminal to the ground potential. 15. The light load control circuit according to claim 9, wherein: During the sleep period, the input switching unit keeps the first terminal in a floating state, and the output switching unit keeps the second terminal in another floating state.

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