CN1877480A - Light load control circuit of lifting voltage transducer - Google Patents

Abstract

The invention discloses a light load control circuit which makes the switching circuit of the rise-fall type voltage converter operate in plural circulation and sleep duration alternately. Each circulation phase includes a rising phase, a falling phase and a maintaining phase. During the rising phase, the operation of the switching circuit makes the inductance current rise. During the falling phase, the operation of the switching circuit makes the inductance current fall. During the maintaining phase, the operation of the switching circuit makes the inductance current nearly constant. In the sleep duration, the coupling of the two terminals of the inductance with any two of the input voltage, output voltage and the ground voltage is prevented.

Description

The underload control circuit of lift type voltage converter

Technical field

The present invention relates to a kind of DC/DC electric pressure converter, relate in particular to a kind of underload control circuit of lift type voltage converter.

Prior art

Fig. 1 has shown the circuit diagram of existing lift type voltage converter.With reference to Fig. 1, existing lift type voltage converter comprises synchronous commutation circuit 10, lift control circuit 11, driving circuit 12 and underload control circuit 13.

Lift control circuit 11 is based on output voltage V _OutFeedback, produce a voltage transitions control signal VCS.In response to voltage transitions control signal VCS, driving circuit 12 produces four drive signal D1 to D4, in order to drive switch unit S1 to S4 respectively.By means of suitably conducting and/or the not conducting of control switch unit S1 to S4, and the ratio of ON time or non-ON time, input voltage V _InCan convert output voltage V effectively to _Out, input voltage V wherein _InCan greater than, equal or less than output voltage V _OutHad the lift control circuit 11 of many kenels on prior art, for example United States Patent (USP) the 6th, 166, and No. 527 and the 6th, 788, disclosed circuit and method in No. 033 technical literature such as grade.

As load 50 needed load current I _OutHour, in order to improve voltage transitions efficient, existing lift type voltage converter can enter in the operation of light load mode.In the operation of light load mode, driving circuit 12 no longer continues the voltage transitions control signal VCS in response to lift control circuit 11, is controlled by underload control circuit 13 and change in addition.For example, Fig. 3 and 4 of the 10th page of the product description (Datasheet) of the LT3438 " MicropowerSynchronous Buck-Boost DC/DC Converter " that printed and distribute October calendar year 2001 of Linear Technology discloses the existing light load mode of lift type voltage converter.

Fig. 2 (A) is presented in the existing light load mode, inductive current I _LSequential chart.With reference to Fig. 2 (A), existing light load mode comprises ascent stage and decline stage.In ascent stage, promptly from time t1 to t2, inductive current I _LRise to predetermined peak I from zero line _PkIn the decline stage, promptly from time t2 to t3, inductive current I _LFrom peak I _PkLinearity drops to zero.

The mode of operation synoptic diagram of Fig. 2 (B) display synchronization commutation circuit 10 in ascent stage.With reference to Fig. 2 (B), all conductings and switch unit S2 and not conductings of S3 make the first end La of inductance L be coupled to input voltage V of switch unit S1 and S4 _InAnd the second end Lb is coupled to ground potential.Therefore, inductive current I _LWith (V _In/ L) linear rising of speed.

The mode of operation synoptic diagram of Fig. 2 (C) display synchronization commutation circuit 10 in the decline stage.With reference to Fig. 2 (C), not conducting and all conductings of switch unit S2 and S3 of switch unit S1 and S4 make the first end La of inductance L be coupled to ground potential and the second end Lb is coupled to output voltage V _OutTherefore, inductive current I _LWith (V _Out/ L) linear decline of speed.

In existing light load mode, the maximum average value of the load current that can provide can be calculated and be got by following equation (1):

$I_{\mathrm{out}\_\mathrm{ave}\left(\max \right)}=\left(\frac{I_{\mathrm{pk}}}{2}\right)\left(\frac{V_{\mathrm{in}}}{V_{\mathrm{in}}+V_{\mathrm{out}}}\right)---\left(1\right)$

If load current I _OutSurpass the represented maximum underload average output current I of equation (1) _{Out_ave (max)}, then existing lift type voltage converter can leave light load mode, and its operation is come back under the control of lift control circuit 11.

As previously mentioned, no matter input voltage V _InGreater than, equal or less than output voltage V _Out, lift type voltage converter all can be with input voltage V _InConvert predetermined output voltage V to _OutThat is, lift type voltage converter can be applicable to have the input voltage V of broad range _InYet, input voltage V _InVariation can have influence on the maximum underload average output current I of light load mode _{Out_ave (max)}Particularly, consider equation (1) for input voltage V _InCarry out the partial differential computing, then can obtain following equation (2):

$\left(\frac{\∂}{{\∂V}_{\mathrm{in}}}\right)I_{\mathrm{out}\_\mathrm{ave}\left(\max \right)}=\left(\frac{I_{\mathrm{pk}}}{2}\right)\left(\frac{V_{\mathrm{out}}}{{(V_{\mathrm{in}}+V_{\mathrm{out}})}^2}\right)---\left(2\right)$

Because equation (2) input voltage V _InA function, thereby for different input voltage V _In, underload control circuit 13 causes lift type voltage converter at different maximum underload average output current I _{Out_ave (max)}Under leave light load mode.

Yet desired is a kind of underload control circuit, can be for the input voltage V of broad range _In, stably control the startup and the termination of the light load mode of lift type voltage converter.

Summary of the invention

Because foregoing problems, one object of the present invention is to provide a kind of underload control circuit, can stably control the startup and the termination of the light load mode of lift type voltage converter for the input voltage of broad range.

Another object of the present invention is to provide a kind of underload control circuit, can reduce the influence property that the variation of input voltage is caused for maximum underload average output current effectively.

According to an aspect of of the present present invention, provide a kind of underload control circuit, in order to the commutation circuit of control lift type voltage converter.Commutation circuit has input switch unit and output switch unit.First end of the selectively coupled inductance of input switch unit is to input voltage and ground potential.Second end of the selectively coupled inductance of output switch unit is to output voltage and ground potential.

The underload control circuit has stage control module and sleep control module.The stage control module makes commutation circuit operate in a plurality of step cycle.Each step cycle has ascent stage, decline stage and maintenance stage.In ascent stage, commutation circuit system is operable to the inductive current that makes this inductance of flowing through and rises.Perhaps, commutation circuit system is operable to make across first end of inductance and the potential difference (PD) between second end and has first polarity.In the decline stage, commutation circuit system is operable to inductive current is descended.Perhaps, commutation circuit system is operable to make across first end of inductance and the potential difference (PD) between second end and has second polarity.Second polarity system is in contrast to first polarity.In the maintenance stage, commutation circuit system is operable to that inductive current is kept is almost fixing.Perhaps, commutation circuit system is operable to first end and the potential difference (PD) between second end that make across inductance and is essentially zero.

After this output voltage reaches predetermined sleep reference voltage, first end that the sleep control module operates in commutation circuit to prevent inductance between sleep period and second end be coupled in respectively input voltage, output voltage, with ground potential in times both.In between sleep period, the supply of load current system reaches by the discharge of output capacitance separately.

The operation of the maintenance stage that is provided by the underload control circuit, maximum underload average output current is by the caused rate of change of output voltage thereby be suppressed.So, for the input voltage of broad range, can stably control the startup and the termination of the light load mode of lift type voltage converter according to underload control circuit of the present invention.

Description of drawings

Fig. 1 shows the circuit diagram of existing lift type voltage converter;

Fig. 2 (A) is presented at the sequential chart of inductive current in the existing light load mode;

The mode of operation synoptic diagram of Fig. 2 (B) display synchronization commutation circuit in ascent stage;

The mode of operation synoptic diagram of Fig. 2 (C) display synchronization commutation circuit in the decline stage;

Fig. 3 shows the circuit diagram according to the lift type voltage converter of first embodiment of the invention;

Fig. 4 is presented at the sequential chart according to feedback voltage signal and inductive current in the light load mode of first embodiment of the invention;

The mode of operation synoptic diagram of Fig. 5 (A) display synchronization commutation circuit in ascent stage;

The mode of operation synoptic diagram of Fig. 5 (B) display synchronization commutation circuit in the decline stage;

The mode of operation synoptic diagram of Fig. 5 (C) display synchronization commutation circuit in the maintenance stage;

The synoptic diagram of the six kind modes of operation of Fig. 5 (D) display synchronization commutation circuit between sleep period;

Fig. 6 shows the detailed circuit diagram according to the control module of holding time of first embodiment of the invention;

Fig. 7 (A) shows the circuit diagram according to the underload control circuit of second embodiment of the invention;

Fig. 7 (B) is presented at the sequential chart according to inductive current in the light load mode of second embodiment of the invention;

Fig. 8 (A) shows the circuit diagram according to the underload control circuit of third embodiment of the invention; And

Fig. 8 (B) is presented at the sequential chart according to inductive current in the light load mode of third embodiment of the invention.

The main element symbol description

10,30 synchronous commutation circuit 11,31 lift control circuits

12,32 driving circuits, 13,33,73,83 underload control circuits

34 voltage feedback circuits, 35 start units

36,76,86 stage control module 36-1, the 36-2 current comparator

36-3,76-3, the 86-3 control module of holding time

50 loads of 37 sleep control modules

AT, AT1, AT2 trigger end AO, AO1, AO2 output terminal

B _mBuffer inverter C _OutOutput capacitance

C _mCapacitor C P _mVoltage comparator

D1～D4 drive signal L inductance

La, the two ends I of La inductance _LInductive current

I _OutLoad current I _PkPeak point current

I _BmValley point current I _ThCritical current

I _mCharging current S1～S4 switch unit

S _mNmos pass transistor T _mHold time

V _InInput voltage V _OutOutput voltage

V _FbVoltage feedback signal V _ThCritical voltage

V _mReference voltage V holds time _SlpThe sleep reference voltage

V _HysHysteresis voltage VCS voltage transitions control signal

LM underload enabling signal LX underload termination signal

RX rising termination signal FX decline termination signal

MX, MX1, MX2 keeps termination signal

The SLP sleep signal

Embodiment

Explanation hereinafter and accompanying drawing will make aforementioned and other purposes of the present invention, feature, more obvious with advantage.Now with reference to the preferred embodiment of the present invention of graphic detailed description foundation.

Fig. 3 shows the circuit diagram according to the lift type voltage converter of first embodiment of the invention.Lift type voltage converter system is in order to conversion input voltage V _InBecome output voltage V _Out, input voltage V wherein _InCan greater than, equal or less than output voltage V _OutWith reference to Fig. 3, lift type voltage converter comprises synchronous commutation circuit 30, lift control circuit 31, driving circuit 32, underload control circuit 33 and voltage feedback circuit 34.

Commutation circuit 30 has input switch unit and output switch unit synchronously.Particularly, the input switch unit is made of the first switch unit S1 and the second switch unit S2, and the output switch unit is made of the 3rd switch unit S3 and the 4th switch unit S4.The first switch unit S1 is arranged at input voltage V _InAnd between the first end La of inductance L.The second switch unit S2 is arranged between the first end La and ground potential of inductance L.The 3rd switch unit S3 is arranged at second end Lb and the output voltage V of inductance L _OutBetween.The 4th switch unit S4 is arranged between the second end Lb and ground potential of inductance L.

Voltage feedback circuit 34 is coupled in synchronous commutation circuit 30, in order to produce a voltage feedback signal V _Fb, to represent output voltage V _OutFor example, voltage feedback circuit 34 is implemented by the voltage divider that a plurality of resistance in series constituted.

In response to voltage feedback signal V _Fb, lift control circuit 31 produces voltage transitions control signal VCS, in order to conducting or the not conducting of the switch unit S1 to S4 that determines synchronous commutation circuit 30, and ON time and non-ON time.Voltage transitions control signal VCS comprises a plurality of independently of one another or subsignals that are mutually related, in order to control switch unit S1 to S4 respectively.Voltage transitions control signal VCS specifically forms four drive signal D1 to D4 via driving circuit 32, in order to drive switch unit S1 to S4 respectively.By means of suitably conducting and/or the not conducting of control switch unit S1 to S4, and the ratio of ON time and non-ON time, input voltage V _InCan convert output voltage V effectively to _OutNo matter, input voltage V _InGreater than, equal or less than output voltage V _OutOwing to lift control circuit 31 has been that one of ordinary skill in the art institute is known, so locate to repeat no more.Please note that the present invention relates generally to underload control circuit 33, and can be applicable to all known at present or may develop in the future lift type voltage converters according to underload control circuit 33 of the present invention, but not only be limited to the specific lift control circuit 31 of minority.

As load 50 needed load current I _OutHour, in order to improve voltage transitions efficient, can enter in the operation of light load mode according to lift type voltage converter of the present invention.In the operation of light load mode, driving circuit 32 no longer continues the voltage transitions control signal VCS that produced in response to lift control circuit 31, is controlled by underload control circuit 33 and change in addition.Particularly, underload control circuit 33 comprises start unit 35, stage control module 36, sleep control module 37 and stops unit 38.

Start unit 35 is in order to detect inductive current I _LAnd in inductive current I _LBe lower than a predetermined critical current I _ThIn time, triggered and produced a underload enabling signal LM.In response to underload enabling signal LM, driving circuit 32 changes immediately by underload control circuit 33 and is controlled, so that have the light load mode operation of greater efficiency.For example, start unit 35 can be implemented by a current comparator, in order to compare inductive current I _LWith critical current I _Th, make as inductive current I _LThe subcritical electric current I _ThThe time, current comparator is triggered and is produced underload enabling signal LM.

Stage control module 36 usefulness are so that synchronous commutation circuit 30 operates in a plurality of step cycle, and wherein each step cycle has ascent stage, decline stage and maintenance stage.As shown in Figure 4, in ascent stage, that is from time t1 to t2, inductive current I _LFrom predetermined valley I _BmLinearity rises to predetermined peak I _PkIn the decline stage, promptly from time t2 to t3, inductive current I _LFrom peak I _PkLinearity drops to valley I _BmIn the maintenance stage, promptly from time t3 to t4, inductive current I _LBe maintained at almost fixing state, that is be maintained at the valley I of time t3 _Bm

Stage control module 36 is provided with current comparator 36-1, in order to compare inductive current I _LWith predetermined peak point current I _PkAs inductive current I _LThe linear rising reaches peak point current I _PkThe time, current comparator 36-1 is triggered and is produced rising termination signal RX, makes driving circuit 32 stop the ascent stage operation of synchronous commutation circuit 30.

Stage control module 36 also is provided with another current comparator 36-2, in order to compare inductive current I _LWith predetermined valley point current I _BmAs inductive current I _LLinear decline reaches valley point current I _BmThe time, current comparator 36-2 is triggered and is produced decline termination signal FX, makes driving circuit 32 stop the decline stage operation of synchronous commutation circuit 30.For example, valley point current I _BmCan be set at zero.

Stage control module 36 also is provided with the control module 36-3 that holds time, in order to the decision shared T that holds time of maintenance stage _mLength.The control module 36-3 that holds time has trigger end AT and output terminals A O.When trigger end AT received decline termination signal FX, the control module 36-3 that holds time started the clock.In case through the predetermined T that holds time _mAfterwards, the output terminals A O of the control module 36-3 that holds time produces and keeps termination signal MX, makes driving circuit 32 stop the maintenance stage operation of synchronous commutation circuit 30.

Shown in Fig. 5 (A), in ascent stage, all conductings and switch unit S2 and not conductings of S3 make the first end La of inductance L be coupled to input voltage V of switch unit S1 and S4 _InAnd the second end Lb is coupled to ground potential.Therefore, inductive current I _LWith (V _In/ L) linear rising of speed.

Shown in Fig. 5 (B), in the decline stage, not conducting and all conductings of switch unit S2 and S3 of switch unit S1 and S4 make the first end La of inductance L be coupled to ground potential and the second end Lb is coupled to output voltage V _OutTherefore, inductive current I _LWith (V _Out/ L) linear decline of speed.

Shown in Fig. 5 (C), in the maintenance stage, not conductings and all conductings of switch unit S2 and S4 make the first end La of inductance L and the second end Lb all be coupled to ground potential of switch unit S1 and S3.Because first end La of inductance L and the potential difference (PD) between the second end Lb are zero, so inductive current I _LFreely flow in the loop and be maintained at almost fixing state (if slightly resistance coefficient of being had of inductance L and switch unit S2 and S4).

Refer back to Fig. 3 and 4, in the operation of aforementioned a plurality of step cycle, as voltage feedback signal V _FbReach predetermined sleep reference voltage V _SlpThe time, sleep control module 37 is triggered and produces sleep signal SLP.In response to sleep signal SLP, driving circuit 32 operates in commutation circuit and prevents between sleep period that the first end La of inductance L and the second end Lb are coupled in input voltage V respectively _In, output voltage V _Out, with ground potential in any two.

For example, shown in Fig. 5 (D), synchronously commutation circuit 30 can be between sleep period six kinds of modes of operation wherein any.With regard to example 1, the first switch unit S1 conducting and second to the 4th not conductings of switch unit S2 to S4 make the first end La of inductance L be coupled to input voltage V _In, and the second end Lb of inductance L is in floating state.With regard to example 2, the second switch unit S2 conducting and first, the 3rd, with the 4th switch unit S1, S3, with not conductings of S4, make the first end La of inductance L be coupled to ground potential, and the second end Lb of inductance L is in floating state.With regard to example 3, the 3rd switch unit S3 conducting and first, second, with the 4th switch unit S1, S2, with not conductings of S4, make the first end La of inductance L be in floating state, and the second end Lb of inductance L is coupled to output voltage V _OutWith regard to example 4, the 4th switch unit S4 conducting and first to the 3rd not conductings of switch unit S1 to S3 make the first end La of inductance L be in floating state, and the second end Lb of inductance L is coupled to ground potential.With regard to example 5, all conductings and the first and the 3rd switch unit S1 and not conductings of S3 make the first end La of inductance L and the second end Lb all be coupled to ground potential of the second and the 4th switch unit S2 and S4.With regard to example 6, first to fourth not conductings of switch unit S1 to S4 make the first end La of inductance L and the second end Lb all be in floating state.

In between sleep period, load current I _OutSupply separately by means of output capacitance C _OutDischarge and realize.Because the required load current I of light load mode _OutMinimum, so output capacitance C _OutDischarge can not cause output voltage V _OutAcute variation takes place.For example, sleep control module 37 must be implemented by a voltage comparator with hysteresis effect.Between sleep period, begin to carry out (for example time t5 of Fig. 4) afterwards, in case voltage feedback signal V _FbBecause of output capacitance C _OutDischarge and from sleep reference voltage V _SlpA hysteresis voltage V who is scheduled to has descended _Hys(for example time t6 of Fig. 4) then stops reverting between sleep period the step cycle of being controlled by stage control module 36.

In light load mode, as maximum underload average output current I _{Out_ave (max)}Still can't satisfy the actual loading electric current I _OutDemand the time, stop unit 38 and produce underload termination signal LX.In response to underload termination signal LX, driving circuit 32 changes immediately by lift control circuit 31 and is controlled, and returns to general lift voltage transitions operation.For example, stopping unit 38 must be implemented by a voltage comparator, in order to comparative voltage feedback signal V _FbWith a predetermined critical voltage V _ThAs maximum underload average output current I _{Out_ave (max)}Still can't satisfy the actual loading electric current I _OutDemand the time, voltage feedback signal V _FbCan descend gradually.Therefore, can suitably set a critical voltage V _Th, make as voltage feedback signal V _FbDrop to subcritical voltage V _ThThe time, the voltage comparator that stops unit 38 is triggered and is produced underload termination signal LX.Should note this critical voltage V _ThMust set for less than sleep reference voltage V _SlpDeduct hysteresis voltage V _HysPoor.

According to of the present invention by ascent stage, step cycle that decline stage and maintenance stage constituted in, suppose valley point current I _BmSystem is set at zero, the maximum underload average output current I that then can provide _{Out_ave (max)}Can calculate and get by following equation (3):

$I_{\mathrm{out}\_\mathrm{ave}\left(\max \right)}=\left(\frac{I_{\mathrm{pk}}}{2}\right)\left(\frac{V_{\mathrm{in}}}{(1+\frac{T_m{\·V}_{\mathrm{out}}}{I_{\mathrm{pk}}\·L})V_{\mathrm{in}}+V_{\mathrm{out}}}\right)---\left(3\right)$

As previously mentioned, no matter input voltage V _InSystem greater than, equal or less than output voltage V _Out, lift type voltage converter all can be with input voltage V _InConvert a predetermined output voltage V to _OutThat is, lift type voltage converter can be applicable to have the input voltage V of broad range _InYet, input voltage V _InVariation can have influence on the maximum underload average output current I of light load mode _{Out_ave (max)}Particularly, consider equation (3) for input voltage V _InCarry out the partial differential computing, then can obtain following equation (4):

$\left(\frac{\∂}{{\∂V}_{\mathrm{in}}}\right)I_{\mathrm{out}\_\mathrm{ave}\left(\max \right)}=\left(\frac{I_{\mathrm{pk}}}{2}\right)\left(\frac{V_{\mathrm{out}}}{{((1+\frac{T_m{\·V}_{\mathrm{out}}}{I_{\mathrm{pk}}\·L})V_{\mathrm{in}}+V_{\mathrm{out}})}^2}\right)---\left(4\right)$

Compare equation (2) and equation (4) as can be known, in foundation light load mode of the present invention, maximum underload average output current I _{Out_ave (max)}Rate of change because of the T that holds time _mExistence and descend.In other words, reach the maximum underload average output current I of enhancing effectively according to the maintenance stage of the present invention _{Out_ave (max)}The effect of stability.Input voltage V for broad range _In, can stably control the startup and the termination of the light load mode of lift type voltage converter according to the underload control circuit 33 of first embodiment of the invention.

Please note that in the present invention T holds time _mBe not limited to fixed value and also must be implemented by a controllable changing value.Suppose to hold time T now _mSet for and be proportional to input voltage V _In, that is:

T _m＝k·V _in (5)

Wherein k is a proportionality constant, then according to maximum underload average output current I of the present invention _{Out_ave (max)}Can calculate and get by following equation (6):

$I_{\mathrm{out}\_\mathrm{ave}\left(\max \right)}=\left(\frac{I_{\mathrm{pk}}}{2}\right)\left(\frac{V_{\mathrm{in}}}{\left(\frac{V_{\mathrm{out}}\·k}{I_{\mathrm{pk}}\·L}\right)V_{\mathrm{in}}^2+V_{\mathrm{in}}+V_{\mathrm{out}}}\right)---\left(6\right)$

Therefore, consider equation (6) for input voltage V _InCarry out the partial differential computing, then can obtain following equation (7):

$\left(\frac{\∂}{{\∂V}_{\mathrm{in}}}\right)I_{\mathrm{out}\_\mathrm{ave}\left(\max \right)}=\left(\frac{I_{\mathrm{pk}}}{2}\right)\left(\frac{V_{\mathrm{out}}-\left(\frac{V_{\mathrm{out}}\·k}{I_{\mathrm{pk}}\·L}\right)V_{\mathrm{in}}^2}{{(\left(\frac{V_{\mathrm{out}}\·k}{I_{\mathrm{pk}}\·L}\right)V_{\mathrm{in}}^2+V_{\mathrm{in}}+V_{\mathrm{out}})}^2}\right)---\left(7\right)$

By equation (7) as can be known, as input voltage V _InWhen satisfying following equation (8):

$V_{\mathrm{in}}=\sqrt{\frac{I_{\mathrm{pk}}\·L}{k}}---\left(8\right)$

Maximum underload average output current I _{Out_ave (max)}To not be subjected to input voltage V _InThe influence of change.Therefore, suitably the selection percentage constant k makes the value of equation (8) be positioned at input voltage V _InThe intermediate point of opereating specification, then can effectively reduce input voltage V _InChange for maximum underload average output current I _{Out_ave (max)}The influence that is caused.

Fig. 6 shows the detailed circuit diagram according to the control module 36-3 that holds time of first embodiment of the invention.With reference to Fig. 6, the control module 36-3 that holds time can comprise voltage comparator CP _m, current source I _m, capacitor C _m, nmos pass transistor S _m, and buffer inverter B _mNmos pass transistor S _mGrid as holding time the trigger end AT of control module 36-3, in order to via buffer inverter B _mAnd reception decline termination signal FX.Voltage comparator CP _mOutput terminal as holding time the output terminals A O of control module 36-3, keep termination signal MX in order to provide.When the decline stage finishes, that is inductive current I _LDrop to valley point current I _BmThe time, decline termination signal FX becomes high level from the low level transition.Therefore, nmos pass transistor S _mBe transformed into not on-state from conducting state, make current source I _mBeginning is for capacitor C _mCharging.In case across capacitor C _mThe potential difference (PD) linearity at two ends is increased to and exceeds the predetermined reference voltage V that holds time _m, voltage comparator CP _mBe triggered and make and keep termination signal MX and become high level from the low level transition.Therefore, the T that holds time _mLength can be determined by the control module 36-3 that holds time.

Fig. 7 (A) shows the circuit diagram according to the underload control circuit 73 of second embodiment of the invention.Second embodiment is different from being in the control module 76-3 that holds time of second embodiment of first embodiment to be triggered by rising termination signal RX and begins to calculate and keep time T _mTherefore, in the light load mode of second embodiment, system continued and took place after ascent stage the maintenance stage.Shown in Fig. 7 (B), in ascent stage, promptly from time t1 to t2, inductive current I _LFrom valley I _BmLinearity rises to peak I _PkIn the maintenance stage, promptly from time t2 to t3, inductive current I _LBe maintained at almost fixing state, promptly be maintained at the peak I of time t2 _PkIn the decline stage, that is from time t3 to t4, inductive current I _LFrom peak I _PkLinearity drops to valley I _Bm

Fig. 8 (A) shows the circuit diagram according to the underload control circuit 83 of third embodiment of the invention.The 3rd embodiment is different from being in the control module 86-3 that holds time of the 3rd embodiment of first embodiment and has the first trigger end AT1 and the second trigger end AT2 and the first output terminals A O1 and the second output terminals A O2.The first trigger end AT1 is triggered by rising termination signal RX, and begins to calculate first T that holds time _M1Through first T that holds time _M1Afterwards, termination signal MX1 is kept in first output terminals A O1 output first.Therefore, in the light load mode of the 3rd embodiment, system continued and took place after ascent stage first maintenance stage.Second trigger end AT2 system is triggered by decline termination signal FX, and begins to calculate second T that holds time _M2Through second T that holds time _M2Afterwards, termination signal MX2 is kept in second output terminals A O2 output second.Therefore, in the light load mode of the 3rd embodiment, system continued and took place after the decline stage second maintenance stage.

With reference to Fig. 8 (B), in ascent stage, promptly from time t1 to t2, inductive current I _LFrom valley I _BmLinearity rises to peak I _PkIn first maintenance stage, promptly from time t2 to t3, inductive current I _LBe maintained at almost fixing state, promptly be maintained at the peak I of time t2 _PkIn the decline stage, promptly from time t3 to t4, inductive current I _LFrom peak I _PkLinearity drops to valley I _BmIn second maintenance stage, promptly from time t4 to t5, inductive current I _LBe maintained at almost fixing state, promptly be maintained at the valley I of time t4 _Bm

Though the present invention is illustrated as illustration by preferred embodiment, be appreciated that to the invention is not restricted to this disclosed embodiment.On the contrary, this invention is intended to contain tangible various modifications and similar configuration for those skilled in the art.Therefore, the scope that requires should be according to the widest annotation with all strength, and this type of is revised and similar configuration to contain all.

Claims (15)

1, a kind of underload control circuit is used to control one and switches circuit, and this commutation circuit has the input switch unit, is used for optionally first end to an input voltage and a ground potential of coupling inductance; And the output switch unit, second end to an output voltage of this inductance that is used for optionally being coupled and this ground potential, this underload control circuit comprises:

The stage control module is used to make this commutation circuit to operate in a plurality of step cycle, and each of these a plurality of step cycle has:

Ascent stage rises the inductive current of this inductance of flowing through;

Decline stage, this inductive current is descended; And

Maintenance stage, it is almost fixing that this inductive current is kept, and

The sleep control module, be used for after this output voltage reaches a sleep reference voltage of being scheduled to, this commutation circuit being operated between a sleep period preventing that this first end and this second end are coupled in any two in this input voltage, this output voltage and this ground potential respectively.

2, according to the underload control circuit of claim 1, wherein:

This decline stage betides after this ascent stage, and

This maintenance stage betided after this decline stage.

3, according to the underload control circuit of claim 1, wherein:

This maintenance stage betides after this ascent stage, and

This decline stage betided after this maintenance stage.

4, according to the underload control circuit of claim 1, wherein:

This maintenance stage is divided into one first maintenance stage and one second maintenance stage, makes:

This first maintenance stage betides after this ascent stage;

This decline stage betided after this first maintenance stage; And

This second maintenance stage betided after this decline stage.

5, according to the underload control circuit of claim 1, wherein:

The shared time of this maintenance stage is proportional to this input voltage.

6, according to the underload control circuit of claim 1, wherein:

In this ascent stage, this input switch unit makes this first end be coupled to this input voltage, and this output switch unit makes this second end be coupled to this ground potential.

7, according to the underload control circuit of claim 1, wherein:

In this decline stage, this input switch unit makes this first end be coupled to this ground potential, and this output switch unit makes this second end be coupled to this output voltage.

8, according to the underload control circuit of claim 1, wherein:

In this maintenance stage, this input switch unit makes this first end be coupled to this ground potential, and this output switch unit makes this second end be coupled to this ground potential.

9, a kind of underload control circuit, switch circuit in order to control one, this commutation circuit has an input switch unit, one first end to an input voltage and a ground potential in order to a selectively coupled inductance, and one output switch unit, in order to one second end to an output voltage and this ground potential of selectively coupled this inductance, this underload control circuit comprises:

One stage control module, with so that this commutation circuit operates in a plurality of step cycle, each of these a plurality of step cycle has:

Phase one, make across the potential difference (PD) between this first end and this second end to have one first polarity;

Subordinate phase makes across this potential difference (PD) between this first end and this second end to have one second polarity, and this second polarity system is in contrast to this first polarity; And

Phase III makes across this potential difference (PD) between this first end and this second end and is essentially zero, and

The sleep control module, in order to reach at this output voltage after the predetermined sleep reference voltage, this commutation circuit is operated between a sleep period prevent that this first end and this second end are coupled in any two in this input voltage, this output voltage and this ground potential respectively.

10, according to the underload control circuit of claim 9, wherein:

In between this sleep period, this input switch unit makes this first end be coupled to this input voltage, and this output switch unit makes this second end be in a floating state.

11, according to the underload control circuit of claim 9, wherein:

In between this sleep period, this input switch unit makes this first end be coupled to this ground potential, and this output switch unit makes this second end be in a floating state.

12, according to the underload control circuit of claim 9, wherein:

In between this sleep period, this input switch unit makes this first end be in a floating state, and this output switch unit makes this second end be coupled to this output voltage.

13, according to the underload control circuit of claim 9, wherein:

In between this sleep period, this input switch unit makes this first end be in a floating state, and this output switch unit makes this second end be coupled to this ground potential.

14, according to the underload control circuit of claim 9, wherein:

In between this sleep period, this input switch unit makes this first end be coupled to this ground potential, and this output switch unit makes this second end be coupled to this ground potential.

15, according to the underload control circuit of claim 9, wherein:

In between this sleep period, this input switch unit makes this first end be in a floating state, and this output switch unit makes this second end be in another floating state.

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