CN1869793A - Method for forming thin film transistor in liquid crystal display - Google Patents
Method for forming thin film transistor in liquid crystal display Download PDFInfo
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- CN1869793A CN1869793A CN 200510072851 CN200510072851A CN1869793A CN 1869793 A CN1869793 A CN 1869793A CN 200510072851 CN200510072851 CN 200510072851 CN 200510072851 A CN200510072851 A CN 200510072851A CN 1869793 A CN1869793 A CN 1869793A
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Abstract
A method for preparing film transistor in liquid crystal display includes forming a buffer layer and a polysilicon layer in sequence on transparent then utilizing substrate plasma processing mode to form grid insulation layer on surface of polysilicon layer at temperature of 300-600 deg.c, finally forming a grid layer on grid insulation layer and forming source electrode and drain electrode at two sides of grid layer.
Description
Technical field
The present invention relates to a kind of method that forms thin film transistor (TFT) in LCD, particularly relates to a kind of method that forms the high-breakdown-voltage gate insulator in Thin Film Transistor-LCD.
Prior art
At present, in the driving element in LCD, generally can use thin film transistor (TFT), make that the quality of display is preferable because thin film transistor (TFT) has swift characteristic.At present, the structure of thin film transistor (TFT) has two kinds of bottom grid and top grids.In Fig. 1, introduce a kind of structural representation of thin film transistor (TFT) in each step that forms top grid.
Among Figure 1A, deposition one deck cushion 102 and one deck amorphous silicon layer 104 on glass substrate 100, wherein the material of cushion 102 can be selected monox or silicon nitride.Then, shown in Figure 1B, via quasi-molecule laser annealing (Excimer Laser Annealing; Or continuous crystallisation silicon (Continuous Grain Silicon ELA); CGS), side solidifies (Sequential Lateral Solidification continuously; SLS), metal induced crystallization (MetalInduced Crystallization; MIC), perhaps metal induced side crystallization (Metal InducedLateral Crystallization; MILC) etc. mode forms polysilicon layers 106 with amorphous silicon layer 104.Afterwards, in Fig. 1 C, use plasma gain chemical vapor deposition (PECVD) method or low-pressure chemical vapor deposition (LPCVD) mode that grid oxic horizon 108 is deposited on the polysilicon layer 106.The mode of deposition is used silicomethane and N
2O or O
2Reaction forms monox or uses silicon ethyl methane (TEOS) to resolve into monox.Then, shown in Fig. 1 D, on grid oxic horizon 108, form gate metal layer 110.The mode that forms comprises layer metal deposition on grid oxic horizon, use then photolithography and etched mode with the design transfer of grid to metal level.In Fig. 1 E, in polysilicon layer 106, form lightly mixed drain area 112 in the mode of ion implantation apparatus (ion implanter) or ion shower (ion shower), be in the both sides of gate metal layer 110.Afterwards, shown in Fig. 1 F, on the sidewall of grid layer 110, form clearance wall 114.Then, in Fig. 1 G, the mode of injecting with ion forms source electrode and drain region 116 in polysilicon layer 106, be in the both sides of gate metal layer 110.
Because tradition is used chemical vapour deposition technique, no matter be plasma gain chemical vapor deposition or low-pressure chemical vapor deposition, the gate oxidation that is deposited (gate oxide) layer, its voltage breakdown (breakdown voltage) is smaller usually and boundary defect (interface defect) meeting polysilicon and oxide layer is many, be easy to generate leakage current.The quality of such grid oxic horizon can't reach its demand for dwindling with integrated of following element.Therefore, in order to improve the quality of grid oxic horizon, need to solve voltage breakdown and cross problem low and leakage current; Also promptly increase its voltage breakdown and reduce grid oxic horizon and polysilicon boundary defect.
Summary of the invention
In view of the problems that grid oxic horizon was produced and the shortcoming that form with chemical vapour deposition technique traditionally in the foregoing invention background, the main purpose of the present invention is to provide a kind of mode of plasma treatment of utilizing to form gate insulator.Mainly be to utilize essential polysilicon (intrinsic polysilicon) that has formed and the plasma that comprises oxygen or nitrogen to react down at temperature 300-600 ℃ to form monox, silicon nitride or silicon oxynitride etc. are as the dielectric material of gate insulator.
Another object of the present invention is to make to utilize the formed gate insulator tool of plasma treatment by high voltage breakdown.
Another purpose of the present invention is to make to utilize the formed gate insulator of plasma treatment to have lower boundary defect, thereby has lower leakage current.
A further object of the present invention is to use different reacting gas, can select the material of the gate insulator of needs growth in the process of plasma treatment.
According to above-described purpose, the invention provides a kind of method that in LCD, forms a thin film transistor (TFT), its step is included in and forms one deck cushion and one deck polysilicon layer on the transparency carrier in regular turn.Afterwards, on this polysilicon layer surface with the plasma treatment polysilicon layer to form one deck gate insulator.Then, on above-mentioned gate insulator, form one deck grid layer.Then, in above-mentioned polysilicon layer, form a source electrode and a drain region, be in the both sides of above-mentioned grid layer.
The present invention also provides a kind of method that forms the high-breakdown-voltage gate insulator in Thin Film Transistor-LCD, and its step is included in and forms one deck polysilicon layer on the transparency carrier.Afterwards, between 300-600 ℃ with the above-mentioned polysilicon layer of plasma treatment to form one deck gate insulator, wherein form isoionic reacting gas and can comprise oxygen or nitrogen, and above-mentioned gate insulator can be a monox, silicon nitride, perhaps silicon oxynitride.
Brief description of drawings
Fig. 1 shows a kind of structural representation of thin film transistor (TFT) in each step that forms top grid in a conventional manner;
Fig. 2 shows a kind of structural representation of thin film transistor (TFT) in each step that forms top grid with method of the present invention; And
Fig. 3 shows the structural representation that forms the equipment of gate insulator with plasma treatment.
Implementation method
Some embodiments of the present invention can be described in detail as follows.Yet except the embodiment that describes in detail, the present invention can also implement widely in other embodiments, and scope of the present invention do not limited, its with after claims be as the criterion.
Moreover for clearer explanation being provided and being more readily understood the present invention, the each several part shown in the figure is not drawn according to its relative size, and some size is compared with other relative dimensions by exaggerative; Incoherent detail section is not drawn fully yet, in the hope of illustrated succinct.
The present invention utilizes essential polysilicon and the plasma that comprises gases such as oxygen or nitrogen, temperature 300-600 ℃ of reaction down, forms gate insulator then.If reacting gas is mainly based on oxygen, then gate insulator is a monox.If reacting gas is based on nitrogen, then gate insulator is a silicon nitride.If reacting gas comprises oxygen and nitrogen, then gate insulator can be a silicon oxynitride.Because by the formed gate insulator of essential polysilicon, can become finer and close through after the pyroprocessing, therefore also just can obtain higher voltage breakdown.And the interfacial characteristics between gate insulator and the polysilicon is also preferable, so leakage current also can reduce.Moreover, transparency carrier is placed on the rotatable platform (Table), can increase the homogeneity of the film thickness of gate insulator layer film.
The invention provides a kind of method that in LCD, forms a thin film transistor (TFT), its step is included in and forms one deck cushion and one deck polysilicon layer on the transparency carrier in regular turn, and transparency carrier wherein can be glass substrate or other high molecular polymer.The generation type of above-mentioned polysilicon layer can be elder generation's deposited amorphous silicon layer on above-mentioned cushion, and the mode with annealing converts amorphous silicon layer to polysilicon layer then.The mode of above-mentioned annealing can be a quasi-molecule laser annealing.Yet, also there is other mode directly to form polysilicon layer, continuous crystallisation silicon for example, side solidifies continuously, the metal induced crystallization, the crystallization of metal induced side (, perhaps solid phase crystallization (Solid Phase Crystallization; SPC).Afterwards, on this polysilicon layer surface with the plasma treatment polysilicon layer to form one deck gate insulator.Then, on above-mentioned gate insulator, form one deck grid layer.In polysilicon layer, form the lightly doped drain zone, be in the grid layer both sides, and on the grid layer sidewall, form clearance wall.Then, in above-mentioned polysilicon layer, form a source electrode and a drain region, be in described grid layer both sides.
Wherein plasma treatment step is between temperature 300-600 ℃, can comprise oxygen or nitrogen and become above-mentioned isoionic reacting gas, for example O
2, N
2, H
2O, NH
3, N
2O.When reacting gas is mainly oxygen, O for example
2, N
2O or H
2O, above-mentioned gate insulator are monox.When reacting gas is mainly nitrogen, N for example
2O, N
2Or NH
3, above-mentioned gate insulator is a silicon nitride.When reacting gas comprises oxygen and nitrogen, O for example
2, N
2, H
2O, N
2O is with NH
3, above-mentioned gate insulator can be a silicon oxynitride.
The present invention provides a kind of method that forms the high-breakdown-voltage gate insulator in Thin Film Transistor-LCD simultaneously, and its step is included in and forms one deck polysilicon layer on the transparency carrier.Afterwards, between 300-600 ℃ with the above-mentioned polysilicon layer of plasma treatment to form one deck gate insulator, wherein form isoionic reacting gas and can comprise that oxygen or nitrogen or both comprise, hydrogen oxide for example, oxygen, perhaps nitrogen oxide.Above-mentioned gate insulator can be a monox, silicon nitride, nitrogen, or silicon oxynitride.
Preferred temperature is between 450-550 ℃ in above-mentioned plasma treatment step.Above-mentioned transparency carrier can rotation in plasma treatment step.Before plasma treatment step, can introduce the inert gas cleaning and remove the natural oxidizing layer on polysilicon layer surface.
Preferred implementation of the present invention will be described in detail with reference to the structural representation of each shown step of Fig. 2.
Shown in Fig. 2 A, on a transparency carrier 200, form one deck cushion 202.The material of transparency carrier 200 can use glass substrate, acryl, or high molecular polymer such as clear plastic.Cushion 202 can use monox or silicon nitride.The material that the material of cushion 202 can mainly select the grating constant with silicon crystal lattice to be complementary, and need to consider the permeability of light, the simple and easy and acceptance rate of technology etc.Generally speaking, monox is a good material, because the deposition of existing monox, for example plasma gain chemical vapour deposition technique or Low Pressure Chemical Vapor Deposition all are very ripe technology.Moreover cushion 202 can also prevent that the metallic ion of transparency carrier 200 from entering into amorphous silicon layer, causes the generation of element leakage current.In one embodiment, the thickness of cushion 202 is about the 1000-4000 dust.
Present embodiment is to form polysilicon as an illustration via the mode of annealing then to form amorphous silicon earlier for the mode that forms polysilicon.Yet can directly form polysilicon layer, the mode of its formation has continuous crystallisation silicon, and side solidifies continuously, metal induced crystallization, the crystallization of metal induced side, or solid phase crystallization.
Then, on cushion, form one deck amorphous silicon layer 204.The generation type of amorphous silicon layer 204 can be used the plasma gain chemical vapour deposition technique or the Low Pressure Chemical Vapor Deposition of present maturation.A kind of mode is to use hydrogen to remove to decompose silicomethane as the precursor of silicon, perhaps silicon ethane.With plasma gain chemical vapour deposition technique is example, and the temperature of technology is about 200-600 ℃, and the pressure of reaction chamber is about 0.1-2000mtorr, and the flow of hydrogen is about 20-1000SCCM and the flow of silicomethane is about 50-1000SCCM.The thickness of the amorphous silicon layer 104 of deposition is about the 50-500 dust.
Shown in Fig. 2 B, amorphous silicon layer 104 annealing are formed polysilicon layer 106.The characteristic of semiconductor of polysilicon layer 106 is better than amorphous silicon, therefore need convert amorphous silicon to polysilicon.The simplest conversion regime is the mode of annealing that directly heats up, but must consider the temperature that transparency carrier 200 can bear.In the present invention, the mode of preferred annealing can be the quasi-molecule laser annealing mode.
Then, shown in Fig. 2 C, between 300-600 ℃, handle the surface of polysilicon layer 206 to form gate insulator 208 with plasma 220.The selection of plasma 220 is mainly determined by the material of gate insulator 208.Plasma 220 used herein can use the oxygen containing plasma of bag, to form the gate insulator 208 of monox, also can use nitrogenous plasma to form the gate insulator 208 of silicon nitride.Moreover, also can use the plasma that contains aerobic and nitrogen to form the gate insulator 208 of silicon oxynitride simultaneously.
If gate insulator 208 is a monox, then the input gas of plasma 220 can be O
2, H
2O or N
2O, the flow of input gas is about 20-5000SCCM, and chamber pressure is about 1-1000mtott, and preferred temperature is about 450-550 ℃.With above-mentioned condition, the thickness of the monox of formation is about the 100-1000 dust.If gate insulator is a silicon nitride, then the input gas of plasma 220 can be N
2, N
3H, N
2O, the flow of input gas is about 20-5000SCCM, and chamber pressure is about 1-1000mtorr, and preferred temperature is about 450-550 ℃.With above-mentioned condition, the thickness of the silicon nitride of formation is about the 100-1000 dust.If gate insulator is a silicon oxynitride, then the input gas of plasma 220 can be O
2, H
2O, N
2O, N
3H, NO, the flow of input gas is about 20-5000SCCM, and chamber pressure is about 1-1000mtorr, and preferred temperature is about 450-550 ℃.With above-mentioned condition, the thickness of the silicon oxynitride of formation is about the 100-1000 dust.
Afterwards, shown in Fig. 2 D, on gate insulator 208, form grid layer 210.The mode that forms has comprised several steps: depositing metal layers on gate insulator 208, on metal level, form photoresist layer, with the mode of photolithography with the design transfer of grid to photoresist layer, be the shade etch metal layers with the photoresist layer, and remove photoresist layer.In above-mentioned technology, the material of metal can be an aluminium, chromium, nickel, cadmium, or above-mentioned wherein alloy.The depositional mode of metal level can be chemical vapor deposition or physical vapour deposition (PVD).Photoresist layer can use positive photoetching rubber or negative photoresist, and the light frequency of exposure is depended in the use of its material.Etched mode can be isotropic etching or anisotropic etching.
Shown in Fig. 2 E, following step can be optionally.Because there is the transistor of lightly mixed drain area 212 that preferable element characteristic is arranged.With the ion implantation apparatus or the mode of ion shower impurity is injected in the polysilicon layer 206.Here the particle of Can Zaing mainly is the element that can provide as the electronics of conduction charge carrier, generally can be the element of pentavalent, for example phosphorus, perhaps arsenic.The lightly doped meaning is meant that the concentration ratio source/drain of doping is low, is less than about every square centimeter 10 greatly
3Individual.
Shown in Fig. 2 F, step afterwards is the sidewall formation clearance wall 214 in gate metal layer 210.The mode that forms comprises that conformal (conformal) dielectric layer of deposition one deck carries out etching in the mode of anisotropic etching then earlier.This step has several advantages, and the source/drain regions that inject to form of ion covers this lightly mixed drain area 212 afterwards, and provide grid and source/drain regions between preferable electrical isolation.
Shown in Fig. 2 G, with ion implantation apparatus or in the mode of ion shower impurity is injected into and forms source electrode and drain region 216 in the polysilicon layer 206.Here the particle of Can Zaing can be identical or inequality with the impurity of lightly mixed drain area 212 injections before.Concentration ratio lightly mixed drain area 212 height that mix.
Fig. 3 is the structural representation that shows the reaction chamber in the plasma treatment step.Conduit 302 is incorporated into reacting gas 304 and current-carrying gas in the reaction chamber 300, and substrate 200 is placed on the platform bracket 320.Radio-frequency power supply 306 is provided in reaction chamber 300, allows reacting gas 304 form plasma.Reaction chamber 300 has a well heater 308 near platform brackets 320, and substrate 200 is heated to suitable temperature, and reacting gas promptly can be on substrate 200 and polysilicon reaction becoming gate insulator.Platform bracket 200 can rotate, and makes can react with reacting gas equably on the surface of polysilicon, and the thickness of the gate insulator of feasible growth is even.In addition, a valve 310 is extracted the gas in the reaction chamber 300 out.
In this step, before this at first with inert gas, for example argon gas imports in the reaction chamber 300, the action of cleaning, and can remove autoxidation (native oxide) layer at polysilicon surface.The flow of gas input is about 1000-8000SCCM, and the duration is about 10-60 second.Close inert gas then, input reacting gas, and the power of adjustment radio frequency are to adjust the plasma concentration that is produced.Reaction chamber 300 is heated to suitable temperature.The reaction platform is rotated, and the frequency of rotation is about per minute 1-100 changes.The pressure of reaction chamber is about 1-1000mtorr.
By the formed gate insulator of the mode of plasma treatment, no matter be the oxide of silicon, nitride or oxides of nitrogen are produced by polysilicon layer and plasma reaction.By this way the gate insulator of Xing Chenging than before chemical vapour deposition technique preferable quality is arranged, therefore the compactness height of material can have higher voltage breakdown.In addition, by gate insulator that polysilicon layer and plasma reaction produced and the defective between the polysilicon than before chemical vapour deposition technique less, therefore can reduce leakage current.
To being familiar with the technician in this field, though the present invention illustrate as above with a preferred embodiment, yet it is not in order to limit spirit of the present invention.Modification of being done in not breaking away from spirit of the present invention and scope and similarly arrangement all should be included in the following interest field, and such scope should be consistent with the broadest annotation that covers all modifications and similar structures.Therefore, illustrate a preferred embodiment of the present invention as above, can be used to differentiate do not break away from the various changes of being done in spirit of the present invention and the scope.
Claims (21)
1, a kind of method that forms a thin film transistor (TFT) in LCD comprises:
On a transparency carrier, deposit one deck cushion and one deck polysilicon layer successively;
With this polysilicon layer of plasma treatment to form one deck gate insulator;
On this gate insulator, form one deck grid layer; And
In this polysilicon layer, form a source electrode and a drain region, be in this grid layer both sides.
2, the method for formation thin film transistor (TFT) as claimed in claim 1, wherein above-mentioned plasma treatment step are between temperature 300-600 ℃.
3, the method for formation thin film transistor (TFT) as claimed in claim 2, wherein above-mentioned plasma comprises oxygen.
4, the method for formation thin film transistor (TFT) as claimed in claim 3, wherein above-mentioned plasma comprises nitrogen.
5, the method for formation thin film transistor (TFT) as claimed in claim 3, wherein above-mentioned gate insulator is a monox.
6, the method for formation thin film transistor (TFT) as claimed in claim 4, wherein above-mentioned gate insulator is a monox.
7, the method for formation thin film transistor (TFT) as claimed in claim 2, wherein above-mentioned plasma comprises nitrogen.
8, the method for formation thin film transistor (TFT) as claimed in claim 7, wherein above-mentioned gate insulator is a silicon nitride.
9, the method for formation thin film transistor (TFT) as claimed in claim 4, wherein above-mentioned gate insulator comprises monox and silicon nitride.
10, the method for formation thin film transistor (TFT) as claimed in claim 1, wherein above-mentioned cushion is monox or silicon nitride.
11, the method for formation thin film transistor (TFT) as claimed in claim 1, the method for wherein above-mentioned this polysilicon layer of formation comprises:
Deposition one deck amorphous silicon layer on this cushion; And
Convert this amorphous silicon layer to this polysilicon layer in the quasi-molecule laser annealing mode.
12, the method for formation thin film transistor (TFT) as claimed in claim 1, the method for wherein above-mentioned this polysilicon layer of formation are continuous crystallisation silicon, and continuously side solidifies, the metal induced crystallization, the crystallization of metal induced side, or solid phase crystallization one of them.
13, the method for formation thin film transistor (TFT) as claimed in claim 1 also comprised before this formation source electrode, drain region step:
In this polysilicon layer, form the lightly doped drain zone, be in this grid layer both sides; And
On this grid layer sidewall, form clearance wall.
14, the method for formation thin film transistor (TFT) as claimed in claim 1, wherein above-mentioned transparency carrier is a glass substrate.
15, a kind of method that forms the high-breakdown-voltage gate insulator in Thin Film Transistor-LCD comprises:
A transparency carrier is provided;
On this substrate, form one deck polysilicon layer;
Between 300-600 ℃ with this polysilicon layer of plasma treatment to form one deck gate insulator, wherein above-mentioned plasma comprises oxygen or comprises nitrogen, and this gate insulator is a monox, silicon nitride, or silicon oxynitride.
16, the method for formation high-breakdown-voltage gate insulator as claimed in claim 15, the temperature of wherein above-mentioned step with plasma treatment is between 450-550 ℃.
17, the method for formation high-breakdown-voltage gate insulator as claimed in claim 16, wherein above-mentioned plasma comprises oxygen and nitrogen.
18, the method for formation high-breakdown-voltage gate insulator as claimed in claim 17, wherein above-mentioned transparency carrier rotates in this plasma treatment step.
19, the method for formation high-breakdown-voltage gate insulator as claimed in claim 18, the wherein above-mentioned gas of being introduced with the step of plasma treatment is hydrogen oxide, oxygen, nitrogen, or nitrogen oxide.
20, the method for formation high-breakdown-voltage gate insulator as claimed in claim 19, wherein above-mentioned gate insulator is a monox.
21, the method for formation high-breakdown-voltage gate insulator as claimed in claim 15 also comprised before plasma treatment step and introduces the inert gas cleaning and remove the natural oxidizing layer on this polysilicon layer surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100728518A CN100386690C (en) | 2005-05-24 | 2005-05-24 | Method for forming thin film transistor in liquid crystal display |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100728518A CN100386690C (en) | 2005-05-24 | 2005-05-24 | Method for forming thin film transistor in liquid crystal display |
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| CN1869793A true CN1869793A (en) | 2006-11-29 |
| CN100386690C CN100386690C (en) | 2008-05-07 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108346561A (en) * | 2018-02-09 | 2018-07-31 | 信利（惠州）智能显示有限公司 | Polysilicon layer processing method and processing system before gate insulating layer film forming |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB9927287D0 (en) * | 1999-11-19 | 2000-01-12 | Koninkl Philips Electronics Nv | Top gate thin film transistor and method of producing the same |
| GB0017471D0 (en) * | 2000-07-18 | 2000-08-30 | Koninkl Philips Electronics Nv | Thin film transistors and their manufacture |
| JP4901020B2 (en) * | 2001-05-23 | 2012-03-21 | 東芝モバイルディスプレイ株式会社 | Method for manufacturing polysilicon thin film transistor |
| JP2004288864A (en) * | 2003-03-20 | 2004-10-14 | Seiko Epson Corp | Thin film semiconductor, manufacturing method thereof, electro-optical device and electronic equipment |
| CN1265428C (en) * | 2003-04-02 | 2006-07-19 | 友达光电股份有限公司 | Method of manufacturing film transistor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108346561A (en) * | 2018-02-09 | 2018-07-31 | 信利（惠州）智能显示有限公司 | Polysilicon layer processing method and processing system before gate insulating layer film forming |
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