CN1862274A - Multi-scanning chain LSI circuit test data compressing method - Google Patents
Multi-scanning chain LSI circuit test data compressing method Download PDFInfo
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Abstract
The present invention relates to a large scale integrated circuit test data compression method of multiple scanning chains. It is characterized by that it utilizes restricted input compaction to make width compression, and utilizes LFSR and folding counter codification to make two-dimensional compression.
Description
Technical field:
The present invention relates to ic test technique, particularly to test data compressing method in built-in self-test (Built-In Self-Test) method of VLSI (very large scale integrated circuit) with multi-scanning chain.
Technical background:
The development of integrated circuit technique make can be in a chip integrated hundreds of millions of device, and can integratedly design and pass through the IP core of checking in advance, as memory core, microprocessor core, DSP are examined etc.The integrated chip of this diversification has become the integrated system that can handle various information, is called as SOC (system on a chip) or System on Chip/SoC SOC.SOC greatly reduces system cost, has shortened the design cycle, has accelerated time to market (TTM), but the test of SOC product faces increasing challenge, as:
1, chip testing point is few, and the test point that can directly control or observe is limited, can only test by the limited I/O pin of chip usually, and the chip internal node is difficult to directly control or observe by macroscopical mechanical hook-up.
2, ATE (automatic test equipment) ATE costs an arm and a leg, and the design and fabrication technology speed of development of chip is faster than the design and fabrication technology development of ATE, and the clock frequency of chip has surpassed the frequency of present state-of-the-art ATE, can't carry out the full speed test.
3, amount of test data is big, and core integrated among the SOC is many more, and required amount of test data is just big more.The capacity that expects the required storer of storage test vector in 2014 is 150 times in 1999, will surpass the storage depth of ATE.
The test of chip has become " bottleneck " of restriction integrated circuit development.Existing a large amount of documents launches research to the method for testing of integrated circuit, mainly contains outer build self-test and two kinds of methods of built-in self-test.
Build self-test method outward and be called the test source partitioning technology again, the method is stored in required test vector among the ATE through overcompression, test period, and the decompression circuit that passes through is applied to its reduction on the circuit-under-test.
Build-in self-test method, dependence chip its other resources is finished the test to chip.The method is embedded in test pattern maker TPG, test process control and test response Function of Evaluation module on the circuit-under-test CUT, has broken away from the dependence to ATE, has reduced testing expense.
Unit of testing and controlling and test response evaluation generally have ripe scheme and solve, and the test pattern generation is comparatively simple relatively, and therefore, the research to BIST both at home and abroad mainly focuses on the in the majority of test pattern generation aspect.Problem at data volume in the BIST test is increased sharply during test, generally will be stored in through the test data of overcompression among the chip ROM, and test period is applied to its reduction on the circuit-under-test by decompression circuit on the sheet again, be called " storage and generation ".At the existing a lot of methods of this technology, as the method that input is simplified, twisted ring counter scheme etc.But the Scan Design of these schemes and standard stream is incompatible, needs the structure of reconstruct scan chain, and cost is very big.
Summary of the invention:
The present invention is for avoiding above-mentioned existing in prior technology weak point, a kind of LSI circuit test data compressing method of multi-scanning chain is provided, it is a kind of test data compressing method of non-intrusion type, need not to change tested circuit structure, especially the structure of scan chain in the circuit, to retrain input and simplify technology, linear feedback shift register LFSR coding and folding counter technology combine, reduce the memory capacity of required test data with it, shorten test application time.
The technical scheme that technical solution problem of the present invention is adopted is:
The characteristics of the inventive method are to simplify by the input of constraint to carry out the width compression, carry out the bidimensional compression by LFSR and folding counter coding again, and concrete steps are:
A, circuit-under-test is carried out pseudorandom test, and utilization fault simulation instrument is determined the fault of not testing;
B, employing automatic test pattern Core Generator ATPG generate the test set T that determines to described fault of not testing;
C, the input that described test set T is retrained are simplified, the input of described constraint is simplified and is, at first described test set T is arranged and carries out compatible compression of multiple scan chains according to the form of multi-scanning chain and obtain compatible compressor units, the test vector after the compatible compression is reset according to the form of single scan chain, the test set after the rearrangement is designated as T again
ETwo test vectors are that compatible and if only if their corresponding position is identical or have one to be don't-care bit;
D, at described T
EIn, choose a test vector and carry out the LFSR coding, generate the seed of LFSR, the LFSR seed of being produced promptly is the test data that needs final storage; To launch again by folding counter by the test vector that described LFSR seed launches, obtain the folding counter sequence, the T that comprises in the described folding counter sequence
EIn test vector note;
E, at T
EIn find out with steps d in the test vector of the test vector compatibility noted, and with the test vector found out from T
EIn delete;
F, the described steps d of circulation and e are until T
EBe sky.
The characteristics of the inventive method also are:
Include don't-care bit " X " in all test vector among the described test set T, and don't-care bit need account for 35%～95% of test vector figure place..
Compatible compressor units is minimum compatible group that adopts the minimum covering algorithm of graph theory to obtain among the described step c.
Described LFSR Methods for Coding is, for the test set T after resetting
EIn arbitrary test vector, LFSR one of its folding sequence of successfully encoding is got final product; The number of degrees of described LFSR be chosen as S
Max-5 to S
Max+ 1, S wherein
MaxBe test set T
EIn have and maximum determine that the test vector of position locatees figure place really; The principle of following for the selection of the test vector that will encode is: the LFSR seed behind this test vector coding, the folding counter sequence that generates through expansion can cover T
EIn maximum test vectors.
The LFSR coding techniques the earliest by B Konemann at document LFSR-Coded test patterns for scan designs.Proceeding of European Test Conference, 1991, propose among the pp.237-242.And proved theoretically, when the number of degrees of LFSR are S
Max+ 20 o'clock, the coding probability of successful was 1-10
-6The method substitutes long test vector with short LFSR seed, thereby has reached the purpose of width compression.
The compression method of folding counter is that the test vector that will determine is embedded in the middle of the sequence of folding device, and the seed (folding seed) that only need store a spot of folding counter just can cover the test vector of all determining.One of them folding seed launches to generate n+1 status switch by folding counter, and wherein n is the figure place of folding seed.Its status switch can be realized by the folding certain upset rule of seed application.If the original state of folding counter is S=(s
1, s
2..., s
n), S ∈ 0,1}
n, the n+1 of its a generation status switch be designated as F (0, S), F (1, S), F (2, S) ..., F (n, S).
Then F (i, S)=(
Inv (1, i)s
1,
Inv (2, i)s
2...,
Inv (n, i)s
n) (0≤i≤n)
Wherein inv (j, i) for the upset function, its formula is:
I is called fold distance, and j represents the j position of test vector.
If (j, i) value is odd number, s to inv
jUpset becomes 1 or become 0 by 1 by 0.If even number, s
jRemain unchanged.What specify is to work as s
jWhen='-' is don't-care bit (don ' t care bit), s
j='-'.The example that is launched the generation folding sequence by folding seed sees Table 1.
Table 1 folding counter sequence generates example
| The state turnover function | Positional value j=1,2,3,4 | Distance value i |
| F(0，S) inv(j，i) | 0 1 1 0 0 0 0 0 | 0 |
| F(1，S) inv(j，i) | 1 0 0 1 1 1 1 1 | 1 |
| F(2，S) inv(j，i) | 1 1 1 0 1 2 2 2 | 2 |
| F(3，S) inv(j，i) | 1 1 0 1 1 2 3 3 | 3 |
| F(4，S) inv(j，i) | 1 1 0 0 1 2 3 4 | 4 |
Table 1 has provided the example of the complete sequence of a folding counter.Each sequence is all by original state 0110, and fold distance value i and upset functional value generate.It is that fold distance i decision generates for which status switch, and the parity of upset functional value determines whether that mode bit overturns, and the number that overturns is an odd number here, and the corresponding mode bit that generates must overturn.For the example test vector in do not contain don't-care bit, when containing don't-care bit in the test vector, upset similarly, just don't-care bit remains unchanged.The detailed operation principle of folding counter is at " S.Hellebrand, Hua-Guo Liang, Hans-Joachim Wunderlich:AMixed Mode BIST Scheme Based on Reseeding of Folding Counters; Proceedings IEEEInternational Test Conference, Atlantic City, NJ, October 2000, pp.778-784." on the books.
At document Hua-Guo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich:Two-DimensionalTest Data Compression for Scan-Based Deterministic BIST; Proceedings IEEE International TestConference, Baltimore, MD, October 30-November 2,2001 introduced the method for LFSR and folding counter assembly coding among the pp.894-902, but this scheme test duration is long.
Compared with the prior art, beneficial effect of the present invention is embodied in:
The present invention simplifies by the input of constraint and realizes the width compression, and the scheme by LFSR and folding counter coding realizes the bidimensional compression again, has not only reduced the test duration in a large number, has also reduced the memory capacity of required test data.
Description of drawings:
The structure of Fig. 1 pseudorandom test of the present invention;
The implementation that Fig. 2 multiple constraint input is simplified;
Fig. 3 retrains the test vector decompress(ion) block diagram after input is simplified;
Fig. 4 is the LFSR coding;
Fig. 5 is a final decompress(ion) structural drawing of the present invention;
Embodiment:
Implementing the present invention carries out as follows:
A, circuit-under-test is carried out pseudorandom test, and utilization fault simulation instrument is determined the fault of not testing;
B, employing automatic test pattern Core Generator ATPG generate the test set T that determines to described fault of not testing;
C, the input that described test set T is retrained are simplified, the input of described constraint is simplified and is, at first described test set T is arranged and carries out compatible compression of multiple scan chains according to the form of multi-scanning chain and obtain compatible compressor units, the test vector after the compatible compression is reset according to the form of single scan chain, the test set after the rearrangement is designated as T again
ETwo test vectors are that compatible and if only if their corresponding position is identical or have one to be don't-care bit;
D, at described T
EIn, choose a test vector and carry out the LFSR coding, generate the seed of LFSR, the LFSR seed of being produced promptly is the test data that needs final storage; To launch again by folding counter by the test vector that described LFSR seed launches, obtain the folding counter sequence, the T that comprises in the described folding counter sequence
EIn test vector note;
E, at T
EIn find out with steps d in the test vector of the test vector compatibility noted, and with the test vector found out from T
EIn delete;
F, the described steps d of circulation and e are until T
EBe sky.
The pseudorandom test:
Referring to Fig. 1, adopt pseudo-random generator.Set original state by given pseudo-random generator, allow it move some clock period continuously, generate the test vector of some.The most frequently used in built-in self-test is to adopt linear feedback shift register LFSR and cellular automaton cellular automata as pseudo-random generator.Apply these test vectors then to circuit-under-test, obtain these test patterns by fault simulation software and measure which fault, which fault does not detect.In containing the circuit-under-test of multi-scanning chain, LFSR is often adopted in the generation of pseudorandom test vector.But, need between LFSR and circuit-under-test, to add some the XOR network of forming by XOR gate, i.e. phase-shifters in order to break the correlativity between the LFSR formation sequence.
Determine the generation of test set:
After the pseudorandom test is finished, at the fault that pseudo-random vector is not tested, adopt atpg tool to generate the test set T that determines, test vector contained among the test set T can be tested the fault that pseudorandom is not tested.。To the selection of atpg tool, make the test vector of its generation contain don't-care bit.Following step is exactly that the definite test set T that generates is compressed.
The constraint input is simplified
It is the test input of multi-scanning chain structural circuit to be carried out simplify that the input of constraint is simplified, and reaches the purpose of width compression.The test vector of multi-scanning chain is that former test set is arranged grouping according to the form of multi-scanning chain, and the input of constraint is simplified at first compatible compression is carried out in grouping, promptly compatible input scan chain, and then reset according to the form of single scan chain.Test vector after the rearrangement is compared with former test vector, and width significantly reduces, simultaneously S
MaxAlso decrease, also further reduced the number of degrees of the required LFSR of LFSR coding in the subsequent step.The implementation that the constraint input is simplified as shown in Figure 2.
Fig. 2 (a) is divided into 4 groups for determining that test set comprises 3 test vectors, is the test data of 4 scan chains.
Fig. 2 (b) is the test set of arranging according to 4 scan chain serial inputs.
Fig. 2 (c) is the test set after the compatible compression of group, and the group number scale of compression back test set is n '=2.
Fig. 2 (d) is the spread pattern that the test set of group after the compatible compression is reduced into former test set, and the merging that wherein can see former test set row is limited between the group and merges, and row are to list existing order according to former group to rearrange out the result.
Key is that new group of arranging among Fig. 2 (b) is carried out compatible merging in this example, can see that here group 1 and 3 is compatible, and 2 and 4 also be compatible, finally is merged into two groups, shown in Fig. 2 (c).Find the solution in the minimum compatible group of available employing graph theory division of figure and the method for minimum covering are solved, its algorithm is as follows:
1, at first set up graph theory model, generate compatible chart, wherein each test vector adds among the figure as a summit, when there is compatibility relation in two test vectors, then links to each other with a nonoriented edge in the middle of them, has so just obtained a non-directed graph G who haves no right.
2, non-directed graph G is copied to an ephemeral data structure G
1In.
3, at G
1In find the summit V of number of degrees maximum.
4, set up a subgraph, subgraph is made of other summit that all link to each other with summit V.This subgraph is copied to G
1, and with summit V join the set C in.
5, if G
1Non-NULL turns back to step 4.If G
1Be sky, then gather the summit that increases newly among the C and constitute a maximal compatible class.
6, G-C is copied to G
1, return step 4, all gathering among the C up to all summits.
By the test vector of former as can be seen 12 bit widths of Fig. 2 (d), be compressed into 6, can be compared to former test circuit input and simplified.Separate laminated structure as shown in Figure 3, n ' controls applying of packed data serial immigration and every row test data for the minimum set of counters that merges among the figure, and leftmost test data is T
EIn the 1st test vector, the fan-out line of buffer output is realized compatible group data decompression.Here the applied compression vector needs 6 clock period.Adopt the single scan chain pattern but to need 12 clock period.Therefore, test application time obviously shortens.
The LFSR coding
The technology that LFSR coding and folding device combine can further reduce the number of degrees of required LFSR.The selection of the LFSR number of degrees is generally at S
Max-5 to S
MaxAll test vectors of just can successfully encoding between+1.The encoding scheme of this programme is from T
EIn choose a test vector, all folding seeds of its correspondence are generated out, as long as any one folding seed is encoded successfully with LFSR, keep the LFSR seed so.And it is launched into that folding kind of subvector with LFSR.The folding counter T that status switch comprises that this kind subvector generates
EOther test vector, also note in the lump.The final LFSR seed that keeps is can cover-most T
EIn test vector, concrete implementation is shown in Fig. 4 and table 2.T
EIn first test vector (1 * 0110) can be encoded to seed (11) by LFSR, keep this seed, (11) be (110110) through the folding kind of subvector that LFSR expansion generates, and it is as shown in table 2 by folding sequence that folding counter launches generation.
The folding sequence that folding kind of the subvector of table 2 launches
| Folding sequence | The counter content |
| F(0，S) | 1 1 0 1 1 0 |
| F(1，S) | 0 0 1 0 0 1 |
| F(2，S) | 0 1 0 1 1 0 |
| F(3，S) | 0 1 1 0 0 1 |
| F(4，S) | 0 1 1 1 1 0 |
| F(5，S) | 0 1 1 1 0 1 |
| F(6，S) | 0 1 1 1 0 0 |
The deletion folding sequence is at T
EThe middle vector that covers
From T
EIf the test vector that the seed that middle deletion keeps has covered is T
EBe sky, then this programme finishes, otherwise capable from LFSR coding lifting retry.Can find out T from table 2
EIn test vector respectively with F (0, s), F (3, s) and F (5, s) compatible, will be with these vectors from T
EMiddle deletion, at this moment T
EBe sky, EOP (end of program).
Finally, the kind subvector that will store in the present embodiment is (11), only needs 2, has reduced required test data memory capacity.
Finally separate laminated structure as shown in Figure 5.Wherein MUX is finished pseudo random test pattern and definite test pattern selection, and LFSR adds phase-shifter and finishes the random pattern generation, the hard fault centralized procurement that generates after the fault simulation is encoded and is folded with compatible compression of multiple scan chains, LFSR compress.Column data after the buffer storage compatible compression of multiple scan chains, i.e. routine data among Fig. 2 (c), its buffer output connects fan-out line decompress(ion), is applied in the multi-scanning chain through MUX.When folding counter shifted out n ' position from the XOR output terminal, n ' column counter notified tested circuit to receive one group of data among the figure, and zero clearing then, repeat count are employed up to a complete test pattern, then continued the next test pattern of control and used.LFSR bears dual role among the figure, and the one, finish pseudo random pattern and generate, the 2nd, to the seed coding of folding counter.
Claims (4)
1, a kind of LSI circuit test data compressing method of multi-scanning chain is characterized in that simplifying by the input of constraint and carries out width compression, carries out the bidimensional compression by LFSR and folding counter coding again, and concrete steps are:
A, circuit-under-test is carried out pseudorandom test, and utilization fault simulation instrument is determined the fault of not testing;
B, employing automatic test pattern Core Generator ATPG generate the test set T that determines to described fault of not testing;
C, the input that described test set T is retrained are simplified, the input of described constraint is simplified and is, at first described test set T is arranged and carries out compatible compression of multiple scan chains according to the form of multi-scanning chain and obtain compatible compressor units, the test vector after the compatible compression is reset according to the form of single scan chain, the test set after the rearrangement is designated as T again
ETwo test vectors are that compatible and if only if their corresponding position is identical or have one to be don't-care bit;
D, at described T
EIn, choose a test vector and carry out the LFSR coding, generate the seed of LFSR, the LFSR seed of being produced promptly is the test data that needs final storage; To launch again by folding counter by the test vector that described LFSR seed launches, obtain the folding counter sequence, the T that comprises in the described folding counter sequence
EIn test vector note;
E, at T
EIn find out with steps d in the test vector of the test vector compatibility noted, and with the test vector found out from T
EIn delete;
F, the described steps d of circulation and e are until T
EBe sky.
2, method according to claim 1 it is characterized in that including don't-care bit " X " in the test vectors all among the described test set T, and don't-care bit need account for 35%～95% of test vector figure place.
3, method according to claim 1 is characterized in that compatible compressor units is minimum compatible group that adopts the minimum covering algorithm of graph theory to obtain among the described step c.
4, method according to claim 1 is characterized in that described LFSR Methods for Coding is, for the test set T after resetting
EIn arbitrary test vector, LFSR one of its folding sequence of successfully encoding is got final product; The number of degrees of described LFSR be chosen as S
Max-5 to S
Max+ 1, S wherein
MaxBe test set T
EIn have and maximum determine that the test vector of position locatees figure place really; The principle of following for the selection of the test vector that will encode is: the LFSR seed behind this test vector coding, the folding counter sequence that generates through expansion can cover T
EIn maximum test vectors.
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| CN104635148A (en) * | 2015-02-13 | 2015-05-20 | 合肥工业大学 | Selective generation method for state vectors of parallel folding counter and hardware circuit for selective generation method |
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| CN106610469A (en) * | 2016-12-07 | 2017-05-03 | 吴海峰 | Test data compression method based on alternate cyclic flipping |
| CN106874601A (en) * | 2017-02-20 | 2017-06-20 | 中国人民解放军国防科学技术大学 | A kind of scan chain weight method for sequencing |
| CN108896905A (en) * | 2018-07-17 | 2018-11-27 | 龙口盛福达食品有限公司 | A kind of intelligent soy milk grinder AI chip circuit automatic fault selftesting method |
| CN109709473A (en) * | 2019-01-29 | 2019-05-03 | 无锡中微腾芯电子有限公司 | A kind of method and system for 3D-SiP chip testing vector compression |
| CN109709473B (en) * | 2019-01-29 | 2021-05-28 | 无锡中微腾芯电子有限公司 | Method and system for compressing test vector of 3D-SiP chip |
| CN112649723A (en) * | 2019-10-11 | 2021-04-13 | 清华大学 | Test simplification method and device under conversion delay fault test compression environment |
| CN112649723B (en) * | 2019-10-11 | 2021-11-12 | 清华大学 | Test simplification method and device under conversion delay fault test compression environment |
| CN110865299A (en) * | 2019-11-28 | 2020-03-06 | 安庆师范大学 | Folding set layered compression method and device based on forward compatibility |
| CN110865299B (en) * | 2019-11-28 | 2021-10-15 | 安庆师范大学 | Folding set layered compression method and device based on forward compatibility |
| CN117825913A (en) * | 2023-12-06 | 2024-04-05 | 中科鉴芯(北京)科技有限责任公司 | Test excitation compression method, device and circuit based on variable length LFSR |
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