CN1860743A

CN1860743A - Network message processing using pattern matching

Info

Publication number: CN1860743A
Application number: CNA2003801105481A
Authority: CN
Inventors: 哈罗德·M.·马丁; 卡洛斯·A.·格里夫斯; 唐·Q.·尼古耶恩; 戴维·J.·努尼兹
Original assignee: Freescale Semiconductor Inc
Current assignee: NXP USA Inc
Priority date: 2003-11-25
Filing date: 2003-11-25
Publication date: 2006-11-08
Also published as: JP2007525037A; KR101017536B1; AU2003298698A1; JP4428537B2; KR20060131758A; WO2005064868A1; EP1690379A1

Abstract

Pattern matching is used in an information processing system to process incoming messages from a network such as an Ethernet-based network to aid in filing such messages in memory and the selective stashing of such messages in cache. Pattern matching increases the efficiency of message acceptance and rejection without increasing software-based processor tasks. The incoming message can be searched for the existence of patterns and the absence of the patterns. The incoming message can be searched for the existence of multiple patterns. The results of pattern matching can be used not only for acceptance and rejection of messages, but also for other post-receipt tasks such as selective storage of incoming messages according to identified relative priorities or absolute criticality of messages having particular pattern matches, and such as selective direction of messages to different processing domains within a multi-processor computer system according to the pattern matches.

Description

Use the internet message of pattern matching to handle

Technical field

The present invention relates to network service, more specifically, relate to the message of processing via the network reception of for example ethernet network.

Background technology

The network of Local Area Network, wide area network (WAN) and other type typically comprise via be connected coupling, according to the various communication protocol bulk information treatment systems of operating based on bag.For example, ethernet ieee 802.3 agreements are based on the lan protocol that is widely used of Carrier Sense Multiple Access/collision detection (CSMA/CD) method.Because Ethernet and IEEE802.3 agreement are similarly, and can coexist as on the identical LAN, so both are known as Ethernet sometimes.10/100 Ethernet provides the ethernet speed of the increase of from 10 to 100 MBPSs (Mbps), and for main line with the server connectivity provides simply, the cost effective choice.Gigabit Ethernet is the another kind of Ethernet protocol that is based upon on the basic Ethernet protocol, but speed is increased to the arrival 1000Mbps or a gigabit per second (Gbps) more than ten times of 10/100 Ethernet.

The common reception of equipment in the network will be given their message and is not the message that will give them.Therefore, this equipment must be at local analytics each enter message and determine whether they should accept this message.Typically, each equipment has the address that must be compared with the address in each received message with certain form.Because address size and a large amount of addresses that will be compared, accurate matching addresses is very intensive on calculating.Because equipment can be accepted message for a large amount of miscellaneous equipments, so very a large amount of message may be received, and the network speed increase, (for example handle, accept or refusal) problem that enters message can cause the bottleneck at various device place in network, and reduce overall performance.The back filtering that traditional destination-address recognition methods need be carried out on the open system interconnection (osi) level higher than medium access control (MAC) level, and need a large amount of softwares and common treatment hardware intervention.Some technology are used Content Addressable Memory (CAM), but all very expensive, the very power consumption and dumb in this technological model ground.Therefore, need enhancement process to enter the performance of message.

Enter the message except just accepting or refusing, each equipment typically has the various tasks of carrying out in response to receiving message.Therefore, need be stored in a short period of time and visit by the more received data of message.Like this, be used for other task with the use that discharges this resource and reduce the processing that the visit stand-by period important or high priority frame strengthens this message and will have superiority by preliminary treatment received message (for example, by before being checked by processor or software-driven system resource at inbound messages with they classification).

Description of drawings

By the reference accompanying drawing, the present invention can be better understood, and its many purposes, feature and advantage are obvious to those skilled in the art.The use of same numeral refers to similar or identical item among the different figure.

Fig. 1 is that diagram is according to the information processing of the embodiment of the invention and the block diagram of communication system.

Fig. 2 is the block diagram of receiving unit of packet controller of the system of pictorial image 1.

Fig. 3 is the block diagram that illustrates the exemplary message address that can be received by the system of Fig. 1 and analyze.

Fig. 4 is the block diagram of the exemplary buffer memory descriptor queue of pictorial image 1.

Fig. 5 is the exemplary pattern coupling of pictorial image 1 and the block diagram of pattern matching property register.

Fig. 6 is the flow chart that diagram is used for the method for the system handles received message by Fig. 1.

Fig. 7 is that diagram is used for hash and the pattern matching flow chart by the part of the method for the message addresses that system received of Fig. 1.

Fig. 8 is that diagram is used for hash and the pattern matching flow chart by another part of the method for the message addresses that system received of Fig. 1.

Fig. 9 is the diagramatic mode coupling flow chart by the method for the message addresses that system received of Fig. 1 in the diagram flow process of Fig. 7.

Figure 10 is shown in the flow chart of handling the method that is accepted message in the system of Fig. 1.

Figure 11 is the flow chart that illustrates the method for the system's extraction of passing through Fig. 1 and the part of collecting (stash) message.

Figure 12 is the table of the processed a large amount of addresses of diagram use hash and/or pattern matching.

Embodiment

Following discussion aims to provide the detailed description of at least one example of the present invention, and should not be considered to the restriction to the present invention itself.In fact, the change of any amount can drop in the scope of the invention that is suitably limited by this specification following claim.

Fig. 1 is that diagram is according to the information processing of the embodiment of the invention and the block diagram of communication system 100.System 100 comprises processor 110, high-speed cache 120, memory 130, system bus 140, peripheral hardware 150 and packet controller 160.Processor 110, high-speed cache 120, memory 130, peripheral hardware 150 and packet controller 160 are all via system bus 140 couplings.System 100 can be Ethernet, G level Ethernet and/or XG level ethernet controller or with its compatibility, can be the network switch or router, perhaps be used for equipment in other type of intra network communication.

Packet controller 160 comprises Bus Interface Unit (BIU) 170, receiving unit 180, translator unit 185 and media access controller (MAC) 190.Bus Interface Unit 170 is coupled to system bus 140.Bus Interface Unit 170 is coupled to receiving unit 180 via connecting 172, is coupled to translator unit 185 via connecting 174.MAC 190 is coupled to receiving unit 180 via connecting 192, is coupled to translator unit 185 via connecting 194.MAC 190 is coupled to physical layer hardware to receive for example message of bag via physics (PHY) connection 198 from miscellaneous equipment.

Message is received and is passed to receiving unit 180 at MAC 190.Message can be depending on Address Recognition, hash, pattern matching or hash and pattern matching (for example, describing with reference to Fig. 2 to 9 at least as following) can be accepted or not be accepted.Be passed to memory 130 from the information that is accepted message.Some information can be identified as by pattern matching and be particularly suitable for by processor 110 or other system resource fast access, in this case, this information is come out from the normal messages extracting data that sends to memory 130, and the data of extracting are collected in the high-speed cache 120 and (for example, describe with reference to Fig. 2 to 6 and Figure 10 to 11 at least as following).

Disclosed destination-address identification protocol will drop to minimum to the needs of back filtering, and can carry out and need not interfering at the further software and hardware of higher OSI level in the medium access control level.For some address set, the user can find the set of patterns that produces fabulous filtering in the MAC level.Deterministic algorithm can be used to produce and be used to guarantee the required pattern of fabulous hash time filtering.Disclosed agreement also allows in being accepted frame integral body but not the only pattern matching search in the destination-address, to improve the result of hash time filtering.

Memory 130 comprises and is used to store the frame data buffer memory 134 that enters message and is used to follow the tracks of the buffer memory descriptor queue 132 of institute's storing message, as is discussed in further detail below.High-speed cache 120 comprise the memory location that can store one or more buffer memory descriptor queue 122 and be used for collection (i.e. storage) the memory location of the data of extracting 124 to be used by processor 110 subsequently.The data of extracting are data that are used for being stored in high-speed cache 120 of extracting from the normal frame data that enters message according to some pattern matching agreement described herein.The data of extracting can be that the access time of for example significant data, service quality (QoS) level data or acceleration may be other high-priority data of its expectation.Memory 130 and high-speed cache 120 can be visited by processor 110, and even can be by miscellaneous equipment in the system 100 or the visit of processor (not shown).

Fig. 2 is the block diagram of receiving unit 180 of the packet controller 160 of system shown 100.Receiving unit 180 comprises direct memory visit (DMA) controller 210, receives FIFO 220 and address/data filter (ADF) 230.ADF 230 is coupled and is used for receiving message and being used for optionally this message being offered FIFO 220 from MAC 190.Have to be wrapped in below with reference to Fig. 3 by the exemplary message of the frame of address/data filter 230 receptions and discuss in more detail.DMA 210 is coupled and is used for receiving information (for example, address and data message, and the message filtering result of the mode state information that for example describes below) from receiving FIFO220 under the control of fifo controller 222.

ADF 230 comprises interim formation 234, pattern matching logic 232 and Address Recognition and hash logic 238.Each is coupled and is used for receiving message (for example frame) from MAC 190 in interim formation 234, pattern matching logic 232 and Address Recognition and the hash logic 238.Interim formation 234 is coupled and is used for from pattern matching logic 232 and Address Recognition and hash logic 238 reception message filtering object informations, and is used for as to the response that receives FIFO 220 frame (or its part) and message filtering information being offered reception FIFO 220.

When not having pattern matching and hash logic, directly and sufficient address relatively must between the destination-address of each received message and system 100 or system 100 are configured to the address of its other system that accepts message, be carried out.This sufficient address more typically comprises with certain form interrupt handler 110, because more typically take place under the control of software.

But in illustrated embodiment, pattern matching logic 232 and hash logic 238 are provided to reduce the frequency that full address relatively takes place, thereby allow 110 free time of processor to carry out other task.232 pairs of frames that received of pattern matching logic carry out the pattern matching analysis, the frame selectivity are accepted according to the pattern matching result with permission.Carry out under the control of the value (for example, control bit or territory) of pattern matching in being stored in pattern matching (PM) register 233.The hash analysis is carried out in the address of 238 pairs of institutes of hash logic received frame, hits or the result of missing the target accepts the frame selectivity according to hash allowing, and highly accepts possible address and carries out full address possibility relatively having with further increase.

The PM register 233 of pattern matching logic 232 comprises 16 clauses and subclauses.Each clauses and subclauses comprises 5 32 bit register.Referring now to Fig. 5, each clauses and subclauses comprises pattern (PMDATA), pattern shielding (PM MASK) and pattern matching control (PM CONTROL) territory.The pattern matching control domain comprises match index (MI) territory, (CSE) territory, reversing (IV) territory, connection mode (CP) territory and pattern matching acceptance control (PMAC) territory are enabled in search continuously.

PM DATA territory comprises and being used for and institute's received frame bit pattern relatively.If PMDATA bit pattern (for example, 4 byte modes) is found in frame, pattern matching is detected so.If PM DATA bit pattern is not found in frame, pattern matching is not detected so.PM DATA territory is 32 bit long in the illustrated embodiment.PM MASK territory comprises the position that makes some conductively-closed when relatively taking place in the pattern.For example, the knowledge of the sale trade mark in the part of frame position can be left in the basket when PM MASK suitably is provided with.

How match index (MI) territory indication pattern matching in institute's received frame should begin to be used for corresponding PM DATA deeply.For example, the MI territory can comprise 6 positions, the hunting zone of indication from 0 to 256 bit.In one embodiment, MI is in the multiple of 4 bytes, and (to FCS, comprising end points from the DA territory) assigned indexes from received frame begins to carry out pattern matching from it.If MI is eliminated, preceding 4 bytes of destination-address are provided for the starting point of pattern matching.The maximum programming value of MI is 63 (252 byte offset) in current discussion embodiment.Even the MI value of each 4 byte mode is also respected (honor) when allowing contiguous or non-adjacent modes.

(CSE) territory influences the action that will take when coupling is found type is enabled in search continuously.Particularly, CSE position indication takes an immediate action when pattern matching, still further emergence pattern match search when pattern matching.If the CSE position that has been provided with indication is mated on clauses and subclauses, pattern matching should continue so.For example, if pattern matching is found and continuous search is activated, pattern matching logic 232 continues the maximum of other coupling of search PM DATA from other register of PM register 233 up to 256 bytes so.If do not have other coupling to be run into, be used with the corresponding attribute of the clauses and subclauses of last coupling so.All continuous patterns necessarily can not be accepted based on the pattern matching refusal is final.For example, first pattern matching must be accepted at least conditionally, and all patterns subsequently are necessary or acceptance, perhaps neither accepts also not refuse so that accept frame.If the refusal of pattern matching subsequently takes place, the value of CSE is left in the basket so, and frame is rejected, and search is stopped.If pattern matching is found and continuous search is under an embargo (CSE=0), search to all other patterns will be stopped by pattern matching logic 232 so, and frame is accepted or rejected, and perhaps another determines to be made by the fact that takes place based on concrete pattern matching.

Connection mode (CP) territory allows the comparison more than 32 bits of PMDATA available in PM register 233 each clauses and subclauses.If the CP position is set up, follow the middle PM register 233 of current PM register back to be counted as the continuation of this pattern, and next PMDATA clauses and subclauses are connected to current PM DATA clauses and subclauses.In this case, each PMDATA clauses and subclauses must be found in pattern matching will the frame to its generation, but two groups of match bit can be in the frame Anywhere according to they MI separately.If the CP position is not set up, does not have pattern to connect so and take place.The CP territory of last PM register 233 is counted as and is eliminated, and no matter be stored in wherein value how.Wherein the minimum digital PM register 233 that is set up of CP contains pattern matching control and the attribute information (except MI) that is used to the pattern that is connected.For each connected pattern, the MI territory must be set to 4 suitable byte multiples, in order to avoid all pattern attempts match preceding 4 bytes (not removing if MI is left) of frame.

Reversing (IV) territory allows pattern and frame with the comparison true or form of benefit.For example, when reversing is not set up (IV=0), pattern matching only takes place when Data Matching (for example, PM DATA is found in institute's received frame) takes place so.When reversing was set up (IV=1), pattern matching did not take place when (for example, PM DATA does not find in institute's received frame) only do not take place in Data Matching.

The PMAC territory is based on the filtering of pattern matching control frame.PMAC stores two positions, and whether their indications (i) are activated the pattern matching of corresponding modes, and if (ii) pattern matching be activated and be used for corresponding pattern, the effect when in a single day pattern matching finishes so.For example, if the PMAC territory is 00, the pattern matching to concrete clauses and subclauses is under an embargo so, does not have pattern matching to occur in corresponding modes, and pattern matching logic 232 freely moves on to the next pattern in the next PM register 233.If the PMAC territory is not 00, pattern matching is activated so.If the PMAC territory is 11, frame is rejected based on pattern matching so.If the PMAC territory is 10, frame or definitely accepted when continuously search is under an embargo (CSE=0) is perhaps accepted when search is activated (CSE=1) continuously conditionally so.If the PMAC territory is 01, frame neither is accepted also and is not rejected so.In this case, pattern is not to be used to accept when coupling takes place or the standard of reject frame, and information is collected the reprocessing that is used for relevant pattern matching result, does not make decision and will accept or reject frame but be based on collected information.Reprocessing can comprise based on preceding mode or based on destination-address identification to be carried out filtering or extracts data received frame, perhaps can comprise other classification feature.Frame can be accepted by hash processing, other pattern matching processing etc. afterwards.

Referring again to Fig. 2, DMA 210 comprises reception buffer memory 211, extracts engine 212, pattern property register 213, changes descriptor and filter processor (BDFP) 214, status register 215 and buffer memory descriptor address register 216 into now.Logical block discussed here is an exemplary, and different embodiment can have different logic functions and divide.For example, in one embodiment, DMA 210 can be counted as comprising the Memory Controller that is used to extract, change into descriptor processing and Filtering Processing.

Reception buffer memory 211 is coupled and is used for receiving message from receiving FIFO 220.Status register 215 is coupled and is used for from receiving FIFO 220 receiving mode states (PS).Mode state comprises that pattern quantity (for example, PM register quantity) and corresponding pattern hit indication.Fifo controller 222 is coupled to the transmission that DMA 210 is used to control this information.Receiving buffer memory 211 is coupled and is used for via connecting 172 frame data being provided to Bus Interface Unit 170.

Extraction engine 212 is coupled and is used for the extraction control information is provided to reception buffer memory 211, is used to continue to deliver to high-speed cache 120 to indicate which frame information to be extracted.Extracting engine 212 is coupled and is used for via connecting 172 the relevant attribute that is extracted information being offered Bus Interface Unit 170.For example, extract engine 212 indications by receiving whether data that FIFO sends to memory or high-speed cache are extracted or normally, perhaps its whether will be stored in the memory 130 or not only be stored in the memory 130 but be collected in high-speed cache 120 and any precedence information associated with the data in.Whether status register 215 offers extraction engine 212 with mode state information and should be extracted with the indication frame data.Extraction engine 212 also is coupled and is used for receiving the extraction control informations from pattern property register 213.For example, pattern property register 213 will extract index and extract length and be provided to extraction engine 212 (following discussion).

Pattern property register 213 be coupled be used for the indication which buffer queue to submit to the submission information of frame data (PMF) to offer buffer memory descriptor address register 216 at.Status register 215 is coupled the pattern matching information that is used for for example indication of realistic model coupling and offers BDFP 214.Buffer memory descriptor address register 216 is coupled the plot that is used for being used for each buffer memory descriptor queue (BDQ 410,420,430 and 440) and each queue pointer (BDQ_BASE, BDQ_CURRENT and BDQ_NEXT) and default queue and offers BDFP 214.BDFP 214 is coupled and is used for via connecting 172 address and data message being offered Bus Interface Unit 170.

The pattern property register is write the action that is used to specify when coupling takes place by the user, and where frame information is provided to, when extracts frame information and how to store received frame and their the buffer memory descriptor that is associated.In the embodiment of current discussion, have 16 registers or clauses and subclauses altogether and be supported.Such register (or replaceable register) can be designated as default register, and comprises the information that is used to specify the action when not having pattern matching to take place.Referring now to Fig. 5, each clauses and subclauses comprises that extraction high-speed cache (for example, L2 high-speed cache) is write type (ELCWT), buffer memory descriptor high-speed cache is write type (BDLWT), formation classification (QC), pattern matching file (PMF), pattern matching extraction (PME), extracted index (EI) and extract length (EL).Other bit field can be comprised other function that is used to enable or support any amount.For example, data detect the position can by comprise be used to support institute's received frame to memory detect or the detecting of the cache memory data that receives visit.In this case, when arriving the visit of memory, high-speed cache can detect the visit that reads or writes of memory, make high-speed cache can detect the address and take suitable action then, the data trnascription of invalid storage in high-speed cache for example, renewal is from the cached data of memory, perhaps with storage in memory almost concurrently with storage in high-speed cache.The pattern property register is the exemplary memory location that is used for the information content of discussing.Other embodiment can comprise other configuration that is used to store this information content, comprises other configuration, distributed register position or the like.

Extracting high-speed cache writes type (ELCWT) territory and specifies and be used for extracting the type of transaction of writing that data carry out.Extraction is write transaction and is taken place when pattern matching is extracted that (PME) territory is set up, the corresponding modes coupling takes place and extracted length (EL) territory for non-zero.In one embodiment, if ELCWT is 00, do not distribute so to be carried out; If ELCWT is 01, does not extract so and take place; If ELCWT is 10, cache line is assigned with so; If ELCWT is 11, cache line is assigned with and is locked so.Under the situation of connection mode configuration, employed ELCWT is from the pattern property register of bottom numeral.Undertaken by detecting (snoop) to writing of high-speed cache.

Buffer memory descriptor high-speed cache is write type (BDLWT) territory and is specified the type of transaction of writing that the buffer memory descriptor be used for received frame carries out.This takes place when pattern matching takes place, and irrelevant with the value of PMF or PME.Carry out to writing of high-speed cache by detecting.In one embodiment, if BDLWT is 00, do not distribute so to be carried out; If BDLWT is 10, cache line is assigned with so; If BDLWT is 11, cache line is assigned with and is locked so.

Whether pattern matching is extracted (PME) territory and is indicated the extraction based on pattern matching to be activated.If pattern matching is extracted the position and is set up (PME=1), extraction is activated.If pattern matching is extracted the position and is not set up (PME=0), extraction is under an embargo so.

Formation classification (QC) is if specify the PMF territory to be set up and the corresponding modes coupling is submitted the reception formation classification that enters frame when taking place therein to.Under the situation of connection mode configuration, employed QC is from preceding 4 byte modes.If QC is 00, formation #0 is used so, and is used at the buffer memory descriptor that is begun by BDQ0_BASE indication address.If QC is 01, formation #1 is used so, and is used at the buffer memory descriptor that is begun by BDQ1_BASE indication address.If QC is 10, formation #2 is used so, and is used at the buffer memory descriptor that is begun by BDQ2_BASE indication address.If QC is 11, formation #3 is used so, and is used at the buffer memory descriptor that is begun by BDQ3_BASE indication address.

Whether pattern matching file (PMF) indication QC territory is used to frame is submitted in the memory 130 wherein.For example, if PMF=0 and coupling take place, the QC territory in the default attribute register is used to determine that frame is submitted wherein so.If PMF=1 and coupling take place, so with the match pattern relevant register in the QC territory be used to determine that frame is submitted wherein.

If pattern property register 213 is also write to specify the pattern matching in pattern matching generation and the register 213 to extract the extraction index that will be used when (PME) position is set up and extract length by the user.Extract index (EI) and point to the first interior byte of received frame, begin to extract data from it.Dma controller 210 extracts that territory (PME=1) is set up and the corresponding modes coupling uses this territory to extract when taking place in pattern matching.Under the situation of connection mode configuration (CP=1), employed EI is from the register (for example, the register of first in connection chain) of bottom numeral.Extracting the appointment of length (EL) territory will be from the byte quantity of institute's received frame extraction.Dma controller 210 extracts in pattern matching and uses this territory to extract when territory (PME=1) is set for the corresponding modes coupling.Under the situation of connection mode configuration, be used from the EL of bottom figure pattern property register.If EL is zero, does not extract so and take place.

Fig. 4 is diagram a plurality of exemplary buffer memory BDQ0 of descriptor queue, BDQ1, the BDQ2 block diagram to BDQM.Each buffer memory descriptor queue comprises several buffer memory descriptors, for example to the memory location shown in the BDQ0: BD0 412, BD1 414, BD2 416 to BDN 418.Each buffer memory descriptor queue has ring structure, and accessed via three pointers: BDQ_BASE, BDQ_CURRENT and BDQ_NEXT.Each storage of buffer memory descriptor memory location and the information-related information of institute's received frame that is stored in the memory 130 and/or in the high-speed cache 120.For example, this information comprises state and control 452, data length 454, metadata cache pointer 456, pattern matching state 458, relative index 460, extraction length 462 and the byte count 464 extracted.Each buffer memory descriptor queue can represent the different priorities of respective frame.As shown in Figure 1, buffer memory descriptor queue is stored in the memory 130, and if sometimes BDLWT suitably be provided with and also be stored in the high-speed cache 120.Under the situation that buffer memory descriptor queue can take place in the corresponding extraction of frame data or be not stored in the case.

Fig. 6 is the flow chart of the example operational stream of system shown 100.In case frame is received in operation 610, ADF 230 is determining 620 to determine whether frame should be accepted.The process that is used to accept frame is here further discussed with reference to Fig. 7 to 9 at least.If determining 620 frames not to be accepted, ADF 230 waits for other frame in operation 610 so.If determining 620 frames to be accepted, be provided to from interim formation 234 at operation 630 frames and mode state so and accepted FIFO 220.Frame and mode state be passed to accept FIFO 220 after, be provided to DMA 210 at operation 640 mode states and frame data.In case pattern has been delivered to DMA 210 forward, in operation 650, DMA 210 can be stored in frame data in the memory.In addition, in operation 650, all be extracted and be collected in the high-speed cache 120 with any data of enabling pattern matching in the pattern matching register 233.Being used for process that storage frame data and collection extract frame data is here further discussed with reference to Figure 10 and 11 at least.

Fig. 3 illustrates the exemplary message bag with the frame that can be received by address/data filter 230 in received frame operation 610.Illustrated form and Ethernet/IEEE 802.3 standard message compatibilities.Message 300 comprises preamble, start frame delimiter (SFD) and frame.Preamble and start frame delimiter provide configuration information to receive and processed frame with help system.Preamble is to be used for 1 and 0 synchronous 7 byte field that replace of receiver sequential.For example, each byte contains value 0x55.The beginning of start frame delimiter indication frame.The example value of start frame delimiter is 0xD5 sequence (10101011 binary systems is because the position preface is least important position beginning).The diagram frame has the length of from 64 to 1518 bytes, and comprises 6 byte destination-address (DA), 6 byte source addresses, 2 byte type/length field, 46 to 1500 byte logic link control (LLC) frames and 4 byte frame checking sequences.

The destination-address of frame comprises the 3 bytes sale quotient field and 3 byte user values.First of user's value is independent address (0) or group address (1) with address designation.Whether second indication address is defined (1) or the whole world by local is defined (0).As shown, the source and destination address comprises 48 bits.Other embodiment can use different address sizes, for example in IEEE802.3 specification 16 bit addresses in the older version more.

Type/length field is corresponding to ethernet type territory and/or IEEE 802.3 length field.Type field is illustrated in the agreement of using in the frame remainder (for example TCP/IP).The length of the data division of length field designated frame.Usually, any kind territory of using in length field and the Ethernet is all different, so that the use of Ethernet and IEEE 802.3 frames on identical network.Type field is by being equal to or greater than 1536 (0x0600) but less than the decimal number of 65535 (0xFFFF) sign.If number is between 0 and 1,500 (0x0000 is to 0x05DC), the length of MAC customer data is indicated in this territory so.In the illustrated embodiment, the scope of from 1,501 to 1,536 (0x5DD is to 0x5ff) is indefinite.

Logic link control (LLC) is responsible to provide service and irrelevant with media type to for example network layer of FDDI, Ethernet, token ring etc.The LLC bedding by llc protocol data unit (PDU) between the upper layer of medium access control (MAC) layer territory protocol stack, to communicate by letter.Three variablees are determined the visit in the upper layer via LLC-PDU.Variable comprises destination service access point (DSAP), source service access point (SSAP) and control variables.DSAP is appointed as the address upper layer and provides the unique identifier in the station of protocol information.SSAP provides identical information for source address.

The LLC frame comprises preamble and information field.Preamble comprises DSAP territory, SSAP territory and control domain.Information field comprises data and optional filling.Fill and generally only need be used for during less than 46 eight bit bytes/byte guaranteeing as minimum frame size in 64 eight bit bytes of IEEE 802.3 standard appointments in input.In 802.3x, two eight bit bytes of first of data field be used as command code (OP) (end=0x0001), and second two eight bit byte be used to connection closed time (PT) parameter (intermission=0x0000 be used to open and 0xFFFF be used for by).In addition, the 3rd termination Control Parameter (PTE) that the eight bit byte territory can be used to expand.Replace LLC, ethernet frame can use the different agreement with similar territory.Because the use in these territories changes along with the variation of used agreement, can significantly accelerate ethernet frame and handle so check ability that they also report their contents, and this ability can be enhanced by using pattern matching.

FCS (FCS) is specified 32 Cyclical Redundancy Checks of standard that use standard CC ITT-CRC multinomial to obtain by to all territories except that preamble, SFD and CRC.

Fig. 7 and 8 is the flow charts that illustrate the method for the message hash filtering of using pattern matching.Referring now to Fig. 7, in operation 610, entering frame after interim formation 234 places are received, whether pattern matching logic 232 visit PM registers 233 and the various clauses and subclauses of selective sequential are comprised in the frame information in the interim formation 234 to determine to be stored in pattern in the PM register 233.

For example, ADF 230 checks and comprises that being used for deterministic model mates the ADF world control register that the pattern matching that whether is activated is enabled position (PMEN).If pattern matching is not activated (PMEN=0), process proceeds to group address and determines 715 so.If pattern matching is activated (PMEN is a non-zero), pattern matching process 710 is activated so.If pattern matching process 710 causes frame to be accepted or rejected (describing in further detail with reference to Fig. 9 as following), so process from piece 710 through diagram " acceptances " or " refusal " flow nodes independent one arrive accept among Fig. 8 frame operate 860 or reject frame operate one independent in 870.Frame is accepted or the refusal decision if pattern matching process 710 does not cause making, and flow process arrives above-mentioned group address from pattern matching process 710 through illustrated " not detecting decision/pattern matching " node and determines 715 so.

Determine 715 in group address, receiving unit 180 determines whether the address in institute's received frame is group address.In the embodiment of current discussion, first of user's value of frame is independent address (0) or group address (1) with address designation.If the address is not a group address, flow process proceeds to station address and determines 720.If the address is a group address, flow process proceeds to broadcast address and determines 725.

Determine 720 at station address, receiving unit 180 is by carrying out coming relatively to determine with accurate 48 bits of frame data whether the address in institute's received frame is station address.If it is station address that the address is confirmed as, flow process proceeds to through illustrated " acceptances " flow points from piece 720 and accepts frame operation 860 Fig. 8 so, and frame is operated 806 and is accepted accepting frame.If it is station address that the address is not confirmed as, flow process proceeds to hash and hits and determine 740 so.

Determine 725 in broadcasting, receiving unit 180 determines whether the address in institute's received frame is broadcast address.The exemplary broadcast address is address 0XFFFFFF-FFFFFF.If it is broadcast address that the address is confirmed as, so flow process proceed to broadcasting enable determine 730.If it is broadcast address that the address is not confirmed as, flow process proceeds to above-mentioned hash and hits and determine 740 so.

Determine 730 what broadcasting was enabled, receiving unit 180 determines whether broadcast capability is activated.When ADF world control register-bit BC_REJ was set up, broadcast capability was activated.If broadcast capability is activated, flow process operates 860 from piece 730 through the frame of accepting that illustrated " acceptances " flow nodes arrive Fig. 8 so, and operates 860 frames and be accepted accepting frame.If broadcast capability is not activated, flow process proceeds to and mixes (promiscuous) pattern and determine 735 so.

Determine 735 at promiscuous mode, receiving unit 180 determines whether promiscuous mode is activated.When ADF world control register mixes the position when being set up (PROM=1), promiscuous mode is activated.When receiving unit is in promiscuous mode, also be not accepted by unaccepted all frames of pattern matching.Usually, promiscuous mode is used to detect and seldom use.If promiscuous mode is activated, flow process operates 860 from piece 735 through the frame of accepting that illustrated " acceptances " flow nodes arrive Fig. 8 so, and operates 860 frames and be accepted accepting frame.If promiscuous mode is under an embargo, flow process operates 870 from piece 735 through the reject frame that illustrated " refusal " flow nodes arrive Fig. 8 so, and operates 870 frames at reject frame and be rejected.

Because can determining to walk abreast before 735 or with it at promiscuous mode, pattern matching carries out in operation 710 (perhaps determining 735 accept before the result) at promiscuous mode, can distinguish promiscuous mode can be used, and wherein the frame from all addresses except the one or more particular frames that contain the pattern that causes frame reject all is accepted.For example, particular address can by pattern matching be rejected and simultaneously all other addresses be accepted.

Hit in hash and to determine 740, receiving unit 180 determines whether determine at frame that hash on the address is hit takes place.48 bits determine the address by use 32 bit Cyclical Redundancy Check (CRC) verifications and a part be mapped in 256 casees (in other embodiments or more) one.Referring to for example Figure 12, it illustrates a large amount of CRC 1224 that are used for a large amount of appropriate address 1222 that produced.Each hexadecimal CRC 1224 of each row is corresponding to the 6 byte hexadecimal destination-address of going together mutually in the row 1201 to 1210.

In the setting up procedure of system 100, CRC check and the position be used to index hash table.In one embodiment, 8 bits are used to index 256 casees (bin) table.Higher 3 positions of 8 bit field are used to be chosen in 8 hash bucket registers in independent hash table and/or the group hash table.Higher 5 bit field are selected the position in selected 32 bit register.When the controller received frame, identical verification and being used.If enter the CRC check and the position of selecting to be arranged in group/independent hash table of address, hash is hit and is taken place so.Otherwise, do not have hash to hit generation.

In the illustrated embodiment, preceding 8 bits of CRC are selected the position in the hash table.Address in the row 1201 to 1203 and 1206 will be received by system, and therefore be used to be provided with hash table.Be expert at 1201, hexadecimal value 0x04 is mapped to hash bucket (bucket) case 4.Be expert at 1202, hexadecimal value 0x0F is mapped to hash bucket case 15.Be expert at 1203, hexadecimal value 0x15 is mapped to hash bucket case 21.Be expert at 1206, hexadecimal value 0xCB is mapped to hash bucket case 203.Like this, having the address of selecting bucket case 4,15,21 and 203 any one CRC will be that hash is hit when being received in this address.

The validity of hash table can descend along with the increase of number of addresses.For example, when the number of addresses in being stored in 256 casees hash tables increased, the overwhelming majority in the hash epi-position was set up, thereby prevented that the undesired frame of a minimum part from arriving memory.The speed that an advantage of hash filtering is a hash does not rely on the quantity of address in the destination-address tabulation.Should also be noted that do not have pattern matching and just the agreement of hash can not be used to refuse to mate the frame of one group of selected address because undesired address can be mapped to the identical bits of the refusal that causes being received frame in the hash table.Therefore, hash filtering itself causes faulty filtering, need be to the back filtering of the frame that arrives memory.This can be by illustrating below with reference to the example that is received destination-address shown in Figure 12.

Hit in hash and to determine 740, the CRC that is used for each institute's receiver address is used to select the hash bucket case.If selected case indication is hit, hash is hit and is taken place so.For example, when address 1201 to 1203 and 1206 when any one is received in 1210, in the case 4,15,21 and 203 one selected, and hash is hit and is taken place.Correspondingly, when address 1204 or address 1205 were received, neither one was selected in the case 4,15,21 and 203, and hash is not hit and taken place.Hit when also not taking place when hash, frame typically is rejected.In this manner, address 1204 and 1205 may be rejected.But the address of Figure 12 1207 to 1210 produces hash and hits, but whether wants the address that received and accept by system 100.Therefore, the alternate manner of filtering must be used.

System 100 uses pattern matching to come further filtering to enter the address, makes to processor/be minimized or even be eliminated based on the needs of the back filtering of software.For example, pattern can be stored in the PM register and to make that causing misleading the address that hash hits may be rejected.In the illustrated embodiment, the address is not intended to be used for the concrete merchant of sale ID (preceding 24 bits of destination-address) time at them and can be rejected.The pattern of 0x0050FC04 is stored in the PM register with the PM MASK of 0XFFFFFF00 as PM DATA.In this manner, each address that does not have 0x0050FC in its preceding 24 bits is rejected by pattern matching.In this case, address 1207 to 1209 is rejected, but 1210 are not rejected because it sells the sale merchant ID of merchant ID coupling expectation.

Further pattern can be stored for development.For example, use 2 patterns, have of PM MASK of PM DATA 0x0050FC04 and 0xFFFFFFFF, and second pattern with PM DATA 0x0050FC03-C of 0XFFFFFFFF-F can be used.In this manner, for hash hit but do not have 0x0050FC04 and do not have each address of 0x0050FC03-C at its preceding 36 bits at its preceding 32 bits

Can be by pattern matching and hash and ignored effectively.In this case, address 1207 to 1210 is because pattern matching and hash and refused effectively, and address only likely is accepted by system 100.

Like this, institute's receiver address 1201 to 1210 causes various result.Address 1204 and 1205 causes the hash failure, therefore is not accepted.Address 1201 to 1203 and address 1206 to 1210 cause hash to be hit.So hit and pattern matching owing to the found here hash that causes of first pattern address 1201 to 1203.Therefore address 1201 to 1203 is accepted.So hit and pattern matching owing to the found here hash that causes of second pattern address 1206.Therefore address 1206 is accepted.Address 1207 to 1210 though cause hash to be hit, can not cause pattern matching, because first and second patterns are not found here.Therefore address 1207 to 1210 is not accepted.

Generally speaking, if 32 group addresss are stored in the hash table and the random groups address is received, hash table prevents that the group address frame of significant percentage (for example, in some cases up to 85% even higher) from arriving memory so.When not having current disclosed pattern matching, those that the software of operation will have to that further filtering (back filtering) arrives memory 130 in system 100 with definite they whether contain correct address.In the example in front, address 1207 to 1210 will also need to comprise the processor 110 of back filtering, and the refusal situation that pattern matching is brought out can not be triggered.

Referring now to Fig. 8, to enable in pattern matching and to determine 845, receiving unit 180 determines whether be activated for the pattern matching of the lectotype PM of institute DATA in the selected register.If pattern matching is not activated (PMEN=0), flow process proceeds to hash/mix and determines 855 so.If pattern matching is activated (PMEN=1), pattern matching process 850 is activated so.If pattern matching process 850 causes frame to be accepted or rejected (describing in further detail with reference to Fig. 9 as following), so flow process from piece 850 through the independent arrival illustrated " acceptances " or " refusal " flow nodes accept frame operate 860 or reject frame operate in 870 independent one.If take place but do not have frame acceptance or refuse to determine to be made in pattern matching process 850 pattern matching, if perhaps there is not pattern matching to take place, flow process is not detected through illustrated " not determining/do not have that pattern matching is detected " node arrival pattern matching from pattern matching process 850 and determines 852.

Be not detected referring now to the pattern matching in the illustrated embodiment of current discussion and determine 852, any one all is not detected in 16 patterns of pattern matching if cause, and flow process is from determining 852 to arrive reject frames through illustrated " refusal " flow nodes and operate 870 so.In other embodiments, frame can be retained with by processor 110 further filtering.In the embodiment that changes, frame can the given frame lower priority more detected than its pattern, makes processor 110 lowly be sure of that frame (but hash hit do not have pattern matching) pays close attention to height before earlier and be sure of frame (hash is hit and pattern matching) paying close attention to.In the embodiment of another variation, frame can be stored in the corresponding different queue of different processing units in.At least one is detected in 16 patterns of pattern matching if cause, and flow process is from determining 852 to arrive above-mentioned hash/mix through illustrated " not decision " flow nodes and determine 855 so.To the unit of Fig. 7 of this description and 8 corresponding to the medium access control function.

Determine 855 in hash/mix, no matter pattern matching is being arranged but during not decision (for example, not accepting and refusal not), perhaps when also not having pattern matching, the data link function all is implemented.Whether receiving unit 180 (for example, the state machine among the ADF 230) is determined that fabulous hash is hit and is taken place and/or whether promiscuous mode is activated.Fabulous hash hit uniquely only the hash of a corresponding address hit when all taking place and take place with pattern matching.Contrast, height be sure of that hash hits corresponding to a small amount of address but hit generation when taking place with pattern matching more than the hash of an address.Height be sure of that hash hits owing to used to strengthen and highly be sure of that the address is actually the pattern matching of the possibility of the address of seeking, so the performance than traditional address smoothing enhancing is provided.Using system and/or network characteristic to the careful selection of pattern can make hash hit into fabulous possibility higher.If fabulous hash is hit and is taken place or promiscuous mode is activated, accept operation 860 at frame so, institute's received frame is accepted.If fabulous hash is hit not generation and promiscuous mode is not activated yet, flow process proceeds to complete matching addresses and determines 865 so.

Determine 855 in complete matching addresses, processor 110 determines whether complete matching addresses take place.System 100 carries out the direct comparison of address and system 100 known addresses.System 100 can be stored in institute's receiver address in the priority query, makes that have higher forecasting accepts the address of possibility (height is be sure of frame) to accept the address of possibility (low be sure of address) processed before having low prediction.This complete and direct processing resource that compares with regard to system 100 is very expensive.Therefore, pattern matching described herein and hash attempt to avoid the direct address of this costliness to compare.In this manner, system 100 can use the pattern matching that does not have the direct address comparison as far as possible to come the enhanced system performance, and matching addresses is last method fully.If complete matching addresses is arranged, accept operation 860 at frame so, institute's received frame is accepted.If there is not complete matching addresses, in frame reject operation 870, received frame is rejected so.

Fig. 9 is the flow chart that diagram is used to mate the method for the message addresses that is received by system 100.Whether the pattern matching that can depend on frame takes place and is accepted or rejected.Any part of message frame can be examined the coupling that comprises the IP address.Unless final disposal (accepting or refusal) is determined owing to the generation of another pattern matching before attempting a pattern matching, otherwise when pattern matching is activated (PMEN=1), (for example allow for corresponding modes coupling recipient designator, PMAC=1) each pattern, the operation of Fig. 9 is performed.If the mode data setting is activated, message data is examined pattern matching so.If the pattern matching data are not activated, if perhaps pattern matching does not have foundly, the selected and process of so next pattern is repeated.If continuous search is activated, the search continuation is carried out next pattern and is had nothing to do with coupling so.

With reference to receiving operation 935, the byte that enters frame is received in the interim formation 234 and is used for interim storage, up to being made about the decision of accepting or refusal enters frame.The byte that enters frame also is provided for pattern matching logic 232 and Address Recognition and hash logic 238, makes this decision to be made when byte is just received by interim formation 234.Received after operation 935 is received in byte, flow process advances to pattern matching and determines operation 905.

Reference pattern coupling is determined operation 905, and pattern matching logic 232 is determined to be stored in pattern matching data in the PM register 233 and whether mated data in institute's received frame.For example, the pattern matching logic with the PM DATA in first of PM register 233 with enter frame data and when it is stored in the interim formation 234, compare.Interim formation 234 is used to storage frame and is made up to decision.For example, if each coupling was according to each of the message data of message index MI location during PM was DATA (nearly 4 bytes), pattern matching takes place so.Coupling may occur to gos deep into the skew that vertical frame dimension reaches 256 bytes and has maximum 256 bytes.Some can be by corresponding PM MASK shielding among the PM DATA.Can not be examined coupling when for example, each of PM DATA is eliminated in corresponding PM MASK position.If the connection mode of preceding mode (CP) territory is set up, just think PM DATA territory (the PM DATA of current PMDATA and previous PM register) just generation of coupling when found in frame so.PMAC determines in the territory whether corresponding PM DATA is activated, and if its be activated, so in case mate a series of action and promptly carry out.Operation 905 can walk abreast with operation 935 and finish.

Reference pattern coupling determines 905, and (for example, PMAC=00), flow process advances to End of Frame (EOF) or formation completely determines 930 so if pattern matching is under an embargo.If determine operation in pattern matching, 905 pattern matching do not have found, and flow process also advances to EOF or formation completely determines 930 so.If determining 910, there are pattern matching and pattern matching not to be under an embargo (for example, PMAC ≠ 00), flow process advances to and accepts frame and determine 915 so.

Completely determine 930 with reference to the EOF/ formation, if interim formation 234 is not full and End of Frame also is not received (and frame also is not rejected), continue to be received in the interim formation 234 in reception operation 935 extra bytes so, and flow process advances to the definite operation 905 of pattern matching to start the pattern matching to the frame information of extra reception.If End of Frame has been received or interim formation 234 is full, flow process advances to all nodes of refusal and determines 940 so.

Determine 940 with reference to all nodes of refusal, if ADF 230 is defined in all nodes of refusal, so frame be rejected and the operating process illustrated pattern matching flow process of Fig. 9 that depended on which corresponding flow startup and as Fig. 7 or 8 continue illustrating.If ADF 230 at all nodes of refusal, is not made about the decision of frame so, and the flow process illustrated pattern matching of Fig. 9 that depended on which flow startup and as Fig. 7 or 8 continue illustrating.

Determine 915 with reference to accepting frame, (for example, for concrete PM DATA, PMAC=10), frame is accepted conditionally so, and flow process advances to continuous search and determines 945 if ADF 230 is accepting to be used for the frame of pattern.If ADF 230 does not have to accept to be used for the frame (for example, for concrete PM DATA, PMAC ≠ 10) of pattern now, flow process advances to 920 of reject frame certificate so.

Determine 920 with reference to reject frame, if the frame that ADF 230 is refusing to be used for pattern (for example, for concrete PM DATA, PMAC=11), entering frame so is rejected, because it contains the PM DATA that is associated with refusal PMAC value (perhaps, cause considering the other factors of for example PM MASK, CP etc. and cause mating).Then, the flow process illustrated pattern matching of Fig. 9 that depended on which flow startup and as Fig. 7 or 8 diagrams, continuing.If ADF230 does not have refusal to be used for the frame (for example, for concrete PM DATA, PMAC ≠ 11) of pattern now, flow process advances to continuous search and determines 925 so.

Determine 925 with reference to continuous search, (for example, CSE=1), flow process advances to EOF or formation completely determines 930 so if the continuous search of pattern is activated.If determine 925 in continuous search, search is not activated and (for example, CSE=0), do not made about the decision of previous mode coupling so, and flow process advances to all nodes of refusal and determines 940 continuously.

Determine 945 with reference to continuous search, (for example, CSE=1), flow process advances to EOF or formation completely determines 950 so if the continuous search of pattern is activated.If determine 945 in continuous search, search is not activated and (for example, CSE=0), enters frame so and be accepted continuously.Frame is accepted, because it contains PM DATA (considering that perhaps for example other factorses such as PM MASK, CP cause coupling) and pattern matching is activated (PMAC=10) and do not have further search need finish (CSE=0).Then flow process depend on which flow startup the illustrated pattern matching of Fig. 9 come as Fig. 7 or 8 continues illustrating.

Completely determine 950 with reference to the EOF/ formation,, enter frame so and be accepted if End of Frame has been received or interim formation 234 is full.Frame is accepted because pattern matching takes place, and pattern matching is activated (PMAC=0) so and End of Frame has arrived or the full further pattern matching of interim formation is impossible.Then flow process depend on which flow startup the illustrated pattern matching of Fig. 9 come as Fig. 7 or 8 continues illustrating.

If completely determine 950 in the EOF/ formation, interim formation 234 less than and End of Frame also be not received, be received in the interim formation 234 receiving operation 955 extra bytes so.And flow process advances to pattern matching and determines that operation 960 is to start the pattern matching of extra institute's received frame information to next pattern (for example, the PMDATA in the PM of next one order register 233).Pattern matching determines that operation 960 is similar with aforesaid operation 905 on function.Operation 955 can walk abreast with operation 960 and finish.After pattern matching operation 960, flow process advances to pattern matching and determines 965.

The reference pattern coupling determines 965, if (for example, the PM DATA in the current selected PM register 233) pattern matching is under an embargo, and (for example, PMAC=00), flow process advances to the EOF/ formation and completely determines 950 so for current institute lectotype.If it is found to determine that in pattern matching operation 965 pattern matching do not have, flow process also advances to the EOF/ formation and completely determines 950 so.If determine 965 to have pattern matching and pattern matching not to be under an embargo (for example, PMAC ≠ 00), flow process advances to not that reject frame determines 970 so.

Determine 970 with reference to reject frame not, if ADF 230 for next pattern (for example, corresponding PM DATA) reject frame (for example, PMAC=01 or PMAC=10) not, flow process advances to the EOF/ formation and completely determines 950 so.Otherwise, enter frame and be rejected, because refusal pattern (PMAC=11) is detected.Then flow process depend on which flow startup the illustrated pattern matching of Fig. 9 come as Fig. 7 or 8 continues illustrating.

Referring now to Figure 10, be to be used in the system of Fig. 1, handling the method that is accepted message.An advantage of illustrated embodiment is can be enhanced by when it is received it being detected system's visit of significant data in wrapping, and is used in the high-speed cache visiting faster subsequently and need not to seek help from more senior resource and it is be sure of to be put into descriptor.

Illustrated flow process mode state in receiving mode state of operation 1005 is activated when being provided for DMA 210 and being placed in the status register 215.Afterwards, general, frame data depend on mode state information and are submitted in the memory 130 and/or are collected in the high-speed cache 120.Submission comprises will wrapping in the memory based on packet signature and divides into groups, and extracts the specific part (for example, extracting index and length value by using) that comprises localization package, and takes out to hide and comprise institute extraction data are copied in the processor high speed spatial cache.Extraction can distribute and the locks processor cache memory, but software is responsible for during milking being carried out release by all data in the high-speed cache of DMA index.The data of extracting from frame data, do not removed; But all frame data are stored in the memory, and have only the data of extraction to be copied in the processor high speed buffer memory.This submission and collection are discussed in further detail below.

With reference to selecting buffer memory descriptor operation 1010, the BDFP 214 of DMA 210 selects the buffer memory descriptor based on the mode state in the pattern matching property register 213 and formation classification (QC) territory.The QC territory determines to use which buffer memory descriptor queue 122/132.Mode state is included in the pointer in suitable QC territory.When having pattern matching to take place, which pattern matching mode state also indicates take place.If pattern matching takes place, the pattern of being mated can make data be extracted from frame and be collected in the high-speed cache 120 as extracting data 124 so.Like this, except buffer memory descriptor 132, buffer memory descriptor queue 122 is also selected.If there is not pattern matching to take place, do not extract so and will take place, thereby cause having only buffer memory descriptor queue 132 to be used.After selecting buffer memory descriptor operation 1010, flow process advances to extracts beamhouse operation 1015.

Extracting beamhouse operation 1015, if mode state pointing-type coupling is extracted engine 212 so and obtained extracting index (EI) and extract length (EL) from pattern property register 213.After extracting beamhouse operation 1015, flow process advances to BDQ can be with determining 1020.

Can be with reference to BDQ with determining 1020, BDFP 214 determines whether selected buffer memory descriptor queue (BDQ) is available.That is, BDFP 214 determines whether free space is arranged in selected BDQ.If selected BDQ can use, flow process advances to through flow nodes " A " and upgrades BDQ pointer operation 1030 so.If selected BDQ is unavailable, flow process advances to flushing operation 1025 so, so frame and status frames length are rinsed out from receive FIFO 220, and flow process advances to receiving mode state of operation 1005.

Reference is BDQ pointer operation 1030 more, and BDFP 214 upgrades buffer memory descriptor current pointers (BDQ_CURRENT) to point to next buffer memory descriptor queue (BDQ_CURRENT=BDQ_NEXT).After current BDQ pointer was updated, it was that sky determines 1035 that flow process advances to BDQ.

With reference to BDQ is that sky determines 1035, and BDFP 214 determines whether the clauses and subclauses of being pointed to by BDQ_CURRENT are empty.If current BDQ clauses and subclauses non-NULL is marked as unavailablely so in the selected buffer memory of the unavailable operation of mark 1040 descriptor queue, and flow process advances to flushing operation 1025.If current BDQ clauses and subclauses are empty, flow process advances to transfer operation 1045 so.

With reference to transfer operation 1045, BDFP 214 is sent to reception buffer memory 211 with frame data from receiving FIFO 220.It is full that transmission continues to be received or to receive buffer memory 211 up to End of Frame (EOF).After frame data were transmitted, flow process advanced to EOF and determines 1050.

Determine 1050 with reference to EOF, if be not received at operation 1045 End of Frames, flow process advances to selective extraction and collection operation 1060 so.If be received at operation 1045 End of Frames, flow process advances to and obtains status frames size operation 1055 so, extracts engine 212 1055 and obtain status frames length from status register 215.After operation 1055, flow process advances to selective extraction and collection operation 1060.

In selective extraction and collection operation 1060, data are controllably extracted from institute's received frame is used for being collected in high-speed cache 120.Selective extraction and collection operation 1060 are more completely described with reference to Figure 11 below.After selective extraction and collection operation 1060, flow process advances to EOF and determines 1065.

Determine 1065 with reference to EOF, if be received at selective extraction and collection operation 1060 End of Frames, flow process advances to EOF and upgrades operation 1080.If be not received at selective extraction and collection operation 1060 End of Frames, flow process advances to buffer memory ending (EOB) and determines 1070 so.

Upgrade operation 1080 with reference to EOF, state and control information that BDFP 214 upgrades in the current cache descriptor queue.For example, the generation of the extraction among the BDFP 214 current BDQ 122 position is set to indicate the data of extracting 124 to be stored in the high-speed cache 120.Next BDQ pointer (BDQ_NEXT) is set to point to the next position among the selected BDQ.The content of current BDQ is copied in the high-speed cache according to BDLWT.For example, if pattern matching takes place, and if BDLWT be 00, do not distribute so to be carried out; If BDLWT is 10, high-speed cache 120 row are assigned with so; If BDLWT is 11, high-speed cache 120 row are assigned with and are locked so.After EOF upgraded operation 1080, flow process advanced to receiving mode state 1005, makes that more data can be processed according to next frame.

Determine 1070 with reference to EOB, if in selective extraction and collection operation 1060, the ending of metadata cache 134 is run in the memory 130, and flow process advances to EOB renewal operation 1075 so.If in selective extraction and collection operation 1060, the ending of metadata cache is not run into, flow process advances to aforesaid transfer operation 1045 so.

Upgrade operation 1075 with reference to EOB, BDFP 214 upgrades the state and the control information of current cache descriptor queue.For example, the generation of the extraction among the BDFP 214 current BDQ 122 position is set to indicate the data of extracting 124 to be stored in the high-speed cache 120.Next BDQ pointer (BDQ_NEXT) is set to point to the next position among the selected BDQ.The content of current BDQ is copied in the high-speed cache according to BDLWT.After EOB upgraded operation 1075, flow process advanced to node A, makes that more data can be processed according to identical frame.

Figure 11 is that diagram is used for using 64 byte buffer memorys to extract and collect the flow chart of the method for a message part by the system of Fig. 1.Illustrated method is by the selective extraction of Figure 10 with take out and hide operation 1060 and call among Figure 11.

With reference to Figure 11, be requested to determine 1105 in extraction, extract engine 212 and determine whether be requested for given pattern matching extraction.Extract engine 212 and also check various extractions territory, for example extract addition (EX_ADD) territory and extract length (EL) territory.Extracting the addition territory equals to extract length and adds corresponding extraction index (for example, EXADD=EL+EI[11: 15]).Be requested (PME=1) if extract, extract additive value greater than 0, and extract length greater than 0, flow process advances to EI≤64 and determines 1125 so.Be not requested if extract, extracting additive value is 0, and perhaps extracting length is 0, and flow process advances to aim at and determines 1110 so.

Determine 1110 with reference to aiming at, if destination address is not 64 byte-aligned addresses, flow process advances to and sends MAX (32B) operation 1120, is sent to memory 130 in 1120 normal data that are 32 bytes to the maximum.MAX (32B) be up to and comprise the byte quantity (for example, wherein x is a byte quantity, MAX (xB)≤x byte) of 32 bytes.If destination address is 64 byte alignment addresses, flow process advances to and sends MAX (64B) operation 1120 so, and here the MAX of normal data (64B) is sent to memory 130.After sending MAX (32B) operation 1115 or sending MAX (64B) operation 1120, extract flow process and withdraw from, and the EOF that flow process advances to Figure 10 determines 1065.

Determine 1125 with reference to EI≤64, if extract index greater than 64, the data that are extracted are not also arrived that flow process advances to and sends MAX (64B) operation 1130,1130, the MAX of normal data (64B) is sent to memory 130.After sending MAX (64B) operation 1130, (for example, EI=EI-64), and extract flow process and withdraw from, the EOF that flow process advances to Figure 10 determines 1065 to be deducted 64 at subtraction EI operation 1135 extraction index.

Determine 1125 referring again to EI≤64, be less than or equal to 64 if extract index, flow process advances to the relative EI operation 1140 of storage.Relatively extract index and be the index that is extracted the position that data begin to locate in the memory 130 in the metadata cache.Relatively extract index by BDFP 214 storage inside to DMA 210, be written to suitable BDQ in memory 130 and/or the high-speed cache operating 1075 or 1080 (Figure 10) afterwards up to it.In the relative EI operation 1140 of storage, flow process advances to EI≤32 and determines 1145.

Determine 1145 with reference to EI≤32, extract engine 212 and carry out and the comparison of extracting index, and check by storage inside extraction data markers in extracting engine 212 for example in DMA 210.For example, if extract index greater than 32, and it is non-true to extract data markers, and flow process advances to and sends MAX (32B) operation 1150, is sent to memory 130 at the MAX of 1150 normal data (32B).After sending MAX (32B) 1150, to extract data markers and be set to very, the extraction flow process withdraws from, and the EOF that flow process advances to Figure 10 determines 1065.

Determine 1145 referring again to EI≤32, be less than or equal to 32 if extract index, perhaps extract data markers for true, flow process advances to less than 32B and determines 1160 so.(for example, EX_ADD 〉=32B), flow process advances to and sends 32B operation 1170 so, is sent to memory 130 and is copied to high-speed cache 120 according to ELCWT in 1,170 32 bytes of extracting data if at least 32 bytes that have data are extracted from institute's received frame.For example, if ELCWT is 00, do not distribute so to be carried out; If ELCWT is 01, does not extract so and take place; If ELCWT is 10, cache line is assigned with so; If ELCWT is 11, cache line is assigned with and is locked so.If being less than 32 bytes and will extracting that (for example, EX_ADD＜32B), flow process advances to the operation 1165 of rounding off so, and in 1165EX_ADD value of being rounded to 32, and flow process is advanced further to and sends 32B and operate 1170 from the institute received frame of data arranged.

After sending 32B operation 1170, flow process advances to subtraction 1175,1175 extract extracted 32 byte section by deducting in the addition territories quantity (for example, EX_ADD=EX_ADD-32).After subtraction 1175,, extract data markers in clear operation 1180 so and be eliminated if End of Frame (EOF) is if arrived or EX_ADD=0.After clear operation 1180, extract flow process and withdraw from, the EOF that flow process advances to Figure 10 determines 1065.

In one embodiment, the part of message frame is received at MAC 190 places of packet controller 160 by system 100.(referring to, Fig. 1 and Fig. 6, operation 610).Institute's receiving unit of message frame (" institute's received frame ") is provided for the interim formation 234 of address/data filter 230 among Fig. 2.Frame is handled to determine whether it should be accepted or rejected by address/data filter 230.(referring to Fig. 6, operation 620) Address Recognition, hash, on institute's received frame, be carried out by Address Recognition and hash logic 238 and pattern matching logic 232 with the hash of fabulous hash and pattern matching (Fig. 7 to 9) by pattern matching.The complete direct address that Address Recognition and hash logic 238 are carried out hash and any necessity compares.PM register 233 comprises and the corresponding a large amount of registers of a large amount of patterns that will mate.Pattern matching logic 232 is carried out pattern matching (for example, by continuous search and/or concatenation ability) based on the Configuration Values that is stored in the PM register 233.If be accepted after pattern matching and hash or the adjusting of other failure safe, institute's received frame and mode state information (pattern matching result) are sent to and receive FIFO 220 (seeing Fig. 6, operation 630) so.

Institute's received frame is sent to then and receives buffer memory 211, and the pattern matching state information is sent to the status register 215 of DMA 210.(referring to Fig. 6, operation 640.) extract engine 212 access module property registers 213 and whether status register 215 should extract from the institute's received frame receiving buffer memory 211, and control being extracted as of this data and can use with specified data.(referring to Figure 10 and 11.) BDFP Access status register 215 and buffer memory descriptor address register, and produce the address and the data message that will be written to memory 130 and/or high-speed cache 120.From the address information of BDFP 214 comprise be used for frame data in the metadata cache the metadata cache pointer (for example, metadata cache pointer (456)) (one or more) pointer of one is (for example in the clauses and subclauses or below pointing in the buffer memory descriptor queue, BDQ_BASE, BDQ_CURRENT, BDQ_NEXT).Data message comprises the state shown in Fig. 4 and control 452, data length 454, metadata cache pointer 456, pattern matching state 458, relative index 460, extraction length 462 and the byte count 464 extracted.

All or part of of frame corresponding descriptor in respective cache descriptor queue 132/122 then is submitted in the memory 130 (" normal data ") and/or is collected in (" extraction data ") in the high-speed cache 120.(referring to Fig. 6, operation 650, and Figure 10 and 11).More specifically; receive buffer memory 211 normal or extraction frame data are offered Bus Interface Unit (BIU) 170; the extraction engine offers attribute frame data is designated BIU 170 normal or that extract, and BDFP 214 offers BIU 170 with address information and buffer memory descriptive data from buffer memory descriptor address register 216.BIU 170 is delivered to bus 140 with frame data and is used for being stored in high-speed cache 120 and/or memory 130.Normal frame data is stored at least one metadata cache 134, and the descriptive data relevant with normal frame data is stored in the buffer memory descriptor queue 132.Take place if extract, extract frame data so and be stored (" collection ") in cache part 124, and the descriptive data relevant with extracting frame data is stored in the buffer memory descriptor queue 122.

Top description is intended to describe at least one embodiment of the present invention.Top description is not intended to limit scope of the present invention.In fact, limit in the scope of the present invention claim below.Like this, other embodiments of the invention comprise above-described various changes, modification, increase and/or improvement.

An embodiment has incorporated a kind of pattern matching of new model into, its allow user to up to 16 4 bytes, can be connected with the pattern that forms long pattern more and can be used to mate the part of frame in preceding 256 bytes and programme.What be associated with each pattern is can be programmed with acceptance/reject frame, be submitted in the memory frame in one of four formations and the frame data that extracted write one group of attribute in the high-speed cache of processor.The pattern matching ability comprise support to up to 16 4 byte unique pattern, based on by turn pattern matching, be deep in the frame matching range up to 256 bytes, up to the skew of 256 bytes, 4 bytes to being increased to programmable pattern size, when coupling is detected, accepting or refusal and be used for the accurately unicast address up to 8 of coupling up to 64 bytes.

This embodiment combines the use of the power of pattern matching and hash filtering to provide not to be needed back filtering and can finish and the Address Recognition method that need not interfere at the further software of logic link control level in the MAC level.Quickening a method that frame handles and be to increase any destination-address that just in time hits hash table actual is be sure oing of one of address of seeking of system.Because will have the CRC of identical 8 most significant bits more than one address, thus have the extra process that the use of the hash table of pattern matching provides remarkable increase to finish on hash is hit (search address and with its with effective destination-address tabulation relatively) method of effortless probability.This is of great value, and the extra memory bus use of engine is hit in undesired hash table because this has reduced.Can also be subjected to the restriction of the fact that hash table validity descends with the increase of address quantity by the number of addresses of hash.Because the user at first sets up hash table and because will lower usually by the number of addresses of hash (32 to 64), so can cover its address if not all also being most sharing model than being easier to find.Use a small amount of pattern matching register, the user just can guarantee to expect any territory in the formation all be hit and can need not comparison sheet just can be processed.

In one embodiment, if CRC check and be chosen in the position that is provided with in group/individual hash table, frame is just accepted unsettled pattern matching result conditionally so.Sell merchant's code, for example, can be used as the pattern that to mate very efficiently.It is just effective more that pattern fastidious more (still less position be used), height be sure of that hash is hit the formation method.Have very fastidious pattern, can be used in that number of addresses in the hash table can be increased and still effective.Though being hash itself, another advantage of this embodiment can not be used to reject frame, do not refused the risk of frame, but the pattern matching and the hash filtering of combination can be used to carry out " by the frame reject of hash ", because the uncertainty of hash collision has been eliminated.Another flexibility is that the user can be submitted to the frame of pattern matching and hash refusal in " high probability do not match formation ", makes frame can be examined the validity with further substantive approach.

As described herein, the various control logics of ADF 230 are distributed between the unit of above-mentioned ADF 230, and are not illustrated as independent logical block.Replacedly, independent control logic piece can comprise the state machine of typical example as being used to control ADF 230 all operations, comprise pattern matching and hash function.This state machine can comprise and is used to realize a large amount of states of institute's describing function here.For example, state machine can be received the state from stupefied state-transition to mode state when being accepted with frame in data.Under the state of mode state, mode state is be sure of to be caught can use receiving FIFO 220.State machine can be converted to the interim queuing data stage then, and wherein, institute's received frame is transmitted from interim formation 234.State machine is the state of incoming frame state then, and wherein, frame length that is associated with destination-address filtering and state (for example, broadcast address, group/individual address, promiscuous mode) are sent to and receive FIFO 220.Other state and state machine can be realized according to function described herein.

In one embodiment, be used for that the method for processing messages is provided in information processing system.Information processing system has memory, high-speed cache and packet controller.Each all is coupled to packet controller memory and high-speed cache.This method comprises reception message and message is carried out pattern matching whether comprise the pattern matching result of first pattern so that the indication received message to be provided, and the pattern matching attribute corresponding to first pattern is provided.Method also comprises based on the pattern matching result to be accepted message and selects buffer memory descriptor queue (BDQ).Message is stored in memory according to selected BDQ, and at least a portion that is accepted message is optionally stored into high-speed cache, and wherein, a described part that is accepted message is indicated by the pattern matching attribute.

In another embodiment, the pattern matching attribute is indicated among a plurality of BDQ and first pattern corresponding one and selected BDQ.In another embodiment, with the corresponding pattern matching attribute of first pattern default BDQ is designated as selected BDQ.In another embodiment, message is accepted based on the pattern matching result.

In another embodiment, the pattern matching attribute provides pattern matching to extract designator, and a described part that is accepted message is extracted designator based on pattern matching and optionally stored into high-speed cache.A described part that is accepted message is extracted the designator indication in pattern matching and is extracted for first pattern and be activated and/or can be stored in high-speed cache when being under an embargo.The pattern matching attribute can provide to extract index and extract length and be stored in that part of of high-speed cache with what indication was accepted message.The described part that the pattern matching attribute can also be indicated is corresponding with first pattern, be used to carry out to be accepted message stores the high-speed cache of high-speed cache into and writes type.

In another embodiment, information processing system comprises a plurality of processors that are coupled to memory and high-speed cache, and each has the BDQ of distribution in the processor.Pattern matching result indicates in a plurality of processors to come processing messages.In another embodiment, pattern matching result indication and the corresponding priority of message.

In another embodiment, at least a portion of selected BDQ is stored in high-speed cache.The pattern matching attribute can indicate the high-speed cache that stores high-speed cache into the corresponding at least a portion that is used to carry out with selected BDQ of first pattern to write type.

In another embodiment, the step that message is carried out pattern matching comprises determining whether first pattern is present in message, by first pattern of modulus matched data indication, have in the pattern matching data of corresponding modes coupling control, and whether exist in response to definite first pattern, the pattern matching result based on pattern matching control is provided.Pattern matching control can comprise concatenating indicator, and whether its first pattern of indicating is the connection of a plurality of patterns.Pattern matching control can comprise continuous search designator, and whether it indicates continuous search to be activated.Pattern matching control can comprise the reversing mode indicators, wherein, when the reversing mode indicators had first value, whether pattern matching result's first pattern of indicating was present in the message, and when the reversing designator had second value, pattern matching result's first pattern of indicating was not present in the message.

In another embodiment, information processing system comprises memory, high-speed cache and is coupled to memory and the packet controller of high-speed cache.Packet controller comprises the input that is used to receive message, store the pattern matching register of a plurality of patterns, the pattern property register of each corresponding pattern matching attribute in storage and a plurality of patterns, be coupled and be used for message is carried out pattern matching and is used to provide the indication received message whether to comprise the pattern matching result's of a plurality of pattern first patterns pattern matching logic, be coupled the reception buffer memory that is used for when received message is accepted the storage received message, and be coupled and be used for and be accepted message is provided to high-speed cache from least a portion that receives buffer memory and be provided to memory and be used for being accepted message Memory Controller.A described part that is accepted message is by indicating with the corresponding pattern matching attribute of first pattern.

In another embodiment, be accepted message and be provided to memory according to selected BDQ.Selected BDQ can be among a plurality of BDQ one and by with the corresponding pattern matching attribute indication of first pattern.Memory Controller can be coupled at least a portion that is used for selected BDQ and be provided to high-speed cache.The pattern matching attribute can indicate the high-speed cache that stores high-speed cache into the corresponding at least a portion that is used to carry out with selected BDQ of first pattern to write type.

In another embodiment, be provided for indicating with the corresponding pattern matching attribute of first pattern and be accepted message and be provided for that part of extraction index of high-speed cache and extract length.In another embodiment, a part that is used to carry out to be accepted message with the indication of the corresponding pattern matching attribute of first pattern high-speed cache that stores high-speed cache into is write type.

In another embodiment, method comprises receiving message and determining whether be detected in received message with corresponding first pattern matching of first pattern.First pattern is by pattern matching data indications, and has corresponding pattern matching designator and designator is enabled in corresponding search continuously.When first pattern matching is detected and corresponding pattern matching when accepting the designator indication and accepting to have the received message of first pattern that is detected, received message is enabled designator and is accepted by selectivity based on corresponding search continuously.

In another embodiment, receive message and comprise at least a portion that receives bag.Bag can also be characterized as the Ethernet bag.

In another embodiment, when first pattern matching was detected and accepts accepting of designator indication received message with the corresponding pattern matching of first pattern, received message had not been accepted during search continuously with the corresponding continuous search designator indication of first pattern.

In another embodiment, when first pattern matching is detected and accepts accepting of designator indication received message with the corresponding pattern matching of first pattern, received message with the corresponding continuous search designator indication of first pattern search and being accepted when being detected continuously with corresponding second pattern matching of second pattern, the corresponding modes that institute's second pattern matching has a refusal of not indicating received message is mated and is accepted designator.Second pattern can be indicated by the pattern matching data, and accepts the designator indication with the corresponding pattern matching of second pattern and accept received message and neither accept also not refuse one of received message.Accept designator with the corresponding pattern matching of second pattern and can indicate and accept received message and neither accept also not refuse one of received message, and pattern matching is under an embargo for second pattern.

In another embodiment, when first pattern matching is detected and accepts accepting of symbol indication received message with the corresponding pattern matching of first pattern, received message is not accepted when being detected with the corresponding continuous search of continuous search designator indication of first pattern and with corresponding second pattern matching of second pattern, and described second pattern has the corresponding modes coupling of the refusal of indication received message and accepts designator.

In another embodiment, corresponding pattern matching accepts that the designator indication is accepted, refusal and neither accepting is not refused in the received message one yet.Refuse information when in another embodiment, method is included in also that first pattern matching is detected and accepts the refusal of designator indication received message with the corresponding pattern matching of first pattern.

In another embodiment, first pattern has corresponding reversing mode indicators, and first pattern matching is detected when received message comprises first pattern when the reversing mode indicators has first value, and first pattern matching is detected when received message does not comprise first pattern when the reversing mode indicators has second value.

In another embodiment, first pattern has the corresponding match index of determining the position whether first pattern matching is detected in the indication received message.

In another embodiment, first pattern has corresponding concatenating indicator.Method also comprises determines that second pattern matching detects in whether in received message.Message is enabled designator based on corresponding search continuously and is optionally accepted when first pattern matching and second pattern matching are detected, and accept the acceptance that designator is indicated received message with the corresponding pattern matching of first pattern, and indicate being connected of first and second patterns with the corresponding concatenating indicator of first pattern.When second pattern matching was not detected and indicates being connected of first and second patterns with the corresponding concatenating indicator of first pattern, first pattern matching was considered to not be detected.

In another embodiment, method comprises whether carry out hash function takes place to determine that hash is hit, wherein when hash is hit generation, first pattern matching is detected, and accept the acceptance that designator is indicated received message with the corresponding pattern matching of first pattern, enable designator based on corresponding search continuously and optionally accept message.

In another embodiment, method comprises receiving whether corresponding first pattern matching of first pattern is detected in message and definite and a plurality of patterns in received message.First pattern has corresponding pattern matching and accepts designator.Method also comprise determine with a plurality of patterns at least one corresponding concatenating indicator when first pattern matching is detected, whether indicate and be connected.Method first pattern that also is included in be detected and a plurality of pattern in described at least one concatenating indicator indication when connecting, determine with a plurality of patterns in corresponding second pattern matching of second pattern in received message, whether be detected.Concatenating indicator is corresponding to one in first and second patterns, and second pattern has corresponding pattern matching and accepts designator.Received message when first pattern matching is detected based on accepting designator with the corresponding pattern matching of first pattern and at least one is optionally accepted with the corresponding pattern matching of second pattern is accepted in the designator, be connected with corresponding concatenating indicator indication in first and second patterns, and second pattern matching is detected.

In another embodiment, with the corresponding pattern matching of first pattern accept designator indication use the acceptance of the message of first mode treatment, refusal and neither accept also not refuse in one, and with the corresponding pattern matching of second pattern accept the designator indication use the acceptance of the message of second mode treatment, refusal and neither accept also not refuse in one.

In another embodiment, a concatenating indicator and pattern matching described pattern matching of accepting to be used in the designator optionally to accept received message is accepted the designator both corresponding in first pattern and second pattern identical one.

In another embodiment, when first pattern matching is detected, be connected with corresponding concatenating indicator indication in first and second patterns, and when second pattern matching is detected, based on the corresponding pattern matching of first pattern accept designator and with the corresponding pattern matching of second pattern accept in the designator at least one the refusal received message.

In another embodiment, wherein, first pattern has corresponding reversing mode indicators and second pattern has corresponding reversing mode indicators, and wherein: when having first value with the corresponding reversing mode indicators of first pattern, first pattern matching is not detected when received message does not comprise first pattern, and when having second value with the corresponding reversing mode indicators of first pattern, first pattern matching is detected when received message comprises first pattern; When having first value with the corresponding reversing mode indicators of second pattern, second pattern matching is not detected when received message does not comprise second pattern, and when having second value with the corresponding reversing mode indicators of second pattern, second pattern matching is detected when received message comprises second pattern.

In another embodiment, when first pattern matching and second pattern matching were detected, first pattern occurred in received message after second pattern.In another embodiment, receive message and comprise at least a portion that receives bag.In another embodiment, wherein, bag is further shown as the Ethernet bag.

In another embodiment, first pattern has the corresponding match index that is used to indicate the primary importance of determining in the received message whether first pattern matching is detected in received message, and second pattern has the corresponding match index that is used to indicate the second place of determining in the received message whether second pattern matching is detected in received message.

In another embodiment, when first pattern matching was detected, the concatenating indicator of at least one indication connected in a plurality of patterns, and second pattern matching is detected, and received message is accepted.

In another embodiment, when first pattern matching is detected, the concatenating indicator of at least one indication connects in a plurality of patterns, and second pattern matching is when being detected, and received message is optionally accepted based on the continuous search designator that indicates whether to search for continuously.

In another embodiment, packet controller comprises input, pattern matching logic and the control logic that receives message.The pattern matching logical response determines whether be detected in received message with corresponding first pattern matching of first pattern in receiving message.The pattern matching logic comprises at least one pattern matching register of the pattern matching data that are arranged to storage indication first pattern, and storage comprises the pattern matching control of accepting designator and enabling designator with the corresponding continuous search of first pattern with the corresponding pattern matching of first pattern.Control logic is coupled to the pattern matching logic.In operating process, control logic is optionally accepted received message based on enabling designator with the corresponding continuous search of first pattern when first pattern matching is detected, and accepts the acceptance that designator is indicated received message with the corresponding pattern matching of first pattern.

In another embodiment, control logic is not accepted received message when searching for continuously with the corresponding continuous search designator indication of first pattern, and accepts the acceptance that designator is indicated received message with the corresponding pattern matching of first pattern.

In another embodiment, when first pattern matching is detected and accepts accepting of designator indication received message with the corresponding pattern matching of first pattern, control logic is accepted received message in following situation: with the corresponding continuous search designator indication of first pattern search continuously, and be detected with corresponding second pattern matching of second pattern, described second pattern is by the indication of pattern matching data and have by the corresponding modes coupling of the pattern matching control indication of the refusal of not indicating received message and accept designator.

In another embodiment, when first pattern matching is detected and accepts accepting of designator indication received message with the corresponding pattern matching of first pattern, control logic is not accepted received message in following situation: with the corresponding continuous search designator indication of first pattern search continuously, and be detected with corresponding second pattern matching of second pattern, described second pattern is indicated by the pattern matching data and is had the corresponding modes coupling of being indicated by the pattern matching control of the refusal of indicating received message and accepts designator.

In another embodiment, corresponding pattern matching accept acceptance, the refusal of designator indication received message and neither accept also not refuse in one.

In another embodiment, pattern matching control comprises and the corresponding reversing mode indicators of first pattern, and wherein when reversing mode indicators when having first value, first pattern is detected when received message comprises first pattern; When the reversing mode indicators had second value, first pattern matching was not detected when received message does not comprise first pattern.

In another embodiment, pattern matching control comprise corresponding with first pattern, be used in reference to and be shown in the match index of determining the position whether first pattern matching is detected in the received message.

In another embodiment, wherein: pattern matching control comprises and the corresponding concatenating indicator of first pattern; The pattern matching control logic determines whether second pattern matching is detected in received message; And control logic is detected with second pattern matching in first pattern matching, enable designator based on corresponding search continuously when accepting the acceptance of designator indication received message with the corresponding pattern matching of first pattern and indicating being connected of first and second patterns with the corresponding concatenating indicator of first pattern optionally accepts message, and thinks that first pattern matching is not detected when second pattern matching is not detected and indicates being connected of first and second patterns with the corresponding concatenating indicator of first pattern.

In one embodiment, packet controller comprises input, pattern matching logic and the control logic that receives message.The pattern matching logic determines whether be detected and whether be detected with corresponding second pattern matching of second pattern with corresponding first pattern matching of first pattern in received message.The pattern matching logic comprises at least one pattern matching register.The pattern matching register-stored is indicated the pattern matching data of first pattern and second pattern.The pattern matching register also store comprise with the corresponding pattern matching of first pattern accept designator, with the corresponding pattern matching of second pattern accept designator, with the corresponding concatenating indicator of first pattern and with the pattern matching control information of the corresponding concatenating indicator of second pattern.Control logic be coupled to the pattern matching logic be detected in first pattern matching, second pattern is detected and when being connected with corresponding concatenating indicator indication in first and second patterns, based on accepting designator with the corresponding pattern matching of first pattern and accepting designator with the corresponding pattern matching of second pattern and optionally accept received message.

In another embodiment, with the corresponding pattern matching of first pattern accept designator and with the corresponding pattern matching of second pattern accept in the designator one and with first and second patterns in corresponding concatenating indicator both corresponding in first pattern and second pattern identical one.In another embodiment, when first pattern matching was detected, second pattern matching is not detected and be connected with corresponding concatenating indicator indication in first and second patterns, control logic was not accepted received message.

In another embodiment, pattern matching control comprise with the corresponding reversing mode indicators of first pattern and with the corresponding reversing mode indicators of second pattern, and wherein: when having first value with the corresponding reversing mode indicators of first pattern, first pattern matching is not detected when received message does not comprise first pattern, and, when having second value with the corresponding reversing mode indicators of first pattern, first pattern matching is detected when received message comprises first pattern; And when having first value with the corresponding reversing mode indicators of second pattern, second pattern matching is not detected when received message does not comprise second pattern, and, when having second value with the corresponding reversing mode indicators of second pattern, second pattern is detected when received message comprises second pattern.

In another embodiment, pattern matching control comprises with first pattern is corresponding being used to indicate to be used in the received message determining whether first pattern matching is detected the mode index of residing primary importance in received message, and with second pattern corresponding be used to indicate be used in the received message determining whether second pattern matching is detected the mode index of the residing second place in received message.In another embodiment, control logic is detected in first pattern matching, is connected with corresponding concatenating indicator indication in first and second patterns and second pattern matching is accepted received message when being detected.In another embodiment, pattern matching control comprise with first pattern and second pattern in a corresponding continuous search enable designator, wherein, control logic is detected in first pattern matching, the concatenating indicator indication of at least one connects and second pattern matching when being detected in a plurality of pattern, enables designator and accepts designator with the corresponding pattern matching of first pattern and at least one optionally accepts received message with the corresponding pattern matching of second pattern is accepted in the designator based on continuous search.

To understand, architecture described herein is an exemplary, realizes that in fact many other architectures of identical function can be implemented.Summary but the arrangement that is used to realize any part of identical function on the still very definite meaning " be associated " effectively and make the function of expectation be implemented.Therefore, being used to of combination here any two parts of realizing concrete function can be counted as each other " being associated " and make function of expectation be implemented, and irrelevant with architecture or mid portion.Any two parts that are associated equally, like this can also be considered to be each other " can be operatively connected " or " but operational coupled " to realize desired function.

Person of skill in the art will appreciate that the border between the logical block is illustrative, and interchangeable embodiment can merge logical block or circuit element or various logic piece or circuit element are carried out interchangeable Function Decomposition.In addition, alternative embodiment can make up a plurality of examples of concrete part.

In addition, person of skill in the art will appreciate that the border between the aforesaid operations function is illustrative.The function of a plurality of operations can be combined into single operation, and/or the function of single operation can be assigned in the extra operation.In addition, alternative embodiment can comprise the multiple situation of concrete operations, and operating sequence can be changed in various other embodiment or even parallel carrying out.

Because foregoing detailed description is an exemplary, so as " embodiment " when being described, it is the embodiment of exemplary.Therefore, the use of word " " is not intended to indicate one and have only an embodiment can have described feature in this context.But many other embodiment can and have the feature of describing of exemplary " embodiment " usually.Therefore, when as above using, when the present invention was described in the context of an embodiment, this embodiment was among the many possibilities of the present invention embodiment.

Though above-mentioned warning relevant for the use of word " embodiment " in detailed description, if but those skilled in the art will understand in the claim element claim below of introducing of specific quantity and be meant, so this meaning will be enunciated in the claims, and just do not have this restriction to exist when not having this narration or meant.For example, in the claim below, when right requires element to be described to have " one " feature, should be restricted to one and be unique of the feature of describing with meaning this element.But, when right requires to be described to comprise in the element claim below or comprises " one " feature, do not mean element and should be restricted to one and be unique of the feature of describing.But, for example, comprise that the claim of " one " feature is understood to include the device or the method for one or more features of being discussed.That is, because device of being discussed or method comprise feature, whether pipe unit or method do not comprise another this similar feature so claim is interpreted as device or method.Word " one " as to this use of the nonrestrictive introducing hat speech of claim feature here the defending party to the application be adopted as with the past be consistent by the explanation of being adopted by many law courts, though may find opposite case law any abnormality or precedent.Similarly, when right requires to be described to comprise in the element claim below or (for example to comprise above-mentioned feature, " described " feature) time, meaning refers to element should not be restricted to one and be accidental unique of using the feature of describing by definite article only.

In addition, in the claim for example the use of the introducing phrase of " at least one " and " one or more " introducing that should not be interpreted as another the claim element of hint by indefinite article " " any concrete claim that will contain the claim element of this introducing be restricted to the invention that only comprises a this element, even when identical claim comprises the indefinite article of introducing property phrase " one or more " or " at least one " and for example " ".The use of definite article too.

Though specific embodiments of the invention are shown and described, will be obviously for those skilled in the art, based on the instruction here, various improvement, replaceable structure and replacement of equal value can be used and not break away from the invention that will protect here.The result is that claims comprise all this changes, modification etc. in their scope, as long as they are in true spirit of the present invention and scope.And, will understand the present invention and only be defined by the following claims.Above description be not intended to provide exhaustive to the embodiment of the invention.Unless statement clearly in addition, each example given here all is nonrestrictive or non exhaustive example, and no matter whether nonrestrictive, non exhaustive term or similar term are expressed in each example simultaneously.Though attempted summarizing some exemplary embodiment and to its exemplary variations, other embodiment and/or distortion also as below in the invention scope that claim limited.

Claims

1. method that is used for processing messages in information processing system with memory, high-speed cache and packet controller, each of described memory and high-speed cache all is coupled to packet controller, and described method comprises:

Receive message;

Message is carried out pattern matching whether comprise the pattern matching result of first pattern, and provide and the corresponding pattern matching attribute of first pattern so that the indication received message to be provided;

Accept message;

Select buffer memory descriptor queue (BDQ) based on the pattern matching result;

According to selected buffer memory descriptor queue with message stores to memory; And

Optionally at least a portion with acceptance message stores high-speed cache into, and wherein, the described part of the message of accepting is indicated by the pattern matching attribute.

2. the process of claim 1 wherein that the pattern matching attribute is indicated in a plurality of buffer memory descriptor queue with first pattern corresponding one, wherein, in a plurality of buffer memory descriptor queue described one corresponding to selected buffer memory descriptor queue.

3. the process of claim 1 wherein, default buffer memory descriptor queue is designated as selected buffer memory descriptor queue with the corresponding pattern matching attribute of first pattern.

4. the method for claim 1, wherein, the pattern matching attribute supplies a pattern to mate and extracts designator, wherein, optionally the described part of acceptance message is stored into and be based on pattern matching in the high-speed cache and extract that designator carries out, and wherein, the described part of the message of accepting is stored in high-speed cache when pattern matching extraction designator indication extraction is activated for first pattern, and the described part of the message of accepting is not stored in high-speed cache when pattern matching extraction designator indication extraction is under an embargo for first pattern.

5. the method for claim 4, wherein, the pattern matching attribute provides and extracts index and extract the described part of length in order to high-speed cache that indication is accepted to be stored in the message.

6. the method for claim 4, wherein, the indication of pattern matching attribute and first pattern be corresponding to be used to carry out the high-speed cache that a described part with acceptance message stores high-speed cache into and to write type.

7. the method for claim 1, wherein, information processing system comprises a plurality of processors that are coupled to memory and high-speed cache, and each in the described processor has the buffer memory descriptor queue that is assigned with, and wherein the pattern matching result indicates and is used for of processing messages in a plurality of processors.

8. the process of claim 1 wherein pattern matching result's indication and the corresponding priority of message.

9. the method for claim 1 comprises that also at least a portion with selected buffer memory descriptor queue stores high-speed cache into.

10. the method for claim 9, wherein, the indication of pattern matching attribute and first pattern be corresponding to be used to carry out the high-speed cache that described at least a portion with selected buffer memory descriptor queue stores high-speed cache into and to write type.

11. the process of claim 1 wherein, message is carried out pattern matching comprise:

Determine whether first pattern is present in the message, described first pattern is by the indication of pattern matching data, and the pattern matching data have corresponding pattern matching control; And

Whether exist in response to definite first pattern, control the matching result that supplies a pattern based on pattern matching.

12. the method for claim 11, wherein, pattern matching control comprises whether indication first pattern is the concatenating indicator of the connection of a plurality of patterns.

13. the method for claim 11, wherein, pattern matching control comprises the continuous search the designator whether continuous search of indication is activated.

14. the method for claim 11, wherein, pattern matching control comprises the reversing mode indicators, wherein, when the reversing mode indicators has first value, whether pattern matching result's first pattern of indicating is present in the message, and when the reversing mode indicators had second value, whether pattern matching result's first pattern of indicating was not present in the message.

15. the process of claim 1 wherein that message is accepted based on the pattern matching result.

16. an information processing system comprises:

Memory;

High-speed cache;

Be coupled to the packet controller of memory and high-speed cache, described packet controller comprises:

Be used to receive the input of message;

Store the pattern matching register of a plurality of patterns;

The pattern property register of each corresponding pattern matching attribute in storage and a plurality of patterns;

The pattern matching logic, it is coupled and is used for message is carried out pattern matching and is used to provide the indication received message whether to comprise the pattern matching result of a plurality of pattern first patterns;

Be coupled the reception buffer memory that is used for storage received message when received message is accepted; And

Memory Controller, be coupled and be used for and offer memory from the message of accepting that receives buffer memory and to be used at least a portion of acceptance message is offered high-speed cache, wherein, the described part of the message of accepting is by indicating with the corresponding pattern matching attribute of first pattern.

17. the information processing system of claim 16, wherein, institute's message of accepting is offered memory according to selected buffer memory descriptor queue.

18. the information processing system of claim 17, wherein, selected buffer memory descriptor queue is in a plurality of buffer memory descriptor queue, and by with the corresponding pattern matching attribute indication of first pattern.

19. the information processing system of claim 17, wherein, Memory Controller is coupled at least a portion that is used for selected buffer memory descriptor queue and offers high-speed cache.

20. the method for claim 19, wherein, pattern matching attribute indication and first pattern be corresponding to be used to carry out the high-speed cache that described at least a portion with selected buffer memory descriptor queue stores high-speed cache into and to write type.

21. the information processing system of claim 16, wherein, with the corresponding pattern matching attribute of first pattern be provided for indicating accept to be provided in the message high-speed cache a described part the extraction index and extract length.

22. the information processing system of claim 16 wherein, is used for carrying out the high-speed cache that a described part with acceptance message stores high-speed cache into the indication of the corresponding pattern matching attribute of first pattern and writes type.

23. a method comprises:

Receive message;

Determine whether to be detected in received message with corresponding first pattern matching of first pattern, wherein, first pattern is by the indication of pattern matching data and have that corresponding pattern matching is accepted designator and designator is enabled in corresponding search continuously; And

When first pattern matching is detected and corresponding pattern matching when accepting the designator indication and accepting to have the received message of detected first pattern, enable designator based on corresponding search continuously and optionally accept received message.

24. the method for claim 23 wherein, receives message and comprises at least a portion that receives bag.

25. the method for claim 24, wherein, bag also is characterized as the Ethernet bag.

26. the method for claim 23, wherein, when first pattern matching is detected and accepts accepting of designator indication received message with the corresponding pattern matching of first pattern, do not accepting received message continuously during search with the corresponding continuous search designator indication of first pattern.

27. the method for claim 23 wherein, when first pattern matching is detected and accepts accepting of designator indication received message with the corresponding pattern matching of first pattern, is accepted received message in following situation:

With the corresponding continuous search designator indication of first pattern search continuously, and

Be detected with corresponding second pattern matching of second pattern, second pattern has the corresponding modes coupling of the refusal of not indicating received message and accepts designator.

28. the method for claim 27, wherein, second pattern by pattern matching data indications and with the corresponding pattern matching of second pattern accept the designator indication accept received message and neither acceptance do not refuse in the received message one yet.

29. the method for claim 27 wherein, accepts designator indication with the corresponding pattern matching of second pattern and accept received message, neither accept also not refuse in the received message one, and pattern matching is under an embargo for second pattern.

30. the method for claim 23 wherein, when first pattern matching is detected and accepts accepting of designator indication received message with the corresponding pattern matching of first pattern, is not accepted received message in following situation:

Be detected with corresponding second pattern matching of second pattern, second pattern has the corresponding modes coupling of the refusal of indication received message and accepts designator.

31. the method for claim 23, wherein, corresponding pattern matching accept acceptance, the refusal of designator indication received message and neither accept also not refuse in one.

32. the method for claim 23 also comprises:

When first pattern matching is detected and accepts the refusal of designator indication received message with the corresponding pattern matching of first pattern, refuse information.

33. the method for claim 23, wherein, first pattern has corresponding reversing mode indicators, and wherein:

When the reversing mode indicators had first value, first pattern matching was detected when received message comprises first pattern;

When the reversing mode indicators had second value, first pattern matching was not detected when received message does not comprise first pattern.

34. the method for claim 23, wherein, first pattern has the corresponding match index of determining the position whether first pattern matching is detected in the indication received message.

35. the method for claim 23, wherein, first pattern has corresponding concatenating indicator, and described method also comprises:

Determine whether second pattern matching is detected in received message, wherein:

When first pattern matching is detected with second pattern matching, accepts the acceptance of designator indication received message with the corresponding pattern matching of first pattern and indicates being connected of first and second patterns with the corresponding concatenating indicator of first pattern, enable designator based on corresponding search continuously and optionally accept message, and

When second pattern matching was not detected and indicates being connected of first and second patterns with the corresponding concatenating indicator of first pattern, first pattern matching was considered to not be detected.

36. the method for claim 23 also comprises:

Whether carry out hash function takes place to determine that hash is hit, wherein, when hash is hit generation, first pattern matching is detected and accept accepting of designator indication received message with the corresponding pattern matching of first pattern, enable designator based on corresponding search continuously and optionally accept message.

37. a method comprises:

Receive message;

Determine with a plurality of patterns in corresponding first pattern matching of first pattern in received message, whether be detected, wherein, first pattern has corresponding pattern matching and accepts designator;

When first pattern matching is detected, determine with a plurality of patterns at least one corresponding concatenating indicator whether indicate and be connected;

When first pattern matching be detected and a plurality of pattern in described at least one concatenating indicator indication when connecting, determine with a plurality of patterns in corresponding second pattern matching of second pattern in received message, whether be detected, wherein, concatenating indicator has corresponding pattern matching corresponding to one in first and second patterns and second pattern and accepts designator; And

When first pattern matching is detected, is connected with a corresponding concatenating indicator indication in first and second patterns and second pattern matching when being detected, based on accepting designator with the corresponding pattern matching of first pattern and at least one optionally accepts received message with the corresponding pattern matching of second pattern is accepted in the designator.

38. the method for claim 37, wherein, with the corresponding pattern matching of first pattern accept designator indication use the acceptance of the message of first mode treatment, refusal and neither accept also not refuse in one, and with the corresponding pattern matching of second pattern accept the designator indication use the acceptance of the message of second mode treatment, refusal and neither accept also not refuse in one.

39. the method for claim 37, wherein, the described pattern matching that concatenating indicator and pattern matching accept to be used in the designator optionally to accept received message is accepted designator all corresponding in first pattern and second pattern identical one.

40. the method for claim 37, wherein, when first pattern matching is detected, is connected with a corresponding concatenating indicator indication in first and second patterns and second pattern matching when being detected, based on accepting designator with the corresponding pattern matching of first pattern and at least one refuses received message with the corresponding pattern matching of second pattern is accepted in the designator.

41. the method for claim 37, wherein, first pattern has corresponding reversing mode indicators and second pattern has corresponding reversing mode indicators, and wherein:

When having first value with the corresponding reversing mode indicators of first pattern, first pattern matching is not detected when received message does not comprise first pattern, and when having second value with the corresponding reversing mode indicators of first pattern, first pattern matching is detected when received message comprises first pattern; And

When having first value with the corresponding reversing mode indicators of second pattern, second pattern matching is not detected when received message does not comprise second pattern, and when having second value with the corresponding reversing mode indicators of second pattern, second pattern is detected when received message comprises second pattern.

42. the method for claim 37, wherein, when first pattern matching and second pattern matching were detected, first pattern occurred in received message after second pattern.

43. the method for claim 37 wherein, receives described message and comprises at least a portion that receives bag.

44. the method for claim 43, wherein, bag also further is characterized as the Ethernet bag.

45. the method for claim 37, wherein, first pattern has the corresponding match index of determining the primary importance that whether first pattern matching is detected in received message in the indication received message, and second pattern has the corresponding match index of determining the second place that whether second pattern matching is detected in received message in the indication received message.

46. the method for claim 37, wherein, when first pattern matching is detected, the concatenating indicator indication of at least one connects and second pattern matching when being detected in a plurality of pattern, received message is accepted.

47. the method for claim 37, wherein, when first pattern matching is detected, the concatenating indicator indication of at least one connects and second pattern matching when being detected in a plurality of pattern, received message is optionally accepted based on the continuous search designator that indicates whether to search for continuously.

48. a packet controller comprises:

Be used to receive the input of message;

Definite pattern matching logic that in received message, whether is detected with corresponding first pattern matching of first pattern, wherein, the pattern matching logic comprises that the pattern matching data of storage indication first pattern and storage comprise with the corresponding pattern matching of first pattern and accepts designator and enable at least one pattern matching register of the pattern matching control of designator with the corresponding continuous search of first pattern; And

Control logic, it is coupled to the pattern matching logic, when it is detected and accepts accepting of designator indication received message with the corresponding pattern matching of first pattern in first pattern matching, optionally accept received message based on enabling designator with the corresponding continuous search of first pattern.

49. the packet controller of claim 48, wherein, control logic is not having search continuously, first pattern matching is being detected and is accepting to accept when designator is indicated accepting of received message received message with the corresponding pattern matching of first pattern with the corresponding continuous search designator indication of first pattern.

50. the packet controller of claim 48, wherein, when first pattern matching was detected and accepts accepting of designator indication received message with the corresponding pattern matching of first pattern, control logic was accepted received message in following situation:

Be detected with corresponding second pattern matching of second pattern, described second pattern is indicated by the pattern matching data and is had the corresponding modes coupling of being indicated by the pattern matching control of the refusal of not indicating received message and accepts designator.

51. the packet controller of claim 48, wherein, when first pattern matching was detected and accepts accepting of designator indication received message with the corresponding pattern matching of first pattern, control logic was not accepted received message in following situation:

Be detected with corresponding second pattern matching of second pattern, described second pattern is indicated by the pattern matching data and is had the corresponding modes coupling of being indicated by the pattern matching control of the refusal of indicating received message and accepts designator.

52. the packet controller of claim 48, wherein, corresponding pattern matching accept acceptance, the refusal of designator indication received message and neither accept also not refuse in one.

53. the packet controller of claim 48, wherein, pattern matching is controlled and is comprised and the corresponding reversing mode indicators of first pattern, and wherein:

54. the packet controller of claim 48, wherein, pattern matching control comprises and the corresponding match index that is shown in the position that whether definite first pattern matching is detected in the received message that is used in reference to of first pattern.

55. the packet controller of claim 48, wherein:

Pattern matching control comprises and the corresponding concatenating indicator of first pattern;

The pattern matching logic determines whether second pattern matching is detected in received message; And

Control logic is detected with second pattern matching in first pattern matching, enable designator based on corresponding search continuously when accepting the acceptance of designator indication received message with the corresponding pattern matching of first pattern and indicating being connected of first and second patterns with the corresponding concatenating indicator of first pattern optionally accepts message, and thinks that first pattern matching is not detected when second pattern matching is not detected and indicates being connected of first and second patterns with the corresponding concatenating indicator of first pattern.

56. a packet controller comprises:

Be used to receive the input of message;

The pattern matching logic of determining in received message, whether to be detected and whether being detected with corresponding second pattern matching of second pattern with corresponding first pattern matching of first pattern, wherein, the pattern matching logic comprises that the pattern matching data of storage indication first pattern and second pattern and storage comprise with the corresponding pattern matching of first pattern and accepts designator, accept designator with the corresponding pattern matching of second pattern, with the corresponding continuous designator of first pattern and with at least one pattern matching register of the pattern matching of the corresponding concatenating indicator of second pattern control; And

Control logic, it is coupled to the pattern matching logic, it is detected in first pattern matching, second pattern matching is detected and when a corresponding concatenating indicator indication in first and second patterns is connected, based on accepting designator with the corresponding pattern matching of first pattern and at least one optionally accepts received message with the corresponding pattern matching of second pattern is accepted in the designator.

57. the packet controller of claim 56, wherein, with the corresponding pattern matching of first pattern accept designator and with the corresponding pattern matching of second pattern accept in the designator described one and with first and second patterns in a corresponding concatenating indicator all corresponding in first and second patterns identical one.

58. the packet controller of claim 56, wherein, when first pattern matching is detected, second pattern matching is not detected and when a corresponding concatenating indicator indication in first and second patterns was connected, control logic was not accepted received message.

59. the packet controller of claim 56, wherein, pattern matching control comprises with first pattern reverses mode indicators and reverse mode indicators accordingly with second pattern accordingly, and wherein:

60. the packet controller of claim 56, wherein, pattern matching control comprises and the corresponding match index that is used to indicate the primary importance of determining in the received message whether first pattern matching is detected in received message of first pattern, and with the corresponding match index that is used to indicate the second place of determining in the received message whether second pattern matching is detected in received message of second pattern.

61. the packet controller of claim 56, wherein, when first pattern matching is detected, is connected with a corresponding concatenating indicator indication in first and second patterns and second pattern matching when being detected, control logic is accepted received message.

62. the packet controller of claim 56, wherein, pattern matching control comprise with first and second patterns in a corresponding continuous search enable designator, wherein, when first pattern matching is detected, at least one concatenating indicator indication in a plurality of pattern connects and second pattern matching when being detected, control logic is enabled designator and based on accepting designator and accept in the designator at least one with the corresponding pattern matching of second pattern with the corresponding pattern matching of first pattern, is optionally accepted received message based on continuous search.