CN1859015A - Receiver circuit, differential signal receiver circuit, interface circuit, and electronic instrument - Google Patents
Receiver circuit, differential signal receiver circuit, interface circuit, and electronic instrument Download PDFInfo
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- CN1859015A CN1859015A CN 200610076547 CN200610076547A CN1859015A CN 1859015 A CN1859015 A CN 1859015A CN 200610076547 CN200610076547 CN 200610076547 CN 200610076547 A CN200610076547 A CN 200610076547A CN 1859015 A CN1859015 A CN 1859015A
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Abstract
A receiver circuit (100), which is connected with a partner transmitter circuit (200) through a signal line (250) and receives a signal based on current which flows through the signal line (250), includes a current/voltage conversion circuit (120) which converts the current which flows through the signal line (250) into voltage, a power supply circuit (140) which adjusts the current which flows through the signal line based on a bias voltage (Vb) and voltage of a node (NDX) connected with the signal line, and a bias voltage generation circuit (130) which outputs the bias voltage (Vb) which is adjusted in connection with characteristics of the power supply circuit (140).
Description
Technical field
The present invention relates to receiving circuit, differential signal receiver circuit, interface circuit and electronic equipment.
Background technology
In recent years, as (Electro Magnet Interference: electromagnetic interference) noise etc. is the interface of purpose, and (Low Voltage Differntial Signaling: the low-voltage differential signal transmission technology) etc. high speed serial transmission interface receives much attention LVDS to reduce EMI.In this high speed serial transmission interface, for example transtation mission circuit sends serialized data by differential wave (DifferentialSignals), the differential amplification differential wave of receiving circuit, thus realize transfer of data.
Therefore, receiving circuit comprises the differential amplifier circuit that is used to amplify each signal that constitutes differential wave.And, by amplifying the differential voltage between above-mentioned each voltage of signals and the bias voltage, detect each signal that minor variations takes place.
But, in the differential amplifier circuit of existing receiving circuit, in case after determining the current potential of transmission medium, the bias voltage corresponding with its current potential also determined by unique.Therefore, in order to apply stable bias voltage to receiving circuit, be the voltage that takes place in the constant voltage generation circuit and make bias voltage.The formation of this constant voltage generation circuit for example is disclosed in patent documentation 1 to patent documentation 3.
Patent documentation 1: the spy opens flat 5-143181 communique
Patent documentation 2: the spy opens flat 5-191167 communique
Patent documentation 3: the spy opens flat 5-191168 communique
But,, consider the manufacture deviation of the composed component of differential amplifier circuit simultaneously, thereby bias voltage be set than the highland in order to guarantee the supply voltage scope of differential amplifier circuit.That is, improve bias voltage, and improve the transistorized current driving ability of burning film semiconductor (Metal Oxide Semiconductor: metal-oxide semiconductor (MOS) abbreviates MOS below as) that constitutes differential amplifier circuit.Therefore, be difficult to make differential amplifier circuit more moving under the low-voltage, thereby situation signal, data delivery more at a high speed of the little amplitude of transmission occurs needing to realize.
Like this, even the stable constant voltage bias voltage as the differential amplifier circuit that amplifies received signal is provided,, certainly lead to the problem of the operation margin of differential amplifier circuit also along with requirement to high speed transmission of signals.Therefore, for realizing high speed transmission of signals, the operation margin that how to reduce differential amplifier circuit becomes very important.
And above-mentioned problem is not only the problem of the high speed transmission of signals of differential wave, also is the problem of signal transmission of the high speed of single-ended signal.
Summary of the invention
In view of above-mentioned defective, the object of the present invention is to provide and to realize receiving circuit, differential signal receiver circuit, interface circuit and the electronics setting that signal at a high speed receives with the low-voltage action.
For addressing the above problem, the present invention is connected with the other side's transtation mission circuit by holding wire, based on the receiving circuit of the electric current received signal of the described holding wire of flowing through, it comprises: current-to-voltage converting circuit, and the described current conversion that is used for the described holding wire of flowing through is a voltage; Power circuit, the voltage of basic bias voltage and the node that is connected with described holding wire, the flow through electric current of described holding wire of adjustment; And bias voltage generating circuit, being used to export described bias voltage, the characteristic interlock of described bias voltage and described power circuit also is adjusted.
According to the present invention, need be based on the flow through electric current of holding wire of the voltage adjustment of fixing bias voltage of current potential and holding wire.Therefore, the characteristic (for example transistorized current driving ability) of the composed component of the power circuit that causes in for example process variations when making etc. during with design not simultaneously, bias voltage generating circuit can produce the bias voltage of its current potential of adjusted.At this moment, the current potential of holding wire also changes, even but the current potential of lower holding wire, because power circuit can detection signal and is adjusted the electric current of the holding wire of flowing through, so even if the characteristic of the composed component of power circuit changes, by the bias voltage corresponding with its variation is provided, thereby bigger nargin (margin) current potential also can be set and make the power circuit action.Thus, can keep the high speed of power circuit, detect the signal in the holding wire of electronegative potential more.
And in receiving circuit involved in the present invention, described power circuit comprises: first electric current is adjusted transistor, is connected with described current-to-voltage converting circuit with described node; And first and second differential transistor, it is differential right to constitute, its each drain current Be Controlled, described first differential transistor, its grid is connected with described node, and its drain electrode adjusts transistorized grid with described first electric current and is connected, the described bias voltage of supply on the grid of described second differential transistor, also can according to described first or the drain current of second differential transistor produce described bias voltage.
According to the present invention, because the output node of holding wire and output output voltage can separate, so can reduce the capacity of the holding wire that drives transtation mission circuit.Therefore, can reduce the capacity that should drive transtation mission circuit.And, can reduce the amplitude of the signal of holding wire, and detect the variation of signal at high speed.
And, in receiving circuit involved in the present invention, described bias voltage generating circuit comprises the bias voltage generation transistor of the conductivity type identical with the conductivity type of described second differential transistor, and described bias voltage transistorized grid takes place is connected with the grid of drain electrode with described second differential transistor.
And, in receiving circuit involved in the present invention, described first and second differential transistor of described bias voltage generation transistor AND gate is formed on the same substrate, adjusts described bias voltage generation transistor drain electric current according to the drain current of described first and second differential transistor.
And, according to receiving circuit of the present invention, described power circuit comprise each drain current of adjusting described first and second differential transistor and second electric current adjust transistor, described bias voltage generating circuit comprises that the 3rd electric current that is used to produce with the proportional electric current of described bias voltage generation transistor drain electric current adjusts transistor, adjusts to provide on the transistorized grid with described second electric current at described the 3rd electric current and adjusts the identical voltage of transistorized grid voltage.
And in receiving circuit according to the present invention, described bias voltage generating circuit comprises: it is identical with the conductivity type of described second differential transistor that transistorized conductivity type takes place for bias voltage generation transistor, described bias voltage; And electric current adjustment transistor, adjust described bias voltage generation transistor drain electric current.
According to the invention of above-mentioned either side, can be with corresponding with variation according to the current driving ability of each transistorized manufacture deviation of bias voltage generating circuit according to the variation of the current driving ability of the manufacture deviation of first and second differential transistor of power circuit.Therefore, can more correctly adjust the current potential of bias voltage.Therefore, can omit nargin current potential (margin potential also can be called the surplus current potential) or littler nargin current potential only is set for bias voltage just passable.
And according to differential signal receiver circuit of the present invention, comprising: first receiving circuit is connected on first holding wire of formation by the differential signal line of transtation mission circuit current drives; Second receiving circuit is connected on the secondary signal line that constitutes described differential signal line; And comparator, based on the output of described first and second receiving circuit, output signal output, at least one of described first and second receiving circuit is above-mentioned each described receiving circuit.
And, according to differential signal receiver circuit of the present invention, described first and second receiving circuit is above-mentioned each described receiving circuit, described comparator compares voltage of being changed by the current-to-voltage converting circuit of described first receiving circuit and the voltage of being changed by the current-to-voltage converting circuit of described second receiving circuit, exports described output signal.
According to above-mentioned invention, can provide the differential signal receiver circuit of realizing receiving at a high speed differential wave with the low-voltage action.
And, the invention still further relates to interface circuit, described interface circuit comprises: above-mentioned each described receiving circuit is connected by described received signal line on the transtation mission circuit of the other side's device of current drives received signal line; And transtation mission circuit, be connected on the receiving circuit of the other side's device by sending holding wire, and the described transmission holding wire of current drives.
According to foregoing invention, the interface circuit that comprises differential signal receiver circuit can be provided, this differential signal receiver circuit is realized the transmitting-receiving of differential wave at a high speed with the low-voltage action.
In addition, the invention still further relates to a kind of like this interface circuit, comprising: above-mentioned differential signal receiver circuit, by described first holding wire, be connected on the differential wave transtation mission circuit of the other side's device of current drives first holding wire, above-mentioned first holding wire constitutes differential signal line; And the differential wave transtation mission circuit, be connected the differential signal receiver circuit of the other side's device and the described secondary signal line of current drives by the secondary signal line that constitutes described differential signal line.
The invention still further relates to electronic equipment, comprising: above-mentioned interface circuit; And communicator, processor, camera head, and display unit at least one.
According to the present invention, can provide the electronic equipment of interface circuit of realizing the transmitting-receiving of signal at a high speed with low-voltage action.
Description of drawings
Fig. 1 is the formation generalized schematic according to the interface circuit of the single-ended signal of present embodiment.
Fig. 2 is the formation generalized schematic according to the receiving circuit of present embodiment.
Fig. 3 (A) is the schematic diagram of an example that produces the circuit of bias voltage Vb as a comparative example.Fig. 3 (B) is the key diagram of the action power voltage of receiving circuit.
Fig. 4 is the circuit diagram of first configuration example of the receiving circuit of Fig. 2.
Fig. 5 is the sequential chart of action example of the receiving circuit of Fig. 4.
Fig. 6 is the circuit diagram of second configuration example of the receiving circuit of Fig. 2.
Fig. 7 is the circuit diagram of the 3rd configuration example of the receiving circuit of Fig. 2.
Fig. 8 is the generalized schematic of formation of interface circuit of the differential wave of present embodiment.
Fig. 9 is the generalized schematic of formation of the differential signal receiver circuit of present embodiment.
Figure 10 is the circuit diagram of first configuration example of the differential signal receiver circuit of Fig. 9.
Figure 11 is the sequential chart of action example of the differential signal receiver circuit of Figure 10.
Figure 12 is the circuit diagram of second configuration example of the differential signal receiver circuit of Fig. 9.
Figure 13 is the circuit diagram of the 3rd configuration example of the differential signal receiver circuit of Fig. 9.
Figure 14 is the block diagram of configuration example of the electronic equipment of present embodiment.
Embodiment
Below, embodiments of the present invention will be described in detail with reference to the accompanying drawings.In addition, the embodiment that the following describes limits improperly to record content of the present invention within the scope of the claims.And the whole of the formation that the following describes may not be to constitute necessary important document of the present invention.
Receiving circuit in the present embodiment described below is applicable to the receiving circuit of single-ended signal or the receiving circuit of differential wave.
1. the interface circuit of single-ended signal
1.1 interface circuit
Fig. 1 shows the formation summary of the interface circuit of single-ended signal in the present embodiment.In addition, in the present embodiment, host apparatus 10 is ends of supplying with clock signal, and destination apparatus 30 is that the clock signal that will supply with is used as clock signal of system and an end of action.
In Fig. 1, DTO is the data (OUT data) of host apparatus 10 (broadly being device) to destination apparatus 30 (broadly being device) output.CLK is the clock signal that host apparatus 10 is supplied with to destination apparatus 30.Host apparatus 10 is exported DTO synchronously with the edge (rising edge, trailing edge) of CLK.Therefore, destination apparatus 30 can use the CLK sampling and catch DTO.And in Fig. 1, destination apparatus 30 is based on provide the clock signal clk that comes to move from host apparatus 10.That is, CLK is the clock signal of system of destination apparatus 30.Therefore, at device PLL (Phase Locked Loop: circuit 12 (broadly being clock signal generating circuit) phase-locked loop), and the PLL circuit is not set is set in 10 in destination apparatus 30.
DTI is the data (IN data) of destination apparatus 30 to host apparatus 10 outputs.STB is the gating signal (broadly being clock signal) that destination apparatus 30 is supplied with to host apparatus 10.Destination apparatus 30 generates STB and output based on the CLK that supplies with from host apparatus 10.And destination apparatus 30 is synchronous with the edge (rising edge, trailing edge) of STB, output DTI.Therefore, host apparatus 10 can use the STB sampling and catch DTI.
Transtation mission circuit (drive circuit) by current drives and DTO, CLK, DTI, STB corresponding respectively holding wire (broadly being serial signal line), send DTO, CLK, DTI, STB respectively.
The interface circuit 20 of host apparatus 10 comprise OUT transmission with (broadly for transfer of data with) transtation mission circuit 22,, the clock signal transmission with transtation mission circuit 24, IN transmission with (broadly for transfer of data with) receiving circuit 26 and gating signal transmission with (broadly transmit and use) receiving circuit 28 for clock signal.The interface circuit 40 of destination apparatus 30 comprise OUT transmission with receiving circuit 42, clock signal transmission with receiving circuit 44 and IN transmission with transtation mission circuit 46, gating signal transmission with transtation mission circuit 48.In addition, its structure also can not comprise the part in these circuit modules.
The OUT transmission sends DTO, CLK by the holding wire of current drives DTO, CLK with transtation mission circuit 22, clock signal transmission respectively with transtation mission circuit 24.OUT transmission is carried out current/voltage conversion based on the electric current of the holding wire of the DTO that flows through, CLK with receiving circuit 42, clock signal transmission respectively with receiving circuit 44, by the voltage that carries out obtaining and the comparison process (differential processing and amplifying) of bias voltage, can detect and receive DTO, CLK by current/voltage conversion.
IN transmission is transmitted with transtation mission circuit 48 with transtation mission circuit 46, gating signal and is sent DTI, STB by the holding wire of current drives DTI, STB respectively.IN transmission is transmitted with receiving circuit 28 respectively based on the electric current of the holding wire of the DTI that flows through, STB with receiving circuit 26, gating signal, carry out the current/voltage conversion, by the voltage that carries out obtaining and the comparison process (differential processing and amplifying) of bias voltage, and receive DTI, STB by current/voltage conversion.
Like this, interface circuit can comprise: receiving circuit is connected by the transtation mission circuit of received signal line with the other side's device that is used for current drives received signal line; And transtation mission circuit, be connected with the receiving circuit of the other side's device by sending holding wire, and current drives sends holding wire.In interface circuit shown in Figure 1 20,40, comprise two transtation mission circuits and two receiving circuits.
1.2 receiving circuit
Fig. 2 shows the formation summary of receiving circuit in the present embodiment.Carry with receiving circuit 28, OUT transmission receiving circuit 42 and clock signal conveys receiving circuit 44 as IN conveying receiving circuit 26, the gating signal of Fig. 1, can adopt the receiving circuit of Fig. 2.
Receiving circuit 100 is connected with holding wire 250 by this transtation mission circuit 200 current drives.Receiving circuit 100 comprises power circuit 140, current-to-voltage converting circuit 120 and bias voltage generating circuit 130.Power circuit 140 can comprise differential amplifier circuit 110.At this moment, the differential voltage of the voltage of differential amplifier circuit 110 amplifying signal lines 250 and bias voltage Vb.Herein, reflection for the transmission signals that prevents holding wire 250, the power circuit 140 of receiving circuit 100 is connected on the holding wire 250 by the impedance matching resistance R, this impedance matching resistance R has the impedance identical with the characteristic impedance of holding wire 250, can be arranged on for example outside of receiving circuit 100.
Current-to-voltage converting circuit 120 will be driven by the current driving circuit 210 of transtation mission circuit 200, and the current conversion of the holding wire 250 of flowing through is a voltage.Current-to-voltage converting circuit 120 is output as the output voltage V out corresponding with reception result.
Bias voltage generating circuit 130 produces bias voltage Vb.More particularly, bias voltage generating circuit 130 output offset voltage Vb, the characteristic of this bias voltage Vb and power circuit 140 (as the characteristic (static characteristic) of the MOS transistor of the composed component of power circuit 140 (differential amplifier circuit etc.)) links and is adjusted.This bias voltage generating circuit 130 can produce the adjustable bias voltage of its current potential.
Like this, in the present embodiment, the bias voltage that is fixed based on its current potential and the voltage of holding wire 250 can not carry out unwanted electric current adjustment.Therefore, for example since the current driving ability of the MOS transistor of the formation power circuit 140 that the operation change when making etc. cause during with design not simultaneously, bias voltage generating circuit 130 can the produce adjusted bias voltage Vb of current potential.At this moment, the transmission medium current potential of holding wire 250 also changes, even but power circuit 140 also can detection signal under lower transmission medium current potential.When establishing the wide W of being of transistorized raceway groove, when raceway groove length was L, this transistorized current driving ability can be expressed as W/L.
The key diagram of the action power voltage of Fig. 3 (A) and Fig. 3 (B) expression receiving circuit.
Shown in Fig. 3 (B), the action power voltage of receiving circuit 100 is the voltage between hot side supply voltage VDD and the low potential side supply voltage VEE.For example, as the transmission medium potential range VR of the scope of the transmission medium current potential of holding wire 250, utilize with given current potential be benchmark up and down the peak value of oscillatory signal determine.
Because in this transmission medium potential range VR, detect the signal that current potential changes, provide the bias voltage Vb of the manufacture deviation of having considered this composed component to differential amplifier circuit.Fig. 3 (A) is cut apart the voltage between hot side supply voltage VDD and the low potential side supply voltage VEE by two permanent circuits, thereby generates bias voltage circuit diagram Vb, as a comparative example.As transmission medium potential range VR during by hot side border current potential VRu and low potential side border current potential VRd regulation, bias voltage Vb only is set to the voltage than the high nargin current potential of hot side border current potential VRu Vm.
Like this, even when causing that owing to the variation of manufacturing process etc. the current driving ability that constitutes the differential amplifier circuit MOS transistor reduces, also can detect the signal that in the transmission medium potential range VR of regulation, changes.
But, in above-mentioned action power voltage, needing nargin current potential Vm, the nargin between the hot side supply voltage VDD and bias voltage Vb reduces so for example often have, and differential amplifier circuit can not be kept situation at a high speed.Therefore, setting or fuse by register value open circuit etc., and bias voltage Vb can be set changeably.But the man-hour that need be used to set.
Relative therewith, according to present embodiment, even causing the current driving ability of the MOS transistor that constitutes power circuit 140, manufacturing process etc. change, but by the bias voltage Vb corresponding with this variation is provided, bigger nargin current potential Vm needn't be set, just can make power circuit 140 actions.Therefore, the high speed of the electric current adjustment of power circuit 140 can be kept, and the interior signal of transmission medium potential range VR of electronegative potential can be detected.
Like this, the receiving circuit of present embodiment can adopt various formations.
1.3 first configuration example
Fig. 4 illustrates the circuit diagram of first configuration example of the receiving circuit of Fig. 2.
In addition, in Fig. 4, with the corresponding expression of circuit diagram of the configuration example of the transtation mission circuit 200 of Fig. 2.And in Fig. 4, the part identical with Fig. 2 marked identical mark, and suitably omits explanation.
Be provided with at the source electrode of transistor QS1 and be used to current source CS1 that electric current I H is flowed.This current source CS1 can be made of N type MOS transistor, and the drain electrode of this N type MOS transistor is connected with the source electrode of transistor QS1, and low potential side supply voltage VEE is provided on its source electrode, and the voltage of regulation is provided on its grid.
The source electrode of transistor QS2 is provided with and is used to make the mobile current source CS2 less than the electric current I L of electric current I H.This current source CS2 can be made of N type MOS transistor, and the drain electrode of this N type MOS transistor is connected with the source electrode of transistor QS2, and low potential side supply voltage VEE is provided on its source electrode, and the voltage of regulation is provided on its grid.
Its result, when the input voltage vin of transtation mission circuit 200 is the hot side supply voltage corresponding with logic level " H ", transistor QS1 is in conducting state, and transistor QS2 is in cut-off state, can import electric current I H (current drive signal line 250) by holding wire 250.And the input voltage vin of transtation mission circuit 200 is when being the low potential side supply voltage corresponding with logic level " L ", transistor QS1 is in cut-off state, transistor QS2 is in conducting state, can import electric current I L (current drive signal line 250) by holding wire 250.
One end of impedance matching resistance R connects holding wire 250, and the other end of impedance matching resistance R is connected on the power circuit 140 of receiving circuit 100.The other end of more particularly, impedance matching resistance R is connected on the differential amplifier circuit 110 of power circuit 140.
The differential amplifier circuit 110 of power circuit 140 comprises formation differential right N type MOS transistor QR11, QR12 (first and second differential transistor).The source electrode of transistor QR11, QR12 interconnects, each transistor drain electric current and be fixed value.Voltage (in Fig. 4, the voltage of the other end of the source voltage of transistor QR1, impedance matching resistance R) grid controlled transistor QR11 based on holding wire 250.The drain voltage of output transistor QR11 is supplied with this output voltage as the output voltage of differential amplifier circuit 110 on the grid of transistor QR1.Based on bias voltage Vb grid controlled transistor QR12.
And power circuit 140 comprises N type MOS transistor QR1 (first electric current is adjusted transistor).Output voltage grid controlled transistor QR1 based on differential amplifier circuit 110.That is, on the grid of transistor QR1, supply with the output voltage of differential amplifier circuit 110, on source electrode, connect holding wire 250 (or other end of Interface Matching resistance R), based on the drain current of this output voltage oxide-semiconductor control transistors QR1.The voltage that makes the other end of Interface Matching resistance R is the voltage of holding wire 250.
By this transistor QR1 is set, can separation signal line 250 and the output node of output output voltage V out, thus reduce the capacity of the holding wire 250 that transtation mission circuit 200 drives.Therefore, can reduce the capacity that transtation mission circuit 200 should drive.And, can reduce the amplitude of the signal of holding wire 250, the fluctuation of detection signal at high speed.
And current-to-voltage converting circuit 120 is exported the voltage corresponding with the drain current of transistor QR1 as output voltage V out.This output voltage V out is the drain voltage of transistor QR1.
This current-to-voltage converting circuit 120 can also comprise the MOS transistor QR2 of the P type (broadly being first conductivity type) as load elements.Supply with hot side supply voltage VDD on the source electrode of transistor QR2, the grid of transistor QR2 and drain electrode are connected with the drain electrode of transistor QR1.Therefore, the electric current that current-to-voltage converting circuit 120 will produce based on the output voltage of differential amplifier circuit 110 as load elements, be that the drain current of transistor QR2 provides, thereby can be converted to and the corresponding voltage of electric current that produces based on the output voltage of differential amplifier circuit 110.
And bias voltage generating circuit 130 produces the voltage corresponding with the drain current of transistor QR12 as bias voltage Vb.
That is, in receiving circuit 110, it is differential right that transistor QR11, QR12 (first and second differential transistor) constitute, and its each drain current is controlled.And when the grid of transistor QR11 (first differential transistor) was connected with node NDX, its drain electrode was connected with the grid of transistor QR1 (first electric current is adjusted transistor).On the grid of transistor QR12 (second differential transistor), provide bias voltage Vb.Transistor QR1 is connected with current-to-voltage converting circuit 120 with node NDX.Bias voltage generating circuit 130 produces bias voltage Vb according to the drain current of transistor QR11, QR12 at least one (first and second differential transistor).
Thus, can produce the current potential of bias voltage Vb according to the current driving ability of transistor QR12, also change so constitute the drain current of differential right transistor QR11, its result can make the drain voltage of transistor QR11 change.Therefore,, nargin current potential Vm need be set on bias voltage Vb, littler nargin current potential Vm maybe can be set for making differential amplifier circuit 110 high speed motion.
And bias voltage generating circuit 130 can comprise MOS transistor QR20 (the first bias voltage generation transistor), and the grid of this MOS transistor QR20 is connected with drain electrode, and conductivity type is identical with the conductivity type (N type) of transistor QR12 (second differential transistor).And as the drain current of transistor QR20, when the corresponding electric current of the drain current with transistor QR11 or transistor QR12 (first or second differential transistor) of flowing through, the grid voltage of transistor QR20 produces as bias voltage Vb.That is, transistor QR20 is formed on the identical substrate with transistor QR11, QR12.And, adjust the drain current of transistor QR20 according at least one the drain current of transistor QR11, QR12.
So, the manufacture deviation of transistor QR12 is identical with the manufacture deviation of transistor QR20, so the variation of the current driving ability of transistor QR12 can be identical with the variation of the current driving ability of transistor QR20.Its result can adjust the current potential of bias voltage Vb according to the current driving ability of transistor QR12.
And, more particularly, differential amplifier circuit 110 can further comprise generation as the drain current of transistor QR11, QR12 and the N type MOS transistor QR13 (second electric current is adjusted transistor) of electric current (adjustment).The reference voltage V a of regulation is provided on the grid of transistor QR13.And bias voltage generating circuit 130 may further include N type MOS transistor QR21 (the second bias voltage generation transistor), and transistor QR20 is provided on the grid of this N type MOS transistor QR21 the grid voltage of (the first bias voltage generation transistor).And differential amplifier circuit 110 comprises current mirroring circuit CM1.Current mirroring circuit CM1 comprises P type MOS transistor QCM1, QCM2, and the grid of transistor QCM1, QCM2 interconnects.The drain electrode of transistor QCM1 is connected with the drain electrode of transistor QR11.The drain electrode of transistor QCM2 is connected with the grid of transistor QCM2 and the drain electrode of transistor QR12.
And, when the current driving ability that the current driving ability that is made as ID, transistor QR20 (the first bias voltage generation transistor) at the current driving ability current driving ability of transistor QR11, the QR12 that will be set up in parallel (first and second differential transistor) and that be made as DD, transistor QR13 (second electric current is adjusted transistor) is made as BD1, transistor QR21 (the second bias voltage generation transistor) was made as BD2, it is identical with BD1/BD2 that DD/ID preferably is set.
Like this, can be corresponding according to the variation of the current driving ability of the manufacture deviation of transistor QR11, the QR12 of differential amplifier circuit 110, QR13 with variation according to the current driving ability of the manufacture deviation of transistorized QR20, the QR21 of bias voltage generating circuit 130.Therefore, more exactly, can adjust the current potential of bias voltage Vb according to the current driving ability of transistor QR12.
In addition, in bias voltage generating circuit 130, will on grid, supply with electric current that reference voltage V a produced as the N type MOS transistor QR30 of grid voltage (the 3rd electric current is adjusted transistor) is generated as transistor QR20, QR21 through current mirroring circuit CM2 drain current.That is, by the electric current proportional electric current of transistor QR30 generation with the transistor QR13 generation of differential amplifier circuit 110.That is, on the grid of transistor QR30, provide the voltage identical, make the proportional electric current of drain current of transistor QR30 generation and transistor QR20 with the grid voltage of transistor QR13.At this, the drain current of transistor QR20 (the first bias voltage generation transistor) can be C (C the is an arithmetic number) electric current doubly of the drain current of transistor QR30.Even like this, also can adjust bias voltage Vb according to the current driving ability of transistor QR12.
Fig. 5 illustrates the sequential chart of action example of the receiving circuit 100 of Fig. 4.
In Fig. 5, show input voltage vin, transtation mission circuit 200 inverter INV2 output node ND1 voltage, receiving circuit 100 input node ND2 voltage, as the voltage of the node ND3 of the grid of transistor QR1 and the variation of output voltage V out.
After input voltage vin was changed to the hot side supply voltage corresponding with logic level " H ", the voltage of node ND1 also was changed to the hot side supply voltage.Thus, as mentioned above, transistor QS1 is set at conducting state, by holding wire 250 conduction current IH.
And the voltage of node ND2 is compared the amplitude size that only rises with the reference potential of given transmission medium.Thus, the impedance of the transistor QR11 of differential amplifier circuit 110 descends, and the voltage of node ND3 descends.Therefore, the impedance of transistor QR1 increases, and the leakage current of transistor QR1 reduces, and the current potential of output voltage V out increases.
Relative therewith, after input voltage vin was changed to the low potential side supply voltage corresponding with logic level " L ", the voltage of node ND1 also was changed to the low potential side supply voltage.Thus, as mentioned above, transistor QS2 is set at conducting state, by holding wire 250 conduction current IL.
And the voltage of node ND2 is compared the amplitude size that only descends with the reference potential of given transmission medium.Thus, the impedance of the transistor QR11 of differential amplifier circuit 110 increases, and the voltage of node ND3 rises.Therefore, the impedance of transistor QR1 descends, and the leakage current of transistor QR1 increases, and the current potential of output voltage V out reduces.
1.4 second configuration example
In the bias voltage generating circuit 130 of first configuration example shown in Figure 4, for producing bias voltage Vb transistor QR20, QR21 are set, but are not limited thereto.
Fig. 6 illustrates the circuit diagram of second configuration example of the receiving circuit of Fig. 2.But in Fig. 6, marked identical mark, and suitably omitted explanation in the part identical with Fig. 4.
The difference of the receiving circuit 300 of second configuration example and the receiving circuit 100 of first configuration example is, has omitted the transistor suitable with the transistor QR21 of bias voltage generating circuit 130 in bias voltage generating circuit 310.Even such formation, also identical with first configuration example, according to the current driving ability of transistor QR12, the current potential of bias voltage Vb can change, also change so constitute the drain current of differential right transistor QR11, its result can change the drain voltage of transistor QR11.Therefore, for making differential amplifier circuit 110 high speed motion, do not need to be provided with bigger nargin current potential Vm for bias voltage Vb.
But, compare with first configuration example because can not precision change bias voltage Vb preferably, so when being necessary to be provided with than fixed bias voltage Vb little but than first configuration example big nargin current potential Vm.But, according to second configuration example, compare with first configuration example, can simplify the formation of bias voltage generating circuit effectively.
1.5 the 3rd configuration example
For reducing nargin current potential Vm, the transistorized manufacture deviation according to constituting differential amplifier circuit 110 needs precision to produce bias voltage Vb preferably.But in first and second configuration example, the situation of the load of differential amplifier circuit 110 is different with the situation of the load of bias voltage generating circuit.Therefore, by make the transistorized current driving ability that constitutes bias voltage generating circuit than and the transistorized current driving ability that constitutes differential amplifier circuit 110 than consistent, thereby the precision of trying one's best generates bias voltage Vb well.
Therefore, in the 3rd configuration example, by the load of differential amplifier circuit 110 is set to simulation in bias voltage generating circuit, thereby this bias voltage generating circuit can precision generate bias voltage Vb better.
Fig. 7 illustrates the circuit diagram of the 3rd configuration example of the receiving circuit of Fig. 2.But in Fig. 7, the part mark identical mark identical with Fig. 4, and suitably omit explanation.
The receiving circuit 400 in the 3rd configuration example and the difference of the receiving circuit 100 in first configuration example are formations of bias voltage generating circuit 410.
Bias voltage generating circuit 410 comprises N type MOS transistor QR40, QR41, QR42 and load circuit R1.Transistor QR40 (the 3rd bias voltage generation transistor) is the N type conductivity type identical with the conductivity type of transistor QR12 (second differential transistor), and its grid connects the grid of transistor QR12.Transistor QR40 is provided on the source electrode of transistor QR41 the grid voltage of (voltage transistor takes place to use the 3rd bias voltage), the drain voltage of transistor QR40 is provided on its grid.Transistor QR13 is provided on the grid of transistor QR42 (the 4th electric current is adjusted transistor) grid voltage of (second electric current is adjusted transistor).That is, transistor QR42 adjusts the drain current of transistor QR40 (the 3rd bias voltage generation transistor).And load circuit R1 is connected with the source electrode of transistor QR41.
That is, transistor QR40 brings into play the effect of the transistor QR20 of first configuration example.Transistor QR41 can be used as current-to-voltage converting circuit 120 transistor QR1 load and play a role.Transistor QR42 produces the electric current identical with the transistor QR13 of differential amplifier circuit 110.Load circuit R1 performance makes the drain current of transistor QR41 flow into the effect of the power line of supplying with low potential side supply voltage VEE.
And, preferably make the current driving ability of transistor QR41 be set at identical with the current driving ability of transistor QR1 (first electric current is adjusted transistor).So, on the grid of transistor QR12, the load that changes according to the manufacture deviation identical with transistor QR11 can be set.Therefore, according to the transistorized manufacture deviation that constitutes differential amplifier circuit 110, can precision adjust bias voltage Vb preferably.
And, when the current driving ability that the current driving ability that is made as ID, transistor QR40 at current driving ability current driving ability and that be made as DD, transistor QR13 with transistor QR11, QR12 is made as BD11, transistor QR42 was made as BD12, it was identical with BD11/BD12 to preferably set DD/ID.
Thus, can be with corresponding with variation according to the current driving ability of the manufacture deviation of transistor QR40, the QR42 of bias voltage generating circuit 410 according to the variation of the current driving ability of the manufacture deviation of transistor QR11, the QR12 of differential amplifier circuit 110, QR13.Therefore, can adjust the current potential of bias voltage Vb accurately according to the current driving ability of transistor QR12.
2. the interface circuit of differential wave
In Fig. 1 to Fig. 7, be that example describes with the interface circuit and the receiving circuit of single-ended signal, but the present invention also go for the interface circuit and the differential signal receiver circuit of differential wave.
2.1 interface circuit
Fig. 8 illustrates the skeleton diagram of the formation of the interface circuit of differential wave in the present embodiment.In addition, in Fig. 8, host apparatus 510 provides an end of clock signal, and destination apparatus 530 is that the clock signal that will supply with is used as clock signal of system and an end of action.
DTO+, DTO-are the data (OUT data) of host apparatus 510 (broadly being device) to destination apparatus 530 (broadly being device) output in Fig. 8.CLK+, CLK-are the clock signals that host apparatus 510 provides to destination apparatus 530.Host apparatus 510 and CLK+/-edge (rising edge, trailing edge) export synchronously DTO+/-.Therefore, destination apparatus 530 can utilize CLK+/-sample and catch DTO+/-.Further, in Fig. 8, destination apparatus 530 based on the clock signal clk that provides from host apparatus 510+/-move.Be CLK+/-be the clock signal of system of destination apparatus 530.Therefore PLL (PhaseLocked Loop) circuit 512 (broadly being clock signal generating circuit) is arranged in the host apparatus 510, and the PLL circuit is not set in destination apparatus 530.
DT1+, DT1-are the data (IN data) of destination apparatus 530 to host apparatus 510 outputs.STB+, STB-are the gating signals (broadly being clock signal) that destination apparatus 530 provides to host apparatus 510.Destination apparatus 530 based on the CLK+ that provides from host apparatus 510/-, generate and output STB+/-.And destination apparatus 530 and STB+/-edge (rising edge, trailing edge) synchronous, output DTI+/-.Therefore, host apparatus 510 can use STB+, STB-the sampling and catch DTI+/-.
By transtation mission circuit (drive circuit) current drives and DTO+/-, CLK+/-, DTI+/-, STB+/-corresponding respectively differential signal line (broadly being serial signal line), thereby send respectively DTO+/-, CLK+/-, DTI+/-, STB+/-.In addition, be to realize transmission more at a high speed, can be provided with DTO+ more than or equal to two couples/-, DTI+/-each differential signal line.
The interface circuit 520 of host apparatus 510 comprises OUT transmission (broadly using for transfer of data) transtation mission circuit 522, clock signal transmission transtation mission circuit 524, IN transmission (broadly using for transfer of data) receiving circuit 526 and gating signal transmission (broadly using for the clock signal transmission) receiving circuit 528 (more broadly being differential signal receiver circuit).The interface circuit 540 of destination apparatus 530 comprise OUT transmission with receiving circuit 542, clock transfer with receiving circuit 544 or IN transmission with transtation mission circuit 546, gating transmission with transtation mission circuit 548 (more broadly being the differential wave transtation mission circuit).In addition, also can not comprise the part of these circuit modules and constitute.
OUT transmission with transtation mission circuit 522, clock transfer with transtation mission circuit 524 respectively by current drives DTO+/-, CLK+/-differential signal line send DTO+/-, CLK+/-.OUT transmission with receiving circuit 542, clock signal transmission with receiving circuit 544 respectively based on the DTO+ that flows through/-, CLK+/-differential signal line electric current and carry out current/voltage conversion, by the comparison process (differential processing and amplifying) of the differential voltage of carrying out obtaining by current/voltage conversion, and receive DTO+/-, CLK+/-.
IN transmission with transtation mission circuit 546, clock signal transmission with transtation mission circuit 548, respectively by current drives DTI+/-, STB+/-differential signal line send DTI+/-, STB+/-.IN carry with receiving circuit 526, gating signal transmission with receiving circuit 528 respectively based on the DTI+ that flows through/-, STB+/-differential signal line electric current and carry out current/voltage conversion, carry out the comparison process (differential processing and amplifying) of the differential voltage that obtains by current/voltage conversion, thus receive DTI+/-, STB+/-.
Thus, interface circuit comprises: differential signal receiver circuit, be connected by first holding wire on the differential wave transtation mission circuit of the other side's device of current drives first holding wire, and this this first holding wire constitutes differential signal line; And the differential wave transtation mission circuit, be connected with the differential signal receiver circuit of the other side's device by the secondary signal line that constitutes differential signal line, and current drives secondary signal line.Comprise two transtation mission circuits and two receiving circuits in the interface circuit 520,530 shown in Figure 8.
2.2 differential signal receiver circuit
In Fig. 9, the summary of the formation of differential signal receiver circuit in the present embodiment is shown.In addition, in Fig. 9, the part mark identical with Fig. 4 gone up identical mark, and suitably omits explanation.
As the IN of Fig. 8 transmission with receiving circuit 526, gating signal transmission with receiving circuit 528, OUT transmission with receiving circuit 542 and gating signal transmission with receiving circuit 544, differential signal receiver circuit that can application drawing 9.
Differential signal receiver circuit 800 (broadly being transtation mission circuit) passes through to be connected with differential signal receiver circuit 700 as the differential signal line 850 of the transmission medium of differential wave.Differential signal receiver circuit 800 comprises first and second current driving circuit 810,820.First and second current driving circuit 810,820 respectively based on send the corresponding input voltage vin of data, current drives differential signal line 850 respectively.By differential wave transtation mission circuit 800 to differential signal line 850 transmission differential signals.OUT transmission transtation mission circuit 522, clock signal transmission as Fig. 8 are transmitted with transtation mission circuit 548 with transtation mission circuit 546 and gating signal with transtation mission circuit 524, IN transmission, can use differential wave transtation mission circuit 800.
Differential signal receiver circuit 700 is connected on first and second holding wire 852,854, the differential signal line 850 that this first and second holding wire 852,854 constitutes by differential wave transtation mission circuit 800 current drives.Differential signal receiver circuit 700 comprises first receiving circuit 710 that is connected on first holding wire 852, is connected second receiving circuit 720 and comparator 730 on the secondary signal line 854.At least one of first and second receiving circuit 710,720 has identical formation with the receiving circuit 100 of Fig. 4.
The formation of first and second receiving circuit 710,720 is identical with the receiving circuit 100 of Fig. 2, so omit explanation.
2.3 first configuration example
Figure 10 illustrates the circuit diagram of first configuration example of the differential signal receiver circuit of Fig. 9.
And in Figure 10, the part mark identical with Fig. 9 gone up identical mark, and suitably omits explanation.And in Figure 10, go up identical mark with the same section mark of Fig. 4, and for differentiation is first receiving circuit 710 or second receiving circuit 720, and mark " H " (first receiving circuit 710) or " L " (second receiving circuit 720) at the end of its mark.
Differential wave transtation mission circuit 800 comprises N type MOS transistor (below, abbreviate transistor as) QS1H, QS2H, QS1L, QS2L.The drain electrode of transistor QS1H, QS2H is connected with first holding wire 852.The drain electrode of transistor QS1L, QS2L is connected with secondary signal line 854.Input voltage vin is cushioned by inverter INV1, INV2.The output voltage of inverter INV2 is provided on the grid of transistor QS1H, QS2L.The output voltage of inverter INV1 is provided on the grid of transistor QS2H, QS1L.
Being provided with the current source CS1H, CS1L current source CS1H, the CS1L that are used to electric current I H is flowed on the source electrode of transistor QS1H, QS1L can be made of N type MOS transistor, the drain electrode of this N type MOS transistor is connected on the source electrode of transistor QS1H, QS1L, and low potential side supply voltage VEE is provided on its source electrode.
On the source electrode of transistor QS2H, QS2L, be provided for current source CS2H, CS2L that the electric current I L littler than electric current I H flowed.Current source CS2H, CS2L can be made of N type MOS transistor, and the drain electrode of this N type MOS transistor is connected with the source electrode of transistor QS2H, QS2L, and low potential side supply voltage VEE is provided on its source electrode.
Its result, when differential wave transtation mission circuit 800 is the hot side supply voltage corresponding with logic level " H " in input voltage vin, transistor QS1H, QS2L are in conducting state, transistor QS2H, QS1L are in cut-off state, can import electric current I H by first holding wire 852, import electric current I L by secondary signal line 854.And, when differential wave transtation mission circuit 800 is the low potential side supply voltage corresponding with logic level " L " in input voltage vin, transistor QS1H, QS2L are in cut-off state, transistor QS2H, QS1L are in conducting state, can import electric current I L by first holding wire 852, import electric current I H by secondary signal line 854.
In differential signal receiver circuit 700, first receiving circuit 710 is a benchmark with bias voltage VbH, detects the corresponding potential change of current strength above-mentioned and driving first holding wire 852, and its result is exported as output voltage V o1.And first receiving circuit 720 is a benchmark with bias voltage VbL, detects the variation of the above-mentioned current potential corresponding with the current strength that drives secondary signal line 854, and its result is exported as output voltage V o2.And comparator 730 relatively output voltage V o1, Vo2, and export as output voltage V out.
In addition, in Figure 10, the low potential side supply voltage of comparator 730 is VEE, and the hot side supply voltage is VDD, but during the voltage outside the hot side supply voltage is VDD, the level shifter that output voltage V o1, Vo2 is carried out level conversion can be set.
Figure 11 illustrates the sequential chart of action example of the differential signal receiver circuit 700 of Figure 10.
Each node shown in Figure 11 is because of corresponding with each node of Fig. 5, so omit its detailed description.
Even because the manufacture deviation of the composed component of the differential amplifier circuit 110 of first and second receiving circuit 710,720 etc. cause that current driving ability changes, but differential signal receiver circuit 700 also can produce bias voltage VbH, the VbL corresponding with this variation in first configuration example.Therefore, identical with the receiving circuit of single-ended signal, do not need additionally to be provided with nargin current potential Vm and can make differential amplifier circuit 110 actions yet, keep the high speed of differential amplifier circuit 110, and can detect the interior signal of transmission medium potential range VR of electronegative potential.
2.4 second configuration example
In the differential signal receiver circuit 900 of second configuration example,, can use receiving circuit shown in Figure 6 300 as first and second receiving circuit 910,920.
In Figure 12, the circuit diagram of second configuration example of the differential signal receiver circuit of Fig. 9 is shown.
In addition, in Figure 12, the part mark identical with Fig. 6 or Fig. 9 gone up identical mark, and suitably omits explanation.
As shown in figure 12, the receiving circuit 300 of application drawing 6, can detect differential wave, so differential signal receiver circuit 900 also need not additionally be provided with nargin current potential Vm and can make differential amplifier circuit 110 actions in second configuration example, and keep the high speed of differential amplifier circuit 110, and can detect the signal in the transmission medium potential range VR of electronegative potential more.And, compare with first configuration example, though can not more correctly produce bias voltage, can reduce transistorized number of elements effectively.
2.5 the 3rd configuration example
In the differential signal receiver circuit 1000 in the 3rd configuration example,, can use receiving circuit shown in Figure 7 400 as first and second receiving circuit 1010,1020.
Among Figure 13, the circuit diagram of the 3rd configuration example of the differential signal receiver circuit of Fig. 9 is shown.
In addition, in Figure 13, the part mark identical mark identical with Fig. 7 or Fig. 9, and suitably omit explanation.
As shown in figure 13, the receiving circuit 400 of application drawing 7, can detect differential wave,, the differential signal receiver circuit 1000 in the 3rd configuration example can make differential amplifier circuit 110 actions so also need not additionally being provided with nargin current potential Vm, keep the high speed of differential amplifier circuit 110, and detect the interior signal of transmission medium potential range VR of electronegative potential.And transistor QR11H, the QR12H of differential amplifier circuit 110, the manufacture deviation of QR13H are identical with the manufacture deviation of transistor QR40H, the QR42H of bias voltage generating circuit 410.And the manufacture deviation of transistor QR11L, the QR12L of differential amplifier circuit 110, QR13L is identical with the manufacture deviation of transistor QR40L, the QR42L of bias voltage generating circuit 410.Therefore, can change the current potential of bias voltage VbH, VbL accurately according to the current driving ability of transistor QR12H, QR12L.
3. electronic equipment
The configuration example of the electronic equipment of present embodiment shown in Figure 14.This electronic equipment comprises the interface circuit 1502,1512,1514,1522,1532 of explanation in the present embodiment.And baseband engine 1500 (broadly being communicator), application engine (broadly being processor), camera 1540 (broadly being camera head) or LCD (Liquid CrystalDisplay: LCD) 1550 (broadly being display unit).In addition, also can omit an above-mentioned part and constitute.Can realize having the portable phone of the Presentation Function of camera-enabled and LCD according to the formation of Figure 14.But the electronic equipment of present embodiment is not limited in portable phone, also applicable to various electronic equipments such as digital camera, PDA, electronic notebook, e-dictionary or portable data assistances.
As shown in figure 14, between being arranged at the host apparatus side interface circuit 1502 on the baseband engine 1500 and being arranged at target side interface circuit 1512 on the application engine 1510 (graphics engine), can carry out Fig. 1 or transfer of data illustrated in fig. 8.And be arranged at the host apparatus side interface circuit 1514 on the application engine 1510 and be arranged at camera interface 1520 or LCD interface 1530 on target side interface circuit 1522,1532 between, also can carry out Fig. 1 or transfer of data illustrated in fig. 8.
Portable information devices such as portable phone comprise: first battery limits are used for the key (character panel) that telephone number input or character are imported; Second battery limits are provided with main LCD (Liquid Crystal Display), sub-LCD and camera (one or more device); And the coupling parts such as hinge that are used to connect first, second battery limits.And the baseband engine 1500 of Figure 14, application engine 1510, interface circuit (data transfer controller) 1502,1512,1514 also can be arranged on first battery limits.And interface circuit 1522,1532, camera interface 1520, LCD interface 1530, camera 1540 and LCD1550 can be arranged on second battery limits.And in the method for prior art, the transfer of data between first battery limits (first substrate) and second battery limits (second substrate) can be undertaken by parallel bus (system bus).
Relative therewith, according to present embodiment, can use the holding wire of universal serial bus or differential signal line to transmit data between first battery limits and second battery limits.Therefore, the quantity of the wiring of the coupling part of passing through first, second battery limits can be significantly reduced, the design or the installation of coupling part can be simplified.And can reduce the generation of EMI noise.
In addition, the present invention is not limited in the above embodiments, can carry out various distortion and implement in the scope of aim of the present invention.
And the interface circuit of receiving circuit of application the above embodiments or transtation mission circuit also is the content that is not limited only to Fig. 1 or Fig. 8 explanation.And the concrete formation of receiving circuit or transtation mission circuit also is not limited only to content illustrated in the above embodiments.
And, in the related invention of dependent claims in the present invention, also can omit institute's dependent claims constitutive requirements a part and constitute.And the portion that wants of the invention that independent claims of the present invention 1 are related also can be subordinated to other independent claims.
Description of reference numerals
10,510 host apparatus
12,512 PLL circuit
20,40,520,540,1502,1512,1514,1522,1532 interface circuits
22,522 OUT transmission transtation mission circuit
24,524 clock transfer transtation mission circuits
26,526 IN transmission receiving circuit
28,528 gating signals transmission receiving circuit
30,530 destination apparatus
42,542 OUT transmission receiving circuit
44,544 clock signals transmission receiving circuit
46,546 IN transmission transtation mission circuit
48,548 gating signals transmission transtation mission circuit
100,300,400 receiving circuits
110 differential amplifier circuits
120 current-to-voltage converting circuits
130,310,410 bias voltage generating circuits
140 power circuits
200 transtation mission circuits
210 current driving circuits
250 holding wires
700,900,1000 differential signal receiver circuits
710,910,1,010 first receiving circuits
720,920,1,020 second receiving circuits
730 comparators, 800 differential wave transtation mission circuits
810 first current driving circuits, 820 second current driving circuits
850 differential signal lines, 852 first holding wires
854 secondary signal lines, 1500 baseband engine
1510 application engines, 1520 camera interfaces
1530 LCD interfaces, 1540 cameras
1550 LCD R impedance matching resistance
Va reference voltage V b bias voltage
Vin input voltage Vout output voltage
Claims (11)
1. a receiving circuit is connected with the other side's transtation mission circuit by holding wire, and based on the electric current received signal of the described holding wire of flowing through, it is characterized in that comprising:
Current-to-voltage converting circuit, the described current conversion that is used for the described holding wire of flowing through is a voltage;
Power circuit based on the voltage of bias voltage with the node that is connected with described holding wire, is adjusted the electric current of the described holding wire of flowing through; And
Bias voltage generating circuit, the characteristic that is used to export with described power circuit links and controlled described bias voltage.
2. receiving circuit according to claim 1 is characterized in that:
Described power circuit comprises:
First electric current is adjusted transistor, and described first electric current is adjusted the described node of transistor AND gate and is connected with described current-to-voltage converting circuit; And
First differential transistor and second differential transistor, it is differential right that described first differential transistor and described second differential transistor constitute, each drain current Be Controlled,
Wherein, the grid of described first differential transistor is connected with described node, and its drain electrode is adjusted transistorized grid with described first electric current and is connected,
On the grid of described second differential transistor, supply with described bias voltage,
Described bias voltage generating circuit produces described bias voltage according to the drain current of described first differential transistor or described second differential transistor.
3. receiving circuit according to claim 2 is characterized in that:
Described bias voltage generating circuit comprises the bias voltage generation transistor of the conductivity type identical with the conductivity type of described second differential transistor,
Transistorized grid takes place and is connected with the grid of drain electrode with described second differential transistor in described bias voltage.
4. receiving circuit according to claim 3 is characterized in that:
Described first differential transistor of described bias voltage generation transistor AND gate and described second differential transistor are formed on the same substrate,
Described bias voltage generation transistor drain electric current is adjusted according to the drain current of described first differential transistor and described second differential transistor.
5. according to claim 3 or 4 described receiving circuits, it is characterized in that:
Described power circuit comprises that second electric current adjusts transistor, described second electric current adjust transistor be used to adjust described first differential transistor and described second differential transistor each drain current and,
Described bias voltage generating circuit comprises the 3rd electric current adjustment transistor, and described the 3rd electric current is adjusted transistor and is used for producing and the proportional electric current of described bias voltage generation transistor drain electric current,
Adjust on the transistorized grid to supply with at described the 3rd electric current and adjust the identical voltage of transistorized grid voltage with described second electric current.
6. receiving circuit according to claim 2 is characterized in that:
Described bias voltage generating circuit comprises:
It is identical with the conductivity type of described second differential transistor that transistorized conductivity type takes place for bias voltage generation transistor, described bias voltage; And
Electric current is adjusted transistor, is used to adjust described bias voltage generation transistor drain electric current.
7. a differential signal receiver circuit is characterized in that, comprising:
First receiving circuit, described first receiving circuit is connected on first holding wire, and described first holding wire constitutes the differential signal line by the transtation mission circuit current drives;
Second receiving circuit, described second receiving circuit is connected on the secondary signal line, and described secondary signal line constitutes described differential signal line; And
Comparator, based on the output of described first receiving circuit and described second receiving circuit, output signal output,
Wherein, at least one in described first receiving circuit and described second receiving circuit is according to each described receiving circuit in the claim 1 to 6.
8. differential signal receiver circuit according to claim 7 is characterized in that:
Described first receiving circuit and described second receiving circuit are according to each described receiving circuit in the claim 1 to 6,
Described comparator compares voltage of being changed by the current-to-voltage converting circuit of described first receiving circuit and the voltage of being changed by the current-to-voltage converting circuit of described second receiving circuit, and exports described output signal.
9 one kinds of interface circuits is characterized in that comprising:
According to each described receiving circuit in the claim 1 to 6, be connected by the received signal line on the transtation mission circuit of the other side's device of the described received signal line of current drives; And
Transtation mission circuit is connected on the receiving circuit of the other side's device by sending holding wire, and the described transmission holding wire of current drives.
10. interface circuit is characterized in that comprising:
According to claim 7 or 8 described differential signal receiver circuits, by first holding wire, be connected on the differential wave transtation mission circuit of the other side's device of described first holding wire of current drives, described first holding wire constitutes differential signal line; And
The differential wave transtation mission circuit is connected by the secondary signal line on the differential signal receiver circuit of the other side's device, and the described secondary signal line of current drives, and described secondary signal line constitutes described differential signal line.
11. an electronic equipment is characterized in that, comprising:
According to claim 9 or 10 described interface circuits; And
In communicator, processor, camera head and the display unit at least one.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005134009 | 2005-05-02 | ||
| JP2005134009 | 2005-05-02 | ||
| JP2006062874 | 2006-03-08 |
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|---|---|
| CN1859015A true CN1859015A (en) | 2006-11-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610076547 Pending CN1859015A (en) | 2005-05-02 | 2006-04-30 | Receiver circuit, differential signal receiver circuit, interface circuit, and electronic instrument |
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| CN (1) | CN1859015A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7719358B2 (en) | 2006-11-21 | 2010-05-18 | Industrial Technology Research Institute | Low frequency analog circuit and design method thereof |
| CN102045276A (en) * | 2009-10-09 | 2011-05-04 | 英特赛尔美国股份有限公司 | System and method for providing a full fail-safe capability in signal transmission networks |
| CN101930277B (en) * | 2009-06-19 | 2013-11-06 | 瑞昱半导体股份有限公司 | Power-saving and awakening device and method |
| CN113348647A (en) * | 2018-12-13 | 2021-09-03 | 法雷奥开关和传感器有限责任公司 | Bidirectional current modulation network communication system for transmitting data |
| CN115314071A (en) * | 2022-08-12 | 2022-11-08 | 程艳 | Full-duplex bidirectional analog front-end hybrid transceiver |
-
2006
- 2006-04-30 CN CN 200610076547 patent/CN1859015A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7719358B2 (en) | 2006-11-21 | 2010-05-18 | Industrial Technology Research Institute | Low frequency analog circuit and design method thereof |
| CN101188406B (en) * | 2006-11-21 | 2010-12-08 | 财团法人工业技术研究院 | Low frequency analog circuit |
| CN101930277B (en) * | 2009-06-19 | 2013-11-06 | 瑞昱半导体股份有限公司 | Power-saving and awakening device and method |
| CN102045276A (en) * | 2009-10-09 | 2011-05-04 | 英特赛尔美国股份有限公司 | System and method for providing a full fail-safe capability in signal transmission networks |
| CN102045276B (en) * | 2009-10-09 | 2014-07-09 | 英特赛尔美国股份有限公司 | System and method for providing a full fail-safe capability in signal transmission networks |
| US8971387B2 (en) | 2009-10-09 | 2015-03-03 | Intersil Americas LLC | System and method for providing a full fail-safe capability in signal transmission networks |
| US9276779B2 (en) | 2009-10-09 | 2016-03-01 | Intersil Americas LLC | System and method for providing a full fail-safe capability in signal transmission networks |
| CN113348647A (en) * | 2018-12-13 | 2021-09-03 | 法雷奥开关和传感器有限责任公司 | Bidirectional current modulation network communication system for transmitting data |
| CN115314071A (en) * | 2022-08-12 | 2022-11-08 | 程艳 | Full-duplex bidirectional analog front-end hybrid transceiver |
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