CN1856713A - Method and system for selectively masking test responses - Google Patents
Method and system for selectively masking test responses Download PDFInfo
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- CN1856713A CN1856713A CN 200480027818 CN200480027818A CN1856713A CN 1856713 A CN1856713 A CN 1856713A CN 200480027818 CN200480027818 CN 200480027818 CN 200480027818 A CN200480027818 A CN 200480027818A CN 1856713 A CN1856713 A CN 1856713A
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Abstract
An apparatus for testing an integrated circuit (10) that comprises a compactor (22) to compress test responses from a circuit-under-test (14) that is part of an integrated circuit (10), and masking circuitry (18) coupled between the circuit-under-rest and the compactor (22) for masking one or more of the test responses from the circuit-under-test (14). The masking circuitry (18) further comprises decompression circuitry for receiving compressed mask data and providing decompressed mask data.
Description
The present invention relates to a kind of equipment that is used for testing integrated circuits (IC), comprising: be used to compress the compressor reducer from the test response of tested circuit, this tested circuit is the part of IC; And be coupling in screened circuit between this tested circuit and the compressor reducer, be used to shield one or more test responses from this tested circuit.
The invention still further relates to a kind of method that is used for test I C.
The invention further relates to a kind of calculating and be used to shield method from the puncture mask data of the test data of IC.
Compression is favourable from the test response of IC, because can reduce this test data volume and test duration like this.Yet the value of some test responses can not be determined by priori, and other test responses may be ternary or insecure.These the unknowns, ternary is called as " X " test response with insecure test response, causes the reliable compression of test response to become very difficult or or even impossible.
Typically, use Automatic Test Equipment (ATE) to carry out, also become the IC tester for the manufacturing test of digital IC.ATE stores test and excitation (test stimuli) and these excitations is applied to IC.ATE observes this IC response subsequently then.ATE compares the response of these observations with the intended response of non-fault IC.Whether so just can determine this IC by this test, and tracing trouble.This ATE stores this test and excitation and non-fault test response in its storer into.
Numeral IC generally includes scan chain (scan chain).This means that in test pattern, it is scan chain that the trigger among the IC can be configured to serial shift registers.Test is undertaken by repeating following steps: (1) is displaced to test and excitation in the scan chain of this IC in test pattern; (2) in its functional application pattern, this IC is carried out a plurality of clock round-robin operations; (3) test response in the test pattern is shifted out.When shifting out this test response, usually new test and excitation is moved into.
According to Moore's Law, the continuous development of IC treatment technology can cause IC to go up the exponential increase of number of transistors.Therefore, the volume of test data also can increase by exponentially.New IC treatment technology has been introduced new fault type, needs other test to detect these faults, and this causes more leap ahead of test data volume.This rapid growth of test data volume has caused the serious problems that relate to ATE use and testing cost.Capacity and execution required time of test that this test data volume can surpass the ATE storer also can increase.
Utilize test data compress technique and embedded self check (BIST) technology that solution is provided.These technology are by using for example multiple input signals feature register (MISR) or space compression logic (SCL) this test response of compression in the space and/or on the time of special test response compressor circuit.This compressor circuit may reside in the chip, chip for example weighted platform (load-board) is gone up outward or ATE in.The test response of this compressor circuit output compression, ATE are observed the test response of this compression and are compared with the compression response of the expection of non-fault circuit.Thereby ATE only needs the test response of this compression of storage now, and this has just reduced storage requirement.
A problem relevant with this area current situation is must ignore or shield some test responses before can compressing this test response.This is about i.e. " X " situation about responding of ternary (Z), unknown (U) and unreliable test response.
Ternary test response has high impedance status (Z), and can for example be produced by two-way I/O pin.
Unknown test response has unknown-value (U), and can be for example produced by in-line memory, mixed signal module and/or conflict (conflicting) or the floating bus of no initializtion.And in the time will encouraging among the immigration IC in test for the first time, unknown-value is moved out of this IC.Unknown test response mean test response be logic low (L) promptly 0, logic high (H) promptly 1 or three-state (Z), still can not before test execution, determine its value.
Insecure test response has perhaps incorrect unreliable result.This can occur in the circuit that for example has a plurality of clock zones, and wherein when the signal wire of clock domain boundaries was passed through in test, meeting was owing to clock skew produces insecure test response.
The test response that compression comprises " X " response will cause insecure compression verification response, and whether the circuit that this response can not be used for determining IC perhaps is used for Fault Diagnosis by test.Thereby the test response compression can not be applied to produce the circuit of " X " response.
Three-state in the test response, the unknown and dubious value should be left in the basket and promptly shield or prevent its generation.
A part solution of this area current situation is to analyze the unknown test response of this circuit inside by adding suitable Testability Design (DfT) hardware.For example, test point can be inserted in the signal wire with unknown-value, this just forces this signal wire to become known fixed value.Yet, in circuit, add DfT and avoid unknown-value to need often circuit to be carried out the people for a change.This will be impossible in the situation of kernal hardware, wherein only in this DfT hardware influence situation regularly this circuit design be only available or unexpected, thereby this tested circuit can not move with required frequency.
A preferred solution shields them before need entering compressor circuit at all three-states, the unknown and insecure test response of this IC output.This can utilize X mask logic (XML) to realize.All " X " responses of this XML shielding, wherein " X " expression ternary (Z), unknown (U) or insecure test response.Shielding mean this " X " respond by known fixed value for example logic high " H " replace.When being implemented in this XML in the chip, ideally, the additional silicon area that is used for this XML should be less.And this XML should be flexibly, thereby it can be adapted to obtain the situation of different test responses, for example because different test patterns or because design variation.The operation of this XML can be controlled by ATE.In this case, ideally, being stored in the data volume that is used to control this XML among the ATE also should be less.And ideally, being used for from ATE also should be less to the bandwidth demand that IC transmits these data.Regrettably, though proposed various XML embodiments in the current situation of this area, these XML embodiments all can not meet aforementioned need fully.
The objective of the invention is to reduce amount of test data.
In a first aspect of the present invention, this purpose realizes that so wherein screened circuit further comprises the decompression circuit that is used to receive the shadow data of compression and the shadow data of decompression is provided.
In advantageous embodiment of the present invention, this decompression circuit also comprises linear feedback shift register.
In advantageous embodiment of the present invention, this decompression circuit also comprises phase shifter.
In another advantageous embodiment of the present invention, this decompression circuit also comprises the weighting logic.
In another advantageous embodiment of the present invention, these puncture mask data comprise at least one control signal.
In another advantageous embodiment of the present invention, this at least one control signal is full-shield (mask all) control signal.
In another advantageous embodiment of the present invention, this at least one control signal is that shielding starts (mask enable) control signal.
In a second aspect of the present invention, this purpose realizes that so wherein: the shadow data of compression is provided to decompression circuit; The shadow data of this compression is decompressed to produce the shadow data that decompresses; With in response to the test response of the shadow data of this decompression shielding from this integrated circuit.
In a third aspect of the present invention, this purpose realizes like this, wherein: generate one group of equation relevant with this shadow data; With find the solution this equation to obtain the shadow data of compression.
In order to understand equipment of the present invention better, and in order to clearly illustrate more how it realizes, illustrates by way of example now with reference to exemplary drawings, wherein:
Fig. 1 shows the example according to X mask logic of the present invention (XML);
Fig. 2 shows the more detailed example according to X mask logic of the present invention (XML); With
Fig. 3 shows the example of the ATPG flow process that is used to calculate the XML control signal.
Fig. 1 shows the example according to X mask logic of the present invention (XML).Fig. 1 comprises IC10, and this IC 10 itself comprises tested circuit 14, XML 18 and compressor reducer 22.Tested circuit 14 comprises n scan chain SC1-SCn, and its output is connected to the compressor reducer 22 that is used to compress from the test response of this tested circuit 14 by XML 18.Compressor reducer 22 for example can realize that this embodiment is known in the field by multiple input signals feature register (MISR) or space compression logic (SCL).Though Fig. 1 is shown as a part that is combined into IC 10 with XML 18 and compressor reducer 22, XML 18 and/or compressor reducer 22 also can be set at outside the chip, for example at Automatic Test Equipment (ATE) weighted platform or in fact in ATE (not shown) itself.
XML18 comprises linear feedback shift register (LFSR) 26, has the phase shifter and the steering logic 34 of weighting logic 30.XML 18 uses control signal mask_all and mask_enable to control by ATE.This ATE is by the logic state of input end at each clock circulation renewal XML 18, and this input end provides signal m
1-m
q, promptly be somebody's turn to do the shadow data that compresses.
XML 18 according to the present invention can reduce this must be stored in shadow data amount among the ATE.Therefore, ATE must be at each this mask_all of clock circulation storage representation, mask_enable and m
1-m
qThe q+2 position of signal.This q+2 input position is by the shielding of XML 18 a boil down to n carry-out bit, wherein q＜＜n.Thereby if not according to XML 18 of the present invention, ATE normally must be for the shielding of each clock circulation storage n position; And need n IC input pin so that this shielding is transferred to IC 10 from this ATE.When using according to XML 18 of the present invention, the advantage of ATE is that it only needs storage q+2 position XML eighteen data for each clock circulation, and it represents this control and shadow data signal mask_all, mask_enable and m
1-m
qAnd only need q+2 IC input pin that these data are transferred to IC10 from ATE.
Fig. 2 shows the more detailed example according to X mask logic of the present invention (XML).
The exemplary XML18 of Fig. 2 shows: comprise tested circuit 14,4 LFSR26, phase shifters 30 of four scan chain SC1-SC4 and comprise three grades steering logic 34.
LFSR26 shown in Figure 2 is well-known structure, comprises the feedback network of phase shifter and XOR (XOR) door.This is the p position from the width that ATE receives the LFSR26 of puncture mask data, and its shift register comprises p trigger in other words: p=4 in this specific example.In each clock cycle period, by input m
1-m
qUse comes the state of partial update LFSR 26 from q the shadow data position of ATE, q≤p wherein, q=1 in this specific example.This renewal can realize by for example adding XOR gate to shift register, and wherein the input of each is connected to receive each input signal m in i XOR gate
i: 1≤i≤q wherein.These LFSR 26 operating part decompression operation are to decompress from the puncture mask data of ATE.Then, use output data that the part from this LFSR 26 decompresses input data as phase shifter 30.
Phase shifter 30 shown in Fig. 2 also is well-known structure, comprises the network of XOR gate.30 pairs of data from LFSR 26 of this phase shifter are carried out further decompression operation, and generate n output signal, wherein p≤n according to p input signal: n=4 in this specific example.Phase shifter 30 disposes like this, so that the output signal of this phase shifter is uncorrelated, promptly each output signal depends on not input signal on the same group.Should be noted that weighting logic (not shown) can be added in the phase shifter 30, wherein this certain output signal of weighting logic permission biasing is the probability of logical zero or logical one.This weighting logic typically comprises some combinational logics, and it uses alternatively from the additional input signal of ATE and controls.
The n of this phase shifter 30 (wherein n=4 in this specific example) output signal is used as the input signal of steering logic 34.
The first order 36 of steering logic 34 comprise by four of mask_enable control signal control with (AND) door, and further decompress from the data of phase shifter 30.When mask_enable is logical one, should equal promptly to reflect their relevant output separately with each output of door from phase shifter 30.When mask_enable was logical zero, all were forced logical zero with the output of door, thereby should become the output shielding that comprises all logical zeros from the n position output shielding of phase shifter 30.The second level of steering logic 34 comprises by four of mask_all control signal control or (OR) door, and further decompresses from the data of the first order 36.When mask_all is logical zero, should or each output of door equal promptly to reflect their relevant output separately from the first order 36 of this steering logic 34.When mask_all was logical one, the output of all or door was forced logical one, thereby should be comprised that the n bit mask of all logical ones replaced from n bit mask of the output of the second level 38 of steering logic.
The third level 40 of steering logic 34 comprise four or, they operationally are arranged to receives output signal from scan chain SC1-SC4 and the second level 38 output signals.The IC test response from scan chain SC1-SC4 is revised in n bit mask this third level 40 or that door is used to 38 steering logics from the second level.
The third level 40 of steering logic 34 always needs, because this level 40 is implemented actual shielding.
The third level 40 is as screened circuit work, its operationally from the second level 38 receive these n bit masks and by n scan chain SC1-SCn from corresponding n output of tested circuit 14 receptions.In first example, from the output signal of the second level 38 be logical one and be applied in the third level 40 or door, then come the corresponding test response of self-corresponding scan chain to be replaced, and described test response conductively-closed by logical one.In second example, are logical zeros from the output signal of the second level 38, then corresponding test response is by this or door and thereby do not have a conductively-closed.Therefore, the test response conductively-closed of the corresponding scan chain of logical one value representation in the shielding, on the contrary, the logical zero in the shielding represents that the test response of corresponding scan chain does not have conductively-closed.The optional embodiment (not shown) of the third level 40 of Fig. 2 will be used for substituting should or door and with door.In this of the third level 40 and door embodiment, the test response conductively-closed of the corresponding scan chain of logical zero value representation in the shielding, on the contrary, this test response of logical one value representation does not have conductively-closed.In this case, the third level should comprise with door to replace or door.Therefore, should be understood that, shown in steering logic only be an one exemplary embodiment, the optional embodiment that uses dissimilar logic gates also is possible.
The first order 36 of steering logic 34 and/or the second level 38 and phase shifter 30 are the same to be optionally, comprises the weighting logic that it is associated.
Steering logic 34 also can be adjusted.For example, accurately this mask_all signal so that it is divided into two independently this control signals.Can use this two mask_all control signals then, so that their each control is from the part of the shielding of the data output of scan chain SC1-SCn.Similarly, also accurately this mask_enable control signal for example also makes it be divided into two independently control signals: can use this two mask_enable control signals then, so that their each control is from the part of the startup/forbidding shielding of the data output of scan chain SC1-SCn.
To in following example, illustrate in greater detail the operation of XML 18 now.
Example among Fig. 2 shows the XML 18 that is used for tested circuit 14, and it comprises four scan chain SC1-SCn.This XML18 comprises 4 LFSR 26, phase shifter 30 and three grades of steering logics.
Symbol x
1, x
2, x
3And x
4The expression initial value, promptly LFSR 26 is in the logic state of clock circulation 1.The state of LFSR 26 in the circulation of subsequently clock can also be represented with the form of the logic state of LFSR 26 except can using the state representation from the input signal m of ATE.Can draw these expression formulas at an easy rate by symbolic simulation.LFSR 26 logic states in ensuing five clocks circulation are as follows, wherein LFSR
iLFSR 26 states among the expression clock circulation i, m
iThe value of expression signal m in clock circulation i.
LFSR
1＝(x
1，x
2，x
3，x
4)
LFSR
2＝(x
3x
4，x
1，x
2m
1，x
3)
LFSR
3＝(x
2x
3m
1，x
3x
4，x
1m
2，x
2m
1)
LFSR
1＝(x
1x
2m
1m
2，x
2x
3m
1，x
3x
1m
3，x
1m
2)
LFSR
5＝(x
1x
3m
4m
2m
3，x
1x
2m
1m
2，x
2x
3m
1m
4，x
3x
4m
3)
LFSR
6＝(x
2x
4m
1m
3m
4，x
1x
3x
4m
2m
3，x
1x
2m
1m
2m
5，x
2x
3m
1m
4)
In a similar fashion, the output signal of phase shifter 30 also can be with symbol x
1, x
2, x
3, x
4And m
iForm represent.
PS
1＝(x
1，x
1x
2，x
3，x
4)
PS
2＝(x
3x
4，x
1x
3x
4，x
2m
1，x
3)
PS
3＝(x
2x
3m
1，x
2x
4m
1，x
1m
2，x
2m
1)
PS
4＝(x
1x
2m
1m
2，x
1x
3m
2，x
3x
4m
3，x
1m
2)
PS
5＝(x
1x
3x
4m
2m
3，x
2x
3x
4m
1m
3，x
2x
3m
1m
4，x
3x
4m
3)
PS
6＝(x
2m
1m
1m
3m
4，x
1x
2x
3m
1m
2m
4，x
1x
2m
1m
2m
5，x
2x
3m
1m
4)
The output of phase shifter 30 is used as shielding.In steering logic, use input mask_enable and mask_all further to upgrade this shielding, described in table 1.
| mask_all | mask_enable | |
| 0 | 0 | There is not scan chain output conductively-closed |
| 0 | 1 | Control the shielding that scan chain is exported by LFSR and phase shifter |
| 1 | 0 | All scan chain output conductively-closeds |
| 1 | 1 | All scan chain output conductively-closeds |
Table 1: control signal
Suppose in the output of the scan chain SC1-SC4 in above six clocks circulation observed
The IC test response is as follows:
R
1＝(
U，
U，
U，
U）
R
2＝(L，L，H，L)
R
3＝(H，
U，L，H)
R
4＝(
U，H，H，L)
R
5＝(H，L，L，H)
R
6＝(L，H，
H，L)
R
4Described in clock circulation four, the output of scan chain 1SC1 is " U ", and the output of scan chain 2 and 3SC2-SC3 is " H ", and the output of scan chain 4SC4 is " L ".
The test response of underscore be should conductively-closed response.This is about R
1, R
3And R
4In the unknown response " U " and about R
6In scan chain 3SC3 in the situation of unreliable response " H ".
Black matrix response (bold response) expression " essence response (essentialresponse) ", ATE can observe failure response by it.When using certain test pattern, response R
1-R
6It is the response of trouble-free tested circuit 14.This test pattern can detect the existence of specific fault among the CUT 14.When this fault is present among the CUT 14, these one or more essence responses will show different value, thereby detect this fault.This essence response should not shielded by XML 18.
Remaining had not both had underscore not have the response of black matrix yet is the response of logic low " L " or logic high " H ".These are non-essence responses, and for by the fault of this test pattern appointment, do not observe fault effect in these responses.Yet it can be this situation, promptly other not by the specified fault of current test pattern caused can these the response in observed fault effect.Yet these faults can be come out by other mode detection.Therefore, this non-essence response can conductively-closed and can not influence this fault coverage.Yet, preferably, do not shield these responses, because can obtain better defective coverage for a plurality of detections of fault.
R
1In all the response all should conductively-closed.This realizes by in clock circulation 1 control signal mask_all being set at logical one.In clock circulation 2-6, mask_all is set to logical zero.
At R
2And R
5In response must conductively-closed, thereby control signal mask_enable is set to logical zero in clock circulation 2 and 5.In remaining clock circulation, need shielding and mask_enable to be set to logical one.
At remaining test response R
3, R
4And R
6In, need following shielding:
-R
3,2, promptly vectorial R
3In the output of scan chain 2, be unknown " U " and should conductively-closed;
-at R
3,3, R
4,3And R
6,2In can observe fault effect, thereby these essence test responses should conductively-closed;
-R
4,1Also be unknown " U " and should conductively-closed;
-R
6,3It is unreliable response and should conductively-closed.
These conditions can be used for the character expression of this shielding combined, and are given as the output of phase shifter 30.This result is following linear equation system:
R
3，2：x
2x
4m
1＝1
R
3，3：x
1m
2＝0
R
4，1：x
1x
2m
1m
2＝1
R
4，3：x
3x
4m
3＝0
R
6，2：x
1x
2x
3m
1m
2m
4＝0
R
6，3：x
1x
2m
1m
2m
5＝1
This linear equation system for example can be found the solution at an easy rate by using Gaussian elimination.Possible separating is: x
1=1, x
2=0, x
3=1, x
4=0, m
1=1, m
2=1, m
3=1, m
4=0, and m
5=0.
This is separated the symbolic equation of substitution phase shifter 30 outputs place, and considers the value of control signal mask_enable and mask_all, obtain following shielding:
mask
1＝(1，1，1，1)
mask
2＝(0，0，0，0)
mask
3＝(0，1，0，1)
mask
4＝(1，1，0，0)
mask
5＝(0，0，0，0)
mask
6＝(0，0，1，0)
Test response after the shielding of the input of compressor reducer 22 as follows now (test response of symbol " m " expression conductively-closed:
R
1'=(
m,
m,
m,
m) (1,1,1,1) is the input at compressor reducer place
R
2’＝(L，L，H，L)(0，0，1，0)
R
3’＝(H，
m，L，m)(1，1，0，1)
R
4’＝(
m，m，H，L)(1，1，1，0)
R
5’＝(H，L，L，H)(1，0，0，1)
R
6’＝(L，H，
m，L)(0，1，1，0)
As can be seen to draw a conclusion:
-response that all should conductively-closed is response all conductively-closeds really of underscore;
-essence response that all should conductively-closed is that the black matrix response does not have conductively-closed really; With
-non-essence response conductively-closed that some can conductively-closed, these are with symbol " m " expression that does not have underscore.
Last example shows a kind of mode of value of the XML of calculating 18 control signals.This process can be included in automatic test pattern at an easy rate and be generated in (ATPG) instrument.
Fig. 3 shows the example of the ATPG flow process that is used to calculate XML 18 control signals.
This atpg tool generates and detects certain fault is the test pattern of target faults.This test pattern comprises test and excitation and corresponding test response.Then, this atpg tool is analyzed this test response discerning three-state, the unknown and the unreliable response that all should conductively-closed, and the essence response that identification should conductively-closed.The essence response is that those should be observed so that detect the response of this target faults.
The value of this mask_all and mask_enable signal determines that by the identification response vector wherein all responses all should conductively-closeds or should conductively-closed.
Then, can find the solution the linear equation system that this obtains according to the symbolic simulation of XML 18 operations, to determine the control input of the LFSR 26 among this XML 18.This system comprise should conductively-closed about all the X response and at least one should conductively-closed the equation of essence response.If this equation system can be found the solution, then other essence responses that show the fault effect of other target faults can be added in this equation system, and be found the solution this equation system once more.Repeat so all to be added in this equation system or till this equation system no longer can be separated up to all essence responses.The essence response being added to the order of this equation system can be determined by the number of faults that each essence response can detect.At first the essence response that detects maximum faults is added in this equation system, or the like.
Final step is to use the test response after the shielding to carry out fault simulation to determine that actual detected has arrived any fault.This step needs, because if this equation system is unsolvable, then some essence responses may conductively-closed.When the pattern that generates subsequently, this target faults that is not detected is by once more as the target of ATPG.
Fig. 3 shows how to calculate XML 18 control signals in each test pattern.Optional embodiment is by only for the part of a test pattern or find the solution this linear equation system for a plurality of test patterns and calculate this control signal.
If the negligible amounts of equation, then the chance that can separate of this equation system is just bigger.The quantity of the test response of therefore, should conductively-closed and should conductively-closed preferably should remain few as much as possible.For this reason, have mask_all and the mask_enable control signal is favourable, because their allow shielding or do not shield complete response vector, and corresponding equation does not need to be found the solution.Similarly, consider that the non-essence response that does not have the target faults response to be observed also is favourable.Then, after all essence responses all were added, as long as this equation system still can be separated, these non-essence responses also can be added in this equation system.
The XML 18 of this proposition provides a kind of effective, flexible and cheap solution that is used to shield the X response as described in the present invention.This XML 18 allows to reduce the shadow data amount that generates and must be stored among the ATE during ATPG, reduced the bandwidth demand that is used for this shadow data is transferred to from ATE IC 10 in addition.
This XML18 can generate a large amount of different shieldings, and this is controlled by ATE.This shielding and the control signal corresponding of controlling this XML 18 can be calculated during ATPG.This XML 18 is based on the sowing again (reseeding) of dynamic LFSR 26, the state of this LFSR 26 of ATE partial update in wherein circulating according to each clock.This just provides a kind of mode of compressing these XML 18 control datas.For the tested circuit 14 with n scan chain, each clock circulation only needs q control bit to be used for sowing this LFSR 26, wherein q＜n again.This LFSR 26 adds weighting logic 30 for this optional phase shifter, and this q input expanded to the n bit mask.For each clock circulation, this additional steering logic allows easily to shield all scan chains or stops shielding.
These XML 18 hardware are simple, need considerably less silicon area when implementing on IC 10.This XML 18 also can partly be implemented in the chip and part is implemented in outside the chip.Be used to control the model of model, phase shifter and weighting logic 30 of quantity, LFSR 26 of the control signal of LFSR 26 states and the quantity of the control signal relevant with mask_all and mask_enable, it is different can being configured to for each design, depends on the description of expection X response.
Should be noted in the discussion above that the foregoing description illustrates but be not restriction the present invention that those of ordinary skills can design the embodiment of plurality of optional and not break away from scope of the present invention as defined by the appended claims.In this claim, any reference marker in the bracket should not be interpreted as limiting this claim.Word " comprises " and " comprising " etc. is not precluded within any claim or the whole instructions element outside listed or the existence of step.Element single quoted and do not got rid of a plurality of of this element and quote, and vice versa.The present invention can realize by the hardware that comprises a plurality of different elements, also can realize by the computing machine of suitable programming.In enumerating the claim of multiple arrangement, can realize these multiple arrangements by same hardware.Do not represent to use the combination of these measurements as preferred about the fact that particular measurement is stated in mutually different dependent claims.
Claims (9)
1. equipment that is used for testing integrated circuits (10), this equipment comprises:
-compressor reducer (22) is used to compress the test response of tested circuit (14), and this tested circuit (14) is the part of integrated circuit 10; With
-be coupling in the screened circuit (18) between this tested circuit and the compressor reducer (22), be used for the one or more test responses of shielding from this tested circuit (14), it is characterized in that, this screened circuit (18) also comprises decompression circuit (26,30,36,38), be used for receiving the shadow data (m of compression from this equipment
1-m
q) and be the shadow data that this screened circuit (40) provides decompression.
2. equipment as claimed in claim 1 is wherein carried out by linear feedback shift register (26) and is decompressed.
3. as the described equipment of any one claim of front, wherein carry out and decompress by phase shifter (30).
4. as the described equipment of any one claim of front, wherein carry out and decompress by the weighting logic.
5. as the described equipment of any one claim of front, wherein the shadow data of this compression comprises that at least one is used to control the control signal of this screened circuit (18).
6. equipment as claimed in claim 5, wherein this at least one control signal is the full-shield control signal.
7. equipment as claimed in claim 5, wherein this at least one control signal is a shielding start-up control signal.
8. method that is used for testing integrated circuits (10) is characterized in that comprising step:
-shadow data of compression is provided to decompression circuit;
The shadow data of-this compression that decompresses is to produce the shadow data that decompresses; With
-in response to the test response of the shadow data of this decompression shielding from this integrated circuit (10).
9. a calculating is used for the method for shielding from the puncture mask data of the test data of integrated circuit (10), it is characterized in that it comprises step:
The set of equations that-generation is relevant with this shadow data; With
-find the solution the shadow data of this equation to obtain compressing.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP03103575.1 | 2003-09-26 | ||
| EP03103575 | 2003-09-26 | ||
| EP04102184.1 | 2004-05-18 |
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|---|---|
| CN1856713A true CN1856713A (en) | 2006-11-01 |
| CN100541219C CN100541219C (en) | 2009-09-16 |
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| CNB2004800278187A Expired - Fee Related CN100541219C (en) | 2003-09-26 | 2004-09-20 | The method and system that is used for selectively masking test responses |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7788562B2 (en) | 2006-11-29 | 2010-08-31 | Advantest Corporation | Pattern controlled, full speed ATE compare capability for deterministic and non-deterministic IC data |
| CN117825913A (en) * | 2023-12-06 | 2024-04-05 | 中科鉴芯(北京)科技有限责任公司 | Test excitation compression method, device and circuit based on variable length LFSR |
-
2004
- 2004-09-20 CN CNB2004800278187A patent/CN100541219C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7788562B2 (en) | 2006-11-29 | 2010-08-31 | Advantest Corporation | Pattern controlled, full speed ATE compare capability for deterministic and non-deterministic IC data |
| CN117825913A (en) * | 2023-12-06 | 2024-04-05 | 中科鉴芯(北京)科技有限责任公司 | Test excitation compression method, device and circuit based on variable length LFSR |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100541219C (en) | 2009-09-16 |
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