CN1848388A - Method for controlling key size deviation in chip etching technology - Google Patents
Method for controlling key size deviation in chip etching technology Download PDFInfo
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- CN1848388A CN1848388A CN 200510126450 CN200510126450A CN1848388A CN 1848388 A CN1848388 A CN 1848388A CN 200510126450 CN200510126450 CN 200510126450 CN 200510126450 A CN200510126450 A CN 200510126450A CN 1848388 A CN1848388 A CN 1848388A
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Abstract
The present invention provides a method for controlling critical dimension deviation in wafer etching process. Said method includes the following steps: creating a data list containing correspondent relationship of wafer critical dimension (CD) deviation uniformity and electrostatic chuck inner and outer ring temperatures, regulating on-line tool for measuring CD deviation and making it be used for controlling inner and outer ring temperatures of said electrostatic chuck and making real-time feedback of CD deviation, real-time measuring CD deviation uniformity before etching and after etching, comparing inner and outer temperatures of electrostatic chuck with correspondent data list and regulating inner and outer ring temperatures of next electrostatic chuck so as to make the uniformity of its CD deviation be better.
Description
Technical field
The present invention relates to the semiconductor etching process field, be specifically related to the method for control key size deviation in chip etching technology.
Background technology
In the silicon chip erosion process, extremely important to CD (critical demension, critical size) the inhomogeneity control of deviation, the CD deviation is exactly the variable quantity of line thickness on the silicon chip of technology front and back.What of side direction etching this width reflected, the distributing homogeneity of CD deviation on whole silicon wafer directly had influence on the performance of silicon wafer to manufacture device, therefore the uniformity of the CD deviation that obtains is extremely important, the uniformity of CD deviation and the temperature of electrostatic chuck have very confidential relation, and be very sensitive to variation of temperature.Mainly utilize at present the measurement result of the CD SEM of off-line to obtain the uniformity of CD deviation, carry out the measurement of CD before carrying out etching and after the etching, the result who subtracts each other with them obtains the CD deviation.Another method of measuring the CD deviation is exactly to utilize the CD survey tool that is integrated on the equipment, be OCD (optical criticaldemension, optics critical size measuring instrument), but present application all is the mean value that obtains whole silicon wafer surface measurement CD deviation, go to instruct the etching process of next step silicon chip and the adjustment of process time by this average effect.
Its shortcoming is that utilizing OCD to measure the CD deviation all is the mean value that rounds the sheet silicon chip, carries out the adjusting between sheet, does not carry out regulating in the sheet; In the adjusting that the OCD FEEDBACK CONTROL is carried out, have only rough the carrying out time to adjust, not to the technological parameter adjustment; Carry out the interior CD measuring technique of regulating of sheet off-line measurement often, taken the plenty of time.
The mode that also has at present the two-region temperature control of a kind of electrostatic chuck, promptly be divided into Internal and external cycle and carry out temperature controlling, the measurement result of the CD deviation of the measurement of temperature on the silicon chip and off-line carries out but be based on for the adjustment of temperature, is not used in the measurement result of line generalization CD deviation and regulates.
Its shortcoming is that the real-time of adjustment is relatively poor, does not play the effect of real-time temperature control, also not and the on-line measurement instrument combine, integration is poor.
Summary of the invention
(1) technical problem that will solve
The purpose of this invention is to provide a kind of method of controlling critical size (CD) deviation efficiently, efficiently.
(2) technical scheme
For achieving the above object, the present invention has following steps:
Pass through experimental test, foundation comprises the tables of data of the corresponding relation of wafer CD deviation uniformity and electrostatic chuck Internal and external cycle temperature, and this corresponding relation is the unfavorable wafer CD of an exponential quantity deviation uniformity and the data corresponding relation of the Internal and external cycle temperature of the electrostatic chuck that can make it to become perfect condition;
In the actual process process, at first, record the CD deviation uniformity of a wafer,, then adjust current electrostatic chuck Internal and external cycle temperature corresponding electrostatic chuck Internal and external cycle temperature value to the described tables of data if the inhomogeneity numerical value of this CD deviation is undesirable.Wherein, also comprise, the technologist is according to the CD deviation uniformity of the current wafer of the intermittent detection of the needs of technological requirement, and when the inhomogeneity numerical value of this CD deviation is undesirable, all adjust current electrostatic chuck Internal and external cycle temperature corresponding electrostatic chuck Internal and external cycle temperature value to the described tables of data.
(3) beneficial effect
Owing to adopt above technical scheme, the present invention compared with the prior art,
1. adopt online integrated OCD measuring equipment.Not only consider the average effect on the full wafer silicon chip, especially the process results in the sheet is measured, thereby improve the processing quality of every silicon chip.Overcome the shortcoming of off-line analysis on time spent and manpower consumption.
2. realization on-line measurement, and carry out the uniformity of FEEDBACK CONTROL CD deviation, save Measuring Time, and improved automaticity.Measure before and after the etching, the result who measures is mated with the data in the model, obtain the temperature of corresponding electrostatic chuck Internal and external cycle, in time control, realize temperature control, the quality of a slice silicon chip under improving by the algorithm match.
3. adapt to the on-line monitoring of smaller szie and the requirement of FEEDBACK CONTROL.Under smaller szie, strict more for the requirement of various technologies and hardware condition, so need accurate like this and carry out the adjusting of various parameters in real time.Fig. 3 contrasts unjustified and with the result of the method CD deviation after adjusting, obviously the uniformity of CD deviation significantly improves.
Description of drawings
Fig. 1 is an electrostatic chuck structural representation of the present invention;
Fig. 2 is the CD uniformity and the electrostatic chuck Internal and external cycle temperature curve schematic diagram of the embodiment of the invention;
Fig. 3 is the equipment connection diagram of the embodiment of the invention;
In the above accompanying drawing, 1, heating rod; 2, electrostatic chuck; 3, outer ring; 4, inner ring.
Embodiment
Following examples are used to illustrate the present invention, but are not used for limiting the scope of the invention.
As shown in Figure 1, be the electrostatic chuck result schematic diagram.Silicon chip places on the electrostatic chuck 2, the distribution of inner ring 4 and outer ring 3 also is divided into interior outskirt on corresponding the electrostatic chuck 2 on the silicon chip, and general etch rate is not very identical at Internal and external cycle, caused the difference of CD deviation like this, heating rod 1 can carry out temperature control respectively to outer ring 3 and inner ring 3.
As shown in Figure 2, at first set up the relation curve of the uniformity and the electrostatic chuck Internal and external cycle temperature of CD deviation.By carrying out a large amount of experiments under the different situation of electrostatic chuck Internal and external cycle temperature, measure the uniformity of its CD deviation, obtain corresponding electrostatic chuck Internal and external cycle temperature and the relation curve between the CD deviation uniformity, and carry out curve fitting, these corresponding datas are saved in the tables of data, as the basis of calculating.
(embodiment one)
As shown in Figure 3, in technology is carried out, mainly utilized optics CD measurement mechanism 11, optics CD measurement mechanism 11 can be integrated on the etching apparatus, before the etching of carrying out a slice silicon chip, transmission platform 12 will send into that the CD value to silicon chip measures CD value N1 in the optics CD measurement mechanism 11, transmission platform in reaction chamber 14, after etching is finished, is sent into chip transmission in the optics CD measurement mechanism 11 once more subsequently, measure its CD value and be N2, N2-N1 can obtain deviate.
The silicon chip CD deviate that obtains is delivered to industrial computer 13, analyze its CD deviation uniformity numerical value, with obtain silicon chip CD deviation uniformity numerical value carry out match with the temperature curve of Fig. 2, carry out corresponding one by one, obtain the corresponding informance of electrostatic chuck 2 Internal and external cycle temperature, thereby the Internal and external cycle temperature to electrostatic chuck 2 is regulated, and improves the uniformity of CD deviation in the silicon chip.
In addition, for technological requirement than higher the time, in order timely technical process to be adjusted, can also intermittently to carry out above-described CD deviation uniformity and detect, and in time adjust the Internal and external cycle temperature of electrostatic chuck 2 according to CD deviation uniformity detection architecture.
The different electrostatic chuck temperature of Internal and external cycle has good regulating effect to the CD deviation, mainly be because the CD deviation is responsive to temperature, so the inside and outside temperature heating system of application electrostatic chuck is regulated the temperature inside and outside it, to improving the CD deviation good effect is arranged.And improved the efficient of technology, saved the time of offline inspection CD.
Claims (2)
1, a kind of method of controlling the technology key dimensional discrepancy in chip etching technology is characterized in that described method comprises the steps:
Pass through experimental test, foundation comprises wafer CD (critical demension, critical size) tables of data of the corresponding relation of deviation uniformity and electrostatic chuck Internal and external cycle temperature, this corresponding relation are the unfavorable wafer CD of exponential quantity deviation uniformities and the data corresponding relation of the Internal and external cycle temperature of the electrostatic chuck that can make it to become perfect condition;
In the actual process process, at first, record the CD deviation uniformity of a wafer by optics critical size survey tool,, then adjust current electrostatic chuck Internal and external cycle temperature corresponding electrostatic chuck Internal and external cycle temperature value to the described tables of data if the inhomogeneity numerical value of this CD deviation is undesirable.
2, the method for claim 1, it is characterized in that, also comprise the CD deviation uniformity of technologist according to the current wafer of the intermittent detection of the needs of technological requirement, and when the inhomogeneity numerical value of this CD deviation is undesirable, all adjust current electrostatic chuck Internal and external cycle temperature corresponding electrostatic chuck Internal and external cycle temperature value to the described tables of data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101264506A CN100405556C (en) | 2005-12-09 | 2005-12-09 | Method for controlling key size deviation in chip etching technology |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005101264506A CN100405556C (en) | 2005-12-09 | 2005-12-09 | Method for controlling key size deviation in chip etching technology |
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| CN1848388A true CN1848388A (en) | 2006-10-18 |
| CN100405556C CN100405556C (en) | 2008-07-23 |
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| CNB2005101264506A Active CN100405556C (en) | 2005-12-09 | 2005-12-09 | Method for controlling key size deviation in chip etching technology |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101459064B (en) * | 2007-12-13 | 2011-03-23 | 中芯国际集成电路制造(上海)有限公司 | Forming method for lateral wall substrate |
| CN101290475B (en) * | 2007-04-20 | 2011-09-07 | 中芯国际集成电路制造(上海)有限公司 | Method for improving characteristic line breadth homogeneity |
| CN102024726B (en) * | 2009-09-23 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Detection method and manufacturing method of MOS device |
| CN102411268A (en) * | 2011-11-30 | 2012-04-11 | 上海华力微电子有限公司 | Photoetching apparatus and method for improving photoetching machine overlay accuracy |
| CN105116690A (en) * | 2015-09-15 | 2015-12-02 | 上海和辉光电有限公司 | Process for processing display screen array substrate |
| CN113496951A (en) * | 2020-04-08 | 2021-10-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor manufacturing method and manufacturing system |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW578234B (en) * | 2003-02-14 | 2004-03-01 | Taiwan Semiconductor Mfg | Method of controlling CD uniformity for wafer etching process |
| US20050064714A1 (en) * | 2003-09-19 | 2005-03-24 | Applied Materials, Inc. | Method for controlling critical dimensions during an etch process |
-
2005
- 2005-12-09 CN CNB2005101264506A patent/CN100405556C/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101290475B (en) * | 2007-04-20 | 2011-09-07 | 中芯国际集成电路制造(上海)有限公司 | Method for improving characteristic line breadth homogeneity |
| CN101459064B (en) * | 2007-12-13 | 2011-03-23 | 中芯国际集成电路制造(上海)有限公司 | Forming method for lateral wall substrate |
| CN102024726B (en) * | 2009-09-23 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Detection method and manufacturing method of MOS device |
| CN102411268A (en) * | 2011-11-30 | 2012-04-11 | 上海华力微电子有限公司 | Photoetching apparatus and method for improving photoetching machine overlay accuracy |
| CN102411268B (en) * | 2011-11-30 | 2014-01-29 | 上海华力微电子有限公司 | Photoetching apparatus and method for improving photoetching machine overlay accuracy |
| CN105116690A (en) * | 2015-09-15 | 2015-12-02 | 上海和辉光电有限公司 | Process for processing display screen array substrate |
| CN105116690B (en) * | 2015-09-15 | 2017-07-14 | 上海和辉光电有限公司 | A kind of display screen array base palte processing technology |
| CN113496951A (en) * | 2020-04-08 | 2021-10-12 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor manufacturing method and manufacturing system |
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| CN100405556C (en) | 2008-07-23 |
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Address after: No. 8, Wenchang Avenue, Beijing economic and Technological Development Zone, 100176 Patentee after: Beijing North China microelectronics equipment Co Ltd Address before: 100016 Jiuxianqiao East Road, Chaoyang District, Chaoyang District, Beijing Patentee before: Beifang Microelectronic Base Equipment Proces Research Center Co., Ltd., Beijing |
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