CN1842917A - Nitride semiconductor device - Google Patents
Nitride semiconductor device Download PDFInfo
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- CN1842917A CN1842917A CNA2004800248054A CN200480024805A CN1842917A CN 1842917 A CN1842917 A CN 1842917A CN A2004800248054 A CNA2004800248054 A CN A2004800248054A CN 200480024805 A CN200480024805 A CN 200480024805A CN 1842917 A CN1842917 A CN 1842917A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 245
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 157
- 239000000758 substrate Substances 0.000 claims abstract description 109
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 101
- 239000010703 silicon Substances 0.000 claims abstract description 100
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 98
- 239000012535 impurity Substances 0.000 claims abstract description 28
- 230000003139 buffering effect Effects 0.000 claims description 82
- 239000000126 substance Substances 0.000 claims description 20
- 230000000694 effects Effects 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 229910052782 aluminium Inorganic materials 0.000 claims description 16
- 238000010276 construction Methods 0.000 claims description 16
- 239000004411 aluminium Substances 0.000 claims description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 13
- 229910052738 indium Inorganic materials 0.000 claims description 13
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 11
- 230000005669 field effect Effects 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 161
- 230000004888 barrier function Effects 0.000 description 30
- 229910002601 GaN Inorganic materials 0.000 description 22
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 21
- 239000000203 mixture Substances 0.000 description 13
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 12
- 238000005036 potential barrier Methods 0.000 description 11
- 229910017083 AlN Inorganic materials 0.000 description 8
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 8
- 239000013078 crystal Substances 0.000 description 8
- 239000002800 charge carrier Substances 0.000 description 7
- 238000009472 formulation Methods 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 7
- 229910021529 ammonia Inorganic materials 0.000 description 6
- 238000005755 formation reaction Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 229910000077 silane Inorganic materials 0.000 description 5
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 239000011777 magnesium Substances 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- MGYGFNQQGAQEON-UHFFFAOYSA-N 4-tolyl isocyanate Chemical compound CC1=CC=C(N=C=O)C=C1 MGYGFNQQGAQEON-UHFFFAOYSA-N 0.000 description 3
- 230000004913 activation Effects 0.000 description 3
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- 238000005516 engineering process Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
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- 229910052733 gallium Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000008676 import Effects 0.000 description 2
- 229910003437 indium oxide Inorganic materials 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 229910052749 magnesium Inorganic materials 0.000 description 2
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- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 208000037656 Respiratory Sounds Diseases 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
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- 229910052757 nitrogen Inorganic materials 0.000 description 1
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- 230000008569 process Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
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Abstract
There is prepared a p-type silicon substrate (1) which is doped with a p-type impurity and has sufficient conductivity. A buffer region (3) composed of n-type AlInGaN, an n-type nitride semiconductor layer (13) composed of n-type GaN, an active layer (14), and a p-type nitride semiconductor layer (15) composed of p-type GaN are epitaxially grown on the substrate (1) sequentially. The carrier-transporting efficiency from the silicon substrate (1) to the n-type buffer region (3) is enhanced by the interface state in the heterojunction between the p-type silicon substrate (1) and the n-type buffer region (3), thereby lowering the driving voltage of the light-emitting diode.
Description
Technical field
The present invention relates to nitride-based semiconductor devices such as light-emitting diode (LED), transistor.
Background technology
The substrate that is used to constitute nitride-based semiconductor device is made of sapphire, carborundum or silicon.Silicon substrate is compared with sapphire substrate and silicon carbide substrate, has easy cut-out, the advantage that cost is low.In addition, silicon substrate can access the conductivity that can not obtain in sapphire substrate.Therefore, silicon substrate can be used as current path.But owing to the potential barrier between silicon substrate and the nitride-based semiconductor produces bigger pressure drop, thereby the driving voltage of light-emitting diode is than higher.
Open in the 2002-208729 communique (below, be called patent documentation 1) the spy, announced the technology of the above-mentioned shortcoming that is used for solving silicon substrate.In this patent documentation 1, on n type silicon substrate, successively epitaxial growth as the AlN (aluminium nitride) of resilient coating layer, have the active layer and the p type GaN layer that constitute with n type InGaN (indium gallium nitride) layer of the same conduction type of silicon substrate, n type GaN (gallium nitride) layer, by InGaN.When this technology of employing, the Al of the In of InGaN layer and Ga and AlN layer spreads in silicon substrate, produces the alloy-layer that is made of Ga, In, Al and Si in the surface region of silicon substrate, promptly produces the metallic compound district.This alloy-layer has the function of the potential barrier that reduces the heterojunction between silicon and the AlN.Consequently, can be reduced in the driving voltage when flowing through predetermined current in the light-emitting diode, reduce power loss, raise the efficiency.
But even under the situation that forms such alloy-layer, the potential barrier between n type silicon substrate and the nitride-based semiconductor is also bigger, and the pressure drop of light-emitting diode is that driving voltage is compared high to about 1.2 times with the light-emitting diode that uses sapphire substrate.
The problems referred to above, beyond the light-emitting diode, in other semiconductor element of the thickness direction upper reaches of silicon substrate overcurrent, also produce, for example in transistor, also produce.
As other problem of light-emitting diode, exist to be difficult to easily form the taking-up and the electrode that is electrically connected both that to satisfy light.That is, generally speaking, indium oxide (In is set on the surface of the semiconductor region with lighting function
2O
3) and tin oxide (ZnO
2) the transmitance electrode of mixture (below, be called ITO) etc., and then in the lip-deep cardinal principle central authorities of transmitance electrode, be provided for connecting the non-radioparent bond pad electrode of light of lead etc.Because the transmitance electrode for example is the thin electrically conductive film of 10nm left and right thickness, so the metal material of bond pad electrode spreads, between semiconductor region and bond pad electrode, form Schottky barrier in the transmitance electrode or in transmitance electrode and semiconductor region.Because this Schottky barrier has the function of the forward current that stops light-emitting diode, suppressed by Schottky barrier so flow through the electric current of following part of the bond pad electrode of semiconductor region, on the contrary, the electric current of the outer circumferential side of semiconductor region part increases.Therefore, the Schottky barrier below the bond pad electrode has the function same with well-known current barrier layer, to improving luminous efficiency contribution is arranged.As everyone knows, so-called current barrier layer be restriction flow through with active layer in the zone of bond pad electrode contraposition in the layer of electric current.As everyone knows, flow through with active layer in the zone of bond pad electrode contraposition in electric current, be the idle current that luminous efficiency is not had contribution.
But such as already explained, the positive drive voltage of the light-emitting diode of use n type silicon substrate is bigger.Like this, when the positive drive voltage of light-emitting diode is bigger, power loss in silicon substrate and the semiconductor region also increases, the caloric value here also increases, the temperature in above-mentioned Schottky barrier district also increases, and the deterioration in characteristics of above-mentioned Schottky barrier is by the leakage current increase of this Schottky barrier, on the contrary, the electric current of outer circumferential side part reduces.Thus, the current blocking function that is caused by Schottky barrier reduces, and luminous efficiency also reduces.
For the light-emitting diode that the well-known current barrier layer that is made of the insulating properties material is set between bond pad electrode and semiconductor region for the idle current of the bottom of limiting the bond pad electrode, utilize the effect of current barrier layer can improve its luminous efficiency, but need to be used to form the special operation of current barrier layer on the contrary, the cost of light-emitting diode must increase.
Patent documentation 1: the spy opens the 2002-208729 communique
Summary of the invention
Therefore, the problem of desire solution of the present invention is: the problem that pressure drop is big and driving voltage is high of using the nitride-based semiconductor device of silicon substrate.
For solving above-mentioned problem, nitride-based semiconductor device of the present invention is characterised in that to possess: the p type silicon substrate with conductivity; The n type nitride-based semiconductor district that on an interarea of above-mentioned p type silicon substrate, forms; Be used to form the main semiconductor district of the major part that is configured in the semiconductor element in the said n type nitride-based semiconductor district; The 1st electrode that is connected with above-mentioned main semiconductor district; And the 2nd electrode that is connected with another interarea of above-mentioned p type silicon substrate.
The major part of above-mentioned semiconductor element means active or activation portion of semiconductor element.In addition, above-mentioned semiconductor element can have the other electrode outside the above-mentioned the 1st and the 2nd electrode.
As above-mentioned semiconductor element, when constituting light-emitting diode, in above-mentioned main semiconductor district, preferably comprise active layer and p type nitride semiconductor layer at least.
As above-mentioned semiconductor element, when transistor formed, in above-mentioned main semiconductor district, preferably comprise p type base and n type emitter region at least.
As above-mentioned semiconductor element, when constituting insulated-gate type field effect transistor, in above-mentioned main semiconductor district, preferably comprise p type tagma and n type source region at least.
Said n type nitride-based semiconductor district is preferably in and can forms from this n type nitride-based semiconductor district under the state of the current path of above-mentioned p type silicon substrate, contacts with above-mentioned p type silicon substrate.
Said n type nitride-based semiconductor district is preferably using chemical formula Al
aIn
bGa
1-a-bMixed in the material that N the represents zone of n type impurity, wherein, a and b are the numerical value that satisfies 0≤a＜1,0≤b＜1.
Above-mentioned semiconductor element is best and then possess the intermediary layer that is configured between said n type nitride-based semiconductor district and the above-mentioned p type silicon substrate, and this intermediary layer usefulness has the thickness that can obtain quantum-mechanical tunnel effect and has the material formation of the resistivity bigger than said n type nitride-based semiconductor district.
The material of above-mentioned intermediary layer is preferably for example used chemical formula Al
xIn
yGa
1-x-yThe nitride-based semiconductor that comprises aluminium that N represents, wherein, x and y are the numerical value that satisfies 0＜x≤1,0≤y＜1,0＜x+y≤1.
Above-mentioned semiconductor element preferably and then have a buffering area that is configured in the sandwich construction between said n type nitride-based semiconductor district and the above-mentioned main semiconductor district, the buffering area of above-mentioned sandwich construction comprises: constitute by the nitride-based semiconductor of the Al that comprises the 1st ratio (aluminium) a plurality of the 1st layer and by not comprising Al or comprise a plurality of the 2nd layer that the nitride-based semiconductor of the Al of 2nd ratio littler than above-mentioned the 1st ratio constitutes, above-mentioned the 1st layer with above-mentioned the 2nd layer alternately laminated.
Said n type nitride-based semiconductor district comprises: a plurality of the 1st floor that are made of the nitride-based semiconductor of the Al that comprises the 1st ratio (aluminium) and by not containing Al or comprising a plurality of the 2nd floor that the nitride-based semiconductor of the Al of 2nd ratio littler than above-mentioned the 1st ratio constitutes are above-mentioned the 1st layer of buffering areas with above-mentioned the 2nd layer of alternately laminated sandwich construction.
Above-mentioned the 1st layer of the buffering area of above-mentioned sandwich construction is preferably by using chemical formula Al
xM
yGa
1-x-yThe material that N represents constitutes, and wherein, above-mentioned M is at least a element of selecting from In (indium) and B (boron), and above-mentioned x and y are the numerical value that satisfies 0＜x≤1,0≤y＜1, x+y≤1, and, have the thickness that can access quantum-mechanical tunnel effect.
Above-mentioned the 2nd layer of the buffering area of above-mentioned sandwich construction is preferably by using chemical formula Al
aM
bGa
1-a-bThe material that N represents constitutes, and wherein, above-mentioned M is at least a element of selecting from In (indium) and B (boron), and above-mentioned a and b are the numerical value that satisfies 0≤a＜1,0≤b≤1, a+b≤1, a＜x.
As above-mentioned semiconductor element, when constituting light-emitting diode, the anode that is electrically connected with above-mentioned p type nitride semiconductor layer preferably is set as above-mentioned the 1st electrode, negative electrode is set as above-mentioned the 2nd electrode.
Can be enough and above-mentioned the conducting film with transmitance of p type nitride semiconductor layer electrical connection use metal level with being connected of on the part on the surface of above-mentioned conducting film, forming, constitute above-mentioned the 1st electrode of above-mentioned light-emitting diode.
Between the above-mentioned p type nitride semiconductor layer and above-mentioned conducting film in the above-mentioned main semiconductor district of above-mentioned light-emitting diode, can dispose n type nitride semiconductor layer.
As above-mentioned semiconductor element, when transistor formed, the emitter be electrically connected with said n type emitter region preferably is set as above-mentioned the 1st electrode, collector electrode is set as above-mentioned the 2nd electrode, and then, the base stage that setting is electrically connected with above-mentioned p type base.
As above-mentioned semiconductor element, when constituting insulated-gate type field effect transistor, the source electrode that is electrically connected with said n type source region preferably is set as above-mentioned the 1st electrode, drain electrode is set as above-mentioned the 2nd electrode, and then, gate electrode is set.
The effect of invention
According to the present invention, keep the crystal property in main semiconductor district good, just can easily reach the driving voltage that reduces semiconductor element significantly.That is, whether no matter use n type nitride-based semiconductor district, be in direct contact with it or by the silicon substrate of the mediate contact of intermediary layer on use p type silicon substrate with existing films of opposite conductivity.Therefore, on the heterojunction boundary of n type nitride-based semiconductor district and p type silicon substrate, there is interface energy level.In addition, under the situation that comprises the intermediary layer with quantum-mechanical tunnel effect, this intermediary layer is mediate, has interface energy level between n type nitride-based semiconductor district and p type silicon substrate.Above-mentioned interface energy level is to the contributive energy level of conductivity between n type nitride-based semiconductor district and the p type silicon substrate.By there being above-mentioned interface energy level, the charge carrier (electronics) in the p type silicon substrate is injected in the n type nitride-based semiconductor district well via above-mentioned interface energy level.Consequently, the potential barrier of the heterojunction between p type silicon substrate and the n type nitride-based semiconductor district, perhaps the potential barrier by the interface between the mediate n type of the intermediary layer with quantum-mechanical tunnel effect nitride-based semiconductor district and the p type silicon substrate reduces, and can reduce the driving voltage of semiconductor element significantly.When driving voltage reduced, the power loss of semiconductor element reduced.
In addition, can be enough existing n type silicon substrate be changed to the simple method of p type silicon substrate, reach the reduction driving voltage.Therefore, do not follow the rising of cost, just can seek the reduction of driving voltage.
In the light-emitting diode of concrete example of the present invention, at above-mentioned the 1st electrode by being connected under the situation about constituting of forming on the conducting film that is electrically connected with above-mentioned p type nitride semiconductor layer and the part with metal level on the surface of above-mentioned conducting film with transmitance, as mentioned above, produce Schottky barrier between connecting with metal level and semiconductor region, this Schottky barrier performance stops the function of the forward current of light-emitting diode.In having the light-emitting diode of this Schottky barrier, when the power loss of light-emitting diode and generate heat when big, just reduce the prevention function of the light-emitting diode forward current that causes because of Schottky barrier.In contrast, because the power loss of the light-emitting diode of concrete example of the present invention and generate heat for a short time so the prevention function of the forward current of the light-emitting diode that causes because of Schottky barrier can suppress to reduce, improves luminous efficiency.
Description of drawings
Fig. 1 is a profile of roughly representing the light-emitting diode of the embodiment of the invention 1.
Fig. 2 is the performance plot of the relation of the light-emitting diode of presentation graphs 1 and existing positive voltage of light emitting diode and electric current.
Fig. 3 is the reduction effect of driving voltage of light-emitting diode of expression comparison diagram 1 and the energy band diagram of existing light-emitting diode.
Fig. 4 is a profile of roughly representing the light-emitting diode of the embodiment of the invention 2.
Fig. 5 is a profile of roughly representing the light-emitting diode of the embodiment of the invention 3.
Fig. 6 is a profile of roughly representing the light-emitting diode of the embodiment of the invention 4.
Fig. 7 is a profile of roughly representing the light-emitting diode of the embodiment of the invention 5.
Fig. 8 is a transistorized profile of roughly representing the embodiment of the invention 6.
Fig. 9 is a profile of roughly representing the field-effect transistor of the embodiment of the invention 7.
Symbol description
1 p type silicon substrate
3 n type buffering areas
4,4a, 4b main semiconductor district
5, the 6 the 1st and the 2nd electrode
11 intermediary layers
Embodiment
Then, with reference to Fig. 1～Fig. 9 embodiments of the present invention are described.
The light-emitting diode of semiconductor element as the embodiment of the invention 1 shown in Figure 1, have p type silicon substrate 1, as the buffering area 3 in n type nitride-based semiconductor district, be used to constitute the main semiconductor district the 4, the 1st and the 2nd electrode 5,6 of main i.e. activation portion of light-emitting diode.Main semiconductor district 4 is made of epitaxially grown successively n type nitride semiconductor layer 13, active layer 14 and p type nitride semiconductor layer 15 on buffering area 3.
P type silicon substrate 1 is a feature structure important document of the present invention, and no matter whether configuration n type buffering area 3 has conduction type in contrast on this layer.The for example concentration 5 * 10 of in this silicon substrate 1, mixing
18Cm
-3～5 * 10
19Cm
-3About p type impurity promptly bring into play for example B 3 family's elements such as (boron) as the acceptor impurity function.Therefore, silicon substrate 1 is the conductive board with the low resistivity about 0.0001 Ω cm～0.01 Ω cm, and performance is as the function of the current path between the 1st and the 2nd electrode 5,6.In addition, this silicon substrate 1 has the thickness that can bring into play as the mechanical support functional substrate in buffering area on it 3 and main semiconductor district 4 etc., for example has 350nm thickness.
Constitute by the n type nitride-based semiconductor that the nitrogen of 1 of 3 families or a plurality of element and 5 families constitutes as the buffering area 3 that is configured in the n type nitride-based semiconductor district on the p type silicon substrate 1.The n type nitride-based semiconductor that is used for this buffering area 3 is preferably being used chemical formula Al
aIn
bGa
1-a-bAdded the nitride-based semiconductor of n type impurity (donor impurity) in the n type nitride-based semiconductor that N represents, wherein, a and b are the numerical value that satisfies 0≤a＜1,0≤b＜1, a+b＜1.That is, buffering area 3 preferably is made of the material of selecting from AlInGaN (indium gallium nitride aluminium), GaN (gallium nitride), AlInN (indium nitride aluminium), AlGaN (aluminum gallium nitride), is made of better indium gallium nitride aluminium (AlInGaN).A in the above-mentioned chemical formula is 0.1～0.7, and b is 0.0001～0.5 better.The composition of the buffering area 3 of this embodiment 1 is Al
0.5In
0.01Ga
0.49N.
The pooling feature that inherit well in the main semiconductor district 4 that is made of the nitride-based semiconductor district that buffering area 3 has mainly that the face orientation that is used for making silicon substrate 1 forms thereon.In order to bring into play this pooling feature well, buffering area 3 preferably has 10nm or above thickness.But in order to prevent the crackle of buffering area 3, the thickness that preferably makes buffering area 3 is 500nm or following.The thickness of the buffering area 3 of this embodiment 1 is 30nm.
The energy difference of the high level of the lowest energy level of the conduction band of nitride-based semiconductor and the valence band of silicon is smaller.Therefore, in the interface 2 of buffering area 3 that constitutes by n type nitride-based semiconductor and p type silicon substrate 1, form the heterojunction of well-known type 2 or type 3.Here, the high level that the heterojunction of so-called type 2 is meant in energy band diagram 2 semi-conductive valence band forming heterojunction is between the lowest energy level of the high level of another semi-conductive valence band and conduction band, and the lowest energy level of a conduction band is positioned at than the knot on the lowest energy level of another conduction band.In addition, the heterojunction of so-called type 3 is meant that the high level of 2 semi-conductive valence band forming heterojunction is positioned at than the knot on the lowest energy level of another semi-conductive conduction band.In the present embodiment, be under the situation of the above-mentioned type 2 at the buffering area 3 that constitutes by the nitride-based compound semiconductor of n type and the heterojunction of p type silicon substrate 1, the band structure of this heterojunction can enough Fig. 3 (B) expression.The n type buffering area 3 in this Fig. 3 (B) expression thermal equilibrium state and the band structure of p type silicon substrate 1 are arranged again.In Fig. 3 (A), (B), Ev represents the high level of valence band, and Ec represents the lowest energy level of conduction band, and Ef represents Fermi level.In addition, the interface energy level of representing the heterojunction between p type silicon substrate 1 and the n type buffering area 3 at the Et shown in the forbidden band of Fig. 3 (B).Under the situation of the heterojunction that forms the above-mentioned type 2 shown in Fig. 3 (B), have many interface energy level Et in the interface 2 of heterojunction, the charge carrier (electronics) that is arranged in the valence band of p type silicon substrate 1 injects the conduction band of the buffering area 3 that is made of n N-type semiconductor N district well via this interface energy level Et.Consequently, the potential barrier of the heterojunction between p type silicon substrate 1 and the n type buffering area 3 reduces, and driving voltage can reduce significantly.
Under the situation of the heterojunction that forms type 3, the charge carrier (electronics) that is arranged in the valence band of p type silicon substrate 1 directly is injected into the conduction band of the buffering area 3 that is made of n N-type semiconductor N district.Therefore, even under the situation of the heterojunction that forms type 3, the potential barrier of the heterojunction between p type silicon substrate 1 and the buffering area 3 that is made of n N-type semiconductor N district reduces, and driving voltage can reduce significantly.
The main semiconductor district 4 that is used for the light-emitting diode of well-known double heterojunction type structure is by n type nitride semiconductor layer 13, active layer 14, the p type nitride semiconductor layer 15 of configuration constitute successively on buffering area 3.Have again, also main semiconductor district 4 can be called lighting function district or activation district.And,, can from main semiconductor district 4, save n type nitride semiconductor layer 13 by n type nitride semiconductor layer 13 said functions of maintenance on the buffering area 3 that constitutes by n type nitride-based semiconductor with main semiconductor district 4.In addition, can save active layer 14 makes n type nitride semiconductor layer 13 directly contact with p type nitride semiconductor layer 15.
The n type nitride semiconductor layer 13 in main semiconductor district 4 is preferably ignored n type impurity and is made of the material with following chemical formulation.
Al
xIn
yGa
1-x-yN, wherein, x and y are the numerical value that satisfies 0≤x＜1,0≤y＜1.
The n type nitride semiconductor layer 13 of this embodiment by with above-mentioned chemical formula in the suitable n type GaN of x=0, y=0 constitute, have the about 2 μ m of thickness.This n type nitride semiconductor layer 13 is the nitride semiconductor layers that also can be called the n covering of light-emitting diode, has the band gap bigger than active layer 14.
In this embodiment, active layer 14 usefulness indium gallium nitrides (InGaN) form.Have again, in Fig. 1,, in fact have well-known multi-quantum pit structure though be roughly to represent active layer 14 with one deck.Certainly, also can constitute active layer 14 by enough one decks.In addition, in this embodiment, though the impurity of the decision conduction type that in active layer 14, do not mix, can doped p type or n type impurity.
Being configured in p type nitride semiconductor layer 15 on the active layer 14 preferably ignores p type impurity and is made of Al the material with following chemical formulation
xIn
yGa
1-x-yN, wherein, x and y are the numerical value that satisfies 0≤x＜1,0≤y＜1.
In this embodiment, the p type GaN of p type nitride semiconductor layer 15 usefulness thickness 500nm forms.This p type nitride semiconductor layer 15 is the nitride semiconductor layers that also can be called the p covering, has the band gap also bigger than active layer 14.
Owing to constitute n type nitride semiconductor layer 13, active layer 14 and the p type nitride semiconductor layer 15 in main semiconductor district 4, by buffering area 3 mediate being formed on the silicon substrate 1, so its crystal property is relatively good.
The 1st electrode 5 as anode is connected with p type nitride semiconductor layer 15, is connected with the following of silicon substrate 1 as the 2nd electrode 6 of negative electrode.Have again,, on p type nitride semiconductor layer 15, append the p type nitride semiconductor layer that contact usefulness is set, can connect the 1st electrode 5 here in order to connect the 1st electrode 5.
Then, the manufacturing method for LED of key diagram 1.
At first, preparing to have in the face orientation of the crystallization of representing with Miller index with (111) face is the p type silicon substrate 1 of interarea.
Then, with the corrosive liquid of HF class silicon substrate 1 is implemented well-known hydrogen finalization process.
Then, it is in the reative cell of organic metal epitaxially growing equipment that substrate 1 is put into well-known OMVPE (Organometallic VaporPhase Epitaxy), is warmed up to for example 1170 ℃.Then, the heat of carrying out under 1170 ℃ 10 minutes is cleaned, and behind the oxide-film on the surface of removing substrate 1, is set in 1000 ℃ or above predetermined temperature, for example is set in 1000～1100 ℃, then, and by OMVPE method epitaxial growth buffering area 3 on silicon substrate 1.Under the situation that buffering area 3 is made of n type indium gallium nitride aluminium (AlInGaN), in reative cell with predetermined ratio import well-known trimethyl aluminium gas (below, be called TMA), trimethyl indium gas (below, be called TMI), trimethyl gallium gas (below, be called TMG), ammonia and silane gas (SiH
4).Silane gas (SiH
4) Si (silicon) performance as the function of n type impurity.
Then, on buffering area 3, form n type nitride semiconductor layer 13, active layer 14 and p type nitride semiconductor layer 15 successively, obtain main semiconductor district 4 by well-known epitaxial growth method.For example, in order to form the n type nitride semiconductor layer 13 that constitutes by n type GaN, the temperature of substrate 1 is set in for example 1000～1110 ℃, for example, with predetermined ratio with TMG, silane (SiH
4) and ammonia supply response chamber.Thus, obtain the n type nitride semiconductor layer 13 that the n type GaN by thickness 2 μ m constitutes.The n type impurity concentration of this n type nitride semiconductor layer 13 for example is 3 * 10
18Cm
-3, lower than the impurity concentration of silicon substrate 1.When n type nitride semiconductor layer 13 began to form, because the crystal property of the buffering area 3 under it keeps good, the n type nitride semiconductor layer 13 in main semiconductor district 4 had the good crystal property of the crystal property of inheriting buffering area 3.
Then, on the n type nitride semiconductor layer 13 of performance, form the active layer 14 of well-known multi-quantum pit structure as n type covering function.In Fig. 1, for simplicity of illustration, the active layer 14 of multi-quantum pit structure is expressed as 1 layer, be actually by a plurality of barrier layers and a plurality of trap layer and constitute, barrier layer and trap layer replace repeated configuration, for example 4 repeated configuration.When forming this active layer 14, after forming the n type nitride semiconductor layer 13 that constitutes by n type GaN, stop to supply with to the gas of OMVPE device reaction chamber, the temperature of substrate 1 is dropped to 800 ℃, then, in reative cell, supply with TMG, TMI and ammonia, form for example by In with predetermined ratio
0.02Ga
0.98Constitute and the barrier layer that have thickness 13nm of N then, changes the ratio of TMI, forms for example by In
0.2Ga
0.8That N constitutes and have for example trap layer of 3nm of thickness.By for example repeating the formation of this barrier layer and trap layer for 4 times, obtain the active layer 14 of multi-quantum pit structure.Active layer 14 is inherited the crystal property of the n type nitride semiconductor layer 13 below it, has good crystal property.Have, for example impurity of p type can mix in active layer 14 again.
Then, the temperature of silicon substrate 1 is risen to 1000～1110 ℃, with predetermined ratio for example in the reative cell of OMVPE device, supply with trimethyl gallium (TMG), ammonia, two luxuriant magnesium gas (Biscyclopentadienyl, below, be called Cp
2Mg), on active layer 14, form the p type nitride semiconductor layer 15 that the p type GaN by the about 500nm of thickness constitutes.The concentration that imports magnesium (Mg) for example 3 * 10
18Cm
-3, performance is as the function of p type impurity.
Then, form the 1st and the 2nd electrode 5, finish light-emitting diode by well-known vacuum vapour deposition.
The characteristic curve A of Fig. 2 is illustrated on the 1st electrode 5 and is just applying, when applying negative forward voltage on the 2nd electrode 6, in the light-emitting diode of the foregoing description 1, flows through the electric current of this light-emitting diode.The electric current of the light-emitting diode of the B characteristic curve representation of Fig. 2 when substrate 1 and above-mentioned patent documentation 1 being had equally apply forward voltage on the existing light-emitting diode of n type silicon substrate.From this Fig. 2 as can be known, in order to be 3.36V during at characteristic curve A, when characteristic curve B, be 3.98V at the necessary driving voltage of the electric current that flows through 20mA on the light-emitting diode.Therefore, be altered to the so extremely simple method of p type from existing n type, just can be used in the driving voltage that flows through the 20mA electric current and reduce 0.62V by conduction type with substrate 1.
The effect of present embodiment then, is described with reference to the energy band diagram of Fig. 3.In order to compare the energy carrier state of the heterojunction of expression prior art in Fig. 3 (A), the energy carrier state of Fig. 3 (B) expression heterojunction of the present invention.
The heterojunction of the prior art shown in Fig. 3 (A) is made of n type Si substrate (n-Si) and direct epitaxially grown n type nitride semiconductor layer (AlInGaN) thereon.Has the potential barrier of the higher Δ Eb of aspect ratio owing in the heterojunction of this Fig. 3 (A), produce, so it is bigger to comprise the driving voltage of semiconductor element of this heterojunction.
In contrast, the p type silicon substrate 1 of the embodiments of the invention shown in Fig. 3 (B) is lower with the potential barrier of the heterojunction of the n type buffering area 3 that is made of n type nitride-based semiconductor (AlInGaN), and, on the interface 2 of this heterojunction, there are many interface energy level Et.This interface energy level Et has raising in the generation in the electronics at the interface 2 of heterojunction and hole and the function of combination again between the lowest energy level of the conduction band of the high level of the valence band of p type silicon substrate 1 and n type buffering area 3.To comprise the interface 2 of this interface energy level Et and generation that near zone is called electronics and hole thereof and the promotion district of combination again.In the present embodiment, the charge carrier (electronics) in the p type silicon substrate 1 shown in the right side of Fig. 3 (B) median surface 2 can be injected into via this interface energy level Et in the n type buffering area 3 shown in the left side at interface 2 well.Thus, charge carrier can be transported to the n type buffering area 3 from p type silicon substrate 1 effectively.Consequently, the heterojunction between p type silicon substrate 1 and the n type buffering area 3 is smaller to the potential barrier of the charge carrier (electronics) in the p type silicon substrate 1, can reduce the driving voltage of the forward of light-emitting diode significantly.
As mentioned above,, can keep the crystal property in main semiconductor district 4 well, easily reach the driving voltage that reduces light-emitting diode significantly according to present embodiment.When driving voltage reduced, the power consumption of light-emitting diode reduced.
In addition, use existing n type silicon substrate is changed to p type silicon substrate 1 so simple method, can reach the driving voltage that reduces light-emitting diode.Therefore, the cost that can not be accompanied by light-emitting diode rises, and just can seek the reduction of driving voltage.
The light-emitting diode of embodiment shown in Figure 42 then, is described.But in Fig. 4 and Fig. 5～Fig. 9 described later, the same symbol of mark omits its explanation on substantially identical with Fig. 1 part.
The light-emitting diode of Fig. 4 is arranged on the buffering area 3a of the distortion of the buffering area 20 that has added sandwich construction on the buffering area 3 of Fig. 1, is identical structure with Fig. 1 in addition.The distortion buffering area 3a of Fig. 4 is that the buffering area 20 of configuring multi-layer structure forms by on the n type buffering area 3 that constitutes at the n type indium gallium nitride aluminium (AlInGaN) with the same formation of Fig. 1.The sandwich construction buffering area 20 of Fig. 4 is by repeating a plurality of the 1st layer 21 and a plurality of the 2nd layer of 22 formations of alternate configurations.A plurality of the 1st layer of 21 nitride-based semiconductors by the Al that comprises the 1st ratio (aluminium) form.A plurality of the 2nd layer 22 is made of the nitride-based semiconductor that does not comprise Al or comprise the Al of the 2nd ratio littler than above-mentioned the 1st ratio.
Preferably ignore n type impurity and constitute Al by nitride-based semiconductor for above-mentioned the 1st layer 21 with following chemical formulation
xM
yGa
1-x-yN, wherein, above-mentioned M is at least a kind of element selecting from In (indium) and B (boron), above-mentioned x and y are the numerical value that satisfies 0＜x≤1,0≤y＜1, x+y≤1.
Above-mentioned the 1st layer 21 preferably has the thickness that can access quantum-mechanical tunnel effect, for example has the thickness of 1～10nm.Have, in this embodiment, the 1st layer 21 is made of n type AlN, comprises Si (silicon) as n type impurity again.But the 1st layer 21 also can be the nitride-based semiconductor that does not comprise the non-doping of n type impurity.
Above-mentioned the 2nd layer 22 preferably constitutes Al by ignoring the nitride-based semiconductor of n type impurity with following chemical formulation
aM
bGa
1-a-bN, wherein, above-mentioned M is at least a kind of element selecting from In (indium) and B (boron), above-mentioned a and b are the numerical value that satisfies 0≤a＜1,0≤b≤1, a+b≤1, a＜x.
Preferably comprise Si (silicon) for the 2nd layer 22 as n type impurity.In addition, the 2nd layer of 22 the most handy and n type buffering area 3 same nitride-based semiconductors form, and in this embodiment, GaN constitutes by the n type.Have again, the 2nd layer 22 thickness preferably than the 1st layer 21 thicker and also be quantum-mechanical tunnel effect do not take place thickness promptly 10 μ m or more than.But, also can make the 2nd layer 22 and become the thickness that can access quantum-mechanical tunnel effect or with the 1st layer of 21 identical thickness.
When the buffering area 20 of the sandwich construction that forms distortion buffering area 3a, behind the n type buffering area 3 that forms downside, for example with TMA (trimethyl aluminium) 50 μ mol/min, silane (SiH
4) ratio of 20nmol/min, ammonia 0.14mol/min flows in the reative cell, be made of n type AlN the 1st layer 21 of epitaxial growth thickness 5nm.Then, stop the supply of TMA, continue to supply with silane and ammonia, meanwhile, with the proportional flow TMG of 50 μ mol/min, the 2nd layer 22 of constituting by the n type GaN of thickness 25nm of epitaxial growth.Repeat 1 and the 2nd layer 21,22 formation operation of 20 order, obtain the buffering area 20 of sandwich construction.In Fig. 4,, only represent 4 layers respectively for the 1st and the 2nd layer 21,22 for simplicity of illustration.
As shown in Figure 4, when appending the buffering area 20 of sandwich construction, can improve the uppermost flatness of buffering area 3a.
Have again, in Fig. 4, also can save buffering area 3, the buffering area 20 of sandwich construction is directly contacted with p type silicon substrate 1.That is, the buffering area 20 of sandwich construction of Fig. 4 can be set to replace the buffering area 3 of Fig. 1 and Fig. 6～Fig. 9.Under the buffering area 20 of the sandwich construction that makes Fig. 4 and situation that p type silicon substrate 1 directly contacts, both go up and add n type impurity to be preferably in the 1st and the 2nd layer 21,22.
The light-emitting diode of embodiment 3 shown in Figure 5, the intermediary layer 11 that configuration is made of the nitride-based semiconductor that comprises aluminium between the p of Fig. 1 type silicon substrate 1 and n type buffering area 3, and also as n type covering, other and Fig. 1 are same spline structures with n type buffering area 3 dual-purposes.In Fig. 5, intermediary layer 11 is shown distortion buffering area 3b with the combination table of n type buffering area 3, and active layer 14 is shown main semiconductor district 4a with the combination table of the p type nitride-based semiconductor district 15a that is made of InGaN.
Al
xIn
yGa
1-x-yN
Wherein, x and y are the numerical value that satisfies 0＜x≤1,0≤y＜1,0＜x+y≤1.In this embodiment 3, in intermediary layer 11, do not comprise n type impurity.But, in intermediary layer 11, also can comprise n type impurity.
Intermediary layer 11 is the films with resistivity higher than the resistivity of n type buffering area 3.This intermediary layer 11 preferably has the thickness of 1～60nm scope, in addition, more wishes to have the thickness of for example 1～10nm that can access quantum-mechanical tunnel effect, and, preferably have the thickness about 2～3nm.Have at intermediary layer 11 under the situation of the thickness that can access quantum-mechanical tunnel effect,, can ignore intermediary layer 11 in fact the n type buffering area 3 that constitutes by n type nitride-based semiconductor district and the conductivity between the p type silicon substrate 1.Therefore, the charge carrier (electronics) in the p type silicon substrate 1 via the interface energy level Et in the heterojunction boundary that is present between n type buffering area 3 and the p type silicon substrate 1, is injected in the n type buffering area 3 that is made of n type nitride-based semiconductor district well.Consequently, similarly to Example 1, the potential barrier of the heterojunction between p type silicon substrate 1 and the n type buffering area 3 reduces, and the driving voltage of light-emitting diode can reduce significantly.Intermediary layer 11 on the characteristic preferably the difference of the lattice constant between intermediary layer 11 and the p type silicon substrate 1 than the little material of difference of the lattice constant between n type buffering area 3 or main semiconductor district 4～4c and the p type silicon substrate 1.In addition, intermediary layer 11 is the thermal coefficient of expansion between intermediary layer and the p type silicon substrate 1 poor preferably on the characteristic, than the littler material of difference of the thermal coefficient of expansion between n type buffering area 3 or main semiconductor district 4～4c and the p type silicon substrate 1.
Embodiment 4
The light-emitting diode of embodiment 4 shown in Figure 6 has the 1st electrode 5a that has been out of shape, and other are identical structures with Fig. 1.
The 1st electrode 5a of Fig. 6 is made of with being connected with metal level 52 transmitance conducting film 51, and above-mentioned transmitance conducting film 51 is by the indium oxide (In that promptly forms on the surface of p type nitride semiconductor layer 15 almost all on the surface in main semiconductor district 4
2O
3) and tin oxide (ZnO
2) mixture be formations such as ITO, above-mentioned connection is to form on the lip-deep cardinal principle middle body of this conducting film 51 with metal level 52, also can be called the bond pad electrode.
The current potential that applies the 1st electrode 5a between the 1st and the 2nd electrode 5a, 6 is during than the high forward voltage of the current potential of the 2nd electrode 6, and electric current flows to the main semiconductor district 4 from conducting film 51.Since connect with metal level 52 and main semiconductor district 4 Schottky contacts, thus electric current suppressed by Schottky barrier, mediate by the Schottky barrier that connects with between metal level 52 and the main semiconductor district 4, flow through electric current hardly.Therefore, occupy the major part of the electric current between the 1st and the 2nd electrode 5a, 6 from the outer circumferential side electric current composition partly in conducting film 51 inflow main semiconductor districts 4.Based on the light that electric current took place of the outer circumferential side part that flows through main semiconductor district 4, do not hindered ground to take out with metal level 52 from the top of transmitance conducting film 51 by the not radioparent connection of light.
As illustrating, along with the rising Schottky barrier deterioration of temperature, by the leakage current increase of Schottky barrier.Because the light-emitting diode of the light-emitting diode of the embodiment 4 of Fig. 6 and the embodiment 1 of Fig. 1 is same, the light-emitting diode that is to use p type silicon substrate 1 to constitute, so the driving voltage of forward is smaller similarly to Example 1, power consumption and heating are littler than the light-emitting diode that uses existing n type silicon substrate.Therefore, suppress based on the connection of the heating in silicon substrate 1 and main semiconductor district 4 deterioration with the Schottky barrier between metal level 52 and the main semiconductor district 4, the electric current by Schottky barrier reduces.Consequently, the light-emitting diode of electric current between the 1st and the 2nd electrode 5a, 6 and the existing n type silicon substrate of use under similar circumstances, the electric current that flows through the outer circumferential side part in main semiconductor district 4 increases circuital ratio, and luminous efficiency is bigger than the luminous efficiency of the light-emitting diode that uses existing n type silicon substrate.In addition, the heating and the heating of the light-emitting diode that uses existing n type silicon substrate of the main semiconductor district 4 of Fig. 6 and silicon substrate 1 can be identical situation under, can partly flow through than existing bigger electric current the luminous efficiency increase at the outer circumferential side in main semiconductor district 4.
Even in this embodiment 4, also can obtain effect similarly to Example 1 based on p type silicon substrate 1.
Have, the structure of the 1st electrode 5a of the distortion of Fig. 6 also can be applied to Fig. 4 and embodiment 2 shown in Figure 5 and 3 light-emitting diode again.
The light-emitting diode of embodiment 5 shown in Figure 7, in addition the auxiliary nitride semiconductor layer 53 of additional n type between the 1st electrode 5a of the light-emitting diode of the embodiment 4 of Fig. 6 and main semiconductor district 4 is the structure identical with Fig. 6.The auxiliary nitride semiconductor layer 53 of n type preferably is made of the material of ignoring the enough following chemical formulations of n type impurity energy.
Al
xIn
yGa
1-x-yN
Wherein, x and y are the numerical value that satisfies 0≤x＜1,0≤y＜1.
The auxiliary nitride semiconductor layer 53 of the n type of the embodiment 5 of Fig. 7 is made of the n type GaN that is equivalent to x=0, y=0 in the above-mentioned chemical formula.
An interarea of the additional auxiliary nitride semiconductor layer 53 of n type contacts with p type nitride semiconductor layer 15 in Fig. 7, and another interarea contacts with transmitance conducting film 51.Under the situation that transmitance conducting film 51 is made of ITO, because ITO has the characteristic same with the n N-type semiconductor N, conducting film 51 is extremely low with the resistance value of the ohmic contact of the auxiliary nitride semiconductor layer 53 of n type, and the power consumption here reduces, further reduce positive drive voltage, improve luminous efficiency.
In order to prevent that the pn knot between auxiliary nitride semiconductor layer 53 of n type and the p type nitride semiconductor layer 15 from hindering forward current, preferably making the thickness of the auxiliary nitride semiconductor layer 53 of n type is 1～30nm, is that 5～10nm is better.In addition, the thickness of the auxiliary nitride semiconductor layer 53 of n type preferably can access the thickness of quantum-mechanical tunnel effect.
When applying forward voltage between the 1st and the 2nd electrode 5a, 6 at Fig. 7, electric current flow into the p type nitride semiconductor layer 15 from conducting film 51 by the auxiliary nitride semiconductor layer of n type 53 is mediate.In this embodiment 5, by the forward voltage drop between auxiliary nitride semiconductor layer 15 of the p type of the auxiliary nitride semiconductor layer 53 intervenient states of n type and the conducting film 51, littler than the forward voltage drop between auxiliary nitride semiconductor layer 15 of the p type of Fig. 6 and the conducting film 51.Therefore, can reduce positive drive voltage, improve luminous efficiency.
The embodiment 2 and 3 that structure and the auxiliary nitride semiconductor layer 53 of n type of the 1st electrode 5a of Fig. 7 can be applied to Fig. 4 and Fig. 5.
The transistor of embodiment 6 shown in Figure 8, the main semiconductor district 4 that will be used for the light-emitting diode of Fig. 1 is replaced as and is used for transistorized main semiconductor district 4b, is identical structure with Fig. 1 in addition.In this Fig. 8, the n type nitride-based semiconductor district 13 that the n type GaN of main semiconductor district 4b constitutes and than it more the structure of downside be identical with Fig. 1.For transistor formed, main semiconductor district 4b has epitaxially grown base region 31 that is made of p type nitride-based semiconductor and the epitaxially grown emitter region 32 that is made of n type nitride-based semiconductor thereon thereon outside the n type nitride-based semiconductor district 13 as collector area performance function.On base region 31, connect base stage 33, on emitter region 32, connect emitter 34 as the 1st electrode.Following electrode 6 performances of p type silicon substrate 1 are as the function of collector electrode.
Because the transistor of Fig. 8 is the npn transistor npn npn,, emitter 34 effluent overcurrent from collector electrode 6 side direction so when its conducting driven, make collector electrode 6 be maximum potential.Even in this transistor, also can and the pressure drop of Fig. 1 when similarly reducing conducting between 2 electrodes 6,34.
Embodiment 7
The insulated-gate type field effect transistor of embodiment 7 shown in Figure 9, the main semiconductor district 4 that will be used for the light-emitting diode of Fig. 1 is replaced as the main semiconductor district 4c that is used for field-effect transistor, in addition, is the structure identical with Fig. 1.On the main semiconductor district of Fig. 9 4c, the n type nitride-based semiconductor district 13 that is made of the n type GaN identical with Fig. 1 is set.In Fig. 9,13 performances of n type nitride-based semiconductor district are as the function in drain region.By in n type nitride-based semiconductor district 13, importing p type impurity, the tagma 41 that is made of p type nitride-based semiconductor is set, by in this tagma 41, importing n type impurity, the source region 42 that is made of n type nitride-based semiconductor is set.On source region 42 and surface as the tagma 41 between the n type nitride-based semiconductor district 13 in drain region, dielectric film 43 mediate configuration gate electrodes 44.On source region 42, connect source electrode 45 as the 1st electrode.Following the 2nd electrode 6 performances of p type silicon substrate 1 are as the function of drain electrode.
Even in the field-effect transistor of Fig. 9, source electrode 45 when conducting drives and the pressure drop between the drain electrode 6 also reduce.
The present invention only limits to the above embodiments, for example also can be following distortion.
(1) buffering area 3 of the field-effect transistor of the transistorized buffering area 3 of the buffering area 3 of the light-emitting diode of Fig. 6 and Fig. 7, Fig. 8 and Fig. 9 can be replaced as the buffering area 3a of Fig. 4 or the buffering area 3b of Fig. 5.
(2) buffering area 3 of Fig. 8 and Fig. 9 can be also used as collector area or drain region.
(3) in Fig. 4, Fig. 6, Fig. 7, Fig. 8 and Fig. 9, can between buffering area 3 and p type silicon substrate 1, dispose the intermediary layer 11 that has by the quantum-mechanical tunnel effect that constitutes with same AlN of Fig. 5 etc.That is, in Fig. 4, Fig. 6, Fig. 7, Fig. 8 and Fig. 9, can with between chain-dotted line 11 ' and the p type silicon substrate 1 as the intermediary layer that constitutes by AlN etc. with quantum-mechanical tunnel effect.
(4) in the buffering area 3 of each embodiment, 3a, 3b, can further add other semiconductor layer.
(5) though in each execution mode, in buffering area 3,3a, 3b, comprise In, also can be the layer that does not comprise In.
(6) can apply the present invention to have the rectifier diode of pn knot and have in the Schottky diode of Schottky barrier electrode.In addition, can apply the present invention in all semiconductor elements of the thickness direction upper reaches of substrate 1 overcurrent.
Industrial applicability
The present invention can be applied to light emitting diode, transistor, field-effect transistor and rectification two In the semiconductor elements such as utmost point pipe.
Claims (14)
1. nitride-based semiconductor device is characterized in that possessing:
P type silicon substrate with conductivity;
The n type nitride-based semiconductor district that on an interarea of above-mentioned p type silicon substrate, forms;
Be used to form the main semiconductor district of the major part that is configured in the semiconductor element in the said n type nitride-based semiconductor district;
The 1st electrode that is connected with above-mentioned main semiconductor district; And
The 2nd electrode that is connected with another interarea of above-mentioned p type silicon substrate.
2. nitride-based semiconductor device as claimed in claim 1 is characterized in that,
Said n type nitride-based semiconductor district contacts with above-mentioned p type silicon substrate forming from this n type nitride-based semiconductor district under the state of the current path of above-mentioned p type silicon substrate.
3. nitride-based semiconductor device as claimed in claim 1 is characterized in that,
Said n type nitride-based semiconductor district is using chemical formula Al
aIn
bGa
1-a-bMixed in the material that N the represents zone of n type impurity, wherein, a and b are the numerical value that satisfies 0≤a＜1,0≤b＜1.
4. nitride-based semiconductor device as claimed in claim 1 is characterized in that,
Also possess: be configured in the intermediary layer between said n type nitride-based semiconductor district and the above-mentioned p type silicon substrate, the material formation that has the thickness that can obtain quantum-mechanical tunnel effect and have the resistivity bigger of this intermediary layer than said n type nitride-based semiconductor district.
5. nitride-based semiconductor device as claimed in claim 4 is characterized in that,
The material of above-mentioned intermediary layer is the nitride-based semiconductor that comprises aluminium.
6. nitride-based semiconductor device as claimed in claim 5 is characterized in that,
Said n type nitride-based semiconductor district is using chemical formula Al
aIn
bGa
1-a-bMixed in the material that N the represents zone of n type impurity, wherein, a and b are the numerical value that satisfies 0≤a＜1,0≤b＜1,
And above-mentioned intermediary layer is to use chemical formula Al
xIn
yGa
1-x-yThe material that N represents constitutes, and wherein, x and y are the numerical value that satisfies 0＜x≤1,0≤y＜1,0＜x+y≤1, a＜x.
7. nitride-based semiconductor device as claimed in claim 1 is characterized in that,
Also has the buffering area that is configured in the sandwich construction between said n type nitride-based semiconductor district and the above-mentioned main semiconductor district, the buffering area of above-mentioned sandwich construction comprises: constitute by the nitride-based semiconductor of the Al that comprises the 1st ratio (aluminium) a plurality of the 1st layer and by not comprising Al or comprise a plurality of the 2nd layer that the nitride-based semiconductor of the Al of 2nd ratio littler than above-mentioned the 1st ratio constitutes, above-mentioned the 1st layer with above-mentioned the 2nd layer alternately laminated.
8. nitride-based semiconductor device as claimed in claim 1 is characterized in that,
Said n type nitride-based semiconductor district comprises: a plurality of the 1st floor that are made of the nitride-based semiconductor of the Al that comprises the 1st ratio (aluminium) and by not containing Al or comprising a plurality of the 2nd floor that the nitride-based semiconductor of the Al of 2nd ratio littler than above-mentioned the 1st ratio constitutes are above-mentioned the 1st layer of buffering areas with above-mentioned the 2nd layer of alternately laminated sandwich construction.
9. as claim 7 or 8 described nitride-based semiconductor devices, it is characterized in that,
Above-mentioned the 1st layer by using chemical formula Al
xM
yGa
1-x-yThe material that N represents constitutes, and wherein, above-mentioned M is at least a element of selecting from In (indium) and B (boron), and above-mentioned x and y are the numerical value that satisfies 0＜x≤1,0≤y＜1, x+y≤1, and, have the thickness that can access quantum-mechanical tunnel effect,
Above-mentioned the 2nd layer by using chemical formula Al
aM
bGa
1-a-bThe material that N represents constitutes, and wherein, above-mentioned M is at least a element of selecting from In (indium) and B (boron), and above-mentioned a and b are the numerical value that satisfies 0≤a＜1,0≤b≤1, a+b≤1, a＜x.
10. nitride-based semiconductor device as claimed in claim 1 is characterized in that,
Above-mentioned main semiconductor district is the zone that is used to form light-emitting diode, at least have active layer and the p type nitride semiconductor layer that is configured on this active layer, above-mentioned the 1st electrode is the anode that is electrically connected with above-mentioned p type nitride semiconductor layer, and above-mentioned the 2nd electrode is a negative electrode.
11. nitride-based semiconductor device as claimed in claim 10 is characterized in that,
Above-mentioned the 1st electrode comprises: by the conducting film with transmitance that is electrically connected with above-mentioned p type nitride semiconductor layer and being connected of forming use metal level on the part on the surface of above-mentioned conducting film.
12. nitride-based semiconductor device as claimed in claim 11 is characterized in that,
Above-mentioned main semiconductor district also has the n type nitride semiconductor layer that is configured on the above-mentioned p type nitride semiconductor layer,
Above-mentioned conducting film is connected with said n type nitride semiconductor layer.
13. nitride-based semiconductor device as claimed in claim 1 is characterized in that,
Above-mentioned main semiconductor district is the zone that is used for transistor formed, at least have p type base and n type emitter region, above-mentioned the 1st electrode is the emitter that is electrically connected with said n type emitter region, and above-mentioned the 2nd electrode is a collector electrode, and then, have the base stage that is electrically connected with above-mentioned p type base.
14. nitride-based semiconductor device as claimed in claim 1 is characterized in that,
Above-mentioned main semiconductor district is the zone that is used to constitute insulated-gate type field effect transistor, at least have p type tagma and with this p type tagma in abutting connection with the configuration n type source region, above-mentioned the 1st electrode is the source electrode that is electrically connected with said n type source region, above-mentioned the 2nd electrode is a drain electrode, and then, have gate electrode.
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| CN103730478A (en) * | 2012-10-10 | 2014-04-16 | 三垦电气株式会社 | Semiconductor light emitting device |
| CN107871803A (en) * | 2017-11-02 | 2018-04-03 | 厦门三安光电有限公司 | A kind of nitride semiconductor LED and preparation method thereof |
| CN110707148A (en) * | 2019-09-02 | 2020-01-17 | 华南师范大学 | Epitaxial wafer, epitaxial wafer manufacturing method, diode and rectifier |
| CN117594442A (en) * | 2024-01-18 | 2024-02-23 | 常州承芯半导体有限公司 | Semiconductor device and method of forming the same |
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2004
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103730478A (en) * | 2012-10-10 | 2014-04-16 | 三垦电气株式会社 | Semiconductor light emitting device |
| CN103730478B (en) * | 2012-10-10 | 2016-05-04 | 三垦电气株式会社 | Semiconductor light-emitting apparatus |
| CN107871803A (en) * | 2017-11-02 | 2018-04-03 | 厦门三安光电有限公司 | A kind of nitride semiconductor LED and preparation method thereof |
| CN107871803B (en) * | 2017-11-02 | 2019-11-19 | 厦门三安光电有限公司 | A kind of nitride semiconductor LED and preparation method thereof |
| CN110707148A (en) * | 2019-09-02 | 2020-01-17 | 华南师范大学 | Epitaxial wafer, epitaxial wafer manufacturing method, diode and rectifier |
| WO2021042407A1 (en) * | 2019-09-02 | 2021-03-11 | South China Normal University | Epitaxial wafer, method of manufacturing epitaxial wafer, diode, and current rectifier |
| CN110707148B (en) * | 2019-09-02 | 2021-08-17 | 华南师范大学 | Epitaxial wafer, epitaxial wafer manufacturing method, diode and rectifier |
| US12087868B2 (en) | 2019-09-02 | 2024-09-10 | South China Normal University | Epitaxial wafer, method of manufacturing the epitaxial wafer, diode, and current rectifier |
| CN117594442A (en) * | 2024-01-18 | 2024-02-23 | 常州承芯半导体有限公司 | Semiconductor device and method of forming the same |
| CN117594442B (en) * | 2024-01-18 | 2024-05-28 | 常州承芯半导体有限公司 | Semiconductor device and method of forming the same |
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