CN1841747A - Semiconductor device and method for fabricating the same - Google Patents

Semiconductor device and method for fabricating the same Download PDF

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CN1841747A
CN1841747A CN 200510125091 CN200510125091A CN1841747A CN 1841747 A CN1841747 A CN 1841747A CN 200510125091 CN200510125091 CN 200510125091 CN 200510125091 A CN200510125091 A CN 200510125091A CN 1841747 A CN1841747 A CN 1841747A
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film
semiconductor substrate
silicon
groove
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CN100474593C (en
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小仓寿典
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Fujitsu Ltd
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Fujitsu Ltd
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Abstract

Provided are a semiconductor device and method for manufacturing the same. The semiconductor device comprises a silicon substrate 14 having a step formed in the surface which makes the surface in a flash memory cell region 10 lower than the surface in a peripheral circuit region 12 ; a device isolation region 20 a formed in a trench 18 in the flash memory cell region 10 ; a device isolation region 20 c formed in a trench 24 deeper than the trench 18 in the peripheral circuit region 12 ; a flash memory cell 46 including a floating gate 32 and a control gate 40 formed on the device region defined by the device isolation region 20 a; and transistors 62, 66 formed on the device regions defined by the device isolation region 20 c.

Description

Semiconductor device and manufacture method thereof
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, relate more specifically to a kind of semiconductor device and manufacture method thereof that comprises nonvolatile memory.
Background technology
In comprising the semiconductor device of nonvolatile memory, except flash cell, the low voltage transistor that is used to control the high voltage transistor of flash memory and be used for high performance logic circuits is integrated in a semiconductor chip.Flash cell has the grid of stepped construction (stacked structure), and the grid of this stepped construction is made of stacked control grid and floating grid, and it is different from the grid of the single layer structure of high voltage transistor and low voltage transistor.Therefore, comprise that the semiconductor device of nonvolatile memory has special manufacturing process, wherein form the grid of single layer structure and the grid of stepped construction respectively by same technology.
For example, in the process of making semiconductor device, wherein this semiconductor device comprises the flash cell of the small stepped construction that meets the 90nm technology, and the degree of depth of the groove that forms in the device isolation process by STI (shallow trench isolation from) must be different between peripheral circuit region and flash cell district.That is to say, in peripheral circuit region, the ditch groove depth that forms by STI to a certain degree, to guarantee to be applied in the insulation between the high-tension transistor.On the other hand, in the flash cell district, the groove that forms by STI must be more shallow than those grooves in the peripheral circuit region, to prevent as device isolation region defective such as complete filling not.
The degree of depth that forms groove and groove by STI different technology between peripheral circuit region and flash memory area is independently to carry out the device isolation based on STI in peripheral circuit region and flash cell district.
Yet,, need high (overlay) accuracy that covers for meeting for example micro devices pattern of 90nm technology.The device isolation based on STI of therefore, independently carrying out in peripheral circuit region and flash cell district needs step management less feasible.This can not satisfy the needs that reduce the device pattern size, promptly reduces the design rule of (mitigate) peripheral circuit etc., so that it is bigger to be used to form the room for maneuver of pattern, thereby satisfies the needs that cover accuracy.
In addition, for the impurity diffusion zone that will in Semiconductor substrate, form, need have the high accuracy that covers.Make diffusion of impurities in these impurity diffusion layers by heat treatment.When increasing heat treated number of times in some cases, for example in peripheral circuit region and flash cell district, independently carry out device isolation based on STI, then be difficult to satisfy the required covering accuracy of impurity diffusion zone.And increased the room for maneuver that is used to form pattern in this case, but can not satisfy the needs of the size that reduces device pattern.
The technology that is used for form the groove of different depth based on the device isolation of STI has been described in list of references 1 (Japanese kokai publication hei No.Hei 7-66276 (1995)).
Yet the technology of describing in patent documentation 1 has following shortcoming.
At first, buried dielectric in the groove of the different depth that forms by STI, for example polysilicon etc.Therefore, be difficult to guarantee insulation, and this is to comprise that the semiconductor device of flash cell is required by device isolation.The device isolation of the semiconductor device of flash cell then can not obtain required device property if the technology of describing in the patent documentation 1 is applied to comprise.
In the technology that list of references 1 is described, be used to form the heat treatment of the groove of different depth time and again, and the diffusion of impurity is inevitable in the trap.This diffusion of impurity is the obstacle that reduces the semiconductor device size.
In another technology that list of references 1 is described, below NSG (non-impurity-doped silicate glass) film of etching mask, forming polysilicon film pattern.In mask film, be provided with owing to the step (step) that exists and do not exist polysilicon film to form.Utilize step in the mask film in silicon substrate, to form the groove of different depth.Yet, on up-and-down step, be very difficult to form micro pattern.
For example, in Japanese kokai publication hei No.2002-76148 and Japanese kokai publication hei No.2003-289114 background technology of the present invention is disclosed.
Summary of the invention
The purpose of this invention is to provide a kind of semiconductor device and manufacture method thereof that comprises nonvolatile memory, thereby allow under the condition that can not make step become complicated, to form the groove of different depth, and form small memory cell with pinpoint accuracy.
According to a scheme of the present invention, a kind of semiconductor device is provided, it comprises: Semiconductor substrate, it forms a step in the surface, and this step makes surface ratio second district surperficial low in the district that wins; First device isolation region, it is formed in first groove that forms in the Semiconductor substrate in this first district; Second device isolation region, it is formed in second groove that forms in the Semiconductor substrate in this second district, and this second groove is than the first ditch groove depth; Memory cell, it comprises: floating grid, it is formed on first device region of this first device isolation area definition, and forms first dielectric film between this floating grid and this first device region; And the control grid, it is formed on this floating grid, and forms second dielectric film between this control grid and this floating grid; And transistor, it is formed on second device region of this second device isolation area definition.
According to another aspect of the present invention, a kind of manufacture method of semiconductor device is provided, it comprises the steps: to form first conducting film that will become floating grid on the Semiconductor substrate in first district, and form first dielectric film between this first conducting film and this Semiconductor substrate, this first dielectric film has the etching characteristic that is different from this Semiconductor substrate; Form mask on the Semiconductor substrate in this first conducting film and second district, this mask has first opening that is formed in first district and second opening that is formed in this second district; Be etched in first conducting film, first dielectric film and the Semiconductor substrate that expose in this first opening, be etched in the Semiconductor substrate that exposes in this second opening simultaneously, in the Semiconductor substrate in this first district, to form first groove, form second groove than this first ditch groove depth simultaneously in the Semiconductor substrate in this second district, this first conducting film is patterned into this floating grid; In first groove that limits first device region, form first device isolation region, in second groove that limits second device region, form second device isolation region simultaneously; And on this floating grid, form the control grid, and between this control grid and this floating grid, form second dielectric film, on this second device region, form transistorized grid simultaneously.
According to the present invention, on the Semiconductor substrate in first district, form first conducting film that will become floating grid, and form first dielectric film between this first conducting film and this Semiconductor substrate, the etching characteristic of this first dielectric film is different from the etching characteristic of this Semiconductor substrate; Form mask on the Semiconductor substrate in first conducting film and second district, this mask has first opening that is formed in first district and second opening that is formed in this second district; Be etched in first conducting film, first dielectric film and the Semiconductor substrate that expose in this first opening, be etched in the Semiconductor substrate that exposes in this second opening simultaneously; Form the first more shallow groove relatively thus in the Semiconductor substrate in this first district, in this first groove, be formed for limiting first device isolation region of first device region, form the second darker groove relatively simultaneously in the Semiconductor substrate in second district, in this second groove, be formed for limiting second device isolation region of second device region.
According to the present invention, in the surface of this Semiconductor substrate, form a step, thereby surperficial low in this second district of the surface ratio in this first district can make the upper level of first conducting film that forms floating grid be substantially equal to the upper level of the Semiconductor substrate in this second district thus.Therefore, can be with the Semiconductor substrate in pinpoint accuracy patterning second district and first conducting film, this makes can provide the semiconductor device that comprises small memory cell.
According to the present invention, the step that forms in the surface of this Semiconductor substrate guarantees to form the flatness of the substrate surface of conducting film, and this conducting film is used to form control grid in first district and the grid in second district.Therefore, can in first district, form small control grid, in second district, form small grid simultaneously with pinpoint accuracy with pinpoint accuracy.
According to the present invention, when first conducting film that forms floating grid is patterned, be formed on first groove that wherein forms first device isolation region in first district by autoregistration, thus, can not form first groove by the pinpoint accuracy aligned pattern.Therefore, the present invention can help to reduce the size of memory cell.
According to the present invention, on sidewalls of floating gates, form the sidewall sections of second conducting film, this feasible electric capacity that can increase between floating grid and the control grid.According to the present invention,, also can fully guarantee the electric capacity between floating grid and the control grid even when further reducing the size of memory cell.Therefore, according to the present invention, even when reducing the size of memory cell, memory cell also can have required coupling efficiency and good electrical characteristics.
Description of drawings
Figure 1A and 1B are the sketch according to the semiconductor device of first embodiment of the invention, and it shows the structure of this semiconductor device;
Fig. 2 A-2B, 3A-3B, 4A-4B, 5A-5B, 6A-6B, 7A-7B, 8A-8B, 9A-9B, 10A-10B, 11A-11B, 12A-12B, 13A-13B, 14A-14B, 15A-15B, 16A-16B, 17A-17B, 18A-18B, 19A-19B, 20A-20B, 21A-21B, 22A-22B, 23A-23B, 24A-24B, 25A-25B, 26A-26B, 27A-27B, 28A-28B, 29A-29B, 30A-30B, 31A-31B, 32A-32B, 33A-33B, 34A-34B, 35A-35B, 36A-36B, 37A-37B, 38A-38B, 39A-39B, 40A-40B and 41A-41B are the sketch of semiconductor device in its step of manufacturing according to first embodiment of the invention, and it shows this method;
Figure 42 A-42B, 43A-43B, 44A-44B, 45A-45B, 46,47 and 48 are the cutaway view of semiconductor device in its step of manufacturing, and it is illustrated in the inconvenience that causes when not forming step on the surface of silicon;
Figure 49 A-49B, 50A-50B and 51A-51B are the cutaway view of semiconductor device in its step of manufacturing according to the remodeling of first embodiment of the invention, and it illustrates this method;
Figure 52 A and 52B are the sketch according to the semiconductor device of second embodiment of the invention, and it illustrates the structure of this semiconductor device; And
Figure 53 A-53B, 54A-54B, 55A-55B, 56A-56B, 57A-57B, 58A-58B and 59A-59B are the cutaway view of semiconductor device in its step of manufacturing according to second embodiment of the invention, and it illustrates this method.
Embodiment
[first embodiment]
Below with reference to semiconductor device and the manufacture method thereof of Figure 1A to 48 explanation according to first embodiment of the invention.Figure 1A and 1B are the sketch according to the semiconductor device of present embodiment, and it shows the structure of this semiconductor device.Fig. 2 A to 41B is the sketch of semiconductor device in its step of manufacturing according to present embodiment, and it shows this method.Figure 42 A to 48 is the cutaway view of semiconductor device in its step of manufacturing, and it is illustrated in the inconvenience that causes when not forming step in the surface of silicon.
At first, with reference to the structure of Figure 1A and 1B explanation according to the semiconductor device of present embodiment.Figure 1A is the vertical view of semiconductor device, and it shows the structure of this semiconductor device.Figure 1B is the cutaway view along A-A ' line among Figure 1A and B-B ' line.
Semiconductor device according to present embodiment comprises flash cell district 10 that forms flash cell 46 and the peripheral circuit region 12 that forms peripheral circuit.Peripheral circuit region 12 comprises nmos pass transistor district 12n that forms nmos pass transistor 62 and the PMOS transistor area 12p that forms PMOS transistor 66.
In the surface of silicon substrate 14, between flash cell district 10 and peripheral circuit region 12, form a step.That is to say that the surface of the silicon substrate 14 in the flash cell district 10 is lower than the surface of the silicon substrate 14 in the peripheral circuit region 12.The upper level of the silicon substrate 14 in the peripheral circuit region 12 is substantially equal to the upper level of the doped amorphous silicon film 34 that hereinafter will describe.
On step 16 on silicon substrate 14 surfaces of the boundary vicinity between flash cell district 10 and the peripheral circuit 12, as hereinafter describing, residual silicon dioxide film 30 and doped amorphous silicon film 34, it has been used to form the tunnel oxide film (tunnel oxide film) and the floating grid of flash cell 46 respectively.
In the silicon substrate 14 in flash cell district 10, be formed for the groove 18 of device isolation.In the process of patterning doped amorphous silicon film 34, also form grooves 18 by etched silicon substrate 14 with formation floating grid 32.That is to say, when forming floating grid 32, form groove 18 by self-aligned manner at patterning doped amorphous silicon film 34.In groove 18, form the device isolation region 20a that silicon dioxide film constitutes.In the silicon substrate 14 in the flash cell district 10 of the boundary vicinity between flash cell district 10 and peripheral electricity district 12, be formed for the groove 22 of device isolation, it is darker than groove 18.In groove 22, form the device isolation region 20b that constitutes by silicon dioxide film.
Be formed for the groove 24 of device isolation in the silicon substrate 14 in peripheral circuit region 12.The degree of depth of the groove 18 in the depth ratio flash cell district 10 of groove 24 is dark, and is substantially equal to the degree of depth of the groove 22 of the boundary vicinity between flash cell district 10 and peripheral electricity district 12.In groove 24, form the device isolation region 20c that silicon dioxide film constitutes.
In the silicon substrate 14 in flash cell district 10, form n moldeed depth trap 26.In n moldeed depth trap 26, form the p type trap 28 more shallow than n moldeed depth trap 26.
In flash cell district 10, on the silicon substrate 14 in the device region that limits by the device isolation region 20a that is formed in the groove 18, form floating grid 32 and tunnel oxide film 30 and be formed between floating grid 32 and this silicon substrate.Each floating grid 32 comprises main part 34 and sidewall sections 36, this main part 34 is formed by the doped amorphous silicon film that is formed on the tunnel oxide film 30, and this sidewall sections 36 is formed by the doped amorphous silicon film on the sidewall of the main part 34 that is formed on device isolation region 20a side.A plurality of floating grids 32 are arranged on the silicon substrate 14 between the device isolation region 20a that imbeds in the groove 18.
On floating grid 32, form grid (control grid) 40 that polysilicon film constitutes and the ONO film 38 that constitutes by silicon dioxide/silicon nitride/silicon dioxide between grid 40 and floating grid 32.Above the device isolation region 20a in groove 18, control grid 40 is formed the bar shaped of extending on a plurality of floating grids 32.
In the silicon substrate 14 of control grid 40 both sides, form the source/drain regions 42 of LDD structure.
On the sidewall of the sidewall of controlling grid 40 and floating grid 32, form side wall insulating film 44.
Therefore, form the flash cell 46 of laminated gate structure in flash cell district 10, each flash cell 36 comprises floating grid 32, control grid 40 and source/drain regions 42.
In the silicon substrate 14 in the formation regulation nmos transistor region of the nmos pass transistor district of peripheral circuit region 12 12n, form n moldeed depth trap 48.Form comprising in nmos pass transistor district 12n in the silicon substrate 14 in zone of n moldeed depth trap 48, form the p type trap 50 more shallow than n moldeed depth trap 48.
In the silicon substrate 14 in the PMOS of peripheral circuit region 12 transistor area 12p, form the n type trap 54 more shallow than n moldeed depth trap 48.
In nmos pass transistor district 12n, on the silicon substrate 14 in the device region that limits by the device isolation region 20c that is formed in the groove 24, form grid 56 and gate insulating film 54 and be formed between grid 54 and this silicon substrate 14.In the silicon substrate 14 of grid 56 both sides, form the source/drain regions 58 of LDD structure.On the sidewall of grid 56, form side wall insulating film 60.Therefore, in nmos pass transistor district 12n, form the nmos pass transistor 62 that comprises grid 56 and source/drain regions 58.
In PMOS transistor area 12p, on the silicon substrate 14 in the device region that limits by the device isolation region 20c that is formed in the groove 24, form grid 56 and gate insulating film 54 and be formed between grid 56 and this silicon substrate 14.In the silicon substrate 14 of grid 56 both sides, form the source/drain regions 64 of LDD structure.On the sidewall of grid 56, form side wall insulating film 60.Therefore, in PMOS transistor area 12p, form the PMOS transistor 66 that comprises grid 56 and source/drain regions 64.
Form silicide film 68 on control grid 40 in flash cell district 10 and the source/drain regions 42.Form silicide film 68 on grid 56 in peripheral circuit region 12 and the source/drain regions 58,64.
In the zone in the flash cell district 10 of peripheral circuit region 12 sides (in this zone, not forming flash cell 46) and in the zone of the peripheral circuit region 12 of flash cell district 10 sides (in this zone, not forming transistor), on the doped amorphous silicon film 34 at silicon substrate 14, device isolation region 20b and 20c and step 16 places, form ONO film 38.
Interlayer dielectric 70 is formed on the silicon substrate 14, and flash cell 46 is formed in the flash cell district 10, and nmos pass transistor 62 and PMOS transistor 66 are formed in the peripheral circuit region 12.
In flash cell district 10, in interlayer dielectric 70, form the contact hole 74 of the contact hole 72 of the silicide film 68 on the control grid 40 and the silicide film 68 on the source/drain regions 42.The embedding electrode plug 76 that is electrically connected with control grid 40 in contact hole 72.The embedding electrode plug 78 that is electrically connected with source/drain regions 42 in contact hole 74.
In peripheral circuit region 12, in interlayer dielectric 70, form the contact hole 82,84 of the contact hole 80 of the silicide film 68 on the grid 56 and the silicide film 68 on the source/drain regions 58,64.The embedding electrode plug 86 that is electrically connected with grid 56 in contact hole 80.The embedding electrode plug 88,90 that is electrically connected with source/drain regions 58,64 in contact hole 82,84.
Thus, formation is according to the semiconductor device of present embodiment.
A main feature according to the semiconductor device of present embodiment is: form a step in the surface of silicon substrate 14, thereby the surface of the silicon substrate 14 in the flash cell district 10 is lower than the surface of the silicon substrate 14 in the peripheral circuit region 12; And the shallow trench 18 that is formed for device isolation in the silicon substrate in flash cell district 10 14, and form the groove that be used for device isolation 24 darker in the silicon substrate 14 in peripheral circuit region 12 than groove 18.
According to present embodiment, because the step that forms in the surface of silicon substrate 14 makes the surface of the silicon substrate 14 in the flash cell district 10 be lower than the surface of the silicon substrate 14 in the peripheral circuit region 12, the upper level that therefore forms the doped amorphous silicon film 34 of floating grid 32 can be substantially equal to the upper level of the silicon substrate in the peripheral circuit region 12.As hereinafter illustrating, this allows to make photoresist 104 (referring to Figure 13 A and 13B) exposure with very high accuracy, and this photoresist 104 is used for the silicon substrate 14 of patterning peripheral circuit region 12 and the doped amorphous silicon film 34 in the flash cell district 10.Therefore, according to present embodiment, can and form the doped amorphous silicon film 34 of floating grid 32 with the silicon substrate in the pinpoint accuracy patterning peripheral circuit region 12 14, thereby the semiconductor device that comprises small memory cell can be provided.
In addition,, be formed on below the doped amorphous silicon film 34 because have the tunnel oxide film 30 of low etch-rate according to present embodiment, as will be described below, so the etch-rate in the flash cell district 10 is lower.Therefore, the groove 24 in the peripheral circuit region 12 can form deeplyer relatively, and the groove 18 in the flash cell district 10 can form more shallowly relatively.
As will be described below, a main feature according to the semiconductor device of present embodiment is also to form groove 18 when the doped amorphous silicon film 34 that forms floating grid 32 is patterned, that is to say, when the doped amorphous silicon film 34 that forms floating grid 32 is patterned, be formed self-aligned groove 18.
According to present embodiment, when being patterned, the doped amorphous silicon film 34 that forms floating grid 32 also forms groove 18, and can not aim at thus and form groove 18 by pinpoint accuracy.Therefore present embodiment can easily satisfy the needs of the size that reduces memory cell.
In addition, be that according to a main feature of the semiconductor device of present embodiment floating grid 32 includes: main part 34, by forming groove 18 with its autoregistration; And sidewall sections 36, it is formed on the sidewall of main part 34.
Because the sidewall sections 36 of floating grid 32, therefore can make electric capacity between floating grid 32 and the control grid 40 greater than the floating grid 32 that only forms by main part 34 and control electric capacity between the grid 40.Therefore, according to present embodiment,, also can guarantee the electric capacity between floating grid 32 and the control grid 40 fully even when further reducing the size of memory cell.Therefore, even when reducing the size of memory cell, present embodiment also can provide the memory cell with required coupling efficiency and good electrical characteristics.
Next, with reference to the manufacture method of Fig. 2 A to 41B explanation according to the semiconductor device of present embodiment.The figure A of Fig. 2 to 41 is a vertical view.The figure B of Fig. 2 to 37 is respectively along the cutaway view of the A-A ' line among the figure A of Fig. 2 to 37.The figure B of Figure 38 to 41 is respectively the A-A ' line among the figure A of Figure 38 to 41 and the cutaway view of B-B ' line.
At first, on silicon substrate 14, grow silicon dioxide film 92 that for example 10nm is thick as sacrificial oxidation film (referring to Fig. 2 A and 2B) by for example thermal oxidation.
Then, on silicon dioxide film 92, form the photoresist 84 (referring to Fig. 3 A and 3B) that covers peripheral circuit region 12 and expose flash cell district 10 by photoetching.
Then, use photoresist 94 to carry out ion and inject, to form n moldeed depth trap 26 (referring to Fig. 4 A and 4B) in the silicon substrate in flash cell district 10 14 as mask.
Then, use photoresist 94 to carry out ion and inject, in n moldeed depth trap 26, to form p type trap 28 (referring to Fig. 5 A and 5B) as mask.
Next, use photoresist 94 as mask, by for example wet etching, etch silicon dioxide film 92 is to remove the silicon dioxide film 92 (referring to Fig. 6 A and 6B) in the flash cell district 10.
Next, remove photoresist 94 by for example ashing treatment.
Then, use silicon dioxide film 92 as mask, by for example chemical dry ecthing, the surface of etched silicon substrate 14 is so that the surface of the silicon substrate 14 in the flash cell district 10 is lower than the surface (referring to Fig. 7 A and 7B) of the silicon substrate 14 in the peripheral circuit region 12.At this moment, in the surface of silicon substrate 14, form step, thereby make the upper level of the silicon substrate 14 in the peripheral circuit region 12 be substantially equal to hereinafter the upper level of the doped amorphous silicon film 34 that will describe.Particularly, the surface of the silicon substrate 14 in the flash cell district 10 and the step between the surface in the silicon substrate 14 in the peripheral circuit region 12 for example are 70nm.
After removing photoresist 94, only use silicon dioxide film 92 as mask, thereby the organic substance that contains in the photoresist 94 can not pollute the surface of silicon substrate 14.
After having formed step thus between the surface of the silicon substrate 14 in flash cell district 10 and the surface of the silicon substrate 14 in the peripheral circuit region 12, remove silicon dioxide film 92 (referring to Fig. 8 A and 8B) by for example wet etching.
Then, on silicon substrate 14, grow silicon dioxide film that for example 5-200nm is thick as sacrificial oxidation film by for example thermal oxidation.Thereby the damage that the surface of repairing silicon substrate 14 is subjected to.Subsequently, remove silicon dioxide film by for example wet etching.
Next, by for example thermal oxidation, the silicon dioxide film 30 that for example 10nm is thick of on silicon substrate 14, growing.Silicon dioxide film 30 will be as hereinafter with the tunnel oxide film of the flash cell 46 described.
Then, by CVD (chemical vapour deposition (CVD)), on silicon dioxide film 30, form the doped amorphous silicon film 34 that for example 70nm is thick (referring to Fig. 9 A and 9B).Doped amorphous silicon film 34 will be as the main part of the floating grid 32 of flash cell 46.
Preferably the thickness with doped amorphous silicon film 34 is arranged so that the upper level of the doped amorphous silicon film 34 in the flash cell district 10 is substantially equal to the upper level of the silicon substrate 14 in the peripheral circuit region 12.This is because if the upper level of the upper level of the silicon substrate 14 in the peripheral circuit region 12 and the doped amorphous silicon film 34 in the flash cell district 10 equates basically, the photoresist 104 of the doped amorphous silicon film 34 in silicon substrate 14 that is used for patterning peripheral circuit region 12 and flash cell district 10 (referring to Figure 13 A and 13B) is when being exposed thus, and the accuracy of exposure can be very high.Therefore, can and form the doped amorphous silicon film 34 of floating grid 32 with the silicon substrate in the pinpoint accuracy patterning peripheral circuit region 12 14, thereby the semiconductor device that comprises small memory cell can be provided.
Then, in flash cell district 10, form photoresist 96 by photoetching on doped amorphous silicon film 34, this photoresist 96 covers the zone that is used to form flash cell 46 and exposes remaining zone (referring to Figure 10 A and 10B).
Next, use photoresist 96 as mask, by for example dry ecthing, etching doped amorphous silicon film 34 will be removing (referring to Figure 11 A and 11B) except the doped amorphous silicon film in the zone the zone that will form flash cell 48 34.On the step 16 in silicon substrate 14 surfaces, keep doped amorphous silicon film 34.
Then, use photoresist 96 as mask, etch silicon dioxide film 30.
Next, remove photoresist 96 by for example ashing treatment.
Then, carry out and the corresponding thermal oxidation of for example 10nm, on silicon substrate 14 and doped amorphous silicon film 34, to grow as the silicon dioxide film 98 of sacrificial oxidation film.
Then, by for example CVD, on silicon dioxide film 98, form the silicon nitride film 100 that for example 100nm is thick (referring to Figure 12 A and 12B).
Then, form photoresist 104 on silicon nitride film 100, it has opening 102a, 102b, 102c, and these openings expose the zone (referring to Figure 13 A and 13B) of the groove 18,22,24 that will be formed for device isolation.As mentioned above, the upper level of the doped amorphous silicon film 34 in the upper level of the silicon substrate 14 in the peripheral circuit region 12 and the flash cell district 10 is set to equate basically, when making photoresist 104 exposures by photoetching, can expose thus with very high accuracy.Therefore, can and form the doped amorphous silicon film 34 of floating grid 32 with the silicon substrate in the pinpoint accuracy patterning peripheral circuit region 12 14, thereby the semiconductor device that comprises small memory cell can be provided.
Then, use photoresist 104 as mask, by for example dry ecthing, silicon nitride film 100, to form opening 106a, 106b, 106c, these openings expose the zone (referring to Figure 14 A and 14B) of the groove 18,22,24 that will be formed for device isolation.
Then, remove photoresist 104 (referring to Figure 14 A and 14B) by for example ashing treatment.
Then, use silicon nitride film 100 as mask, by for example dry ecthing, the silicon dioxide film 98 that exposes among the etching openings 106a, doped amorphous silicon film 34, silicon dioxide film 30 and silicon substrate 14, silicon dioxide film 98 and the silicon substrate 14 (referring to Figure 15 A-15B, 16A-16B and 17A-17B) that exposes among etching openings 106b, the 106c simultaneously.Thus, in flash cell district 10, be formed for the groove 18,22 of device isolation, in peripheral circuit region 12, be formed for the groove 24 (referring to Figure 17 A and 17B) of device isolation simultaneously.At this moment, the selection percentage that etching condition is arranged so that silicon layer (doped amorphous silicon film 34 and silicon substrate 14) and silicon dioxide film is as being 10.The selection ratio of silicon layer and silicon dioxide film differs and is decided to be 10, and can do suitable change corresponding to the degree of depth of the groove 18,22,24 that will form.
Here, after etching away silicon dioxide film 98, etch silicon layer (silicon substrate 14) only in the opening 106b, the 106c that expose the zone will form groove 22,24.Yet, in the opening 106a that exposes the zone that will form groove 18, below doped amorphous silicon film 34, have silicon dioxide film 30.Because the etching characteristic of silicon dioxide film 30 is different with silicon layer, thus the etching among the opening 106a carry out slow among ratio open 106b, the 106c.Therefore groove 18 forms more shallowly than groove 22,24.
Specifically, at first, 34 etched whiles of doped amorphous silicon film silicon substrate 14 etched degree of depth that equate with doped amorphous silicon film 34 etched thickness in opening 106b, 106c in opening 106a, and in silicon substrate 14, form groove 22,24 (referring to Figure 15 A and 15B).For example, doped amorphous silicon film 34 etched 60nm are thick in opening 106a, and silicon substrate 14 etched 60nm are thick in opening 106b, 106c simultaneously, and form the dark groove 22,24 of 60nm in silicon substrate 14.
Figure 15 A and 15B illustrate the state that exposes silicon dioxide film 30 among the opening 106a by being etched in.
Then, further carry out etching, in opening 106a with relatively low speed etch silicon dioxide film 30, simultaneously in opening 106b, 106c with higher relatively speed etched silicon substrate 14 (referring to Figure 16 A and 16B).For example, the selection that makes silicon layer and silicon dioxide film when use is during than the etching condition that is 10, in opening 106a, etch away the thick silicon dioxide film of 10nm 30, in opening 106b, 106c, etch away the dark silicon substrate of 100nm 14 simultaneously, and the degree of depth of groove 22,24 is total up to 160nm.
Figure 16 A and 16B illustrate the state that exposes silicon substrate 14 among the opening 106a by being etched in.
Then, further carry out etching, particularly, in opening 106a and opening 106b, 106c, further carry out etching (referring to Figure 17 A and 17B) with substantially the same speed.For example, when in opening 106a, etching away the dark silicon substrate 14 of 140nm, in opening 106b, 106c, also further etch away the dark silicon substrate of 140nm 14, and the degree of depth of groove 22,24 is total up to 300nm.Therefore, form the dark groove 18 of 140nm in the silicon substrate 14 in opening 106a, form the dark groove 22,24 of 300nm darker simultaneously in the silicon substrate 14 in opening 106b, 106c than groove 18.
In the groove 18,22,24 that is formed for device isolation, the doped amorphous silicon film 34 and the silicon dioxide film 30 that are used to form floating grid 32 in flash cell district 10 are patterned as mentioned above.That is to say, in manufacture method, when the doped amorphous silicon film 34 that is used to form floating grid 32 is patterned, form groove 18 by autoregistration according to the semiconductor device of present embodiment.When the doped amorphous silicon film 34 that is used to form floating grid 32 is patterned, form groove 18, can not aim at thus and form groove 18 by the pattern of pinpoint accuracy.Therefore, present embodiment can easily reduce the size of memory cell.
Next, carry out thermal oxidation etc. on the inner surface of groove 18,22,24, to form silicon dioxide film (not shown), on whole surface, deposit the silicon dioxide film 20 that for example 500-900nm is thick (referring to Figure 18 A and 18B) by for example high-density plasma CVD then as liner (liner).
Then, by for example CMP (chemico-mechanical polishing) polishing silicon dioxide film 20, up to the surface that exposes silicon nitride film 100, to remove the silicon dioxide film 20 on the silicon nitride film 100.Therefore, imbed silicon dioxide film 20 in the groove in being formed at silicon substrate 14 18,22,24.
Thus, form device isolation region 20a, 20b, 20c by STI, it constitutes (referring to Figure 19 A and 19B) by the silicon dioxide film in the groove 18,22,24 of imbedding different depth.
In the surface of silicon substrate 14, do not form under the situation of step, promptly different with present embodiment, then inconvenience below regular meeting takes place.Situation with reference to Figure 42 A to 48 explanation in the surface of silicon substrate 14, formation step.
At first, to be formed with on the silicon substrate 14 of n moldeed depth trap 26 and D type trap 28,, and in the surface of silicon substrate 14, do not form step by for example thermal oxide growth silicon dioxide film 30 that for example 9.5nm is thick with identical as mentioned above mode.
Next, on silicon dioxide film 30, deposit the doped amorphous silicon film 34 that for example 70nm is thick (referring to Figure 42 A) by for example CVD.
Then, in flash cell district 10, form photoresist 96 by photoetching on doped amorphous silicon film 34, this photoresist 96 covers zone that is used to form flash cell 46 and the zone (referring to Figure 42 B) that exposes other.
Next, use photoresist 96 as mask, by for example dry ecthing, etching doped amorphous silicon film 34 will be removing (referring to Figure 43 A) except the doped amorphous silicon film in the zone the zone that is used to form flash cell 46 34.
Next, use photoresist 96 as mask, etch silicon dioxide film 30.
Next, remove photoresist 96 by for example ashing treatment.
Then, carry out and the corresponding thermal oxidation of for example 10nm, on silicon substrate 14 and doped amorphous silicon film 34, to grow as the silicon dioxide film 98 of sacrificial oxidation film.
Next, on silicon dioxide film 98, deposit the silicon nitride film 100 that for example 100nm is thick (referring to Figure 43 B) by for example CVD.
Next, form the photoresist 104 with opening 102a, 102c by photoetching on silicon nitride film 100, these openings expose the zone (referring to Figure 44 A) of the groove 18,24 that will be formed for device isolation.
Then, use photoresist 104 as mask, by for example dry ecthing, silicon nitride film 100 is to form opening 106a, 106c, and these openings expose the zone (referring to Figure 44 B) of the groove 18,24 that will be formed for device isolation,
Next, remove photoresist 104 (referring to Figure 44 B) by for example ashing treatment.
Then, use silicon nitride film 100 as mask, by for example dry ecthing, be etched in the silicon dioxide film 98, doped amorphous silicon film 34, silicon dioxide film 30 and the silicon substrate 14 that expose among the opening 106a, be etched in the silicon dioxide film 98 and the silicon substrate 14 (referring to Figure 45 A, 45B and 46) that expose among the opening 106c simultaneously.Therefore, in flash cell district 10, be formed for the groove 18 of device isolation, in peripheral circuit region 12, be formed for the groove 24 (referring to Figure 46) of device isolation simultaneously.
After etching away silicon dioxide film 98, etch silicon layer (silicon substrate 14) only in the opening 106c that exposes the zone will form groove 24; Simultaneously, in the opening 106a that exposes the zone that will form groove 18, below doped amorphous silicon film 34, there is silicon dioxide film 30.Because the etching characteristic of silicon dioxide film 30 is different with silicon layer, thus the etching among the opening 106a carry out slow among the ratio open 106c.Therefore groove 18 forms more shallowly than groove 24.
Specifically, at first, 34 etched whiles of doped amorphous silicon film silicon substrate 14 etched degree of depth that equate with doped amorphous silicon film 34 etched thickness in opening 106c in opening 106a, and in silicon substrate 14, form groove 24 (referring to Figure 45 A).For example, doped amorphous silicon film 34 etched 60nm are thick in opening 106a, and silicon substrate 14 etched 60nm are thick in opening 106c simultaneously, and form the dark groove 24 of 60nm in silicon substrate 14.
Figure 45 A illustrates the state that exposes silicon dioxide film 30 among the opening 106a by being etched in.
Then, further carry out etching, particularly, in opening 106a with relatively low speed etch silicon dioxide film 30, simultaneously in opening 106c with higher relatively speed etched silicon substrate 14 (referring to Figure 45 B).For example, the selection that makes silicon layer and silicon dioxide film when use is during than the etching condition that is 10, in opening 106a, etch away the thick silicon dioxide film of 9.5nm 30, in opening 106c, further etch away the thick silicon substrate of 95nm 14 simultaneously, and the degree of depth of groove 24 is total up to 155nm.
Figure 45 B illustrates the state that exposes silicon substrate 14 among the opening 106a by being etched in.
Then, further carry out etching, particularly, in opening 106a and opening 106c, further carry out etching (referring to Figure 46) with substantially the same speed.For example, when in opening 106a, etching away the dark silicon substrate 14 of 125nm, in opening 106c, also further etch away the dark silicon substrate of 125nm 14, and the degree of depth of groove 24 is total up to 280nm.Therefore, form the dark groove 18 of 125nm in the silicon substrate 14 in opening 106a, and form the dark groove 24 of 280nm in the silicon substrate 14 in opening 106c.
In the groove 18,24 that is formed for device isolation, in flash cell district 10, will be used to form the doped amorphous silicon film 34 and silicon dioxide film 30 patternings of floating grid 32 as mentioned above.That is to say, when the doped amorphous silicon film 34 that is used to form floating grid 32 is patterned, form groove 18 by autoregistration.
Next, carry out thermal oxidation etc. on the inner surface of groove 18,24, to form silicon dioxide film (not shown), on whole surface, deposit the silicon dioxide film 20 (referring to Figure 47) that for example 500-900nm is thick by for example high-density plasma CVD then as liner.
Next, by for example CMP polishing silicon dioxide film 20, up to the surface that exposes silicon nitride film 100, thus the silicon dioxide film 20 on the removal silicon nitride film 100.Therefore, imbed silicon dioxide film 20 in the groove in being formed at silicon substrate 14 18,24.
Therefore, form device isolation region 20a, 20c by STI, it constitutes (referring to Figure 48) by the silicon dioxide film in the groove 18,24 of imbedding different depth.
Yet, in the surface of silicon substrate 14, do not form under the situation of step, when the silicon nitride film 100 of polishing silicon dioxide film 20 in exposing peripheral circuit region 12, in flash cell district 100, usually get rid of all silicon nitride films 100.In this case, the silicon dioxide film 98 on the floating grid (doped amorphous silicon film 34), or even doped amorphous silicon film 34 is all owing to the polishing of being undertaken by CMP damages.In flash cell district 10, when removing silicon nitride film 100, can expose silicon dioxide film 98 or even doped amorphous silicon film 34, thereby can not carry out step subsequently.
Compare with the situation that in the surface of silicon substrate 14, does not form step and this inconvenience appearance, in the surface of silicon substrate 14, form step in the present embodiment, thereby the silicon substrate 14 in the surface ratio peripheral circuit region 12 of the silicon substrate 14 in the flash cell district 10 is surperficial low.This can prevent the polishing removal that the silicon nitride film 100 on the doped amorphous silicon film is undertaken by CMP, to form device isolation region 20a, 20b, 20c.In order to ensure preventing that the silicon nitride film 100 on the doped amorphous silicon film 34 is removed, in the surface of silicon substrate 14, form step, thereby the upper level of the silicon substrate 14 in the peripheral circuit region 12 is substantially equal to or greater than the upper level of the doped amorphous silicon film 34 that forms in flash cell district 10.
Therefore, manufacture method according to the semiconductor device of present embodiment can not produce following inconvenience, promptly, silicon dioxide film 98 on the doped amorphous silicon film 34 and doped amorphous silicon film 34 are damaged by the polishing of being undertaken by CMP, and can not carry out the step after device isolation region 20a, 20b, the 20c formation.
After under the situation of avoiding above-mentioned inconvenience by formation step in the surface of silicon substrate 14, forming device isolation region 20a, 20b, 20c, form photoresist 108 by photoetching, this photoresist 108 covers peripheral circuit regions 12 and in the frontier district in the flash cell district 10 of peripheral circuit region 12 sides, and exposes the zone that will form flash cell 46.
Then, use photoresist 108,, the top that is used to form the device isolation region 20a in the zone of flash cell is etched away for example 140nm thick (referring to Figure 20 A and 20B) by for example dry ecthing as mask.At this moment, it is slightly higher than tunnel oxide film 30 that the top of device isolation region 20a is etched into the upper surface that makes device isolation region 20a, perhaps is in substantially the same height with it.
Next, by for example amorphous silicon film 36 of CVD dopant deposition on whole surface (referring to Figure 21 A and 21B).Therefore, doped amorphous silicon film 36 be embedded between the main part 34 of adjacent floating grid 32, be arranged in the opening on the device isolation region 20a.
Next, etch-back doped amorphous silicon film 36 is gone up and is removed from other zones so that it only stays device isolation region 20a.At this moment, doped amorphous silicon film 36 is etched back and carves to making the upper surface of the doped amorphous silicon film 36 on the device isolation region 20a be in the identical height of upper surface of the silicon dioxide film 98 on the main part 34 with floating grid 32.
Then, by for example thermal oxidation silicon dioxide film 110 that for example 10nm is thick (referring to Figure 22 A and 22B) of on doped amorphous silicon film 36, growing.
Next, on whole surface, deposit the silicon nitride film 112 that for example 5nm is thick, as barrier film (referring to Figure 23 A and 23B) by for example CVD.
Then, etch-back silicon nitride film 112 so that it only stays on the sidewall of the silicon nitride film 100 on the main part 34 of floating grid 32, and is removed from other zones.
Next, use silicon nitride film 112 as mask, by for example dry ecthing, etching doped amorphous silicon film 36 makes on the sidewall of its main part of staying floating grid 32 34 (referring to Figure 24 A and 24B).
Therefore, on the sidewall of the main part 34 of floating grid 32, form the sidewall sections 36 of the floating grid 32 of doped amorphous silicon film by self-aligned manner.The floating grid 32 that does not have sidewall sections 36 with only being formed by main part 34 is compared, and the floating grid 32 that is formed by main part 34 and sidewall sections 36 is because sidewall sections 36 and have less clearance (gap) with adjacent floating grid.This can increase the electric capacity between floating grid 32 and the control grid 40.Therefore, even the size of memory cell further reduces, present embodiment also can be guaranteed the enough electric capacity between floating grid 32 and the control grid 40.When even the size of memory cell further reduces, present embodiment also can provide the memory cell with required coupling efficiency and good electrical characteristics.
Then, by for example using the CVD of TEOS, on whole surface, deposit the silicon oxide film 114 that for example 100nm is thick (referring to Figure 25 A and 25B) as raw gas.
Next, by for example wet etching, etch-back silicon dioxide film 114.Therefore, silicon dioxide film 114 is embedded between the floating grid 32, and removes from other zones.At this moment, or even silicon dioxide film the device isolation region 20b, the 20c that constitute also be etched back quarter (referring to Figure 26 A and 26B).Device isolation region 20c is etched back quarter, and the step between the upper surface of the upper surface of device isolation region 20c and the device region that limited by device isolation region 20c becomes enough little of form device in peripheral circuit region 12 till.Specifically, silicon dioxide film 114 is etched back quarter, till the upper surface low for example 70nm of the upper surface that is embedded in the silicon dioxide film 114 between the floating grid 32 than silicon nitride film 100.At this moment, device isolation region 20b, 20c also are etched back quarter, and the upper surface of device isolation region 20b, 20c is than the low for example 70nm of upper surface of silicon nitride film 100.
Then, carry out wet etching, remove silicon nitride film 100,112 (referring to Figure 27 A and 27B) by for example using phosphoric acid.At this moment, the doped amorphous silicon film 34,36 that forms floating grid 32 is surrounded by silicon dioxide film 98,110,114, avoids etching to protect it.Remove the doped amorphous silicon membrane portions that is not used as floating grid 32 by this wet etching process.
Then, form the photoresist 116 that covers peripheral circuit region 12 and expose flash cell district 10 by photoetching.
Then, use photoresist 116 as mask, by for example wet etching, the silicon dioxide film 98,100 (referring to Figure 28 A and 28B) on silicon dioxide film 114 on the removal devices isolated area 20a and the floating grid 32 (doped amorphous silicon film 34,36).At this moment, the top of the device isolation region 20b in the frontier district in the flash cell district 10 of peripheral circuit region 12 sides is also etched.Thus, the upper surface of device isolation region 20b is reduced to the position of the upper surface of device isolation region 20a.
Next, remove photoresist 116 by for example ashing treatment.
Then, deposit silicon dioxide film and the thick silicon nitride film of for example 10nm that for example 6nm is thick by for example CVD on whole surface, the surface of this silicon nitride film of thermal oxidation then is with the thick silicon dioxide film of about 5nm of growing.Therefore, on whole surface, form ONO film 38 (referring to Figure 29 A and 29B) with silicon dioxide/silicon nitride/silicon dioxide structure.
Next, form photoresist 118, will form the nmos pass transistor district 12n of the nmos pass transistor 62 of regulation among a plurality of nmos pass transistors district 12n in its exposure peripheral circuit region 12, and cover other zone by photoetching.
Then, use photoresist 118 to carry out ion and inject, to form n moldeed depth trap 48 in the silicon substrate 14 among the nmos pass transistor district 12n that will form the nmos pass transistor of stipulating 62 among a plurality of nmos pass transistors district 12n in peripheral circuit region 12 as mask.(referring to Figure 30 A and 30B).
Then, remove photoresist 118 by for example ashing treatment.
Then, form photoresist 120 by photoetching, it exposes nmos pass transistor district 12n that forms n moldeed depth trap 48 and the nmos pass transistor district 12n that does not form n moldeed depth trap 48, and covers other zones.
Then, use photoresist 120 to carry out ion and inject, in the silicon substrate 14 of the nmos pass transistor district of peripheral circuit region 12 12n, to form p type trap 50 (referring to Figure 31 A and 31B) as mask.
Next, remove photoresist 120 by for example ashing treatment.
Then, form exposure PMOS transistor area 12p and cover other regional photoresists 122 by photoetching.
Next, use photoresist 122 to carry out ion and inject, in the silicon substrate 14 of the PMOS of peripheral circuit region 12 transistor area 12p, to form n type trap 52 (referring to Figure 32 A and 32B) as mask.
Then, remove photoresist 122 by for example ashing treatment.
Then, form nmos pass transistor district 12n and the PMOS transistor area 12p in the exposure peripheral circuit region 12 and cover other regional photoresists 124 by photoetching.
Next, use photoresist 124 as mask, by for example dry ecthing, etching ONO film 38 is with nmos pass transistor district 12n in the removal peripheral circuit region 12 and the ONO film 38 (referring to Figure 33 A and 33B) among the PMOS transistor area 12p.
Next, remove photoresist 124 by for example ashing treatment.
Then, by for example thermal oxidation, form the gate insulating film 54 of the silicon dioxide film formation that for example 1-2nm is thick on the silicon substrate 14 among nmos pass transistor district 12n in peripheral circuit region 12 and the PMOS transistor area 12p.
Next, on whole surface, deposit the polysilicon film 126 that for example 120nm is thick (referring to Figure 34 A and 34B) by for example CVD.
Then, by photoetching and dry ecthing, the polysilicon film 126 in patterning flash cell district 10 and the peripheral circuit region 12.Thus, in flash cell district 10, form the grid (control grid) 40 that constitutes by polysilicon film 126, and in peripheral circuit region 12, form the grid 56 that constitutes by polysilicon film 126.In addition, in flash cell district 10, come patterning ONO film 38 and floating grid 32 (referring to Figure 35 A and 35B) by photoetching and dry ecthing.
The step that forms in the surface of silicon substrate 14 has slowed down because the step that tunnel oxide film 30 and floating grid 32 produce at substrate surface, and has guaranteed the substrate surface planarization with polysilicon film 126 to be formed on it.Therefore, can form smooth polysilicon film 126.Thereby can carry out and to be used for the exposure-processed of the photoresist (not shown) exposure of patterned polysilicon film 126 with very high accuracy.Therefore, can form small control grid 40 and small grid 56 with pinpoint accuracy.
Then, form exposure flash cell district 10 and cover other regional photoresist (not shown) by photoetching.Next, use this photoresist to carry out ion and inject, with the LDD district 42a of the source/drain regions that forms flash cell 46 as mask.After forming LDD district 42a, remove the photoresist that is used as mask by for example ashing treatment.
Next, form exposure nmos pass transistor district 12n and cover other regional photoresist (not shown) by photoetching.Next, use photoresist to carry out ion and inject, with the LDD district 58a of the source/drain regions 58 that forms nmos pass transistor 62 as mask.After forming LDD district 58a, remove the photoresist that is used as mask by for example ashing treatment.
Next, form exposure PMOS transistor area 12p and cover other regional photoresist (not shown) by photoetching.Next, use photoresist to carry out ion and inject, with the LDD district 64a of the source/drain regions 64 that forms PMOS transistor 66 as mask.After forming LDD district 64a, remove the photoresist that is used as mask by for example ashing treatment.
Therefore, the LDD district 64a (referring to Figure 36 A and 36B) of the source/drain regions 64 of the LDD district 58a of the source/drain regions 58 of the LDD district 42a of the source/drain regions 42 of formation flash cell 46, nmos pass transistor 62 and PMOS transistor 66.
Next, on whole surface, form silicon dioxide film or the silicon nitride film that for example 1-100nm is thick by for example CVD.Then, this silicon dioxide film of etch-back or silicon nitride film, with the side wall insulating film 44 of formation silicon dioxide film or silicon nitride film formation on the sidewall of grid (control grid) 40 and floating grid 32, and the side wall insulating film 60 (referring to Figure 37 A and 37B) that on the sidewall of grid 56, forms silicon dioxide film or silicon nitride film formation.
Then, form exposure flash cell district 10 and cover other regional photoresist (not shown) by photoetching.Next, use photoresist to carry out ion and inject, to form the source/drain regions 42 of flash cell 46 as mask.After forming source/drain regions 42, remove the photoresist that is used as mask by for example ashing treatment.
Then, form exposure nmos pass transistor district 12n and cover other regional photoresist (not shown) by photoetching.Next, use photoresist to carry out ion and inject, to form the source/drain regions 58 in nmos pass transistor district 62 as mask.After forming source/drain regions 58, remove the photoresist that is used as mask by for example ashing treatment.
Next, form exposure PMOS transistor area 12p and cover other regional photoresist (not shown) by photoetching.Next, use photoresist to carry out ion and inject, to form the source/drain regions 64 of PMOS transistor area 66 as mask.After forming source/drain regions 64, remove the photoresist that is used as mask by for example ashing treatment.
Therefore, form source/drain regions 42, the source/drain regions 58 of nmos pass transistor 62 and the source/drain regions 64 (referring to Figure 38 A and 38B) of PMOS transistor 66 of flash cell 46.
Then, by the top of known silicification technics selective silicon chemical control system grid 40, grid 56 and source/ drain regions 42,58,64, on control grid 40, grid 56 and source/ drain regions 42,58,64, to form silicide film 68 (referring to Figure 39 A and 39B).
Therefore, on silicon substrate 14, form flash cell 46, nmos pass transistor 62 and PMOS transistor 66.
Next, be formed with in the above on the silicon substrate 14 of flash cell 46 grades, form silicon dioxide film by CVD for example, and by CMP for example with the flattening surface of this silicon dioxide film.Therefore, form the interlayer dielectric 70 (referring to Figure 40 A and 40B) that constitutes by the thick silicon dioxide film of for example 250-500nm.
Yet, in interlayer dielectric 70, forming contact hole 72,74,80,82,84, and form electrode plug 76,78,86,88,90, it imbeds (referring to Figure 41 A and 41B) in the contact hole 72,74,80,82,84.
Thus, make semiconductor device according to the present embodiment shown in Figure 1A and the 1B.
As mentioned above, according to present embodiment, in the surface of silicon substrate 14, form step, thereby the silicon substrate 14 in the surface ratio peripheral circuit region 12 of the silicon substrate 14 in the flash cell district 10 is surperficial low, can be used in the upper level of the doped amorphous silicon film 34 that forms floating grid 32 and the upper level of the silicon substrate 14 in the peripheral circuit region 12 thus and equate basically.This makes it possible to be used in very high accuracy photoresist 104 exposures of silicon substrate 14 in the patterning peripheral circuit region 12 and the doped amorphous silicon film 34 in the flash cell district 10.Therefore, according to present embodiment, can and form the doped amorphous silicon film 34 of floating grid 32 with the silicon substrate in the pinpoint accuracy patterning peripheral circuit region 12 14, thereby the semiconductor device that comprises small memory cell can be provided.
In addition, according to present embodiment, because there is the low tunnel oxide film of etch-rate 30 below doped amorphous silicon film 34, the etch-rate in the flash cell district 10 is lower.Therefore, darker groove 24 relatively can be in peripheral circuit region 12, formed, more shallow groove 18 relatively can be in flash cell district 10, formed simultaneously.
According to present embodiment, the step that forms in the surface of silicon substrate 14 is guaranteed the flatness on silicon substrate 14 surfaces, forms polysilicon film 126 and control grid 40 and grid 56 to form on this surface of silicon, thereby can form smooth polysilicon film 126.Therefore, can be used in the photoresist exposure of patterned polysilicon film 126 with very high accuracy.Therefore, can form small control grid 40 and small grid 56 with pinpoint accuracy.
According to present embodiment, when the doped amorphous silicon film 34 that forms floating grid 32 is patterned, form groove 18 by autoregistration, this allows not form groove 18 by pinpoint accuracy ground aligned pattern.Therefore, present embodiment helps to reduce the size of memory cell.
In addition, according to present embodiment, floating grid 32 includes: main part 34, by forming groove 18 with its autoregistration; And sidewall sections 36, it is formed on the sidewall of main part 34, and this can make floating grid 32 and the electric capacity of control between the grid 40 greater than the floating grid 32 that is only formed by main part 34 and control electric capacity between the grid 40.Therefore, according to present embodiment,, also can guarantee the electric capacity between floating grid 32 and the control grid 40 fully even when further reducing the size of memory cell.According to present embodiment, even when reducing the size of memory cell, memory cell also can have required coupling efficiency and good electrical characteristics.
(remodeling)
Next, with reference to the manufacture method of Figure 49 A to 51B explanation according to the semiconductor device of the remodeling of present embodiment.Figure 49 A to 51B is the cutaway view of semiconductor device in its step of manufacturing according to this remodeling, and it illustrates this method.
The surface that is the silicon substrate 14 in the flash cell district 10 according to the characteristics of the manufacture method of the semiconductor device of this remodeling by oxidation optionally to form silicon dioxide film, remove this silicon dioxide film then, in the surface of silicon substrate 14, form step thus, thereby the surface of the silicon substrate 14 in the flash cell district 10 is lower than the surface of the silicon substrate 14 in the peripheral circuit region 12.
Until form these steps identical with shown in Fig. 2 A to 5B all of the step of n moldeed depth trap 26 and p type trap 28 in the silicon substrate 14 in flash cell district 10, no longer repeat their explanation here.
Then, by after for example the ashing treatment removal is used to form the photoresist 94 of n moldeed depth trap 26 and p type trap 28, on silicon dioxide film 92, deposit the silicon nitride film 128 that for example 110nm is thick (referring to Figure 49 A) by for example CVD.
Next, form the photoresist 130 that exposes flash cell district 10 and cover peripheral circuit region 12 by photoetching.
Then, use photoresist 130 as mask, by for example wet etching, silicon nitride film 128 is to remove the silicon nitride film 128 (referring to Figure 49 B) in the flash cell district 10.
Next, remove photoresist 130 by for example ashing treatment.
Then, by for example thermal oxidation and use silicon nitride film 128, make the surface oxidation of silicon substrate 14, the silicon dioxide film 132 that for example 160nm is thick (referring to Figure 50 A) of growing on the surface with the silicon substrate in flash cell district 10 14 as mask.
Next, by for example wet etching, silicon nitride film 128 is to remove the silicon nitride film 128 (referring to Figure 50 B) in the peripheral circuit region 12.
Then, by for example wet etching, etch silicon dioxide film 92 and silicon dioxide film 132 are to remove silicon dioxide film 92 and the silicon dioxide film 132 in the flash cell district 10 (referring to Figure 51 A) in the peripheral circuit region 12.Silicon dioxide film 132 in the flash cell district 10 is removed, and forms step thus in the surface of silicon substrate 14, thereby the surface of the silicon substrate 14 in the flash cell district 10 is lower than the surface of the silicon substrate 14 in the peripheral circuit region 12.
Then, on whole surface, form the silicon dioxide film 30 that for example 10nm is thick by for example thermal oxidation.Silicon dioxide film 30 will be used as the tunnel oxide film of flash cell 46.
Next, on silicon dioxide film 30, deposit the doped amorphous silicon film 34 that for example 70nm is thick (referring to Figure 51 B) by for example CVD.Doped amorphous silicon film 34 will be used as the main part of the floating grid 32 of flash cell 46.
Form doped amorphous silicon film 34 step afterwards with described identical, no longer repeat their explanation here above with reference to Figure 10 A to 41B.
Described in this remodeling, the surface of the silicon substrate 14 in the flash cell district 10 is by optionally oxidation, to form silicon dioxide film 132, remove this silicon dioxide film 132 then, in the surface of silicon substrate 14, form step thus, thereby the surface of the silicon substrate 14 in the flash cell district 10 is lower than the surface of the silicon substrate 14 in the peripheral circuit region 12.
[second embodiment]
With reference to semiconductor device and the manufacture method thereof of Figure 52 A to 59B explanation according to second embodiment of the invention.Figure 52 A and 52B are the sketch according to the semiconductor device of present embodiment, and it illustrates the structure of this semiconductor device.Figure 53 A-59B is the cutaway view of semiconductor device in its step of manufacturing according to present embodiment, and it illustrates this method.Represent by identical Reference numeral in the present embodiment with according to the identical parts of the semiconductor device of first embodiment and those parts in the manufacture method thereof, and no longer repeat or simplify its explanation.
At first, with reference to the structure of Figure 52 A and 52B explanation according to the semiconductor device of present embodiment.Figure 52 A is the vertical view according to the semiconductor device of present embodiment, and it shows the structure of this semiconductor device.Figure 52 B is the cutaway view along A-A ' line among Figure 52 A and B-B ' line.
According to the basic structure of the semiconductor device of present embodiment with substantially the same according to the semiconductor device of first embodiment.Mainly be epitaxial growth silicon layer 134 on the surface of the silicon substrate 14 in peripheral circuit region 12 according to the characteristics of the semiconductor device of present embodiment, and the low thickness corresponding to silicon layer 134 in the surface of the silicon layer 134 in the surface ratio peripheral circuit region 12 of the silicon substrate in the flash cell district 10 14.In other words, the low thickness in the surface of the silicon substrate 14 in the surface ratio peripheral circuit region 12 of the silicon substrate 14 in the flash cell district 10 corresponding to silicon layer 134.
Shown in Figure 52 B, form epitaxially grown silicon layer 134 on the surface of silicon substrate in peripheral circuit region 12.Form a step in the surface of the silicon substrate 14 of silicon layer 134 between flash cell district 10 and peripheral circuit region 12.That is to say the low thickness in the surface of the silicon substrate 134 in the surface ratio peripheral circuit region 12 of the silicon substrate 14 in the flash cell district 10 corresponding to silicon layer 134.In other words, the low thickness in the surface of the silicon substrate 14 in the surface ratio peripheral circuit region 12 of the silicon substrate 14 in the flash cell district 10 corresponding to silicon layer 134.The apparent height of the silicon layer 134 in the peripheral circuit region 12 is substantially equal to the upper level of the doped amorphous silicon film 34 of formation in flash cell district 10.
As in semiconductor device according to first embodiment, in flash cell district 10, on silicon substrate 14, form flash cell 46, this silicon substrate 14 has the device isolation region 20a that is formed in the groove 18.
As in semiconductor device according to first embodiment, in peripheral circuit region 12, on silicon substrate 14, form nmos pass transistor 62 and PMOS transistor 66, on this silicon substrate 14, be formed with silicon layer 134.
Because in semiconductor device according to present embodiment, in the surface of silicon substrate 14, form step by epitaxial growth silicon layer 134 on the surface of the silicon substrate in peripheral circuit region 12 14, thereby the surface of the silicon substrate 14 in the flash cell district 10 is lower than the surface of the silicon substrate 14 in the peripheral circuit region 12.
Next, with reference to the manufacture method of Figure 53 A to 59B explanation according to the semiconductor device of present embodiment.
At first, be formed with therein on the silicon substrate 14 of n moldeed depth trap 26 and p type trap 28 by for example CVD and deposit the silica 1 36 that for example 80nm is thick (referring to Figure 53 A).
Then, form the photoresist 138 (referring to Figure 53 B) that exposes peripheral circuit region 12 and cover flash cell district 10 by photoetching.
Then, by for example wet etching, and use photoresist 138 as mask, etch silicon dioxide film 136 is to remove the silicon dioxide film 136 in the peripheral circuit region 12.
Next, remove photoresist 138 (referring to Figure 54 A) by for example ashing treatment.
Then, in the fixed surface treatment of silicon substrate 14 enterprising professional etiquettes, to clean the surface of silicon substrate 14.
Next,, and use silicon dioxide film 136, the epitaxial growth silicon layer 134 that for example 70nm is thick (referring to Figure 54 B) optionally on the surface of the silicon substrate 14 in peripheral circuit region 12 as mask by for example CVD.
Next, remove silicon dioxide film 136, to remove the silicon dioxide film 136 (referring to Figure 55 A) in the flash cell district 10 by for example wet etching.
Then, by for example thermal oxidation, the silicon dioxide film 30 that for example 10nm is thick of on silicon substrate 14, growing, wherein epitaxial growth has silicon layer 134 (referring to Figure 55 B) on the surface of this silicon substrate 14 in peripheral circuit region 12.Silicon dioxide film 30 will be used as the tunnel oxide film of flash cell 46.
Next, on silicon dioxide film 30, deposit the doped amorphous silicon film 34 that for example 70nm is thick (referring to Figure 56 A) by for example CVD.Doped amorphous silicon film 34 will be used as the main part of the floating grid 32 of flash cell 46.
Next, on doped amorphous silicon film 34, form the photoresist 96 that covers flash cell district 10 and expose peripheral circuit region 12 by photoetching.
Next, use photoresist 96 as mask, by for example dry ecthing, etching doped amorphous silicon film 34 will be removing (referring to Figure 56 B) except the doped amorphous silicon film in the zone the flash cell district 10 34.
Then, use photoresist 96 as mask, etch silicon dioxide film 30.
Next, remove photoresist 96 by for example ashing treatment.
Then, carry out and the corresponding thermal oxidation of for example 10nm, on silicon layer 134 and doped amorphous silicon film 34, to grow as the silicon dioxide film 98 of sacrificial oxidation film.
Next, on silicon dioxide film 98, deposit the silicon nitride film 100 that for example 100nm is thick (referring to Figure 57 A) by for example CVD
Next, form photoresist 104 by photoetching on silicon nitride film 100, it has opening 102a, 102b, 102c, and these openings expose the zone (referring to Figure 57 B) of the groove 18,22,24 that will be formed for device isolation.The upper level that is formed with the doped amorphous silicon film 34 in upper level and the flash cell district 10 of silicon substrate 14 of silicon layer 134 in the peripheral circuit region 12 its is set to equate basically, can expose to photoresist 104 by photoetching with very high accuracy thus.Therefore, can come the silicon substrate 14 in the patterning peripheral circuit region 12 and be used to form the doped amorphous silicon film 34 of floating grid 32 with pinpoint accuracy, thereby the semiconductor device that comprises small memory cell can be provided.
Then, use photoresist 104 as mask, by for example dry ecthing, silicon nitride film 100, to form opening 106a, 106b, 106c in silicon nitride film 100, these openings expose the zone (referring to Figure 58 A) that will form groove 18,22,24.
Next, use photoresist 104 and silicon nitride film 100 as mask, be etched in the silicon dioxide film 98, doped amorphous silicon film 34, silicon dioxide film 30 and the silicon substrate 14 that expose among opening 106a, the 106b, the silicon substrate 14 (referring to Figure 58 B, 59A and 59B) that epitaxial growth has silicon layer 134 is gone up on the silicon dioxide film 98 that exposes among the etching openings 106c and its surface simultaneously.Therefore, in flash cell district 10, be formed for the groove 18,22 of device isolation, in peripheral circuit region 12, be formed for the groove 24 (referring to Figure 59 B) of device isolation simultaneously.At this moment, the etching condition selection percentage that is arranged so that silicon layer (doped amorphous silicon film 34, silicon substrate 14 and silicon layer 134) and silicon dioxide film is as being 10.
Here, after etching away silicon dioxide film 98, etch silicon layer (epitaxial growth has the silicon substrate 14 of silicon layer 134) only in the opening 106c that exposes the zone will form groove 24.Yet, in the opening 106a, the 106b that expose the zone that will form groove 18,22, below doped amorphous silicon film 34, have silicon dioxide film 30.Because the etching characteristic of silicon dioxide film 30 is different with silicon layer, thus the etching among opening 106a, the 106b carry out slow among the ratio open 106c.Therefore groove 18,22 forms more shallowly than groove 24.
Specifically, at first, doped amorphous silicon film 34 is etched in opening 106a, 106b, while silicon substrate 14 lip-deep silicon layer 134 etched degree of depth that equate with doped amorphous silicon film 34 etched thickness in opening 106c, and in silicon layer 134, form groove 24 (referring to Figure 58 B).For example, doped amorphous silicon film 34 etched 60nm are thick in opening 106a, 106b, and silicon layer 134 etched 60nm are dark in opening 106c simultaneously, and form the dark groove 24 of 60nm in silicon layer 134.
Figure 58 B illustrates the state that exposes silicon dioxide film 30 in the opening 106 by being etched in.
Then, further carry out etching, particularly, in opening 106a, 106b,, the silicon substrate 14 (referring to Figure 59 A) of silicon layer 134 is arranged simultaneously with higher relatively speed etch epi-growth in opening 106c with relatively low speed etch silicon dioxide film 30.For example, the selection that makes silicon layer and silicon dioxide film when use is during than the etching condition that is 10, in opening 106a, 106b, etch away the thick silicon dioxide film of 10nm 30, and further etch away the silicon substrate 14 that the dark epitaxial growth of 100nm has silicon layer 134 in opening 106c, and the degree of depth of groove 24 is total up to 160nm.
Figure 59 A illustrates the state that exposes silicon substrate 14 among the opening 106a by being etched in.
Then, further carry out etching, particularly, in opening 106a, 106b and opening 106c, further carry out etching (referring to Figure 59 B) with substantially the same speed.For example, when in opening 106a, 106b, etching away the dark silicon substrate 14 of 140nm, in 106c, also further etch away the silicon substrate 14 that the dark epitaxial growth of 140nm has silicon layer 134, and the degree of depth of groove 24 is total up to 300nm.Therefore, form the dark groove 18 of 140nm in the silicon substrate 14 in opening 106a, 106b, and the epitaxial growth in opening 106c has and forms the dark groove 24 of 300nm darker than groove 18 in the silicon substrate 14 of silicon layer 134.
In the groove 18,22,24 that is formed for device isolation, in flash cell district 10, will be used to form the doped amorphous silicon film 34 and silicon dioxide film 30 patternings of floating grid 32 as mentioned above.That is to say, in manufacture method according to the semiconductor device of present embodiment, when the doped amorphous silicon film 34 that is used to form floating grid 32 is patterned, form groove 18 by autoregistration, as in manufacture method according to the semiconductor device of first embodiment.When the doped amorphous silicon film 34 that is used to form floating grid 32 is patterned, form groove 18, can not aim at thus and form groove 18 by the pattern of pinpoint accuracy.Therefore, present embodiment can easily reduce the size of memory cell.
Next, remove photoresist 104 by for example ashing treatment.
Later step is identical with those steps according in the manufacture method of the semiconductor device of first embodiment shown in Figure 18 A to 41B, no longer repeats their explanation here.
[modification embodiment]
The invention is not restricted to the foregoing description, and can cover other various modifications.
For example, in the above-described embodiments, come etched silicon substrate 14 or the silicon dioxide film 132 of removal, in the surface of silicon substrate 14, form step by silicon substrate 14 surface oxidations are formed by chemical dry ecthing.Yet the surface of removing silicon substrate 14 is not limited to above-mentioned technology with the technology that forms step in the surface.For example, come etched silicon substrate 14 also can in the surface of silicon substrate 14, form step by wet etching.
In the above-described embodiments, in silicon substrate 14, form step, thereby the surface of the silicon substrate 14 in the flash cell district 10 is lower than the surface of the silicon substrate 14 in the peripheral circuit region 12.Yet according to the size of device pattern, process allowance etc. can not form step in the surface of silicon substrate 14.
In the above-described embodiments, floating grid 32 comprises main part 34 and sidewall sections 36.Yet floating grid 32 can only comprise main part 34 and not have sidewall sections 36.

Claims (20)

1. semiconductor device comprises:
Semiconductor substrate, it forms a step in the surface, and this step makes surface ratio second district surperficial low in the district that wins;
First device isolation region, it is formed in first groove that forms in the Semiconductor substrate in this first district;
Second device isolation region, it is formed in second groove that forms in the Semiconductor substrate in this second district, and this second groove is than the first ditch groove depth;
Memory cell, it comprises: floating grid, it is formed on first device region of this first device isolation area definition, and forms first dielectric film between this floating grid and this first device region; And the control grid, it is formed on this floating grid, and forms second dielectric film between this control grid and this floating grid; And
Transistor, it is formed on second device region of this second device isolation area definition.
2. semiconductor device as claimed in claim 1, wherein
The surface of the Semiconductor substrate in this first district is removed.
3. semiconductor device as claimed in claim 1 also comprises:
Semiconductor layer, it is formed on the Semiconductor substrate in this second district, and forms the step in the surface of this Semiconductor substrate.
4. semiconductor device as claimed in claim 1, wherein
The upper level of the Semiconductor substrate in the upper level of this floating grid and this second district equates basically.
5. semiconductor device as claimed in claim 2, wherein
The upper level of the Semiconductor substrate in the upper level of this floating grid and this second district equates basically.
6. semiconductor device as claimed in claim 3, wherein
The upper level of the Semiconductor substrate in the upper level of this floating grid and this second district equates basically.
7. semiconductor device as claimed in claim 1, wherein
This floating grid comprises: main part, and it is formed on this Semiconductor substrate, and this first dielectric film is formed between this main part and this Semiconductor substrate; And sidewall sections, it is formed on the sidewall of this main part.
8. semiconductor device as claimed in claim 2, wherein
This floating grid comprises: main part, and it is formed on this Semiconductor substrate, and this first dielectric film is formed between this main part and this Semiconductor substrate; And sidewall sections, it is formed on the sidewall of this main part.
9. semiconductor device as claimed in claim 3, wherein
This floating grid comprises: main part, and it is formed on this Semiconductor substrate, and this first dielectric film is formed between this main part and this Semiconductor substrate; And sidewall sections, it is formed on the sidewall of this main part.
10. the manufacture method of a semiconductor device comprises the steps:
Form first conducting film that will become floating grid on the Semiconductor substrate in first district, and form first dielectric film between this first conducting film and this Semiconductor substrate, this first dielectric film has the etching characteristic that is different from this Semiconductor substrate;
Form mask on the Semiconductor substrate in this first conducting film and this second district, this mask has first opening that is formed in this first district and second opening that is formed in second district;
Be etched in first conducting film, first dielectric film and the Semiconductor substrate that expose in this first opening, be etched in the Semiconductor substrate that exposes in this second opening simultaneously, in the Semiconductor substrate in this first district, to form first groove, at second groove that forms in the Semiconductor substrate in this second district than this first ditch groove depth, this first conducting film is patterned into this floating grid simultaneously;
In first groove that limits first device region, form first device isolation region, in second groove that limits second device region, form second device isolation region simultaneously; And
On this floating grid, form the control grid, and between this control grid and this floating grid, form second dielectric film, on this second device region, form transistorized grid simultaneously.
11. the manufacture method of semiconductor device as claimed in claim 10 before the step that forms this first conducting film, also comprises the steps:
In the surface of this Semiconductor substrate, form a step, make surperficial low in this second district of surface ratio in this first district.
12. the manufacture method of semiconductor device as claimed in claim 11, wherein
Form in the surface of this Semiconductor substrate in the described step of this step, the surface of the Semiconductor substrate in this first district of etching optionally is with this step of formation in the surface of this Semiconductor substrate.
13. the manufacture method of semiconductor device as claimed in claim 11, wherein
Form in the surface of this Semiconductor substrate in the described step of this step, optionally this oxide-film is removed to form this step in the surface of this Semiconductor substrate then to form oxide-film in the surface of the Semiconductor substrate in this first district of oxidation.
14. the manufacture method of semiconductor device as claimed in claim 11, wherein
Form in the surface of this Semiconductor substrate in the described step of this step, grown semiconductor layer optionally on the surface of the Semiconductor substrate in this second district is with this step of formation in the surface of this Semiconductor substrate.
15. the manufacture method of semiconductor device as claimed in claim 11, wherein
In forming the described step of this first conducting film, this first conducting film formed make the upper level of the Semiconductor substrate in this second district be substantially equal to the upper level of first conducting film in this first district.
16. the manufacture method of semiconductor device as claimed in claim 12, wherein
In forming the described step of this first conducting film, this first conducting film formed make the upper level of the Semiconductor substrate in this second district be substantially equal to the upper level of first conducting film in this first district.
17. the manufacture method of semiconductor device as claimed in claim 13, wherein
In forming the described step of this first conducting film, this first conducting film formed make the upper level of the Semiconductor substrate in this second district be substantially equal to the upper level of first conducting film in this first district.
18. the manufacture method of semiconductor device as claimed in claim 10 after the described step that forms this first device isolation region and this second device isolation region and before the described step that forms this control grid, also comprises the steps:
On this sidewalls of floating gates, form the sidewall sections of second conducting film.
19. the manufacture method of semiconductor device as claimed in claim 11 after the described step that forms this first device isolation region and this second device isolation region and before the described step that forms this control grid, also comprises the steps:
On this sidewalls of floating gates, form the sidewall sections of second conducting film.
20. the manufacture method of semiconductor device as claimed in claim 18, wherein
In forming the described step of this sidewall sections, this second conducting film is embedded between the floating grid adjacent in a plurality of floating grids, and this second conducting film is etched to selectivity stays on the described sidewalls of floating gates.
CNB2005101250912A 2005-03-31 2005-11-18 Semiconductor device and method for fabricating the same Active CN100474593C (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105810637A (en) * 2014-12-31 2016-07-27 上海格易电子有限公司 Integration method for 3D NAND peripheral device
CN117577586A (en) * 2024-01-16 2024-02-20 合肥晶合集成电路股份有限公司 Semiconductor structure and preparation method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105810637A (en) * 2014-12-31 2016-07-27 上海格易电子有限公司 Integration method for 3D NAND peripheral device
CN105810637B (en) * 2014-12-31 2019-01-08 上海格易电子有限公司 A kind of integrated approach of 3D NAND peripheral components
CN117577586A (en) * 2024-01-16 2024-02-20 合肥晶合集成电路股份有限公司 Semiconductor structure and preparation method thereof
CN117577586B (en) * 2024-01-16 2024-04-30 合肥晶合集成电路股份有限公司 Semiconductor structure and preparation method thereof

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