CN1841475A - Array substrate - Google Patents
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- CN1841475A CN1841475A CN 200610071856 CN200610071856A CN1841475A CN 1841475 A CN1841475 A CN 1841475A CN 200610071856 CN200610071856 CN 200610071856 CN 200610071856 A CN200610071856 A CN 200610071856A CN 1841475 A CN1841475 A CN 1841475A
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Abstract
An array substrate includes an insulating substrate, pixel circuits arranged in a matrix on the insulating substrate, and video signal lines arranged correspondently with columns which the pixel circuits form. Each pixel circuit includes a drive transistor whose source is connected to a power supply terminal, a pixel electrode, an output control switch connected between a drain of the drive transistor and the pixel electrode, a selector switch connected between the drain and the video signal line, a diode-connecting switch including switching elements connected in series between the drain and a gate of the drive transistor, a first capacitor including an electrode connected to the gate, and a second capacitor including an electrode to which two of the switching elements are connected in parallel.
Description
Technical field
The present invention relates to the array substrate that can in Active Matrix LCD At, use.
Background technology
U.S. Patent No. 6,373,454 have described therein, and each image element circuit utilizes the active matrix organic electroluminescence (EL) of current mirroring circuit to show.This image element circuit comprises that the n slot field-effect transistor connects switch as driving transistors, organic EL, electric capacity, output control switch, selector switch and diode.
The source electrode of driving transistors is connected to first power lead that has than electronegative potential.Electric capacity is connected between the grid and first power lead of driving transistors.Output control switch is connected between the negative electrode of the drain electrode of driving transistors and organic EL.The anode of organic EL is connected to the second source line with high potential.Selector switch is connected between the drain electrode and video signal cable of driving transistors.Diode connects switch and is connected between the drain and gate of driving transistors.Each switch all is made up of field effect transistor usually.
By the foregoing circuit representative, each image element circuit in the active matrix OLED display comprises organic EL and field effect transistor.In the production run of OLED display, after forming pixel electrode and before finishing organic EL, field effect transistor may suffer electrostatic damage.This pixel is looked is a luminous point or stain to the electrostatic damage of field effect transistor in pixel.
Summary of the invention
The objective of the invention is to suppress to being included in transistorized electrostatic damage in each image element circuit.
According to a first aspect of the invention, a kind of array substrate is provided, this array substrate comprises insulating substrate, be arranged in the image element circuit of matrix and form the video signal cable that row are arranged corresponding to image element circuit on described insulating substrate, each image element circuit comprises that its source electrode is connected to the driving transistors of power end, pixel electrode, be connected the output control switch between driving transistors drain electrode and the pixel electrode, be connected the selector switch between drain electrode and the video signal cable, the diode that has comprised the on-off element that is connected in series between the driving transistors drain and gate connects switch, comprise first electric capacity of the electrode that is connected to grid and comprise with on-off element in second electric capacity of two first electrodes that are connected in parallel.
According to a second aspect of the invention, a kind of array substrate is provided, this array substrate comprises insulating substrate, on described insulating substrate, be arranged in the image element circuit of matrix and form the video signal cable that row are arranged corresponding to image element circuit, each image element circuit comprises that its source electrode is connected to the driving transistors of power end, pixel electrode, be connected the output control switch between driving transistors drain electrode and the pixel electrode, be connected the selector switch between drain electrode and the video signal cable, the diode that has comprised the on-off element that is connected in series between the driving transistors drain and gate connects switch, the electric capacity that comprises the electrode that is connected to grid, wherein, connect the conductive path of driving transistors drain and gate and the conductive layer of each image element circuit and overlap when when observing described array substrate perpendicular to the insulating substrate first type surface.
According to a third aspect of the invention we, a kind of array substrate is provided, this array substrate comprises insulating substrate, be arranged in the image element circuit of matrix and form the video signal cable that row are arranged corresponding to image element circuit on described insulating substrate, each image element circuit comprises that its source electrode is connected to the driving transistors of power end, pixel electrode, be connected between driving transistors drain electrode and the pixel electrode and comprise the output control switch of switching transistor, be connected the selector switch between drain electrode and the video signal cable, the diode that connects between the driving transistors drain and gate connects switch, comprise first electric capacity of the electrode that is connected to described grid and be connected described pixel electrode and described switching transistor grid between second electric capacity.
According to a forth aspect of the invention, a kind of array substrate is provided, this array substrate comprises insulating substrate, on described insulating substrate, be arranged in the image element circuit of matrix, form the capable scan signal line of being arranged and form the video signal cable that row are arranged corresponding to image element circuit corresponding to image element circuit, each image element circuit comprises that its source electrode is connected to the driving transistors of power end, pixel electrode, be connected between driving transistors drain electrode and the pixel electrode and comprise that its grid is connected to the output control switch of the switching transistor of described scan signal line, be connected the selector switch between drain electrode and the video signal cable, the diode that is connected between the driving transistors drain and gate connects switch, the electric capacity that comprises the electrode that is connected to grid, wherein when described array substrate when observing perpendicular to the insulating substrate first type surface, the scan signal line of described pixel electrode and each image element circuit is overlapped.
Description of drawings
Fig. 1 is the planimetric map that schematically shows the display example that comprises array substrate according to first embodiment of the invention;
Fig. 2 is the partial cross section figure that schematically shows the structure example that can be used for display shown in Figure 1;
Fig. 3 is the equivalent circuit diagram that is included in the pixel in the display shown in Figure 1;
Fig. 4 is the planimetric map that schematically shows the structure example that can be used for display picture element shown in Figure 1;
Fig. 5 is the planimetric map that schematically shows the display example that comprises array substrate according to second embodiment of the invention;
Fig. 6 is the equivalent circuit diagram that is included in the pixel in the display shown in Figure 5;
Fig. 7 is the planimetric map that schematically shows the structure example that can be used for display picture element shown in Figure 5;
Fig. 8 is the planimetric map that schematically shows the display example that comprises array substrate according to third embodiment of the invention;
Fig. 9 is the equivalent circuit diagram that is included in the pixel in the display shown in Figure 8;
Figure 10 is the planimetric map that schematically shows the structure example that can be used for display picture element shown in Figure 8.
Embodiment
Describe various embodiments of the present invention below with reference to accompanying drawings in detail.Identical label represents to have the assembly of identical or similar functions in whole accompanying drawing, with the repeat specification of omitting it.
Fig. 1 is the planimetric map that schematically shows the display example that comprises array substrate according to first embodiment of the invention.Fig. 2 is the partial cross section figure that schematically shows the structure example that can be used for display shown in Figure 1.Fig. 3 is the equivalent circuit diagram that is included in the pixel in the display shown in Figure 1.Fig. 4 is the planimetric map that schematically shows the structure example that can be used for display picture element shown in Figure 1.
In Fig. 2, draw display and make its display surface, promptly its front or light-emitting area are facing to this figure bottom, and its back side then faces toward the top of this figure.Fig. 4 show from positive unilateral observation to dot structure.
This display is to use the bottom-emission OLED display of driven with active matrix method.This OLED display comprises the insulating substrate SUB such as glass substrate.
As the undercoat UC shown in Fig. 2, can be with for example SiN
XLayer and SiO
XLayer order stack is added on this substrate.
The semiconductor layer SC of order stack such as polysilicon layer on undercoat UC, the grid G of using the formed gate insulator GI of tetraethyl orthosilicate (TEOS) and can being made up of for example MoW wherein all forms source electrode and drain electrode to form the top grid type thin film transistor (TFT) in each layer semiconductor layer SC.In this embodiment, shown in Fig. 1,3 and 4, this thin film transistor (TFT) is the p channel thin-film transistor and is used as driving transistors DR and switch (perhaps on-off element) SW1, SW2 and SW3a to SW3c.
The on-off element SW3a to SW3c of semiconductor layer SC is as the hearth electrode of describing capacitor C 2a to C2c subsequently corresponding to the part of source electrode.Part of grid pole insulator GI on this hearth electrode then is used as the dielectric layer of capacitor C 2a to C2c.
Scan signal line SL1 and SL2 and electrode E1 and the FEa to FEc shown in the further Pareto diagram 1,3 and 4 on gate insulator GI.These assemblies can form in same steps as with grid G.
As shown in Figure 1, scan signal line SL1 and SL2 promptly extend on directions X along each row of pixel PX; And each row along pixel PX on the Y direction are arranged.Scan signal line SL1 and SL2 are connected to sweep signal line drive YDR.
Each electrode E1 is connected to the grid of each driving transistors DR respectively.Use the hearth electrode of electrode E1 as the capacitor C of describing subsequently 1.
Electrode FEa to FEc is in quick condition.Floating electrode FEa to FEc is used separately as the top electrode of capacitor C 2a to C2c.
Interlayer insulating film II has as shown in Figure 2 covered gate insulator GI, grid G, scan signal line SL1 and SL2 and electrode E1 and FEa to FEc.Interlayer insulating film II for example can be the SiO that is formed by plasma CVD
XLayer.With the dielectric layer of the part of interlayer insulating film II on electrode E1 as capacitor C 1.
On interlayer insulating film II, arranged as Fig. 2 and source S E shown in Figure 4 and drain D E, video signal cable DL and power lead PSL and electrode E2 shown in Figure 4 shown in Fig. 1,3 and 4.These assemblies all form in same step and have for example three-decker of Mo, Al and Mo.
Source S E and drain D E are via source electrode and the drain electrode that the hole is electrically connected to thin film transistor (TFT) of touching that forms in interlayer insulating film II.
As shown in Figure 1, video signal cable DL extends on the Y direction and arranges on directions X.Video signal cable DL is connected to vision signal line drive XDR.
For example, power lead PSL is extending on the directions X and is arranging on the Y direction.
Electrode E2 is connected to power lead PSL.Electrode E2 is as the top electrode of capacitor C 1.
Passivating film PS shown in Figure 2 has covered source S E, drain D E, video signal cable DL, power lead PSL and electrode E2.Passivating film PS for example can be by SiN
XForm.
As shown in Figure 2, on passivating film PS, arrange the light transmission first electrode PE as preceding electrode, thereby they are spaced from each other.Each first electrode PE is the pixel electrode that is connected to drain D E in passivating film PS by the through hole that forms, and wherein drain D E links to each other with the drain electrode of switch SW a.
In this embodiment, the first electrode PE is an anode.Can use the material of the transparent conductive oxide of tin indium oxide (ITO) for example as the first electrode PE.
Partition insulation course PI as shown in Figure 2 further is placed on the passivating film PS.Cut off insulation course PI have the through hole that forms on the position corresponding to the first electrode PE or on corresponding to the position of the column or row that form by the first electrode PE otch that forms.For instance, cut off insulation course PI and have the through hole that on position, forms corresponding to the first electrode PE.
Cutting off insulation course PI for example can be organic insulator.For example can use photoetching technique to form and cut off insulation course PI.
On each first electrode PE, place and comprise that the organic layer ORG of luminescent layer is as active layer.For example, luminescent layer can be the film that comprises the luminous organic compound that sends red, green or blue light.Except this luminescent layer, organic layer ORG also can comprise hole injection layer, hole transmission layer, hole blockade layer, electron transfer layer and electron injecting layer.
Cutting off insulation course PI and organic layer ORG is covered by the second electrode CE as counter electrode.The second electrode CE is the common electrode between pixel PX.In this embodiment, the second electrode CE is the light reflective cathode as backplate.For example, the layer that forms video signal cable DL is thereon gone up formation wire electrode (not shown), and via the hole of touching that forms in passivating film PS and partition insulation course PI the second electrode CE is electrically connected to this wire electrode.Each organic EL (OLED) is made up of the first electrode PE, organic layer ORG and the second electrode CE.
On insulating substrate SUB, pixel PX is arranged in matrix.Place the point of crossing of each pixel PX near video signal cable DL and scan signal line SL1.
In this embodiment, shown in Fig. 1,3 and 4, each pixel PX comprises the organic OLED of organic EL, driving transistors DR, output control switch SW1, selector switch SW2, on-off element SW3a to SW3c and capacitor C 1 and the C2a to C2c as display element.The pixel electrode PE of organic EL OLED, output control switch SW1, selector switch SW2, on-off element SW3a to SW3c and capacitor C 1 and C2a to C2c have formed image element circuit.
As mentioned above, in this embodiment, driving transistors DR, switch SW 1 and SW2, on-off element SW3a to SW3c are the p channel thin-film transistors.On-off element SW3a to SW3c has formed diode and has connected switch SW 3.Selector switch SW2 is connected switch SW 3 and has formed switches set with diode, this group can and disconnect between their interconnective second states at drain and gate and interconnective first state of video signal cable DL of driving transistors DR to be switched.
Driving transistors DR, output control switch SWa and organic EL OLED are connected in series in proper order with this between the first power end ND1 and second source end ND2.In this embodiment, the first power end ND1 is the high potential power end, and second source end ND2 is the low potential power source end.
The grid of drive current supply control switch SW1 is connected to scan signal line SL1.Selector switch SW2 links to each other between video signal cable DL and driving transistors DRT.The grid of selector switch SW2 is connected to scan signal line SL2.On-off element SW3a to SW3c connects in proper order with this between the source electrode of driving transistors DR and grid.The grid of on-off element SW3a to SW3c is connected to scan signal line SL2.
Notice array substrate corresponding to a kind of structure of from OLED display, deleting vision signal line drive XDR, sweep signal line drive YDR, organic layer ORG and the second electrode CE therein, perhaps corresponding to a kind of structure of from OLED display, having deleted vision signal line drive XDR, sweep signal line drive YDR therein, having cut off insulation course PI, organic layer ORG and the second electrode CE.Array substrate can comprise vision signal line drive XDR and/or sweep signal line drive YDR.
When display image on OLED display, but for example scan signal line SL1 and scan signal line SL2 of sequential scanning just.During will writing the write cycle time of specific pixel PX to vision signal, at first, sweep signal line drive YDR exports to the scan signal line SL1 that is connected to above-mentioned pixel to sweep signal as voltage signal, thereby disconnects the switch SW 1 in this pixel.Next, sweep signal line drive YDR exports to the scan signal line SL2 that is connected to above-mentioned pixel PX to sweep signal as voltage signal, thus Closing Switch SW2 and on-off element SW3a to SW3c.Under this state, vision signal line drive XDR exports to the video signal cable DL that is connected to above-mentioned pixel PX to vision signal as current signal, thereby the value of the gate source voltage of driving transistors DR is set corresponding to the vision signal value.After this, sweep signal line drive YDR exports to the scan signal line SL2 that is connected to above-mentioned pixel to sweep signal as voltage signal, thereby cut-off switch SW2 and on-off element SW3a to SW3c, and subsequently sweep signal is being exported to the scan signal line SL1 that is connected to above-mentioned pixel PX as voltage signal, thereby Closing Switch SW1.
During effective display cycle that switch SW 1 disconnects, drive current flows through organic EL OLED with the value corresponding to the gate source voltage of driving transistors DR.Organic EL is with luminous corresponding to the brightness of drive current value.
After forming pixel electrode and before finishing organic EL, the semiconductor layer of thin film transistor (TFT) is not covered by counter electrode.Like this, for example when the evaporation mask of being made up of metal during near array substrate, semiconductor layer and evaporation mask form the current potential of electric capacity with each thin film transistor (TFT) source electrode of saltus step and drain electrode.When current potential significantly changes, may between the grid of each thin film transistor (TFT) and source electrode or drain electrode, apply big voltage and make its short circuit.This is the reason that thin film transistor (TFT) suffers electrostatic damage.
In this embodiment, the hearth electrode of capacitor C 2a to C2c is connected to the source electrode and/or the drain electrode of thin film transistor (TFT), and the top electrode of capacitor C 2a to C2c is in quick condition.Like this when the evaporation mask of forming by metal during near array substrate, those parts of the semiconductor layer of the hearth electrode that is connected to capacitor C 2a to C2c and near bigger jump in potential can not appear just.Therefore, just can avoid between the grid of each thin film transistor (TFT) and source electrode or drain electrode, applying big voltage.The result has just suppressed their short circuit.
The capacitance of each capacitor C 2a to C2c for example can be between 0.01 to 0.1pF.When electric capacity is too small, can't fully produce above-mentioned effect.When electric capacity is excessive, just be difficult to write at short notice vision signal.
In this embodiment, three on-off element SW3a to SW3c are connected in series between the drain and gate of driving transistors DR.The on-off element quantity that connects between the drain and gate of driving transistors DR without limits.
In this embodiment, the electrode of the electrode of capacitor C 2a electrode, capacitor C 2b and capacitor C 2c is connected to the source electrode of on-off element SW3a to SW3c.However, these electrodes can be connected to the source electrode and/or the drain electrode of other thin film transistor (TFT)s.In addition in this embodiment, as having comprised an electrode and a electric capacity that is connected to thin film transistor (TFT) source electrode or drain electrode, be that a pixel PX has arranged three capacitor C 2a to C2c at the electrode of quick condition.Be arranged in the interior electric capacity quantity of pixel PX without limits.
In this embodiment, OLED display is the bottom-emission display.OLED display also can be the top light emitting display.In addition in this embodiment, in pixel PX, use circuit shown in Figure 3.Alternatively, can in pixel PX, use other circuit.For example pixel PX can comprise the circuit of working voltage signal as vision signal, replaces using the circuit of current signal as vision signal.
Following the second embodiment of the present invention will be discussed.
Fig. 5 is the planimetric map that schematically shows the display example that comprises array substrate according to second embodiment of the invention.Fig. 6 is the equivalent circuit diagram that is included in the pixel in the display shown in Figure 5.Fig. 7 is the planimetric map that schematically shows the structure example that can be used for display picture element shown in Figure 5.
Fig. 7 show from positive unilateral observation to dot structure.The cross-section structure of this display is with similar with reference to the description of figure 1 and Fig. 2.
This display is to use the bottom-emission OLED display of driven with active matrix method.Except using following structure, this display have with according to the similar structure of the display of first embodiment.
Diode connects switch SW 3 except on-off element SW3a to SW3c, also comprises on-off element SW3d and SW3e.In this embodiment, these on-off elements are p channel thin-film transistors.On-off element SW3a to SW3e connects in proper order with this between the source electrode of driving transistors DR and grid.The grid of on-off element SW3a to SW3e is connected to scan signal line SL2.
Be different from Fig. 1 and pixel PX shown in Figure 3, each pixel PX does not comprise electrode FEa to FEc.Instead, semiconductor layer SC faces toward scan signal line SL1 corresponding to the part of on-off element SW3a to SW3d drain electrode, and has inserted gate insulator GI between them.The on-off element SW3a drain electrode, scan signal line SL1 and the gate insulator GI that insert between them have formed capacitor C 2a '.The drain electrode of the on-off element SW3d that inserts between them, scan signal line SL1 and gate insulator GI have formed capacitor C 2b '.
That is to say that each pixel PX comprises capacitor C 2a ' and C2b ', rather than capacitor C 2a and C2b.Capacitor C 2a ' is connected between the drain electrode and scan signal line SL1 of on-off element SW3a.Capacitor C 2b ' then is connected between the drain electrode and scan signal line SL1 of on-off element SW3b.
For example can be by coming driving display with the same procedure of in first embodiment, describing.
When conventional pixel used diode connection switch to comprise the structure of a plurality of on-off elements that are connected in series, the on-off element of diode connection switch etc. just was easy to take place electrostatic damage.It is exactly a bright spot or stain that its on-off element is looked by the pixel of electrostatic damage.
The present inventor has anatomized this phenomenon.The result is that the inventor has found the following fact.
After forming pixel electrode and before finishing organic EL, the semiconductor layer of thin film transistor (TFT) is not covered by counter electrode.Like this, for example when the evaporation mask of being made up of metal during near array substrate, semiconductor layer just forms electric capacity.This with regard to saltus step the current potential of each thin film transistor (TFT) source electrode and drain electrode.
Formed the place that the electric capacity of big capacitance is arranged with wiring closet on semiconductor layer, perhaps in the place that is connected to the electric capacity that has big capacitance, or near position these places, jump in potential is not remarkable.When jump in potential hour, just can not apply big voltage with source electrode or between draining, thereby they just are not easy short circuit at the grid of each thin film transistor (TFT).
However, when a plurality of on-off element of only simple series connection in conventional pixel circuit, the semiconductor layer of on-off element neither can form the electric capacity that big capacitance is arranged with wiring closet, also can not be connected to the electric capacity that has big capacitance.Like this, just between the grid of each thin film transistor (TFT) and source electrode or drain electrode, apply big voltage, thereby they just are easy to generate short circuit.
In this embodiment, capacitor C 2a ' is connected between the drain electrode and scan signal line SL1 of on-off element SW3a, and capacitor C 2b ' then is connected between the drain electrode and scan signal line SL1 of on-off element SW3b.So this just can effectively suppress above-mentioned jump in potential.Therefore according to this embodiment, just can avoid applying big voltage at grid and the source electrode of on-off element SW3a to SW3e or between draining.So just can not be subjected to electrostatic damage by protection switch element SW3a to SW3e.
The capacitance of each capacitor C 2a ' and C2b ' for example can be between 0.01 to 0.1pF.When the capacitance of capacitor C 2a ' and/or capacitor C 2b ' is too small, can't fully produce above-mentioned effect.When the capacitance of capacitor C 2a ' and/or capacitor C 2b ' is excessive, the just rising of possibility delaying sweep signal.
In this embodiment, diode connection switch SW 3 has five on-off element SW3a to SW3e.As long as the on-off element quantity that are included in the diode connection switch SW 3 are at least 2 just without limits.
In this embodiment, OLED display is the bottom-emission display.Alternatively, it also can be the top light emitting display.
Following the third embodiment of the present invention will be discussed.
Fig. 8 is the planimetric map that schematically shows the display example that comprises array substrate according to third embodiment of the invention.Fig. 9 is the equivalent circuit diagram that is included in the pixel in the display shown in Figure 8.Figure 10 is the planimetric map that schematically shows the structure example that can be used for display picture element shown in Figure 8.
Figure 10 show from positive unilateral observation to dot structure.The cross-section structure of this display is with similar with reference to the description of figure 1 and Fig. 2.
This display is to use the bottom-emission OLED display of driven with active matrix method.Except following utilization structure, this display have with according to the similar structure of the display of first embodiment.
Place of switches element SW3a to SW3c, every pixel PX comprise that an on-off element connects switch SW 3 as diode.In this embodiment, switch SW 3 is p channel thin-film transistors.On-off element SW3 is connected between the source electrode and grid of driving transistors DR.The grid of switch SW 3 is connected to scan signal line SL2.
Be different from Fig. 1 and pixel PX shown in Figure 3, each pixel PX does not comprise electrode FEa to FEc.
That is to say that each pixel PX does not comprise Fig. 1 and capacitor C 2a and C2b shown in Figure 3.
Instead, in each pixel PX, pixel electrode PE faces toward scan signal line SL1, and has inserted interlayer insulating film II and passivating film PS between them.Pixel electrode PE, scan signal line SL1, spacer insulator film II and passivating film PS form capacitor C 2.That is to say that each pixel PX comprises capacitor C 2, rather than capacitor C 2a to C2c.Capacitor C 2 is connected between the drain and gate of switch SW 1.
By convention, after forming the first electrode PE and before finishing organic EL OLED, output control switch is easy to suffer electrostatic damage.It is exactly a bright spot that its output control switch SW1 is looked by the pixel of electrostatic damage.
As the result who has anatomized this phenomenon, found the following fact.
After forming pixel electrode and before finishing organic EL, the first electrode PE is not covered by counter electrode.Like this, for example when the evaporation mask of being made up of metal during near array substrate, the first electrode PE just forms electric capacity.This with regard to saltus step the drain potential of output control switch SW1.The result applies big voltage between the drain electrode of output control switch SW1 and scan signal line SL1 in common array substrate, therefore just be short-circuited easily.
In this embodiment, because an electrode of capacitor C 2 is connected to the drain electrode of output control switch SW1, will be not easy the appearance potential saltus step.In addition, because another electrode of capacitor C 2 is connected to the grid of output control switch SW1, then the grid potential of output control switch SW1 changes corresponding to the variation of the drain potential of output control switch SW1.Therefore according to present embodiment, just can avoid between the grid of output control switch SW1 and scan signal line SL1, applying big voltage.So just can comprise output control switch SW1 and not be subjected to electrostatic damage.
The capacitance of capacitor C 2 for example can be between 0.01 to 0.1pF.When the capacitance of capacitor C 2 is too small, can't fully produce above-mentioned effect.When the capacitance of capacitor C 2 is excessive, the just rising and/or the decline of possibility delaying sweep signal.
Typically, the first electrode PE is set, makes when when observing perpendicular to the insulating substrate first type surface, this electrode PE do not arrive SW3 with scan signal line SL2, video signal cable DL, power lead PSL, driving transistors DR, switch SW 1 and capacitor C 1 not overlapping.In addition, typically, the first electrode PE is set, makes it only overlapping with one of scan signal line SL1 that is connected to pixel PX, wherein said pixel PX comprises the above-mentioned first pixel PE.According to this structure, just can under the situation that operation does not have a negative impact to transistor, avoid signal delay.
As shown in figure 10, capacitor C 2 can be formed by the first electrode PE and scan signal line SL1.Alternatively, capacitor C 2 also can be formed by other assemblies.For example can design the drain D E that output control switch SW1 is connected to the first electrode PE, so that
Drain D E is facing to scan signal line SL1.In the case, drain D E and scan signal line SL1 can be used as the electrode of capacitor C 2.
In this embodiment, the diode of every pixel PX connects switch SW 3 and comprises an on-off element.Alternatively, diode connects switch SW 3 and also can comprise two or more on-off elements as first and second embodiment.In this embodiment, OLED display is the bottom-emission display.Alternatively, it also can be the top light emitting display.In this embodiment, pixel PX uses circuit shown in Figure 3.Pixel PX can use other circuit.For example, pixel PX can use the circuit of voltage signal as vision signal, replaces the circuit of current signal as vision signal.
Can make up the technology of utilization described in first to the 3rd embodiment.For example, also can comprise capacitor C 2a ' and the capacitor C as shown in C2b ' or Fig. 8 to Figure 10 2 as shown in Fig. 5 to Fig. 7, perhaps capacitor C 2, C2a ' and C2b ' at the pixel PX shown in Fig. 1,3 and 4.Similarly, the capacitor C 2 of pixel PX shown in also can the person of comprising Fig. 8 to Figure 10.
Additional advantages and modifications are conspicuous for a person skilled in the art.Therefore, broadly the invention is not restricted to described herely show with described specific detail and represent embodiment.Therefore, can make various modifications and not depart from spirit and scope by the defined total inventive concept of the equivalent of claims and they.
Claims (14)
1. an array substrate comprises insulating substrate, is arranged in the image element circuit of matrix and the video signal cable of arranging corresponding to the row that image element circuit forms on described insulating substrate, and described each image element circuit comprises:
Driving transistors, its source electrode is connected to power end;
Pixel electrode;
Output control switch, it is connected between described driving transistors drain electrode and the described pixel electrode;
Selector switch, it is connected between drain electrode and the video signal cable;
Diode connects switch, and it has comprised the on-off element that is connected in series between the driving transistors drain and gate;
First electric capacity, it comprises the electrode that is connected to described grid; And
Second electric capacity, it comprise with on-off element in two first electrodes that are connected in parallel.
2. array substrate as claimed in claim 1, it is characterized in that, also comprise the scan signal line of arranging corresponding to the row of image element circuit formation, wherein in each image element circuit, described output control switch comprises that its grid is connected to the switching transistor of described scan signal line, and described second electric capacity also comprises second electrode that faces toward described first electrode and be connected to described scan signal line.
3. array substrate as claimed in claim 2 is characterized in that, described second electrode is a polysilicon layer.
4. array substrate as claimed in claim 1 is characterized in that, described second electric capacity also comprises the floating electrode as second electrode that faces toward first electrode.
5. array substrate as claimed in claim 4 is characterized in that described floating electrode is a metal level.
6. an array substrate comprises insulating substrate, is arranged in the image element circuit of matrix and the video signal cable of arranging corresponding to the row that image element circuit forms on described insulating substrate, and described each image element circuit comprises:
Driving transistors, its source electrode is connected to power end;
Pixel electrode;
Output control switch, it is connected between described driving transistors drain electrode and the described pixel electrode;
Selector switch, it is connected between drain electrode and the video signal cable;
Diode connects switch, and it has comprised the on-off element that is connected in series between the driving transistors drain and gate;
Electric capacity, it comprises the electrode that is connected to described grid,
Wherein, connect the conductive path of driving transistors drain and gate and the conductive layer of each image element circuit and overlap when when observing described array substrate perpendicular to the insulating substrate first type surface.
7. array substrate as claimed in claim 6, it is characterized in that, also comprise the scan signal line of arranging corresponding to the row of image element circuit formation, wherein in each image element circuit, described output control switch comprises that its grid is connected to the switching transistor of described scan signal line, and described conductive layer is the part of described scan signal line.
8. array substrate as claimed in claim 7 is characterized in that described conductive layer is a polysilicon layer.
9. array substrate as claimed in claim 6 is characterized in that described conductive layer is a floating electrode.
10. array substrate as claimed in claim 9 is characterized in that described floating electrode is a metal level.
11. an array substrate comprises insulating substrate, is arranged in the image element circuit of matrix and the video signal cable of arranging corresponding to the row that image element circuit forms on described insulating substrate, described each image element circuit comprises:
Driving transistors, its source electrode is connected to power end;
Pixel electrode;
Output control switch, it is connected between described driving transistors drain electrode and the described pixel electrode and comprises switching transistor;
Selector switch, it is connected between drain electrode and the video signal cable;
Diode connects switch, and it is connected between the driving transistors drain and gate;
First electric capacity, it comprises the electrode that is connected to described grid; And
Second electric capacity, it is connected between described pixel electrode and the described switching transistor grid.
12. array substrate as claimed in claim 11, it is characterized in that, described second electric capacity comprises first electrode that is connected to described switching transistor grid and facing to described first electrode and be connected to second electrode of described pixel electrode, the material of described first electrode is identical with the material of described switching transistor grid, and the material of described second electrode is identical with the material of described pixel electrode.
13. array substrate, scan signal line that the row that comprise insulating substrate, be arranged in the image element circuit of matrix on described insulating substrate, forms corresponding to image element circuit is arranged and the video signal cable of arranging corresponding to the row that image element circuit forms, described each image element circuit comprises:
Driving transistors, its source electrode is connected to power end;
Pixel electrode;
Output control switch, it is connected between driving transistors drain electrode and the pixel electrode and comprises that its grid is connected to the switching transistor of described scan signal line;
Selector switch, it is connected between drain electrode and the video signal cable;
Diode connects switch, and it is connected between the driving transistors drain and gate; And
Electric capacity, it comprises the electrode that is connected to grid,
Wherein when when observing described array substrate perpendicular to the insulating substrate first type surface, the scan signal line of described pixel electrode and each image element circuit is overlapped.
14. array substrate as claimed in claim 13, it is characterized in that, also comprise the power lead that is connected to described power end, wherein when when observing described array substrate perpendicular to the insulating substrate first type surface, described pixel electrode only with each pixel in a described scan signal line in each scan signal line, video signal cable and the power lead overlap.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005105098 | 2005-03-31 | ||
| JP2005105096 | 2005-03-31 | ||
| JP2005104647 | 2005-03-31 | ||
| JP2005104647A JP2006284915A (en) | 2005-03-31 | 2005-03-31 | Display device and array substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1841475A true CN1841475A (en) | 2006-10-04 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610071856 Pending CN1841475A (en) | 2005-03-31 | 2006-03-30 | Array substrate |
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| Country | Link |
|---|---|
| JP (1) | JP2006284915A (en) |
| CN (1) | CN1841475A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101573625B (en) * | 2007-01-15 | 2011-08-17 | 株式会社岛津制作所 | Tft array drive device |
| CN109074765A (en) * | 2016-04-22 | 2018-12-21 | 索尼公司 | Display device and electronic equipment |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9391965B2 (en) | 2012-01-25 | 2016-07-12 | Mitsubishi Electric Corporation | Data search device, data search method, data search program, data registration device, data registration method, data registration program, and information processing device |
| TWI686738B (en) * | 2019-04-24 | 2020-03-01 | 友達光電股份有限公司 | Touch display apparatus |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4155389B2 (en) * | 2001-03-22 | 2008-09-24 | 株式会社半導体エネルギー研究所 | LIGHT EMITTING DEVICE, ITS DRIVE METHOD, AND ELECTRONIC DEVICE |
| US7483001B2 (en) * | 2001-11-21 | 2009-01-27 | Seiko Epson Corporation | Active matrix substrate, electro-optical device, and electronic device |
| JP3783064B2 (en) * | 2003-01-22 | 2006-06-07 | 東芝松下ディスプレイテクノロジー株式会社 | Organic EL display and active matrix substrate |
| JP4166783B2 (en) * | 2003-03-26 | 2008-10-15 | 株式会社半導体エネルギー研究所 | Light emitting device and element substrate |
| JP4574130B2 (en) * | 2003-06-18 | 2010-11-04 | 株式会社半導体エネルギー研究所 | Semiconductor devices, electronic equipment |
-
2005
- 2005-03-31 JP JP2005104647A patent/JP2006284915A/en active Pending
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2006
- 2006-03-30 CN CN 200610071856 patent/CN1841475A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101573625B (en) * | 2007-01-15 | 2011-08-17 | 株式会社岛津制作所 | Tft array drive device |
| CN109074765A (en) * | 2016-04-22 | 2018-12-21 | 索尼公司 | Display device and electronic equipment |
| CN109074765B (en) * | 2016-04-22 | 2021-11-05 | 索尼公司 | Display device and electronic equipment |
| US11710456B2 (en) | 2016-04-22 | 2023-07-25 | Sony Group Corporation | Display apparatus and electronic device with light emitting device drive circuit including transistors with different semiconductor materials |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2006284915A (en) | 2006-10-19 |
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