CN1838560A - Method for facilitating TD-SCDMA physical layer time slot processing - Google Patents
Method for facilitating TD-SCDMA physical layer time slot processing Download PDFInfo
- Publication number
- CN1838560A CN1838560A CN 200510024541 CN200510024541A CN1838560A CN 1838560 A CN1838560 A CN 1838560A CN 200510024541 CN200510024541 CN 200510024541 CN 200510024541 A CN200510024541 A CN 200510024541A CN 1838560 A CN1838560 A CN 1838560A
- Authority
- CN
- China
- Prior art keywords
- time slot
- time
- gap
- slot
- facilitating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Mobile Radio Communication Systems (AREA)
Abstract
This invention relates to a simplifying TD-SCDMA physics time-gap processing method, which is to solve the problem that in present technique, because the switching working quantum from up-traveling to down traveling is relatively collective, so the efficient is low, and the soft and hard wares are difficult to design. In the processing, when the synchronous time-gap is combined to the adjacent business time-gap, the soft and hard wares deal a combined time-gap that is when the down-traveling synchronous time-gap is combined to the adjacent business time-gap, the up-traveling synchronous time-gap is combined to the up-traveling business time-gap. So the software dealing quantum in the switching point from the up-traveling to the down-traveling is smoother, which predigests time-gap modulation and improves the systems efficient.
Description
Technical field
The present invention relates in a kind of TD-SCDMA physical layer protocol software and hardware realization, the method to the uplink and downlink timeslots of different sizes in the subframe are handled especially relates to the method that a kind of facilitating TD-SCDMA physical layer time slot is handled.
Background technology
The TD-SCDMA physical layer protocol is a time division duplex agreement.The downstream-to-upstream switching point is DwPTS (Downlink pilot time slot, downlink synchronization slot)-Gap (guard time at interval between up-downgoing)-UpPTS (Uplink pilot time slot, uplink synchronous time slot) in its subframe structure.In time division communication system, the mode that the memory cell utilance is the highest is that two table tennis memories (referenced patent 200410084718.x) are shared in up-downgoing, and each memory can hold the data volume of a time slot.Because DwPTS, Gap and UpPTS are much smaller than other time slots, so concentrated relatively in the workload of this switching point place software and hardware.As shown in Figure 1, at the downstream-to-upstream switching point, the software burden is very heavy, and during TS0 (TS0 is a descending time slot), hardware deposits the TS0 data that receive in memory buf1; Simultaneously, the reception data (is under the situation of receiving slot at the TS6 of last subframe time slot) of previous time slot TS6 read and handle by software from memory buf2.Consider that TS6 and TS0 are the business time-slot of 864chips, average each chip (5mS/6400chip=0.78125uS/chip) of software reads and handles the data of 1chip.
During DwPTS (DwPTS0 is a descending time slot), hardware deposits the DwPTS0 data that receive in memory buf2; Simultaneously, the reception data of previous time slot TS0 read and handle by software from memory buf1.Consider that TS0 is the business time-slot of 864chips, and DwPTS only has 96chips, average each chip of software reads and handles the data of 9chip.
During Gap (Gap is the protection time slot), the reception data of previous time slot DwPTS read and handle by software from memory buf2, and software also will be with the transmission writing data into memory buf1 of a back time slot UpTPS.Consider that DwPTS, Gap and UpPTS have 96chips, 96chips and 160chips respectively, average each chip of software reads and handles the data of 1chip and writes the data of 1.67chip.
During UpPTS (UpPTS is an ascending time slot), hardware sends the UpPTS data among the memory buf1; Simultaneously, software is with the transmission writing data into memory buf2 of a back time slot TS1.Consider that TS1 has 864chips, and UpPTS has 160chips, average each chip of software need write the data of 5.4chip.
During TS1 (TS1 is an ascending time slot), hardware sends the TS1 data among the memory buf2; Simultaneously, software is with the transmission writing data into memory buf1 (is under the situation of sending time slots at the TS2 time slot) of a back time slot TS2.Consider that TS1 and TS2 are the business time-slots of 864chips, average each chip of software need write the data of 1chip.
For the arbitrary time slot among TS2, TS3, TS4, TS5 and the TS6, because itself all is the business time-slot of 864chips with the front and back time slot, average each chip of software need read and handle the data of 1chip or write the data of 1chip.
By above description as can be seen, (TS0 and TS1～TS6), to the requirement of software processes ability only be: each chip need read and handle the data of 1chip or write the data of 1chip in the most of the time.And during DwPTS, average each chip (time segment) of software need read and handle the 9chip data; During UpPTS, average each chip of software need prepare and write the 5.4chip data.System need provide the software processes ability that is equivalent to 9 times of mean values, satisfies the requirement of this peak value disposal ability, but in the most of the time, system is in not busy in midair state.Simultaneously, the frequent switching of system is caused in three continuous cracks in short-term, and the real-time of software systems is also had higher requirement.In a word, these characteristics of TD-SCDMA structure of time slot cause system effectiveness low, the design of hardware and software difficulty.
Summary of the invention
Technical problem to be solved by this invention is at the deficiencies in the prior art, and a kind of method of facilitating TD-SCDMA physical layer time slot processing is provided, and can eliminate the concentrated relatively defective of switching point workload of downstream-to-upstream, improves system effectiveness.
The object of the present invention is achieved like this: the method that a kind of facilitating TD-SCDMA physical layer time slot is handled, and it is characterized in that: synchronization slot is incorporated in contiguous business time-slot, and software and hardware is handled a time slot after the merging at every turn.
Compared with prior art, the invention has the beneficial effects as follows: because synchronization slot is incorporated in contiguous business time-slot, so on the switching point of downstream-to-upstream, the software processes amount is greatly level and smooth, has simplified timeslot scheduling, has improved system effectiveness.
Description of drawings:
Fig. 1 is a downstream-to-upstream switching point software and hardware scheduling schematic diagram in the prior art.
Fig. 2 is TD-SCDMA radio frames subframe structure figure.
Fig. 3 is downstream-to-upstream switching point software and hardware scheduling schematic diagram in the method for a kind of facilitating TD-SCDMA physical layer time slot processing of the present invention.
Embodiment
Below in conjunction with drawings and Examples the present invention is further described.
See also shown in Figure 2ly, in one 5 milliseconds subframe, have the uplink and downlink business time-slot simultaneously, amount to 7, be TS0-TS6.Must be used for the up direction except that business time-slot TS0 must be used for descending, business time-slot TS1, the direction of all the other business time-slots can change, and has and only has one and be up to descending switching point.The corresponding descending respectively and uplink synchronous time slot of DwPTS and UpPTS, GP are guard time interval between up-downgoing.Between downlink business time slot TS0 and uplink service time slot TS1, have downlink synchronization slot 96CHIPS, be that guard time then is the uplink synchronous time slot of 160CHIPS at interval between the up-downgoing of 96CHIPS then.
See also shown in Figure 3ly, TS0 and DwPTS are merged into a time slot (being called TS0+DwPTS) handle, UpPTS and TS1 are merged into a time slot (being called UpPTS+TS1) handle.
During TS0+DwPTS (TS0+DwPTS is a descending time slot), hardware deposits the TS0+DwPTS data that receive in memory buf1; Simultaneously, the reception data (is under the situation of receiving slot at the TS6 of last subframe time slot) of previous time slot TS6 read and handle by software from memory buf2, and the UpPTS+TS1 data are write among the buf2.Consider that TS6, TS0+DwPTS and UpPTS+TS1 have 864chips, 960chips and 1024chips respectively, average each chip of software reads and handles the data of 0.9chip, and writes the data of 1.07chip.
During TS0+DwPTS (TS0+DwPTS is a descending time slot), hardware deposits the TS0+DwPTS data that receive in memory buf1; Simultaneously, the reception data (is under the situation of receiving slot at the TS6 of last subframe time slot) of previous time slot TS6 read and handle by software from memory buf2, and the UpPTS+TS1 data are write among the buf2.Consider that TS6, TS0+DwPTS and UpPTS+TS1 have 864chips, 960chips and 1024chips respectively, average each chip of software reads and handles the data of 0.9chip, and writes the data of 1.07chip.
During UpPTS+TS1 (UpPTS+TS1 is a descending time slot), hardware sends the UpPTS+TS1 data among the memory buf2; Simultaneously, the reception data of previous time slot TS0+DwPTS read and handle by software from memory buf1, and the TS2 data are write among the buf1.Consider that TS0+DwPTS, UpPTS+TS1 and TS2 have 960chips, 1024chips and 864chips respectively, average each chip of software reads and handles 0.94 data, and writes the data of 0.84chip.
In addition, can further the Gap time slot be merged to TS0+DwPTS time slot (being called the TS0+DwPTS+Gap time slot); Also the Gap time slot can be merged to UpPTS+TS1 (being called the Gap+UpPTS+TS1 time slot).These two kinds of schemes all can further reduce the requirement to software peak value disposal ability.
In sum, the present invention has finished inventor's purpose, and the method is level and smooth, and downstream-to-upstream is cut Change the peak value work for the treatment of amount at a place, also just reduced the requirement to system processing power, reduced and be System cost and power consumption. Simultaneously, the reciprocal process of hardware and software is also greatly simplified, and the method can be effective Timeslot scheduling is simplified on ground, improves system effectiveness.
Claims (8)
1. the method handled of a facilitating TD-SCDMA physical layer time slot, it is characterized in that: synchronization slot is incorporated in contiguous business time-slot, and software and hardware is handled a time slot after the merging at every turn.
2. the method that facilitating TD-SCDMA physical layer time slot as claimed in claim 1 is handled, it is characterized in that: the uplink synchronous time slot is incorporated in contiguous uplink service time slot.
3. the method that facilitating TD-SCDMA physical layer time slot as claimed in claim 2 is handled, it is characterized in that: downlink synchronization slot is incorporated in contiguous downlink business time slot.
4. the method that facilitating TD-SCDMA physical layer time slot as claimed in claim 3 is handled, it is characterized in that: the uplink service time slot is TS1, the downlink business time slot is TSO.
5. the method that facilitating TD-SCDMA physical layer time slot as claimed in claim 1 is handled, it is characterized in that: downlink synchronization slot is incorporated in contiguous downlink business time slot.
6. the method that facilitating TD-SCDMA physical layer time slot as claimed in claim 5 is handled, it is characterized in that: the uplink synchronous time slot is incorporated in contiguous uplink service time slot.
7. the method that facilitating TD-SCDMA physical layer time slot as claimed in claim 6 is handled, it is characterized in that: the uplink service time slot is TS1, the downlink business time slot is TSO.
8. as the method for each described facilitating TD-SCDMA physical layer time slot processing among the claim 1-7, it is characterized in that: described business time-slot further merges empty slot.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510024541 CN1838560A (en) | 2005-03-23 | 2005-03-23 | Method for facilitating TD-SCDMA physical layer time slot processing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510024541 CN1838560A (en) | 2005-03-23 | 2005-03-23 | Method for facilitating TD-SCDMA physical layer time slot processing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1838560A true CN1838560A (en) | 2006-09-27 |
Family
ID=37015838
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510024541 Pending CN1838560A (en) | 2005-03-23 | 2005-03-23 | Method for facilitating TD-SCDMA physical layer time slot processing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1838560A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101557253B (en) * | 2008-04-09 | 2012-07-18 | 邦讯技术股份有限公司 | TD-SCDMA fiber optic repeater and method for processing uplink and downlink of signals |
-
2005
- 2005-03-23 CN CN 200510024541 patent/CN1838560A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101557253B (en) * | 2008-04-09 | 2012-07-18 | 邦讯技术股份有限公司 | TD-SCDMA fiber optic repeater and method for processing uplink and downlink of signals |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1906548A3 (en) | Method and apparatus for scheduling data considering its power in a communication system | |
| CN103064761B (en) | A kind of method of data synchronization, equipment and system | |
| CN1741423A (en) | Method for eliminating interference of downgoing pilot channel | |
| CN103391554B (en) | A kind of multi-slot binding transmission method and device | |
| CN107283508A (en) | It is a kind of to adjust the food cutting device of blade spacing | |
| CN1838560A (en) | Method for facilitating TD-SCDMA physical layer time slot processing | |
| CN1941669A (en) | Method for inserting down public guide frequency | |
| GB2375925B (en) | Allocation of timeslolts in a cellular communication system | |
| CN101141155A (en) | Method of preventing coexisted interference of PHS and TD-SCDMA | |
| CN102223721B (en) | Channel assignment method and device for downlink temporary block stream | |
| CN101772165B (en) | Time slot configuration method and time slot configuration system for dual-mode base station | |
| CN101277529A (en) | Method for indicating upstream sub-frame corresponding to upstream resource indication signaling | |
| CN103692423A (en) | Carrier mechanism | |
| CN103281792B (en) | A kind of cooperative beam shaping method and device | |
| CN208478360U (en) | Lamination device for silicon wafer one texture-etching side | |
| CN203320790U (en) | W-shaped ceiling notch and trim device | |
| CN101159484A (en) | TDD system signal transmitting method and frame structure | |
| WO2018046016A1 (en) | Device, method and uplink resource allocation device for allocating uplink resources to terminal | |
| EP4040703A1 (en) | Energy-saving information transmission method, base station, and terminal | |
| CN203650481U (en) | Carrier mechanism | |
| CN209465611U (en) | A kind of cable for elevator production cutter device | |
| CN107196730B (en) | Communication means and device for TDD system | |
| CN103503403B (en) | Data processing method and equipment | |
| CN101662835A (en) | Dispatching method of HS-SCCH order and device thereof | |
| CN214412938U (en) | Industrial Internet of things communication gateway |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Open date: 20060927 |