CN1835230A - Stacked semiconductor package - Google Patents
Stacked semiconductor package Download PDFInfo
- Publication number
- CN1835230A CN1835230A CN 200610068170 CN200610068170A CN1835230A CN 1835230 A CN1835230 A CN 1835230A CN 200610068170 CN200610068170 CN 200610068170 CN 200610068170 A CN200610068170 A CN 200610068170A CN 1835230 A CN1835230 A CN 1835230A
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- Prior art keywords
- semiconductor
- semiconductor device
- metal pattern
- semiconductor substrate
- heat
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
A metal pattern for heat dissipation is formed on the backside of a second semiconductor substrate, the metal pattern being in contact with a first semiconductor element mounted on a semiconductor device adjacent to the backside. Vias are formed on the peripheries of semiconductor substrates, the vias penetrating in the thickness direction to transmit heat. The vias and the metal pattern for heat dissipation are connected to each other on the backside of the semiconductor substrate. Solder balls disposed between the semiconductor devices transmit heat having been transmitted to the metal pattern of the semiconductor device to the vias of the semiconductor device adjacent to the backside of the semiconductor device having the metal pattern.
Description
Technical field
The present invention relates to be provided with the semiconductor device of a plurality of installation semiconductor elements and with the stacked semiconductor package of these semiconductor device laminations.
Background technology
Miniaturization, lightweight along with portable information device etc. also require assembly densification, miniaturization, the lightweight of semiconductor device.In order to adapt to these requirements, developed stacked semiconductor package with semiconductor device lamination, multistage installation.But, in this stacked semiconductor package, because the semiconductor device arranged in high density exists the heat that semiconductor element takes place to be trapped in the interior problem of semiconductor device easily.As ways of addressing this issue, TOHKEMY 2000-12765 communique etc. has proposed to be provided with the heat diffusion that semiconductor device is taken place and has arrived outside heat radiation structure, the method for seeking the semiconductor element steady operation.
Fig. 8 is the cutaway view that expression has the existing stacked semiconductor package of such heat radiation structure.The 1st semiconductor element 101 is mounted on the 1st semiconductor substrate 102 with flip-chip.The 2nd semiconductor element 103 is mounted on the 2nd semiconductor substrate 104 with flip-chip too.And the 1st semiconductor substrate 102 and the 2nd semiconductor substrate 104, also have the 2nd semiconductor substrate 104 and motherboard 105, respectively with solder splashes 106 connections that set between these substrates 102,104 and the motherboard 105.And, on the 1st semiconductor substrate the 102, the 2nd semiconductor substrate 104 and motherboard 105, form many paths 107 that heat release is used, so that heat by in these substrates 102,104 and the motherboard 105, is delivered on the opposing face of substrate 102,104 and motherboard 105 easily.Also have, path 107 forms the structure of its inner surfaces with metal plating, or filling comprises the structure of the heat transfer member that the resin material of metal and pottery etc. constitutes.
But, in existing stacked semiconductor package, path 107 as the heat release path is arranged on semiconductor substrate 102, close on semiconductor element 101 in 104,103 place near central authorities, therefore at semiconductor element 101, the semiconductor substrate 102 that flip-chip connects on 103 the electrode, 104 internal electrode terminal with semiconductor element 101 is being installed, when connecting the harness wiring of usefulness between the external electrode terminals that disposes on the opposing face of 103 face, 107 one-tenth in path obstacle, the degree of freedom in the path of distribution process reduces, sometimes can not realize the desirable latch configuration of client, consequently, generation can not realize corresponding semiconductor element 101, the problem of 103 laminationization.
Summary of the invention
The present invention makes in order to solve above-mentioned existing problems, its purpose is to provide and can will a plurality of semiconductor device laminations of semiconductor element be installed respectively, simultaneously exothermal efficiency is good, and the stacked semiconductor package that do not reduce of the degree of freedom in the path of distribution process.
In order to solve the problem that above-mentioned prior art exists, stacked semiconductor package of the present invention has structure as described below.
Stacked semiconductor package of the present invention, it is the stacked semiconductor package that semiconductor element mounting is carried out multistage lamination at the semiconductor device of semiconductor substrate surface side, wherein, on the back side of semiconductor substrate, formation with covering be installed in the adjoining semiconductor device of this rear side on the metal pattern used of the heat release of member state of contact configuration of semiconductor element, near the semiconductor substrate periphery place, form and connect the perforation path that thickness direction transmits heat, the back side at described semiconductor substrate, described perforation path is connected with the metal pattern that heat release is used, the solder splashes of crossing between the semiconductor device is set, utilize heat transferred that this solder splashes makes the metal pattern that is delivered to semiconductor device to the perforation path of the adjoining semiconductor device of the rear side of the semiconductor device that this metal pattern is set.
In this structure, the heat transferred that semiconductor element takes place is to the metal pattern that contacts with the member that covers this semiconductor element, and the heat of this metal pattern discharges after being passed to the perforation path that is connected with metal pattern.And, be delivered to the heat of the metal pattern of semiconductor device, be delivered to and be provided with the perforation path of the adjoining semiconductor device of the rear side of semiconductor device of metal pattern by solder splashes.By means of this, the heat that semiconductor element takes place can scatter well.If adopt said structure, then will be equipped on the place near periphery of semiconductor substrate as the perforation path in heat release path, therefore the leads for connecting of internal electrode terminal and external electrode terminals that is connected to the semiconductor substrate of semiconductor element connects the path and forms obstacle hardly when wiring, the wiring of the lead of connection usefulness can be kept the very high wiring degree of freedom.Thereby, can freely realize the configuration of the desirable latch of client, and can be easily and this stacked semiconductor package stably is provided.
Again, stacked semiconductor package of the present invention, it is the stacked semiconductor package that the semiconductor element upside-down mounting is carried out multistage lamination at the semiconductor device of semiconductor substrate surface side, wherein, on the back side of semiconductor substrate, formation be installed in the adjoining semiconductor device of this rear side on the metal pattern used of the heat release of semiconductor element state of contact configuration, near the semiconductor substrate periphery place, form and connect the perforation path that thickness direction transmits heat, the back side at described semiconductor substrate, described perforation path is connected with the metal pattern that heat release is used, the solder splashes of crossing between the semiconductor device is set, utilize heat transferred that this solder splashes makes the metal pattern that is delivered to semiconductor device to the perforation path of the adjoining semiconductor device of the rear side of the semiconductor device that this metal pattern is set.
In this structure, the heat transferred that semiconductor element takes place is to the metal pattern that contacts with this semiconductor element, and the heat of this metal pattern discharges after being passed to the perforation path that is connected with metal pattern.And the heat that is delivered to the metal pattern of semiconductor device is delivered to and is provided with the perforation path of the adjoining semiconductor device of the rear side of semiconductor device of this metal pattern by solder splashes.By means of this, the heat that semiconductor element takes place can scatter well.If adopt said structure, then will be equipped on the place near periphery of semiconductor substrate as the perforation path in heat release path, therefore the leads for connecting of internal electrode terminal and external electrode terminals that is connected to the semiconductor substrate of semiconductor element connects the path and forms obstacle hardly when wiring, the wiring of the lead of connection usefulness can be kept the very high wiring degree of freedom.Thereby, can freely realize the configuration of the desirable latch of client, and can be easily and this stacked semiconductor package stably is provided.
Again, stacked semiconductor package of the present invention, wherein, the semiconductor element of on metal pattern that the heat release that is provided with on the back side of the semiconductor substrate of semiconductor device is used and the semiconductor device adjacent, installing with the rear side of this semiconductor device, and bonding by the high bonding agent of heat transference efficiency.
Adopt this structure, the heat of semiconductor element is delivered on the metal pattern that heat release uses well by the high bonding agent of pyroconductivity, and consequently, the heat that takes place on the semiconductor element can better dispel the heat.
Again, stacked semiconductor package of the present invention, wherein, the metal pattern that heat release is used is connected to perforation path and the solder splashes that uses as grounding electrode.
Adopt this structure, can make the back side current potential stabilisation of the semiconductor element of installing on the semiconductor substrate, needing to realize the analog IC of reverse bias easily.
Again, stacked semiconductor package of the present invention, wherein, the electrode of semiconductor device is configured to clathrate on the whole surface of this semiconductor element.
Description of drawings
Figure 1A is the cutaway view of the stacked semiconductor package of the present invention the 1st embodiment.
Figure 1B is a plane graph of observing the semiconductor substrate that uses the stacked semiconductor package of the 1st embodiment from below (rear side).
Fig. 2 is the cutaway view of variation of the stacked semiconductor package of the present invention the 1st embodiment.
Fig. 3 A is the cutaway view of the stacked semiconductor package of the present invention the 2nd embodiment.
Fig. 3 B is a plane graph of observing the semiconductor substrate that uses the stacked semiconductor package of the 2nd embodiment from below (rear side).
Fig. 4 A is the cutaway view of the stacked semiconductor package of the present invention the 3rd embodiment.
Fig. 4 B is a plane graph of observing the semiconductor substrate that uses the stacked semiconductor package of the 3rd embodiment from below (rear side).
Fig. 5 A is the cutaway view of the stacked semiconductor package of the present invention the 4th embodiment.
Fig. 5 B is a plane graph of observing the semiconductor substrate that uses the stacked semiconductor package of the 4th embodiment from below (rear side).
Fig. 6 is the cutaway view of the stacked semiconductor package of the present invention the 5th embodiment.
Fig. 7 A is the plane graph of the semiconductor element that uses from the stacked semiconductor package of beneath the 5th embodiment.
Fig. 7 B is a plane graph of observing the semiconductor substrate that uses the stacked semiconductor package of the 5th embodiment from below (rear side).
Fig. 8 is the cutaway view of existing stacked semiconductor package.
Embodiment
Below, describe with reference to the heat radiation structure of accompanying drawing the stacked semiconductor package of embodiments of the invention.
At first, according to Figure 1A and Figure 1B the stacked semiconductor package of the 1st embodiment of the present invention is described.Here, Figure 1A is the cutaway view of the stacked semiconductor package of the present invention the 1st embodiment.Figure 1B is a plane graph of observing the semiconductor substrate that uses the stacked semiconductor package of the 1st embodiment from below (rear side).
Shown in Figure 1A, this stacked semiconductor package is on the 1st semiconductor device 3 that the 1st semiconductor element 1 is installed on the 1st semiconductor substrate 2, and lamination is installed in the 2nd semiconductor element 4 that the 2nd semiconductor device 6 on the 2nd semiconductor substrate 5 constitutes.
Shown in Figure 1B, on the 1st semiconductor substrate 2, the place near periphery on the bottom surface forms a plurality of external electrode terminals 2a, and shown in Figure 1A, the place near central authorities of upper surface forms a plurality of the 1st electrodes (internal electrode terminal) 2b, and the place near periphery of upper surface forms a plurality of the 2nd electrode 2c.And, the 1st semiconductor element 1 is installed in supine mode at the upper surface of the 1st semiconductor substrate 2.The 1st electrode 2b and the 1st semiconductor element 1 are electrically connected by leads such as gold thread 7.And the 1st semiconductor element 1 and lead 7 usefulness sealing resins 8 formation modules.Again, though not shown, utilize to be arranged on the external electrode terminals 2a of the 1st semiconductor substrate 2 as the 1st electrode 2b of the internal electrode terminal of the 1st semiconductor substrate 2 to be electrically connected being connected on the 1st semiconductor substrate 2 with distribution.
And shown in Figure 1B, equally on the 2nd semiconductor substrate 5, the place near periphery in the bottom surface forms a plurality of external electrode terminals 5a, and for example shown in Figure 1A, the place near central authorities at upper surface forms a plurality of the 1st electrodes (internal electrode terminal) 5b, forms a plurality of the 2nd electrode 5c in the place near periphery of upper surface.And the 1st electrode 5b of the 1st semiconductor substrate 5 and the 2nd semiconductor element 4 are connected by projected electrodes such as the solder splashes 9 ground flip-chip that faces down.The installation method of this 2nd semiconductor element 4 is with ventricumbent mode upside-down mounting, still install in supine mode and with sealing resin cover can, be not particularly limited in one.
Again, though not shown, utilize to be arranged on the external electrode terminals 5a of the 2nd semiconductor substrate 5 as the 1st electrode 5b of the internal electrode terminal of the 2nd semiconductor substrate 5 to be electrically connected being connected on the 2nd semiconductor substrate 5 with distribution.
The solder splashes 10 that is electrically connected usefulness with motherboard (not shown) is set on the external electrode terminals 2a of the 1st semiconductor substrate 2 again.
And the upper surface of the 1st semiconductor substrate 2 is connected with solder splashes 11 with the external electrode terminals 5a that the place near periphery of the bottom surface of the 2nd semiconductor substrate 5 is provided with near a plurality of the 2nd electrode 2c that peripheral place is provided with.
Again, form the metal pattern 12 that heat release is used on the back side of the 2nd semiconductor substrate 5, this metal pattern 12 contacts with the sealing resin 8 that covers the 1st semiconductor element 1.
The present invention is not limited to such structure, also can be for example shown in Figure 2, the 1st semiconductor element 1 is with ventricumbent mode upside-down mounting, cover the 1st semiconductor element 1 metal heat liberation board 18 is set, in this case, being formed at the metal pattern 12 that the heat release on the back side of the 2nd semiconductor substrate 5 uses contacts with metallic heat liberation board 18.
This heat liberation board 18 uses the material of chromium plating on the copper for example, but is not limited to this.
The a part of external electrode terminals 5a that forms on the back side of above-mentioned metal pattern 12 and the 2nd semiconductor substrate 5 shown in Figure 1B form that physics (heat conduction) is gone up and electric on being connected.This metal pattern 12 be when making the 2nd semiconductor substrate 5 with the identical back side on the external electrode terminals 5a that forms form simultaneously, nickel plating on metal such as tungsten, molybdenum for example, gold formation.Also have, in this embodiment, on the back side of the 1st semiconductor substrate 2, also form metal pattern 13 with spline structure.The a part of external electrode terminals 2a that forms on the back side of this metal pattern 13 and the 1st semiconductor substrate 2 shown in Figure 1B form that physics (heat conduction) is gone up and electric on being connected, but be not limited to this.
Shown in Figure 1A,, form many perforation paths 14,15 that connect to the back side from upper surface in the place near periphery of each semiconductor substrate 2,5.And the metal pattern 11 that is provided with on the back side of the 2nd electrode 5c that is provided with near the place of periphery of the upper surface that makes the 1st semiconductor substrate 5 by the perforation path 14 that is provided with on the 2nd semiconductor substrate 5 and the 2nd semiconductor substrate 5 form physics (heat conduction) upward with electric on be connected.Again, the metal pattern 12 that is provided with on the back side of the 2nd electrode 2c that is provided with near the place of periphery of the upper surface that makes the 1st semiconductor substrate 2 by the perforation path 15 that is provided with on the 1st semiconductor substrate 2 and the 2nd semiconductor substrate 2 form physics (heat conduction) upward with electric on be connected.Also have, connect path 14,15 and form the structure of its inner surfaces with metal plating, or added metal or comprise metal and the formation of the resin material of pottery etc. gets final product.
In the described in the above structure, at the 1st semiconductor device 3 superimposed layers the 2nd semiconductor device 6, but because as having the metal pattern on the back side that is arranged on the 2nd semiconductor substrate 5 to be in contact with it on the sealing resin 8 of the member of the 1st semiconductor element 1 that covers the 1st semiconductor device 3 and the heat liberation board 18, so the heat that the 1st semiconductor element 1 takes place transmits to metal pattern 12 by sealing resin 8 and heat liberation board 18, the heat of metal pattern 12 is delivered to the solder splashes 11 that below one side of the perforation path 14 of the 2nd semiconductor substrate 5 that top one side of this external electrode terminals 5a is connected and described external electrode terminals 5a is connected from the external electrode terminals 5a with metal pattern 12 contact, the 1st electrode 2c of the 1st semiconductor substrate 2, connect path 15, by being connected to the external electrode terminals 2a of the 1st semiconductor substrate 2 on this perforation path 15, also be delivered to metal pattern 13 and solder splashes 10 again.Thereby, the heat that the 1st semiconductor element 1 produces can be delivered to metal pattern 12, external electrode terminals 5a, perforation path 14, solder splashes the 11, the 2nd electrode 2c well, connect path 15, external electrode terminals 2a, metal pattern 13, solder splashes 10, can keep good radiating efficiency.
Again, because will be as the perforation path 14 in heat release path, 15 are equipped on the 1st, the 2nd semiconductor substrate 2,5 place near periphery rather than close central authorities, by lead 7 and projected electrode 16, each semiconductor substrate 2 of conduct that projected electrode 9 connects, the 2b of 5 internal electrode, 5b and external electrode terminals 2a, when 5a connects the distribution winding displacement of usefulness, described perforation path 14,15 can constitute obstacle hardly, the degree of freedom height of winding displacement, realize the desirable latch configuration of client easily, like this, with semiconductor device 3,6 (semiconductor elements 1,4) can not form obstacle during lamination yet, stablely easily provide such stacked semiconductor package.
Below, according to Fig. 3 A and Fig. 3 B the stacked semiconductor package of the present invention the 2nd embodiment is described.Here, Fig. 3 A is the cutaway view of the stacked semiconductor package of the present invention the 2nd embodiment.Fig. 3 B is a plane graph of observing the semiconductor substrate that uses the stacked semiconductor package of the 2nd embodiment from below (rear side).
As shown in Figure 3A, this stacked semiconductor package is on the 1st semiconductor device 3 that the 1st semiconductor element 1 is installed on the 1st semiconductor substrate 2, and lamination is installed in the 2nd semiconductor element 4 that the 2nd semiconductor device 6 on the 2nd semiconductor substrate 5 constitutes.
Shown in Fig. 3 B, on the 1st semiconductor substrate 2, the place near periphery on the bottom surface forms a plurality of external electrode terminals 2a, and as shown in Figure 3A, the place near central authorities of upper surface forms a plurality of the 1st electrodes (internal electrode terminal) 2b, and the place near periphery of upper surface forms a plurality of the 2nd electrode 2c.And face down by projected electrodes such as solder splashes 16 with the 1st semiconductor element 1 at the 1st electrode 2b of the 1st semiconductor substrate 2 and to be connected in the flip-chip mode.Again, though not shown, utilize to be arranged on the external electrode terminals 2a of the 1st semiconductor substrate 2 as the 1st electrode 2b of the internal electrode terminal of the 1st semiconductor substrate 2 to be electrically connected being connected on the 1st semiconductor substrate 2 with distribution.
And shown in Fig. 3 B, equally on the 2nd semiconductor substrate 5, the place near periphery in the bottom surface forms a plurality of external electrode terminals 5a, again as shown in Figure 3A, the place near central authorities at upper surface forms a plurality of the 1st electrodes (internal electrode terminal) 5b, forms a plurality of the 2nd electrode 5c in the place near periphery of upper surface.And the 1st electrode 5b of the 2nd semiconductor substrate 5 and the 2nd semiconductor element 4 are connected by projected electrodes such as the solder splashes 9 ground flip-chip that faces down.Again, though not shown, utilize to be arranged on the external electrode terminals 5a of the 2nd semiconductor substrate 5 as the 1st electrode 5b of the internal electrode terminal of the 2nd semiconductor substrate 5 to be electrically connected being connected on the 2nd semiconductor substrate 5 with distribution.
On the external electrode terminals 2a of the 1st semiconductor substrate 2, the solder splashes 10 that is electrically connected usefulness with motherboard (not shown) is set again.
And the external electrode terminals 5a near peripheral place setting of a plurality of the 2nd electrode 2c that the place of the close periphery of the upper surface of the 1st semiconductor substrate 2 is provided with and the bottom surface of the 2nd semiconductor substrate 5 connects with solder splashes 11.
Again, form the metal pattern 12 that heat release is used on the back side of the 2nd semiconductor substrate 5, this metal pattern 12 contacts with the back side of the 1st semiconductor element 4.The a part of external electrode terminals 5a that forms on the back side of this metal pattern 12 and the 2nd semiconductor substrate 5 shown in Fig. 3 B form that physics (heat conduction) is gone up and electric on being connected.This metal pattern 12 be when making the 2nd semiconductor substrate 5 with the identical back side on the external electrode terminals 5a that forms form simultaneously, nickel plating on metal such as tungsten, molybdenum for example, gold-plated formation.Also have, in this embodiment, on the back side of the 1st semiconductor substrate 2, also form metal pattern 13 with spline structure.The a part of external electrode terminals 2a that forms on the back side of this metal pattern 13 and the 1st semiconductor substrate 2 shown in Fig. 3 B form that physics (heat conduction) is gone up and electric on being connected, still be not limited to this.
As shown in Figure 3A, in the place near periphery of each semiconductor substrate 2,5, form many perforation paths 14,15 that connect to the back side from upper surface.And, the metal pattern 12 that is provided with on the 2nd electrode 5c that the upper surface that makes the 2nd semiconductor substrate 5 by the perforation path 14 that is provided with on the 2nd semiconductor substrate 5 is provided with near the place of periphery and the back side of the 2nd semiconductor substrate 5 form physics (heat conduction) upward with electric on be connected.Again, the metal pattern 13 that is provided with on the back side of the 2nd electrode 2c that is provided with near the place of periphery of the upper surface that makes the 1st semiconductor substrate 2 by the perforation path 15 that is provided with on the 1st semiconductor substrate 2 and the 2nd semiconductor substrate 2 form physics (heat conduction) upward with electric on be connected.Also have, connect path 14,15 and form the structure of its inner surfaces with metal plating, or added metal or comprise metal and the formation of the resin material of pottery etc. gets final product.
In the described in the above structure, at the 1st semiconductor device 3 superimposed layers the 2nd semiconductor device 6, but owing to have the metal pattern 12 on the back side that is arranged on the 2nd semiconductor substrate 5 to be in contact with it on the 1st semiconductor element 1 of the 1st semiconductor device 3, so the heat that the 1st semiconductor element 1 takes place transmits to this metal pattern 12, the heat of this metal pattern 12 is delivered to the solder splashes 11 that below one side of the perforation path 14 of the 2nd semiconductor substrate 5 that top one side of this external electrode terminals 5a connects and described external electrode terminals 5a is connected from the external electrode terminals 5a that is connected with metal pattern 12, the 2nd electrode 2c of the 1st semiconductor substrate 2, connect path 15, by being connected to the external electrode terminals 2a of the 1st semiconductor substrate 2 on this perforation path 15, also be delivered to metal pattern 13 and solder splashes 10 again.Thereby, the heat that the 1st semiconductor element 1 produces can be delivered to metal pattern 12, external electrode terminals 5a, perforation path 14, solder splashes the 11, the 2nd electrode 2c well, connect path 15, external electrode terminals 2a, metal pattern 13, solder splashes 10, can keep good radiating efficiency.
Again, because will be as the perforation path 14 in heat release path, 15 are equipped on the 1st, the 2nd semiconductor substrate 2,5 place near periphery rather than close central authorities, by projected electrode 9,16 are connected to semiconductor element 1, each semiconductor substrate 2 of the conduct of 4 electrode, the 1st electrode 2b of 5 internal electrode terminal, 5b and external electrode terminals 2a, when 5a connects the distribution winding displacement of usefulness, described perforation path 14,15 can constitute obstacle hardly, the degree of freedom height of winding displacement, can freely realize the desirable latch configuration of client, like this, with semiconductor device 3,6 (semiconductor elements 1,4) can not form obstacle during lamination yet, can be easily and such stacked semiconductor package stably is provided.
Below, according to Fig. 4 A and Fig. 4 B the stacked semiconductor package of the present invention the 3rd embodiment is described.Here, Fig. 4 A is the cutaway view of the stacked semiconductor package of the present invention the 3rd embodiment.Fig. 4 B is a plane graph of observing the semiconductor substrate that uses the stacked semiconductor package of the 3rd embodiment from below (rear side).Also have, for being marked with identical label and omitting its explanation with the parts of each structural element identical function of the stacked semiconductor package of above-mentioned the 2nd embodiment.
Shown in Fig. 4 A, in this stacked semiconductor package, metal pattern that the heat release that is provided with on the back side of the 2nd semiconductor substrate 5 of the 2nd semiconductor substrate 6 is used 12 and the semiconductor element of on the 1st semiconductor device 3 of the rear side of the 2nd semiconductor device 6, installing 1, good by heat-conductive characteristic, the conductive adhesive 17 that promptly pyroconductivity is high is electrically connected.
, as conductive adhesive 17, consider factors such as reliability, thermal stress here, bonding agent adopts for example epoxy resin, the bridging agent that the conductor filler adopts the Ag-Pd alloy to constitute.Again, device conductive adhesive 17 can form paste, also can form sheet.
Adopt such structure, then not only can access identical effect with above-mentioned the 1st, the 2nd embodiment, and the heat of the 1st semiconductor element 1 can be transmitted to the metal pattern 12 of heat transmission well by the conductive adhesive 17 of high thermoconductivity, and therefore the heat that takes place of the 1st semiconductor element 1 can better distribute.
Below, according to Fig. 5 A and Fig. 5 B the stacked semiconductor package of the present invention the 4th embodiment is described.Here, Fig. 5 A is the cutaway view of the stacked semiconductor package of the present invention the 4th embodiment.Fig. 5 B is a plane graph of observing the semiconductor substrate that uses the stacked semiconductor package of the 4th embodiment from below (rear side).Also have, for being marked with identical label and omitting its explanation with the parts of each structural element identical function of the stacked semiconductor package of above-mentioned the 2nd embodiment.
Shown in Fig. 5 B, in this stacked semiconductor package, the metal pattern 12 that forms on the back side of the 2nd semiconductor substrate 5 only is connected with the 5a ' of grounding electrode portion among the external electrode terminals 5a that disposes on the bottom periphery of the 2nd semiconductor substrate 5.And the 5a ' of this grounding electrode portion is connected to perforation path of using as grounding electrode 14 and the solder splashes 11 that uses as grounding electrode.
Adopt such structure, then not only can access identical effect with above-mentioned the 1st, the 2nd embodiment, and because metal pattern 12 only is connected to the 5a ' of grounding electrode portion, can make on the 2nd semiconductor substrate 5 back side current potential stabilisation of the 2nd semiconductor element of installing 4, needing realize the laminationization of the analog IC etc. of reverse bias easily.
Also have, in this embodiment, the metal pattern 13 that forms on the back side of the 1st semiconductor substrate 2 also only is connected with the 2a ' of grounding electrode portion among the external electrode terminals 2a that disposes on the bottom periphery of the 1st semiconductor substrate 2.
Below, according to Fig. 6, Fig. 7 A and Fig. 7 B the stacked semiconductor package of the present invention the 5th embodiment is described.Here, Fig. 6 is the cutaway view of the stacked semiconductor package of the present invention the 5th embodiment.Fig. 7 A is the plane graph of the semiconductor element that uses from the stacked semiconductor package of beneath the 5th embodiment.Fig. 7 B is the plane graph of the semiconductor substrate that uses from the stacked semiconductor package of beneath the 5th embodiment.Also have, for being marked with identical label and omitting its explanation with the parts of each structural element identical function of the stacked semiconductor package of above-mentioned the 2nd embodiment.
Shown in Fig. 7 A, in this stacked semiconductor package, the electrode 1a of the 1st semiconductor element 1 is configured to clathrate on the whole surface of semiconductor element.And corresponding with it, be configured to clathrate as the 1st electrode 2b of the internal electrode terminal of the 1st semiconductor substrate 2 too with the projected electrodes such as solder splashes 16 that are connected them.
Again, same electrode 4a with the 2nd semiconductor element 4 is configured to clathrate on the whole surface of semiconductor element.And corresponding with it, be configured to clathrate as the 1st electrode 5b of the internal electrode terminal of the 2nd semiconductor substrate 5 too with the projected electrodes such as solder splashes 9 that are connected them.
Adopt such structure, then not only can access identical effect with above-mentioned the 1st embodiment, and because will be as the perforation path 14 in heat release path, 15 are equipped on the 1st, the 2nd semiconductor substrate 2,5 place by periphery, so semiconductor element 1,4 electrode 1a, 4a is configured to clathrate on the whole surface of semiconductor element, with its while, projected electrode 16,19 and as semiconductor substrate 2, the 1st electrode 2b of 5 internal electrode terminal, 5b is configured under the cancellate situation, connecting as each semiconductor substrate 2, the 1st electrode 2b of 5 internal electrode terminal, 5b and external electrode terminals 2a, when the distribution winding displacement is used in the connection that 5a uses, connect path 14,15 also form obstacle hardly, connect winding displacement degree of freedom height with distribution, can freely realize the desirable latch configuration of client, like this, even with semiconductor device 3,6 (semiconductor elements 1,4) can not counteract during lamination yet, stablely easily provide such stacked semiconductor package.
Again, in above-mentioned the 1st～the 5th embodiment, the situation of the stacked semiconductor package of 2 grades of laminations has been described, but has been not limited to this, stacked semiconductor package for the semiconductor device laminations more than 2 grades such as 3 grades, 4 grades also can adopt identical heat radiation structure.
Claims (8)
1. a stacked semiconductor package carries out multistage lamination with semiconductor element mounting at the semiconductor device of semiconductor substrate surface side, it is characterized in that,
On the back side of semiconductor substrate, form with covering be installed in the adjoining semiconductor device of this rear side on the metal pattern used of the heat release of member state of contact configuration of semiconductor element,
Near the semiconductor substrate periphery place, form and connect the perforation path that thickness direction transmits heat, and at the back side of described semiconductor substrate, described perforation path is connected with the metal pattern that heat release is used, the solder splashes of crossing between the semiconductor device is set, utilize heat transferred that this solder splashes makes the metal pattern that is delivered to semiconductor device to the perforation path of the adjoining semiconductor device of the rear side of the semiconductor device that this metal pattern is set.
2. a stacked semiconductor package carries out multistage lamination with the semiconductor element upside-down mounting at the semiconductor device of semiconductor substrate surface side, it is characterized in that,
On the back side of semiconductor substrate, form be installed in the adjoining semiconductor device of this rear side on the metal pattern used of the heat release of semiconductor element state of contact configuration,
Near the semiconductor substrate periphery place, form and connect the perforation path that thickness direction transmits heat, and at the back side of described semiconductor substrate, described perforation path is connected with the metal pattern that heat release is used, the solder splashes of crossing between the semiconductor device is set, utilize heat transferred that this solder splashes makes the metal pattern that is delivered to semiconductor device to the perforation path of the adjoining semiconductor device of the rear side of the semiconductor device that this metal pattern is set.
3. stacked semiconductor package according to claim 1 is characterized in that,
The semiconductor element of on metal pattern that the heat release that is provided with on the back side of the semiconductor substrate of semiconductor device is used and the semiconductor device adjacent, installing with the rear side of this semiconductor device, and bonding by the high bonding agent of heat transference efficiency.
4. stacked semiconductor package according to claim 2 is characterized in that,
The semiconductor element of on metal pattern that the heat release that is provided with on the back side of the semiconductor substrate of semiconductor device is used and the semiconductor device adjacent, installing with the rear side of this semiconductor device, and bonding by the high bonding agent of heat transference efficiency.
5. stacked semiconductor package according to claim 1 is characterized in that,
The metal pattern that heat release is used is connected to perforation path and the solder splashes that uses as grounding electrode.
6. stacked semiconductor package according to claim 2 is characterized in that,
The metal pattern that heat release is used is connected to perforation path and the solder splashes that uses as grounding electrode.
7. stacked semiconductor package according to claim 1 is characterized in that,
The electrode of semiconductor device is configured to clathrate on the whole surface of this semiconductor element.
8. stacked semiconductor package according to claim 2 is characterized in that,
The electrode of semiconductor device is configured to clathrate on the whole surface of this semiconductor element.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005076172 | 2005-03-17 | ||
| JP2005076172 | 2005-03-17 | ||
| JP2005325496 | 2005-11-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1835230A true CN1835230A (en) | 2006-09-20 |
Family
ID=37002913
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610068170 Pending CN1835230A (en) | 2005-03-17 | 2006-03-17 | Stacked semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1835230A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522380A (en) * | 2011-12-21 | 2012-06-27 | 华为技术有限公司 | PoP packaging structure |
| CN102171816B (en) * | 2008-10-03 | 2013-09-25 | 松下电器产业株式会社 | Wiring board, semiconductor device and method for manufacturing same |
-
2006
- 2006-03-17 CN CN 200610068170 patent/CN1835230A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102171816B (en) * | 2008-10-03 | 2013-09-25 | 松下电器产业株式会社 | Wiring board, semiconductor device and method for manufacturing same |
| CN102522380A (en) * | 2011-12-21 | 2012-06-27 | 华为技术有限公司 | PoP packaging structure |
| CN102522380B (en) * | 2011-12-21 | 2014-12-03 | 华为技术有限公司 | PoP packaging structure |
| US9318407B2 (en) | 2011-12-21 | 2016-04-19 | Huawei Technologies Co., Ltd. | Pop package structure |
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