CN1831716A - Computer system and method for clearing control circuit and environment set memory - Google Patents
Computer system and method for clearing control circuit and environment set memory Download PDFInfo
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- CN1831716A CN1831716A CN 200510054396 CN200510054396A CN1831716A CN 1831716 A CN1831716 A CN 1831716A CN 200510054396 CN200510054396 CN 200510054396 CN 200510054396 A CN200510054396 A CN 200510054396A CN 1831716 A CN1831716 A CN 1831716A
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Abstract
A method for clearing up environmental set internal memory by clear - up control circuit includes forming computer system by power supply switch, reset switch, environmental set internal memory and clear - up control circuit; using environmental set internal memory to store operation environmental set value of computer system and clearing up operation environmental set value stored in environmental set internal memory by clear - up control circuit when power supply switch and reset switch are triggered simultaneously.
Description
(1) technical field
The invention relates to a kind of motherboard, particularly relevant for a kind of computer system of removing control circuit of environment set memory of motherboard and remove control circuit and remove the method for environment set memory.
(2) background technology
The motherboard of computer system has environment set memory, and the environment of operation when it uses in order to store start is set, for example peripheral pattern and its address and the power-supply management system etc. of being equipped with.In order to make computing machine behind powered-down, when the machine of reopening, still can keep original environment of operation and set, and its setting value that can not run off.Usually the back-up source of meeting after utilizing battery that computer shutdown is provided on the motherboard runs off with the environment of operation setting value of avoiding being stored in the environment set memory.On the other hand, when the user wants to remove environment of operation setting value in the environment set memory, to allow basic input/output (the BasicInput/Output System of motherboard, below be generally called BIOS) reload default environment of operation setting value, perhaps, when computer down consequently can't be started shooting again, also by removing environment set memory, with start again.
And the method for tradition removing environment set memory is, utilizes one to remove circuit to remove environment set memory.Remove circuit and be mode, change the power pin of environment set memory into ground connection, so that the environment set memory discharge is removed its environment of operation setting value with this with wire jumper.So when user's desire was removed environment set memory, necessary first powered-down after opening casing again and finding out corresponding wire jumper circuit, could be removed environment set memory, this kind design is very trouble and inconvenience concerning the user who is ignorant of computing machine.
(3) summary of the invention
In view of this, purpose of the present invention will address the above problem exactly, and a kind of computer system is provided, and allows the user with simpler and mode easily, removes the computer system of environment set memory and removes control circuit and remove the method for environment set memory
The object of the present invention is achieved like this: a kind of computer system, it comprises power switch, reset switch, environment set memory and removing control circuit.When power switch is when being triggered, power switch is in order to open computer system.When reset switch is when being triggered, reset switch is in order to the replacement computer system.Environment set memory is in order to the environment of operation setting value that stores computer system and has power supply supply pin.Remove control circuit and connect power switch, reset switch and power supply supply pin.When power switch and reset switch are when being triggered simultaneously, remove control circuit and supply pin with power supply and be connected to ground voltage, to remove the environment of operation setting value of environment set memory.
Another object of the present invention is achieved in that the removing control circuit that proposes a kind of computer system.Computer system has power switch, reset switch and environment set memory.Environment set memory is in order to the environment of operation setting value that stores computer system and have power supply supply pin.Remove control circuit and comprise first switch, second switch, the 3rd switch, the 4th switch and voltage lifting circuit.One end of first switch connects positive voltage, and the other end of first switch connects power supply supply pin, and the control end of first switch is connected to a node.This node is to connect positive voltage.One end of second switch connects power supply supply pin, and the other end of second switch connects first fixed voltage, and the control end of second switch is connected to node.One end of the 3rd switch is connected to node, and the other end of the 3rd switch connects one second fixed voltage, and the control end of the 3rd switch connects power switch.One end of the 4th switch is connected to node, and the other end of the 4th switch connects one the 3rd fixed voltage, and the control end of the 4th switch connects reset switch.
Voltage lifting circuit is the control end and the control end of the 4th switch that connects the 3rd switch, and when power switch and reset switch are when not being triggered, voltage lifting circuit usefulness is so that the 3rd switch and the 4th switch conduction.When power switch and reset switch are when being triggered simultaneously, remove the environment of operation setting value that control circuit is removed environment set memory.
A further object of the present invention is achieved in that a kind of method of removing environment set memory of computer system, it is characterized in that described computer system has a power switch, a reset switch and environment set memory, described sweep-out method comprises: described environment set memory stores an environment of operation setting value of described computer system; And after described power switch and described reset switch are triggered simultaneously, remove described environment of operation setting value.
Effect of the present invention:
Under traditional design practice, when user's desire was removed environment set memory, necessary first powered-down was after opening casing again and finding out corresponding wire jumper circuit, the corresponding jumper switch (JUMP) of plug changes ground connection into the power pin with environment set memory, could remove environment set memory.This kind design is concerning the user who is ignorant of computing machine, and very trouble is with inconvenient.
In order to solve the operational inconvenience of user, the method of computer system provided by the invention and removing control circuit thereof and removing environment set memory, can be when triggering power switch on the computer system and reset switch simultaneously, remove the environment of operation setting value of environment set memory, allow the user will be more simple in operation with conveniently.
Computer system of the present invention can be under the operating function that does not influence former power switch and reset switch, simplify the step of removing environment set memory, allow the user no longer in order to remove the environment setting of environment set memory, also must open the casing of computer system, after finding out corresponding wire jumper circuit, the jumper switch that plug is corresponding, the inconvenience that could remove environment set memory.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below especially exemplified by an embodiment, and conjunction with figs., elaborate.
(4) description of drawings
Fig. 1 is the calcspar of a kind of computer system architecture of one embodiment of the invention.
Fig. 2 is the circuit diagram of an embodiment of computer system.
The symbol description of primary clustering in the accompanying drawing:
100: computer system 102: environment set memory
104: power supply circuit 106: remove control circuit
108: voltage lifting circuit 110: motherboard
JUMP: wire jumper PS: power switch
RS: reset switch R1, R2, R3, R4, R5: resistance
S1, S2, S3, S4, S5, S6: switch D1, D2: diode
(5) embodiment
Below, with reference to the accompanying drawings, computer system of the present invention and the embodiment removing control circuit and remove the method for environment set memory thereof are elaborated.
Please refer to Fig. 1, it illustrates the calcspar according to a kind of computer system architecture of one embodiment of the invention.Computer system 100 is desktop PC, Barebone or mobile computer for example.Computer system 100 comprises power switch PS, reset switch RS, environment set memory 102 and removes control circuit 106.When power switch PS was triggered, power switch PS was in order to open computer system 100.When reset switch RS was triggered, reset switch RS was in order to replacement computer system 100.Environment set memory 102 is the environment of operation setting values in order to the storage computer system, and has power supply supply pin BATT.The environment of operation setting value for example is BIOS, peripheral pattern and its address and the power-supply management system etc. of being equipped with.Remove control circuit 106 in order to after power switch PS and reset switch RS are triggered simultaneously, supply pin BATT with power supply and be connected to ground voltage, with the environment of operation setting value of removing environment set memory 102.
Furthermore, computer system 100 for example more comprise main frame pull 110 with power supply circuit 104.Environment set memory 102 for example is CMOS RAM, and environment set memory 102, power supply circuit 104 and removing control circuit 106 are together to be disposed on the motherboard 110.Please refer to Fig. 2, it is the circuit diagram of an example of computer system.Power supply circuit 104 is in order to provide environment set memory 102 required power supply, for example positive voltage V1 and V2.Power supply circuit 104 comprises input end IN, the first output terminal OUT1, the second output terminal OUT2, battery BA, diode D1 and D2 and wire jumper JUMP.
Wherein, the positive voltage V3 that input end IN is received for example is (power supply unit is not plotted among Fig. 2) that power supply unit provided in the computer system.After computer system 100 shutdown, the positive voltage V1 that the first output terminal OUT1 is exported and the second output terminal OUT2 export positive voltage V2 just to be provided by battery BA.
Removing control circuit 106 is to comprise first switch S 1, second switch S2, the 3rd switch S 3, the 4th switch S 4 and voltage lifting circuit 108.First switch S 1 for example realizes with PMOS.One end of first switch S 1 is source electrode and the first output terminal OUT1 that connects power supply circuit 104.The other end of first switch S 1 is the power supply supply pin BATT of drain electrode and JA(junction ambient) set memory 102.The control end of first switch S 1 is grid and is connected to a node N.Node N is the second output terminal OUT2 that is connected to power supply circuit 104, and node N for example can be connected to the second output terminal OUT2 via a resistance R 5.
Second switch S2 for example realizes with NMOS, the end of second switch S2 is the power supply supply pin position BATT of drain electrode and JA(junction ambient) set memory 102, the other end of second switch S2 is source electrode and connects one first fixed voltage, first fixed voltage for example is a ground voltage, and the control end of second switch S2 is grid and is connected to node N.
The 3rd switch S 3 and the 4th switch S 4 for example realize with NMOS that an end of the 3rd switch S 3 and an end of the 4th switch are for drain electrode and all be connected to node N.The other end of the 3rd switch S 3 is source electrode with the other end of the 4th switch S 4 and is connected second fixed voltage and the 3rd fixed voltage respectively, second fixed voltage and the 3rd fixed voltage for example are ground voltage, and the control end of the 3rd switch S 3 is grid with the control end of the 4th switch S 4 and is connected power switch PS and reset switch RS respectively.
The 5th switch S 5 for example realizes with NMOS that an end of the 5th switch S 5 is drain electrode and the second output terminal OUT2 that is connected to power supply circuit 104.The other end of the 5th switch S 5 is source electrode and the grid that is connected to the 3rd switch S 3 via first resistance R 1.The control end of the 5th switch is for grid and receive the positive voltage that power supply unit provides.One end of the 6th switch S 6 is drain electrode and the second output terminal OUT2 that is connected to power supply circuit 104.The other end of the 6th switch S 6 is source electrode and the grid that is connected to the 4th switch via second resistance R 2.The control end of the 6th switch S 6 is for grid and receive the positive voltage that power supply unit provides.
One end of the 3rd resistance R 3 is connected to the second output terminal OUT2 of power supply circuit 104, and the other end of the 3rd resistance R 3 is connected to the grid of the 3rd switch S 3.One end of the 4th resistance R 4 is connected to the second output terminal OUT2 of power supply circuit 104.The other end of the 4th resistance is connected to the grid of the 4th switch S 4.
Under the situation of normal running, power switch PS and reset switch RS are when not being triggered, cut-off state for example shown in Figure 2.At this moment, switch S 5 and S6 are by positive voltage V3 conducting.Switch S 5 is during with the S6 conducting, and the positive voltage V2 that the second output terminal OUT2 is exported is just via as shown in Figure 2 path route1, route2, and the control end of keeping switch S 3 and S4 is a noble potential, so that switch S 3 and S4 conducting.When switch S 3 during with the S4 conducting, the positive voltage V2 that the second output terminal OUT2 is exported just via switch S 3 and S4 to ground voltage, making node N is electronegative potential.When node N is electronegative potential, switch S 1 (for PMOS) is switched on, and switch S 2 (for NMOS) is cut off, make positive voltage V1 that the output terminal OUT1 that wins exported via switch S 1 to power supply supply pin BATT, to provide environment set memory 102 required operating voltage.
As described in preface, trigger the power switch PS and reset switch RS on the computer system 100 simultaneously after, just remove the environment of operation setting value that control circuit 106 is removed environment set memory 102, and remove the explanation of control circuit 106 principle of work as after.
Behind computer shutdown, after triggering the power switch PS and reset switch RS on the computer system 100 simultaneously, for example power switch PS and reset switch RS are pressed simultaneously, the control end of the 3rd switch S 3 and the 4th switch S 4 is connected to ground voltage, and the 3rd switch S 3 and the 4th switch S 4 are cut off.After the 3rd switch S 3 and the 4th switch S 4 were cut off, it was noble potential that the positive voltage V2 that the second output terminal OUT2 is exported makes node N via resistance R 5.The node N of noble potential ends first switch S 1, and with second switch S2 conducting.When second switch S2 conducting, power supply supply pin BATT just is connected to ground voltage via second switch S2, so that environment set memory 102 discharges are removed its environment of operation setting value with this.
And after power switch PS and reset switch RS pressed simultaneously, power switch PS and reset switch RS promptly were returned to the cut-off state when not being triggered.When power switch PS and reset switch RS are returned to cut-off state, two control ends that voltage lifting circuit 108 is just kept switch S 3 and S4 are noble potential, so that 1 conducting of first switch S, positive voltage V1 just offers the required operating voltage of environment set memory 102 via first switch S 1 again.
When power switch PS and reset switch RS have only arbitrary one when being triggered, its pairing the 3rd switch S 3 and the 4th switch S 4 also have only one to be cut off.When for example pressing power switch PS with startup computer system 100, its pairing the 3rd switch S 3 is ended by of short duration.Yet after pressing, power switch PS is returned to cut-off state (state that is not triggered) immediately, though its pairing the 3rd switch S 3 is ended by of short duration, the 4th switch is still kept conducting, makes that the voltage on the node N still is electronegative potential.So any one during by conducting in 4, two of the 3rd switch S 3 and the 4th switch S, the voltage on the node N still can be kept electronegative potential, so that positive voltage V1 continues to offer the required power supply of environment set memory 102 via first switch S 1, to keep normal running.
In addition, the removing control circuit 106 of present embodiment is set up outside environment set memory 102, also can be with in the control chip of removing in the motherboard 110 that control circuit 106 be integrated in computer system 100, control chip is south bridge control chip (south bridge control chip is not plotted among Fig. 2) for example.So the present invention only needs slightly to change the configuration of motherboard 110, existing motherboard 110 can be become to have the advantage of removing environment set memory 102 simply.In addition, positive voltage V1, V2 and V3 also can be provided by other circuit, be to be example in present embodiment with power supply circuit 104, but in the present invention, do not limit positive voltage V1, V2 and V3 be provided why provide the source, remove control circuit 106 and keep normal running as long as can make with environment set memory 102.And the switch S 1-S6 in the present embodiment more can reach the mode of operation of above-mentioned switch S 1-S6 by other transistorized logical combination.
Those of ordinary skill in the art will be appreciated that, above embodiment is used for illustrating the present invention, and be not to be used as limitation of the invention, as long as in connotation scope of the present invention, all will drop in the scope of claims of the present invention variation, the modification of the above embodiment.
Claims (9)
1. computer system is characterized in that comprising:
One power switch, when described power switch was triggered, described power switch was in order to open computer system;
One reset switch, when reset switch was triggered, described reset switch was in order to the replacement computer system;
One environment set memory is in order to storing an environment of operation setting value of described computer system, and described environment set memory has power supply supply pin; And
One removes control circuit, connect described power switch, reset switch and described power supply supply pin, when described power switch and described reset switch were triggered simultaneously, described removing control circuit was connected to ground voltage with described power supply supply pin.
2. computer system as claimed in claim 1 is characterized in that described computer system also comprises a power supply circuit, and in order to provide described environment set memory required power supply, described power supply circuit comprises:
One input end is in order to receive a positive voltage;
One first output terminal is connected with described removing control circuit, and described power supply circuit is optionally exported described positive voltage in described first output terminal by the wire jumper mode of wire jumper; And
One second output terminal is connected with described removing control circuit, in order to export described positive voltage.
3. computer system as claimed in claim 2 is characterized in that described removing control circuit comprises:
One first switch, one end of first switch connects first output terminal of described power supply circuit, the other end of described first switch connects described power supply supply pin, the control end of described first switch is connected to a node, and described node is second output terminal that is connected to described power supply circuit;
One second switch, an end of second switch connect described power supply supply pin, and the other end of described second switch connects one first fixed voltage, and the control end of described second switch is connected to described node;
One the 3rd switch, an end of the 3rd switch is connected to described node, and the other end of described the 3rd switch connects one second fixed voltage, and the control end of described the 3rd switch connects described power switch;
One the 4th switch, an end of the 4th switch is connected to described node, and the other end of described the 4th switch connects one the 3rd fixed voltage, and the control end of described the 4th switch connects described reset switch; And
One voltage lifting circuit, be to connect the control end of described the 3rd switch and the control end of described the 4th switch, when described power switch and described reset switch were not triggered, described voltage lifting circuit was with so that described the 3rd switch and the 4th switch conduction.
4. computer system as claimed in claim 3 is characterized in that described voltage lifting circuit comprises:
One the 5th switch, one end of the 5th switch is connected to second output terminal of described power supply circuit, the other end of described the 5th switch is connected to the grid of described the 3rd switch via one first resistance, and the control end of described the 5th switch receives described positive voltage;
One the 6th switch, an end of the 6th switch is connected to second output terminal of described power supply circuit, and the other end of described the 6th switch is connected to the grid of the 4th switch via one second resistance, and the control end of described the 6th switch receives described positive voltage;
One the 3rd resistance, an end of the 3rd resistance is connected to second output terminal of described power supply circuit, and the other end of described the 3rd resistance is connected to the control end of described the 3rd switch; And
One the 4th resistance, an end of the 4th resistance is connected to second output terminal of described power supply circuit, and the other end of described the 4th resistance is connected to the control end of described the 4th switch.
5. computer system as claimed in claim 4 is characterized in that described first switch, second switch, the 3rd switch, the 4th switch, the 5th switch and the 6th switch comprise at least one MOS transistor respectively.
6. the removing control circuit of a computer system, it is characterized in that described computer system has a power switch, a reset switch and an environment set memory, when described power switch is triggered, described power switch is in order to open this computer system, when described reset switch is triggered, described reset switch is in order to this computer system of resetting, described environment set memory is in order to the environment of operation setting value that stores described computer system and have power supply supply pin, and described removing control circuit comprises:
One first switch, an end of first switch connects a positive voltage, and the other end of described first switch connects described power supply supply pin, and the control end of described first switch is connected to a node, and described node is to connect described positive voltage;
One second switch, an end of second switch connect described power supply supply pin, and the other end of described second switch connects one first fixed voltage, and the control end of described second switch is connected to described node;
One the 3rd switch, an end of the 3rd switch is connected to described node, and the other end of described the 3rd switch connects one second fixed voltage, and the control end of described the 3rd switch connects described power switch;
One the 4th switch, an end of the 4th switch is connected to described node, and the other end of described the 4th switch connects one the 3rd fixed voltage, and the control end of described the 4th switch connects described reset switch; And
One voltage lifting circuit, be to connect the control end of described the 3rd switch and the control end of described the 4th switch, when described power switch and reset switch were not triggered, described voltage lifting circuit was with so that described the 3rd switch and the 4th switch conduction;
Wherein, when described power switch and reset switch were triggered simultaneously, described removing control circuit was removed the environment of operation setting value of described environment set memory.
7. the removing control circuit of computer system as claimed in claim 6 is characterized in that described voltage lifting circuit comprises:
One the 5th switch, an end of the 5th switch connects described positive voltage, and the other end of described the 5th switch is connected to the grid of described the 3rd switch via one first resistance, and the control end of described the 5th switch receives described positive voltage;
One the 6th switch, an end of the 6th switch connects described positive voltage, and the other end of described the 6th switch is connected to the grid of described the 4th switch via one second resistance, and the control end of described the 6th switch receives described positive voltage;
One the 3rd resistance, an end of the 3rd resistance is connected to described positive voltage, and the other end of described the 3rd resistance is connected to the control end of described the 3rd switch; And
One the 4th resistance, an end of the 4th resistance is connected to described positive voltage, and the other end of described the 4th resistance is connected to the control end of described the 4th switch.
8. the removing control circuit of computer system as claimed in claim 7 is characterized in that described first switch, second switch, the 3rd switch, the 4th switch, the 5th switch and the 6th switch comprise at least one MOS transistor respectively.
9. the method for the removing environment set memory of a computer system is characterized in that described computer system has a power switch, a reset switch and environment set memory, and described sweep-out method comprises:
Described environment set memory stores an environment of operation setting value of described computer system; And
After described power switch and described reset switch are triggered simultaneously, remove described environment of operation setting value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100543969A CN100361049C (en) | 2005-03-08 | 2005-03-08 | Computer system and method for clearing control circuit and environment set memory |
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| CNB2005100543969A CN100361049C (en) | 2005-03-08 | 2005-03-08 | Computer system and method for clearing control circuit and environment set memory |
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| Publication Number | Publication Date |
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| CN1831716A true CN1831716A (en) | 2006-09-13 |
| CN100361049C CN100361049C (en) | 2008-01-09 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104908644A (en) * | 2015-05-26 | 2015-09-16 | 北京智视信息科技有限公司 | Monitoring method for remote vehicle networking vehicles |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI464746B (en) * | 2012-03-30 | 2014-12-11 | Wistron Corp | A clearing circuit for memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW269038B (en) * | 1993-02-05 | 1996-01-21 | Micron Technology Inc | |
| JPH07143619A (en) * | 1993-11-15 | 1995-06-02 | Toshiba Corp | Load control system |
| US5987601A (en) * | 1997-02-14 | 1999-11-16 | Xyron Corporation | Zero overhead computer interrupts with task switching |
| CN1245673C (en) * | 2002-07-03 | 2006-03-15 | 威盛电子股份有限公司 | Circuit for detecting memory clear operation for settings about computer motherboard and environment and clear method |
| US20040059848A1 (en) * | 2002-09-23 | 2004-03-25 | Institute For Information Industry | Device for automatically switching endian order |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104908644A (en) * | 2015-05-26 | 2015-09-16 | 北京智视信息科技有限公司 | Monitoring method for remote vehicle networking vehicles |
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