CN1831586A - Display device and glass substrate using therefor - Google Patents
Display device and glass substrate using therefor Download PDFInfo
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- CN1831586A CN1831586A CN 200510055324 CN200510055324A CN1831586A CN 1831586 A CN1831586 A CN 1831586A CN 200510055324 CN200510055324 CN 200510055324 CN 200510055324 A CN200510055324 A CN 200510055324A CN 1831586 A CN1831586 A CN 1831586A
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Abstract
The invention relates to a display device, wherein the first to fourth gate driver ICs G 1 to G 4 to be connected to a gate line 18 of a drive element 21 are arranged along a side of a liquid crystal display 2. Along a side of the first to four gate driver ICs G 1 to G 4, a FPC 5 for receiving signals is arranged. A first bus line 15 that branches between the first and second gate driver ICs G 1 and G 2 connects gate-low terminals 11 b and 11 a of the first and second gate driver ICs G 1 and G 2, respectively, to the FPC 5 . A second bus line 16 that branches between the third and fourth gate driver ICs G 3 and G 4 connects gate-low terminals 11 b and 11 a of the third and fourth gate driver ICs G 3 and G 4 , respectively, to the FPC 5 . Gate-high terminals 10 b and 10 a, logic terminals 12 b and 12 a, and signal terminals 13 of the second and third gate driver ICs G 2 and G 3 are connected to the FPC 5. Gate-high terminals 10 a and 10 b, logic terminals 12 a and 12 b, and signal terminals 13 of the first and fourth gate driver ICs G 1 and G 4 are connected to corresponding terminals of the second and third gate driver ICs G 2 and G 3.
Description
The cross reference of related application
The application is based on the 2004-072015 Japanese patent application of application on March 15th, 2004 and the 2005-062736 Japanese patent application of application on March 7th, 2005, and its content is included by reference paper at this.
Technical field
The present invention relates to have the display of driver IC, as LCD, driver IC drives a driving element, and this driving element is that each pixel of display device is provided with.The invention still further relates to a kind of glass substrate, described display device and described driver IC just are installed on this substrate.
Background technology
A kind of conventional liquid crystal is disclosed in Japanese patent application H5-181153 communique.The driver IC that this LCD has a liquid-crystal display section and forms on glass substrate.On described liquid-crystal display section, comprised the pixel that is formed at common electrode on the glass substrate of opposite, arrange with the form of matrix.Each pixel has been provided a driving element of being made by TFT.Each driving element is all supplied to have the signal from driver IC.
Fig. 4 is a planimetric map, the wiring situation of expression LCD.LCD 1 has first to the 4th gate drivers IC G1 to G4, aligns in a kind of like this mode in a side in the face of liquid-crystal display section 2.Because it is higher that the trend of LCD is that resolution becomes gradually, so used four driver ICs.
First to fourth gate drivers IC G1 to G4 by the downward bonding wire in surface on glass substrate 3, and thereby be set in COG (chip on glass) system.First to fourth gate drivers IC G1 presents a high level or low level signal to G4, and this signal is provided for the grid of each driving element.
A plurality of source class driver IC S1 to Sn align in this mode in the face of a side of liquid-crystal display section 2, and to face first to the 4th gate drivers IC G1 adjacent to the side of G4 with that in this side.Source class driver IC S1 to Sn presents a picture signal, and this picture signal is provided for the source electrode of each driving element.
Each all has first to fourth gate drivers IC G1 to G4: the entry terminal 10a and the 10b (being called " grid high level terminal " hereinafter) that are used to offer the high level signal of driving element grid; Be used to offer the entry terminal 11a and the 11b (being called " grid low level terminal " hereinafter) of the low level signal of driving element grid; Be used for entry terminal 12a and the 12b of first to fourth gate drivers IC G1 to the driving source electrode of G4; With a Signal Terminal 13 that is used to receive the scanning timing signal.
These terminals are arranged symmetrically that along its center line center line is perpendicular to the alignment direction (hereinafter be called " column direction ") of first to fourth gate drivers IC G1 to G4.This allows link position to change to the position that G4 arranges according to first to fourth gate drivers IC G1.Like this, first to fourth gate drivers IC G1 can use a shared encapsulation to G4.
To such an extent as to being connected to first to fourth gate drivers IC G1 is formed it like this to the conductor 14a of the grid low level terminal 11a of G4 and 11b and is extended to FPC5 with the direction that is basically perpendicular to described column direction.This allows conductor 14a to form the shortest and identical length, thereby has reduced impedance, and the balanced voltage drop that is caused by impedance.
In like manner, to such an extent as to the conductor 14 that is connected to other terminal that receives the same type signal is formed it like this has from the identical distance of FPC5 and have identical length.Identical configuration is applicable to the conductor of the source class driver IC S1 to Sn on source electrode one side.This has reduced the voltage drop in the conductor 14, and the voltage presented of also balanced conductor 14, therefore provides good sharpness for LCD 1.
Yet, utilizing above-mentioned conventional liquid crystal 1, conductor 14 extends with the direction that is basically perpendicular to column direction from terminal separately, and the width A of FPC5 becomes big at column direction like this.This causes large-sized liquid-crystal apparatus 1, makes it be difficult to effectively utilize that in the FPC both sides space of any side on the column direction, and the device size that causes LCD is installed thereon increases.
Summary of the invention
A target of the present invention is for providing a kind of display and a kind of glass substrate that is used for display, and this display can make device size dwindle.
For obtaining above-mentioned target, in one aspect of the invention, a display comprises: a substrate; A display part, the pixel that wherein has driving element is arranged with matrix form on substrate; First to fourth driver IC, they are installed into like this, promptly sequentially arrange along the side alignment of display part on the base, and remove to drive those driving elements; And be connected to substrate, and receive the wiring lines parts that offer first to fourth driver IC.First and second driver ICs all have the first signal entry terminal, and it can receive same signal, and are oriented to face one another.What form on substrate is: first bus line, its first signal entry terminal with first and second driver ICs links together, and between first and second driver IC branch so that be connected to described wiring part; And second bus line that the first signal entry terminal of third and fourth driver IC is linked together, and between the 3rd and the 4th driver IC branch so that be connected to described wiring part.
In another aspect of the present invention, the part below the glass substrate that is used for display has comprised: the display device zone, be arranged with the display device of pixel thereon, pixel comprises driving element and arranges with matrix form; First to fourth driver region, be arranged a side alignment to such an extent as to be used to drive first to fourth driver IC of these driving elements thereon along described display device zone, the first signal entry terminal that first and second driver region have is oriented to face each other, and the first signal entry terminal that third and fourth driver region has is oriented to face each other; A wiring part zone, it is connected to a wiring part, and this wiring part receives the signal that offers first to fourth driver IC; One first bus line, its first signal entry terminal with first and second driver region links together, and between first and second driver region branch so that can be connected to described wiring part zone; And second bus line, its first signal entry terminal with the 3rd and the 4th driver region links together, and between the 3rd and the 4th driver region branch so that be connected to the wiring part zone.
Description of drawings
Fig. 1 is the side cross-sectional views that shows the LCD of one embodiment of the invention;
Fig. 2 is the circuit diagram that shows the liquid-crystal display section of this embodiment LCD;
Fig. 3 is the planimetric map that shows this embodiment LCD; With
Fig. 4 is the planimetric map that shows conventional liquid crystal.
Embodiment
Below with reference to the accompanying drawings embodiments of the invention are described.Describe for simplifying, indicate by same numbers with those parts of above-mentioned Fig. 4 equivalence.Fig. 1 is the side cross-sectional views that shows the LCD of one embodiment of the invention.LCD 1 has liquid-crystal display section 2, and its on the display device zone of glass substrate 3 (not marking) is provided.Between the glass substrate 3 and 4 that is arranged opposite to each other, formed liquid crystal cells, liquid crystal 7 is sealed in the liquid crystal cells.Polarising sheet 25 is set at respectively on the outside surface of glass substrate 3 and 4.
On glass substrate 3, arrange with matrix form with pixel electrode 22 by the driving element 21 that TFT forms.On glass substrate 4, common electrode 23 is provided, make it in the face of pixel electrode 22.As a result, pixel is to form and arrange with matrix form.
Fig. 2 is the circuit diagram of this liquid-crystal display section 2.The drain electrode of each driving element 21 is connected on the electric capacity of liquid crystal 7 and keeps electric capacity 8.The source electrode of each driving element 21 has been connected to first to fourth source class driver IC S1 to the S4 (see figure 3) by source electrode line 17, and the mode of their alignment is a side in the face of liquid-crystal display section 2.The grid of each driving element 21 is connected to first to fourth gate drivers IC G1 to the G4 (see figure 3) by the gate line 18 with source electrode line 17 quadratures, and the mode of their alignment is another side in the face of liquid-crystal display section 2.
First to fourth gate drivers IC G1 provides high level or low level signal to G4 for the grid of each driving element 21.First to fourth source class driver IC S, 1 to the S4 source electrode for each driving element 21 provides picture signal.When the grid of driving element 21 uprised, driving element 21 became and can conduct electricity, and picture signal is written in the electric capacity of liquid crystal 7 like this.
Fig. 3 is a planimetric map of LCD 1.First to fourth gate drivers IC G1 is connected respectively to first to fourth gate drivers zone (not marking) and first to fourth source class driver region on the glass substrate 3 to G4 and first to fourth source class driver IC S1 to S4 by the downward bonding wire in surface, and thereby is set in the COG system.First to fourth gate drivers IC G1 is sequentially alignd on column direction to G4, with towards liquid-crystal display section 2.First to fourth source class driver IC S1 to S4 sequentially on perpendicular to the direction of column direction alignment arrange (being called " line direction " hereinafter), with towards liquid-crystal display section 2.
Each has grid high level terminal 10a and 10b to first to fourth gate drivers IC G1 to G4, grid low level terminal 11a and 11b (the first signal entry terminal), logical terminal (LTERM) 12a and 12b (the 3rd signal entry terminal); With Signal Terminal 13 (secondary signal entry terminal).These terminals be arranged in symmetrically with first to fourth gate drivers IC G1 to perpendicular center line both sides of row that G4 aligns and arranges.This allows to select link position according to the arrangement of first to fourth gate drivers IC G1 to G4, and thereby allows for first to fourth gate drivers ICG1 to the shared encapsulation of G4 use.
Grid high level terminal 10a and 10b, be aligned to two row with grid low level terminal 11a and 11b, grid high level terminal 10a and 10b are positioned at first to fourth gate drivers IC G1 to each two ends of G4, and grid low level terminal 11a and 11b are positioned at first to fourth gate drivers IC G1 to each two ends of G4.Signal Terminal 13 is arranged between grid low level terminal 11a and the 11b.Logical terminal (LTERM) 12a is between grid low level terminal 11a and Signal Terminal 13, and logical terminal (LTERM) 12b is between grid low level terminal 11b and Signal Terminal 13.For avoiding the chart complexity, do not provide numeral to the terminal of G4 to second to the 4th gate drivers IC G2.Those be set at first grid driver IC G1 same position on terminal describe with same numeral.
In like manner, second bus line 16 links together the grid low level terminal 11b of the 3rd gate drivers IC G3 and the grid low level terminal 11a of contiguous the 4th gate drivers IC G4.Second bus line 16 formed one at the 3rd and the 4th gate drivers IC G3 to the T-branch between the G4, to be connected to FPC5.This allow FPC5 and the third and fourth gate drivers IC G3 between the grid low level terminal of G4 by using the second single bus line 16 to be connected.
In like manner, the distance L 3 between the grid low level terminal 11b of the take-off point 16b of second bus line 16 and the 3rd gate drivers IC G3 equals the distance L 4 between the grid low level terminal 11a of take-off point 16b and the 4th gate drivers ICG4.Live width between live width between the grid low level terminal 11b of the take-off point 16b of second bus line 16 and the 3rd gate drivers IC G3 and the grid low level terminal 11a of take-off point 16b and the 4th gate drivers IC G4 is identical.Take-off point 16b is identical with distance L 3 and L4 with distance between the FPC5.
The Signal Terminal 13 of second grid driver IC G2 is connected to FPC5 by conductor 31.The Signal Terminal 13 of first grid driver IC G1 is connected to the Signal Terminal 13 of second grid driver IC G2 by conductor 39.To such an extent as to conductor 39 passes through between being formed like this and reaching below first and second gate drivers IC G1 and G2.This allows to prevent the short circuit with first bus line 15, and has also reduced the number of conductors that is connected to FPC5.
In like manner, the logical terminal (LTERM) 12b of second grid driver IC G2 is connected to FPC5 by conductor 33.The logical terminal (LTERM) 12a of first grid driver IC G1 is connected to the logical terminal (LTERM) 12b of second grid driver IC G2 by conductor 37.To such an extent as to conductor 37 passes through between being formed like this and reaching below first and second gate drivers IC G1 and G2.
Further, the grid high level terminal 10b of second grid driver IC G2 is connected to FPC5 by conductor 35.The grid high level terminal 10a of second grid driver IC G1, and the grid high level terminal 10a of first gate drivers IC G1 and 10b are connected to the grid high level terminal 10b of second grid driver IC G2 by conductor 41.To such an extent as to conductor 41 passes through between being formed like this and reaching below first and second gate drivers IC G1 and G2.
Same setting is applicable to the 3rd and the 4th gate drivers IC G3 and G4.Particularly, Signal Terminal 13, the grid high level terminal 10a of logical terminal (LTERM) 12a and the 3rd gate drivers IC G3 is connected to FPC5 by conductor separately.Signal Terminal 13, the grid high level terminal 10a of logical terminal (LTERM) 12b and the 4th gate drivers IC G4 and 10b are connected respectively to Signal Terminal 13, logical terminal (LTERM) 12a and the grid high level terminal 10a of the 3rd gate drivers IC G3 by the conductor that passes through between reaching below the 3rd and the 4th gate drivers IC G3 and G4.
These conductors form in center line Y1-Y1 ' both sides symmetrically, and center line Y1-Y1 ' extends with the direction perpendicular to described column direction from the centre between the second and the 3rd gate drivers IC G2 and the G3.Therefore, the signal that is fed to the signal of the first and second gate drivers IC G1 and G2 and is fed to the 3rd and the 4th gate drivers IC G3 and G4 has identical amount.Therefore, this has prevented from extreme change in voltage to occur at the center of display screen, and this prevents the appearance of image border again successively.
As first to fourth gate drivers IC G1 to G4, each all has source electrode high level terminal 60a and 60b to first to fourth source class driver IC S1 to S4, source electrode low level terminal 61a and 61b (the first signal entry terminal), logical terminal (LTERM) 62a and 62b (the 3rd signal entry terminal), and Signal Terminal 63 (secondary signal entry terminal).These terminals are to arrange symmetrically to the S4 vertical center line of the line direction arranged that aligns with first to fourth source class driver IC S1.This allows to select a link position according to the arrangement of first to fourth source class driver IC S1 to S4, and thereby allows for first to fourth source class driver IC S1 to mutual encapsulation of S4 use.
Source electrode high level terminal 60a and 60b, be aligned to two row with source electrode low level terminal 61a and 61b, source electrode high level terminal 60a and 60b are positioned at first to fourth source class driver IC S1 to each two ends of S4, and source electrode low level terminal 61a and 61b are positioned at first to fourth source class driver IC S1 to each two ends of S4.Signal Terminal 63 is arranged between source electrode low level terminal 61a and the 61b.Logical terminal (LTERM) 62a is between source electrode low level terminal 61a and Signal Terminal 63, and logical terminal (LTERM) 62b is between source electrode low level terminal 61b and Signal Terminal 63.For avoiding the chart complexity, do not provide digital to the terminal of S4 for second to the 4th source class driver IC S2.Those be set at the first source class driver IC S1 same position on terminal use same numbers to describe.
In like manner, second bus line 66 links together the source electrode low level terminal 61b of the 3rd source class driver IC S3 and the source electrode low level terminal 61a of contiguous the 4th source class driver IC S4.Second bus line 66 forms T-branch between the 3rd and the 4th source class driver IC S3 and S4, to be connected to FPC55.This allows, and the second single bus line 66 of use is connected between the grid low level terminal of FPC5 and the third and fourth source class driver IC S1 and S4.
The take-off point 65b place branch of first bus line 65 in the middle of being positioned between first and second source class driver IC S1 and S2.Distance L 5 between the source electrode low level terminal 61b of the take-off point 65b and the first source class driver IC S1 equals the distance L 6 between the source electrode low level terminal 61a of the take-off point 65b and the second source class driver IC S2.Live width between live width between the source electrode low level terminal 61b of take-off point 65b and the first source class driver IC S1 and the source electrode low level terminal 61a of the take-off point 65b and the second source class driver IC S2 is identical.Distance between take-off point 65b and FPC55 equals distance L 5 and L6.
In like manner, the distance L 8 that equals between the source electrode low level terminal 61a of take-off point 66b and the 4th source class driver IC S4 of the distance L 7 between the source electrode low level terminal 61b of the take-off point 66b of second bus line 66 and the 3rd source class driver IC S3 is identical.Live width between live width between the source electrode low level terminal 61b of the take-off point 66b of second bus line 66 and the 3rd source class driver IC S3 and the source electrode low level terminal 61a of take-off point 66b and the 4th source class driver IC S4 is identical.Distance between take-off point 66b and FPC55 equals distance L 7 and L8.
The Signal Terminal 63 of the second source class driver IC S2 is connected to FPC55 by conductor 81.The Signal Terminal 63 of the first source class driver IC S1 is connected to the Signal Terminal 63 of the second source class driver IC S2 by conductor 89.To such an extent as to conductor 89 passes through between being formed like this and reaching below first and second source class driver IC S1 and S2.This allows to prevent the short circuit with first bus line 65, and has also reduced the number of conductors that is connected to FPC55.
In like manner, the logical terminal (LTERM) 62b of the second source class driver IC S2 is connected to FPC55 by conductor 83.The logical terminal (LTERM) 62a of the first source class driver IC S1 is connected to the logical terminal (LTERM) 62b of the second source class driver IC S2 by conductor 87.To such an extent as to conductor 87 passes through between being formed like this and reaching below first and second source class driver IC S1 and S2.
Further, the source electrode high level terminal 60b of the second source class driver IC S2 is connected to FPC55 by conductor 85.The source electrode high level terminal 60a of the source electrode high level terminal 60a of the second source class driver IC S1 and the first source class driver IC S1 and 60b are connected to the source electrode high level terminal 60b of the second source class driver IC G2 by conductor 91.To such an extent as to conductor 91 passes through between being formed like this and reaching below first and second source class driver IC S1 and S2.
The same setting is applicable to the 3rd and the 4th source class driver IC S3 and S4.Particularly, Signal Terminal 63, the source electrode high level terminal 60a of logical terminal (LTERM) 62a and the 3rd source class driver IC S3 is connected to FPC55 by conductor separately.Signal Terminal 63, the source electrode high level terminal 60a of logical terminal (LTERM) 62b and the 4th source class driver IC S4 and 60b are connected to Signal Terminal 63, logical terminal (LTERM) 62a and the source electrode high level terminal 60a of the 3rd source class driver IC S3 respectively by the conductor that passes through between reaching below the 3rd and the 4th source class driver IC S3 and S4.
These conductors form in center line X1-X1 ' both sides symmetrically, and center line X1-X1 ' extends from the centre between the second and the 3rd source class driver IC S2 and the S3 with the direction perpendicular to described line direction.Therefore, be fed to the signal of the first and second source class driver IC S1 and S2 and be fed to the 3rd and have identical magnitude with the signal of the 4th source class driver IC S3 and S4.Therefore, this has prevented from extreme change in voltage to occur at the center of display screen, and it has prevented the appearance of image border again successively.
Utilize the LCD 1 of above-mentioned structure, first and second bus line 15 and 16, and first and second bus line 65 and 66 balances enter into the input of grid low level terminal and source electrode low level terminal.This allows to reduce the quantity of the conductor 14 that is connected to FPC5 and 55.Thereby FPC5 and 55 width A and B (see figure 3) can be lowered separately, dwindle so that therefore obtain the size of LCD 1.
Because distance L 1 has identical value with L2, the voltage drop between the grid low level terminal 11a that equals FPC5 and second grid driver IC G2 that becomes of the voltage drop between the grid low level terminal 11b of FPC5 and first grid driver IC G1.Therefore, the variation of the low level voltage of being presented by first and second gate drivers IC G1 and G2 will diminish, thereby the display screen with coherent image quality is provided.
Because distance L 3 has identical value with L4, the voltage drop between the grid low level terminal 11a that equals FPC5 and the 4th gate drivers IC G4 that becomes of the voltage drop between the grid low level terminal 11b of FPC5 and the 3rd gate drivers IC G3.Therefore, the variation of the low level voltage of being presented by the 3rd and the 4th gate drivers IC G3 and G4 will diminish, thereby the display screen with coherent image quality is provided.
Because distance L 5 has identical value with L6, the voltage drop between the source electrode low level terminal 61a that equals the FPC55 and the second source class driver IC S2 that becomes of the voltage drop between the source electrode low level terminal 61b of the FPC55 and the first source class driver IC S1.Therefore, the variation of the low level voltage of being presented by first and second source class driver IC S1 and S2 will diminish, thereby the display screen with coherent image quality is provided.
Because distance L 7 has identical value with L8, the voltage drop between the source electrode low level terminal 61a that equals FPC55 and the 4th source class driver IC S4 that becomes of the voltage drop between the source electrode low level terminal 61b of FPC55 and the 3rd source class driver IC S3.Therefore, the variation of the low level voltage of being presented by the 3rd and the 4th source class driver IC S3 and S4 will diminish, thereby the display screen with coherent image quality is provided.
First and second bus line 15 and 16 is arranged symmetrically with center line Y1-Y1 '.Like this, be fed to first to fourth gate drivers IC G1 and become balanced, thereby offer more uniform images quality of display screen to the voltage drop of the grid low level terminal of G4.In like manner, first and second bus line 65 and 66 is arranged symmetrically with center line X1-X1 '.Like this, be fed to first to fourth source class driver IC S1 and become balanced, thereby offer more uniform images quality of display screen to the voltage drop of the source electrode low level terminal of S4.In this respect, can be balanced to the connection of grid low level terminal, to prevent the degeneration of picture quality, wherein supplying voltage in variation to the influence of picture quality than in grid high level terminal, observed influence wants big in logical terminal (LTERM) and the Signal Terminal.
Table 1 shown FPC5 and separately the resistance value between the conductor (unit: measurement result Ω), these conductors are connected to grid high level terminal, grid low level terminal, logical terminal (LTERM) and the first to fourth gate drivers IC G1 Signal Terminal to G4.These results show the equalizing resistance value of conductor that is connected respectively to grid low level terminal by first and second bus line 15 and 16 by equilibrium, so the voltage that allows to be fed to grid low level terminal remains unchanged.This is equally applicable to first to fourth source class driver IC S1 to S4.
(table 1 vides infra)
Table 1
| IC | Terminal | |||
| The grid height | Grid is low | Logic | Signal | |
| G1 G2 G3 G4 | 88.6 14.3 14.3 88.6 | 72.1 72.1 72.1 72.1 | 314.2 13.3 13.1 314.2 | 367.7 91.6 91.8 368.5 |
Unit: Ω
The signal that is fed to these terminals is standing voltage drop in the driver IC separately.Because first bus line 15 connects together first and second gate drivers IC G1 and G2, simultaneously second bus line 16 connects together the 3rd and the 4th gate drivers IC G3 and G4, second with the 3rd gate drivers IC G2 and G3 in be subjected to the signal of voltage drop be provided to screen center near.But because the grid low level terminal of the second and the 3rd gate drivers IC G2 and G3 receives the voltage of equal value, violent voltage drop can not occur near the screen center, has prevented the generation of deteriroation of image quality like this, as edge line occurs on screen.
In like manner, because first bus line 65 connects together first and second source class driver IC S1 and S2, simultaneously second bus line 66 connects together the 3rd and the 4th source class driver IC S3 and S4, in the second and the 3rd source class driver IC S2 and S3, be subjected to the signal of voltage drop be provided to screen center near.But, because the source electrode low level terminal of the second and the 3rd source class driver IC S2 and S3 receives the voltage of equal value, violent voltage drop can not occur in screen center near, just prevented the generation of deteriroation of image quality like this, as edge line on screen, occurring.
Gate drivers IC does not handle picture signal; Therefore even when the resistance value of its conductor during greater than the resistance value of the conductor of source electrode one side, they also can not disturb the work of LCD 1.Like this, if the resistance value of these conductors can be lowered, as in the present embodiment, so the conductor that is connected to the grid low level terminal of G4 with first to fourth gate drivers IC G1 with can be balanced to the conductor that the source electrode low level terminal of S4 is connected with first to fourth source class driver IC S1.If because some factors, as the material of conductor, it is big that these resistance values become, and has only so with first to fourth gate drivers IC G1 can be balanced to the conductor that the grid low level terminal of G4 is connected.
First grid driver IC G1 passes through to the connection of second grid driver IC G2 and is connected to FPC5, and the 4th gate drivers G4 passes through to the connection of the 3rd gate drivers IC G3 and be connected to FPC5.The first source class driver IC S1 passes through to the connection of the second source class driver IC S2 and is connected to FPC55, and the 4th source class driver IC S4 passes through to the connection of the 3rd source class driver IC S3 and is connected to FPC55.This has reduced the quantity of the conductor 14 that is connected to FPC5 and 55 respectively.
Can be formed between first and second bus line 15 and 16 to each conductor 14 between G4 at FPC5 and first to fourth gate drivers IC G1.Can be formed between first and second bus line 65 and 66 to each conductor between S4 at FPC55 and first to fourth source class driver IC S1.Like this, FPC5 and 55 width A and B separately can be lowered, thereby the size that obtains LCD 1 is dwindled.
To between G4 and the FPC5, see as plane surveying that at first to fourth gate drivers IC G1 first and second bus line 15 and 16 has parallel portion 15a and 16a separately, this is being parallel to column direction setting, and thereby is in alignment with each other.To between S4 and the FPC55, see as plane surveying that at first to fourth source class driver IC S1 first and second bus line 65 has parallel part 65a and 66a separately with 66, this is being parallel to line direction setting, thereby is in alignment with each other.
On the other hand, connect FPC5 and Signal Terminal respectively, the conductor (31,33 of logical terminal (LTERM) and grid high level terminal, 35) be connected FPC55 and Signal Terminal respectively, the conductor of logical terminal (LTERM) and grid high level terminal (81,83,85), can both be to be seen as plane surveying, vertical with column direction or tilt direction setting,, thereby each does not all have parallel portion.
As a result, first to fourth gate drivers IC G1 can be arranged near FPC5 to G4, therefore allows LCD 1 minification.In addition, first to fourth source class driver IC S1 can be arranged near FPC55 to S4, therefore allows LCD 1 minification.Even, connect FPC5 and Signal Terminal respectively, the conductor (31 of logical terminal (LTERM) and grid high level terminal, 33,35) one or two and is connected FPC55 and Signal Terminal respectively, the conductor (81 of logical terminal (LTERM) and grid high level terminal, 83,85), can both see, provide with direction vertical with column direction or that tilt as plane surveying,, to obtain LCD 1 minification.
When setting up, connect distance between the Signal Terminal 13 of the grid low level terminal 11a of first bus line 15 and bonding conductor 31 greater than the logical terminal (LTERM) 12b of bonding conductor 33 and the distance between the Signal Terminal 13 with being connected of second gate drivers IC G2.This makes conductor 31 more close center line Y1-Y1 ', thus first bus line 15 that allows to have parallel portion 15a be positioned at center line Y1-Y1 ' in-plant near.
When setting up with being connected of the 3rd gate drivers IC G3, second bus line 16 with parallel portion 16a can be provided at center line Y1-Y1 ' in-plant near.This allows to reduce the width A of FPC5, thereby the size of acquisition LCD 1 is dwindled.
In like manner, when setting up, connect distance between the Signal Terminal 63 of the source electrode low level terminal 61a of first bus line 65 and bonding conductor 81 greater than the logical terminal (LTERM) 62b of bonding conductor 83 and the distance between the Signal Terminal 63 with being connected of the second source class driver IC S2.This makes conductor 81 be positioned at the position of more close center line X1-X1 ', thus first bus line 65 that allows to have parallel portion 65a be positioned at center line X1-X1 ' in-plant near.
When setting up with being connected of the 3rd source class driver IC S3, second bus line 66 with parallel portion 66a can provide near center line X1-X1 ' is in-plant.This allows to reduce the width B of FPC55, thereby the size of acquisition LCD 1 is dwindled.
In the present embodiment, four driver ICs are provided, to be connected to source line.Alternately, the driver IC of the same structure that provides can be provided LCD, arranges with the line direction alignment, and provides with many groups four quantity.With reference to described LCD, provided above-mentioned explanation.Same structure also is applicable to dissimilar displays, as uses a kind of organic EL, and it has the driving element that is used for each pixel, so that therefore identical effect is provided.
The present invention is applicable to the device with flat-panel monitor, as cellular handset, pocket pc and Vehicular navigation system.
List of reference numbers
1 liquid crystal display
2 liquid-crystal display sections
3,4 glass substrates
5，55 FPC
7 liquid crystal
10a, 10b grid high level terminal
11a, 11b grid low level terminal (the first signal entry terminal)
12a, 12b, 62a, 62b logical terminal (LTERM) (the 3rd signal entry terminal)
13,63 Signal Terminals (secondary signal entry terminal)
14,31,33,35,37,39,41,81,83,85,87,89,91 conductors
15,16,65,66 first, second bus line
15a, 16a, 65a, 66a parallel portion
17 source line
18 grid circuits
21 driving elements
22 pixel electrodes
The 23v common electrode
60a, 60b source electrode high level terminal
61a, 61b source electrode low level terminal (the first signal entry terminal)
G1 is to first to fourth gate drivers IC of G4
S1 is to first to fourth source class driver IC of S4
Claims (15)
1, a kind of display comprises:
A substrate;
A display part, the pixel that wherein has driving element is arranged with matrix form on described substrate;
First to fourth driver IC, it is installed the arrangement so that a side of the display part on the described substrate is alignd in proper order like this, and they drive described driving element; And
A wiring part, it is connected to described substrate and receives the signal that offers described first to fourth driver IC,
Wherein, described first and second driver ICs all have the first signal entry terminal, and its entry terminal can receive same signal and be oriented to face each other,
Wherein, described third and fourth driver IC all has the first signal entry terminal, and its entry terminal can receive same signal and be oriented to face each other,
What wherein form on described substrate is:
First bus line, its first signal entry terminal with described first and second driver ICs links together, and its branch between described first and second driver IC, so that be connected to described wiring part; With
Second bus line, the first signal entry terminal of its described third and fourth driver IC links together, and its branch between the described the 3rd and the 4th driver IC, so that be connected to described wiring part.
2, display as claimed in claim 1,
Has the described first signal entry terminal on each direction that all is aligned along described first to the 4th driver IC at its two ends of wherein said first to the 4th driver IC.
3, display as claimed in claim 2,
Distance between first signal entry terminal of the take-off point of wherein said first bus line and described first grid driver IC equals the distance between first signal entry terminal of the take-off point of described first bus line and described second grid driver IC, and
Distance between the first signal entry terminal of the take-off point of wherein said second bus line and described the 3rd driver IC equals the distance between the first signal entry terminal of the take-off point of described second bus line and described the 4th driver IC.
4, display as claimed in claim 3,
The arrangement that wherein is connected to the conductor of described first and second driver ICs is to be mutually symmetrical about center line with the arrangement that is connected to the conductor of described third and fourth driver IC, this center line is by a central point equidistant with the described second and the 3rd driver IC, and the direction of arranging perpendicular to described first to fourth driver IC alignment.
5, display as claimed in claim 1,
Wherein said first to fourth driver IC has the second and the 3rd signal entry terminal, the second and the 3rd signal entry terminal received signal, and this signal is different from the signal that is received by the described first signal entry terminal,
The described second and the 3rd signal entry terminal of the wherein said second and the 3rd driver IC is connected to described wiring part,
The secondary signal entry terminal of wherein said first and second driver ICs is linked together by the conductor that passes through between reaching below described first and second driver ICs,
The 3rd signal entry terminal of wherein said first and second driver ICs is linked together by the conductor that passes through between reaching below described first and second driver ICs, the secondary signal entry terminal of wherein said third and fourth driver IC by below described third and fourth driver IC and between the conductor that passes through link together and
The 3rd signal entry terminal of wherein said third and fourth driver IC is linked together by the conductor that passes through between reaching below described third and fourth driver IC.
6, display as claimed in claim 5,
Wherein, when from plane geometry, each has all comprised a parallel portion of the alignment orientation that is parallel to described first to fourth driver IC described first and second bus lines, this parallel portion is arranged on a line between described first to fourth driver IC and the described wiring part be in alignment with each other and
Wherein the conductor that described secondary signal entry terminal and wiring part are linked together does not have parallel portion with at least one conductor in the conductor that described the 3rd signal entry terminal and wiring part are linked together, and this parallel portion is the alignment orientation that is parallel to described first to fourth driver IC.
7, display as claimed in claim 1,
Wherein said first to fourth driver IC provides signal for the grid of described driving element.
8, display as claimed in claim 7,
The wherein said first signal entry terminal is an entry terminal, by this entry terminal.A low level has been provided for the grid of described driving element.
9, display as claimed in claim 1,
Wherein said substrate is made by glass, and
Wherein said first to fourth driver IC be the surface downwards by bonding wire to substrate.
10, display as claimed in claim 1,
Wherein said display partly is to be made by liquid crystal cells.
11, a kind of glass substrate that is used for display has comprised following part:
One display device zone is arranged on it and is provided with display element, and described display element has pixel, and these pixels have comprised driving element and by to arrange with matrix form;
First to fourth driver region, to such an extent as to being used to drive first to fourth driver IC of described driving element is arranged like this by a side alignment along described display element zone, first and second driver region with first signal entry terminal are oriented to toward each other, and third and fourth driver region with first signal entry terminal is oriented to toward each other;
A wiring part zone is connected with a wiring part, and described wiring part receives the signal that is provided for described first to fourth driver IC;
One first bus line, its first signal entry terminal with first and second driver region links together, and its between described first and second driver region branch to be connected to described wiring part zone; And
One second bus line, its first signal entry terminal with the 3rd and the 4th driver region links together, and its branch between described third and fourth driver region, to be connected to described wiring part zone.
12, the glass substrate that is used for display as claimed in claim 11,
Distance between the first signal entry terminal of the take-off point of wherein said first bus line and described first driver region equal between the first signal entry terminal of the take-off point of described first bus line and described second driver region distance and
Distance between the first signal entry terminal of the take-off point of wherein said second bus line and described the 3rd driver region equals the distance between the first signal entry terminal of the take-off point of described second bus line and described the 4th driver region.
13, the glass substrate that is used for display as claimed in claim 12,
The arrangement that wherein is connected to the conductor of described first and second driver region is to be mutually symmetrical about a center line with the arrangement that is connected to the conductor of described third and fourth driver region, this center line is by a central point equidistant with the described second and the 3rd driver region, and perpendicular to the alignment orientation of described first to fourth driver region.
14, the glass substrate that is used for display as claimed in claim 11,
Wherein said first to fourth driver region has the second and the 3rd signal entry terminal, wherein said second and the second and the 3rd signal entry terminal of the 3rd drive area be connected to described wiring part zone, the secondary signal entry terminal of wherein said first and second drive areas is by being joined together from described first and second drive areas and the conductor that passes therebetween
The 3rd signal entry terminal of wherein said first and second drive areas is by being joined together from described first and second drive areas and the conductor that passes therebetween,
The secondary signal entry terminal of wherein said third and fourth drive area is by being joined together from described third and fourth drive area and the conductor that passes therebetween,
The 3rd signal entry terminal of wherein said third and fourth drive area is by being joined together from described third and fourth drive area and the conductor that passes therebetween.
15, the glass substrate that is used for display as claimed in claim 14,
Wherein, when from plane geometry, each all comprises a parallel portion that is parallel to described first to fourth driver region alignment orientation described first and second bus lines, a line between first to fourth driver region that described parallel portion is arranged and described and the described wiring part zone be in alignment with each other and
Wherein the conductor that described secondary signal entry terminal and described wiring part zone are linked together does not have parallel portion with at least one conductor in the conductor that described the 3rd signal entry terminal and described wiring part zone are linked together, and this parallel portion is parallel to the alignment orientation of described first to fourth driver region.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004072015 | 2004-03-15 | ||
| JP2005062736A JP4526415B2 (en) | 2004-03-15 | 2005-03-07 | Display device and glass substrate for display device |
| JP2005062736 | 2005-03-07 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1831586A true CN1831586A (en) | 2006-09-13 |
| CN100465706C CN100465706C (en) | 2009-03-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100553246A Expired - Fee Related CN100465706C (en) | 2004-03-15 | 2005-03-15 | Display device and glass substrate using therefor |
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| Country | Link |
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| CN (1) | CN100465706C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101542568B (en) * | 2007-04-06 | 2011-07-13 | 松下电器产业株式会社 | Plasma display device |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3150334B2 (en) * | 1990-11-15 | 2001-03-26 | セイコーエプソン株式会社 | LCD panel |
| JPH05181153A (en) * | 1992-01-07 | 1993-07-23 | Matsushita Electric Ind Co Ltd | Liquid crystal display device |
| JP3643640B2 (en) * | 1995-06-05 | 2005-04-27 | 株式会社東芝 | Display device and IC chip used therefor |
| WO1998012597A1 (en) * | 1996-09-20 | 1998-03-26 | Hitachi, Ltd. | Liquid crystal display device, production method thereof and mobile telephone |
| JP2000137445A (en) * | 1998-11-02 | 2000-05-16 | Toshiba Corp | Flat display device |
| JP2000259091A (en) * | 1999-03-04 | 2000-09-22 | Casio Comput Co Ltd | Display panel, flexible wiring board, and display device provided with them |
| EP1039788B1 (en) * | 1999-03-26 | 2006-04-19 | Seiko Epson Corporation | Flexible printed wiring board, electro-optical device, and electronic equipment |
-
2005
- 2005-03-15 CN CNB2005100553246A patent/CN100465706C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101542568B (en) * | 2007-04-06 | 2011-07-13 | 松下电器产业株式会社 | Plasma display device |
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| Publication number | Publication date |
|---|---|
| CN100465706C (en) | 2009-03-04 |
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