CN1825769A - Fraction N frequency synthesizer and modulator using pure digit phase discriminator - Google Patents
Fraction N frequency synthesizer and modulator using pure digit phase discriminator Download PDFInfo
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Abstract
This invented fraction N frequency composer uses a step delta-sigma frequency discriminator as an output frequency error tester characterizing that the test of error signals is carried out based on comparing the phase state expressed by a bit sequence output by a one-step delta-sigma frequency discriminator with that of one-step delta-sigma quantization digital module applied to necessary fraction frequencies composed of a digital method to eliminate large quantities of noises mixed in the output bit sequence of the discriminator, so the fraction N frequency composer is very good in restraining noises.
Description
Technical field
The invention belongs to the frequency synthesizer field in the circuit engineering.Being specifically related to fraction N frequency synthesizer, can frequency synthesis be the output signal frequency synthesizer of non-integral multiple loop reference frequency promptly.If desired, the output signal of this frequency synthesizer can also have the required signal modulation of transmission information simultaneously.
Background technology
Along with the development of digital technology, the use of frequency synthesizer in circuit engineering more and more widely.Frequency synthesizer is general to use a stable reference oscillator to produce the accurate and controlled output signal of frequency.The most frequently used frequency synthesizer implementation method is to guarantee frequency corresponding relation between output signal and the reference signal with phase-locked loop.Typical phase-locked loop is by voltage-controlled oscillator, feedback division circuit, and phase discriminator and loop filter are formed.Because basic frequency dividing circuit is an integral frequency divisioil, early stage frequency synthesizer can only produce the output signal that frequency is the actual input reference frequency integral multiple of phase discriminator.Fraction N frequency synthesizer has been broken through this restriction, can frequency synthesis be the output signal of non-integral multiple reference frequency.Thereby can use higher loop reference signal frequency to same frequency resolution index.Can be improved aspect synthetic signal quality and the switching rate like this, gradually in various electronic technology, particularly communication technology aspect has obtained increasing application.But the performance of all fraction N frequency synthesizers all is subjected to the restriction of mark clutter more or less, aspect popularization certain difficulty is arranged.Have a lot of inventions to be suggested to overcome this defective, it is the successful technology that wherein compares that analog compensation and delta sigma noise spectrum are moved.
The analog compensation technology be according to fraction division produce phase jitter Changing Pattern and when the detected phase in addition corresponding analog correction signal to reduce the intensity of mark clutter.This compensation can have good effect when the accuracy of simulation part is guaranteed.But owing to the simulation accuracy is easy to change with temperature in time, unless the very high spy of use cost removes measure, compensation performance can not be protected.
The advanced method that grows up with digital processing technology when the delta sigma noise spectrum is moved technology.The principle of this technology be utilize to frequency dividing ratio implement the modulation of high-order delta sigma method so that the phase jitter frequency spectrum of fraction division thereby move to high frequency can be more effectively by the loop filter filtering.Because this method can be stablized and suppress the mark clutter effectively, obtains more application gradually.But, can't satisfy some and require than higher application owing to thoroughly do not solve the clutter problem.Its structure more complicated simultaneously has very high requirement to the linearity of phase discriminator, also becomes the major obstacle of its performance of further raising and integrated level.
We can say that in a sense existing fraction N frequency synthesizer technology is also just to a kind of improvement of traditional PHASE-LOCKED LOOP PLL TECHNIQUE based on the simulation phase discriminator.For obtaining technically, need probably structure is reformed more completely than quantum jump.With the thorough digitlization of phase discriminator is exactly a possible evolutionary path.If phase discriminator can directly be exported digitized phase error signal, then follow-up signal processing can be finished by digital technology.Utilize the flexibility and the accuracy of Digital Signal Processing will probably make frequency synthesizer thoroughly break away from the restriction of conventional art.Existing a lot of research and patent of invention may be inquired into this, but all do not find comparatively ideal scheme.
In the pure digi-tal phase demodulation scheme that has proposed, DSFD (Delta-Sigma Frequency Discriminator, be the delta sigma frequency discriminator) [R.Douglas Beards and Miles A.Copeland, " An Oversampling Delta-Sigma Frequency Discriminator ", IEEETransactions on Circuits and Systems-II:Analog and Digital Signal Processing, Vol.41, No.1, January 1994, pp.26-32] be a kind of very potential structure.The operation principle of DSFD and 1 bit moduli transducer are very similar, and only phase place more to be detected is in advance or lags behind fixed phase, and the accuracy that detects guarantees by improving sampling frequency.This method makes analog parameter drop to bottom line to the influence of accuracy of detection, is highly suitable in the integrated circuit and uses.
The output of DSFD is sequence of digital bit, is the frequency change function of institute's detection signal.More definite, be the delta sigma quantized result of institute's detection signal with respect to the fractional frequency of reference signal.According to the delta sigma quantization principles, one is used the method for DSFD on the surface very intuitively is that the bit sequence of its output just is used as the numerical value of its incoming frequency after delta sigma quantizes.The fractional frequency that this sequence of values is direct and required subtracts each other just can obtain an error signal sequence, just can be used to the frequency drift of correction voltage control generator after digital integration that this error signal sequence process is suitable and the Filtering Processing.Can form fraction N frequency synthesizer [U.S.Pat.No.5 according to this basic principle, 781,044] and modulator [W.T.Bax and M.A.Copeland, " A GMSK Modulator Using a Frequency Discriminator-Based Synthesizer ", IEEE Journal of Solid-State Circuits, Vol.36, No.8, August 2001, pp.1218-1227].But this using method of DSFD intuitively has a basic defective.Optimal DSFD structure is to carry out 1 rank delta sigma to quantize, and its structure will become very complicated as realizing quantizing then by high-order, might also must use conventional phase discriminator, almost completely lose the advantage of DSFD self.But the deriving method of above error signal makes that must carry out the high-order delta sigma quantizes could satisfy clutter inhibition requirement in the conventional application.More than attempt all being based upon on the basis of using high-order DSFD, therefore can not obtain bigger success.
From the principle, basic mark N frequency synthesis technique corresponding to the single order delta sigma quantizes the delta sigma noise spectrum move technology and quantize corresponding to high-order.Above as can be seen the trial is to be subjected to the misleading that the delta sigma noise spectrum is moved technology successful Application in digital to analog converter and fraction N frequency synthesizer.In fact only implement the single order delta sigma and quantize also to obtain good clutter rejection, the analog compensation technology that Here it is uses basic fraction N frequency synthesizer, and the stability problem that just is hampered by analog compensation can't be solved effectively.If but the synthesizer situation that the compensation method that is similar to the analog compensation technology is used for single order DSFD formation is just different fully.The output of DSFD is digital signal, and therefore compensation can be realized by digital method entirely that the stability problem of so original analog compensation technology has not just existed fully.One promptly simple and be easy to integrated, almost thoroughly solved the brand-new frequency synthesizer that clutter suppresses problem, the accuracy that can make full use of digital processing technology and flexibility and just might become a reality.What this patent will be set forth is exactly the method that how to realize this imagination.
Summary of the invention
Key problem in technology of the present invention be with single order DSFD as the phase-detection device to constitute fraction N frequency synthesizer and to compensate its frequency quantization error to come the mark clutter is suppressed with digital method.
Specifically, the output bit sequence of DSFD will be not be gone direct error signal as the fractional frequency numerical value that has quantized simply.New algorithm is that the DSFD operating state that this state will be used as the output bit sequence representative of reference and DSFD compares with the operating state of digital method analog D SFD when importing an ideal signal.Because the input signal of DSFD also approaches ideal signal very much when loop-locking, these two operating states also should be basic the same.Particularly two frequencies that state produced quantification error change rules also are essentially identical.Method by the state comparison can extract required phase error function from its minute differences.Because a large amount of frequency quantization errors have been cancelled in comparison, thereby can not cause very strong mark clutter again.Also we can say earlier from another angle and again it to be deducted from the detection signal of DSFD so that it is not comprised in the phase error function that extracts after simulating frequency quantization error when the desirable operating state with digital method.The operation principle of this and analog compensation is actually the same.
Therefore, the fraction N frequency synthesizer that constitutes according to this patent will have high mark clutter inhibition degree.Digital Simulation and Circuit verification have all confirmed almost to can't see discrete mark clutter spectrum in output spectrum.And, therefore can not be subjected to the influence that the circuit physical property changes because clutter is offset with digital form enforcement.
Second advantage of this structure is to have only voltage controlled oscillator and near the sub-fraction circuit of DSFD to belong to traditional simulation category, and most function realizes with digital form.This not only makes this structure be suitable for using in integrated circuit, the more important thing is and has only seldom several elements can introduce analogue noise.This just makes that doing the Design of Low Noise ratio is easier to, thereby this synthesizer might have fabulous noise objective.
This structure also has an advantage can add additional function with digital form to loop more easily exactly.Because it is the just digital processing part that will change, many difficult with the complexity compensation accomplished with control and to implement concerning traditional synthesizer.An important use of this advantage is exactly that synthetic signal is carried out the modulation of frequency or phase place.
To in embodiment one joint, provide in conjunction with the accompanying drawings further specifying of the art of this patent principle.
Description of drawings
Fig. 1: the structure chart of single order DSFD.
Fig. 2: the sequential chart of single order DSFD signal.
Fig. 3: single order delta sigma accumulator graph of equation shape is explained.
Fig. 4: utilize DSFD to constitute a kind of possible structure of fraction N frequency synthesizer.
Fig. 5: according to a kind of possible structure of Digital Signal Processing piecemeal in Fig. 4 structure of this patent conceptual design.
Fig. 6: the another kind according to Digital Signal Processing piecemeal in Fig. 4 structure of this patent conceptual design has comprised the possible structure that the detection of two classes is handled.
Fig. 7: may mode to a kind of of the additional two point form wide-band modulation of composite signal.
Embodiment
Here elder generation is described in more detail with auxiliary explanation to the patent principle the operation principle of DSFD.
Referring to Fig. 1, f
sBe the frequency input signal of DSFD, f
RefIt is reference signal frequency.Input signal is held input from the input (In) of double modulus divider (1), through holding data (D) end of delivering to d type flip flop (2) to carry out bit comparison mutually with the reference signal of importing from the clock end of d type flip flop (2) from the output (Out) of double modulus divider (1) after the frequency translation.Leading as the reference signal phase place, then the rising edge of bimodulus divider output arrives after with reference to the edge, and output (Q) end of d type flip flop (2) will be 0.Otherwise output will be 1.
The modulus control end (Mod) of double modulus divider (1) is by output (Q) the end control of d type flip flop (2).The bit of output is that the modulus of 1 o'clock divider will be set as N+1.The bit of output be 0 and the modulus of divider will be set as N.
Quantitatively, establish f
sCan represent with following formula:
f
s＝(N+S)f
ref 0＜S＜1 (1)
Wherein N is a positive integer, S be one less than 1 mark and the fractional frequency mentioned of front just.If use f
sAnd f
RefT cycle of oscillation
sAnd T
RefRepresent that following formula can also be written as:
T
ref＝(N+S)T
s (2)
Referring to Fig. 2, be located at i with reference to along the time double modulus divider modulus be N+M
i, M wherein
iCan be 0 or 1.If S
iFor beginning this N+M when divider
iReference signal (is used T by differing from the real time with respect to phase of input signals during cycle count
sObtain after the normalization).The phase place S of reference signal when the divider counting finishes
I+1Will for:
S
i+1＝S
i+(N+S)-(N+M
i)＝S
i+S-M
i (3)
M
I+1Value will be determined by the quantized result of fixed phase and the structure of bimodulus divider.Concerning general bimodulus divider, change its modulus control signal and can only change next division modulus of periodicity number.Like this, if S
I+1＞0, then not M
I+1, but M
I+2To be set as 1, on the contrary M
I+2To be set as 0.On the angle of phase-detection,, accuracy and the stability that detects all there is infringement though this delay does not produce destruction completely.Even fortunately the bimodulus divider can be become divider current period to be begun to count by particular design on the structure but as long as before counting finishes in the enough time early its modulus control signal of change just can change the modulus of current period.Concerning this divider, if S
I+1＞0, M
I+1To be set as 1, on the contrary M
I+1To be set as 0.If this concerns establishment, then according to the delta sigma quantification theory as can be known following formula be exactly the single order delta sigma accumulator equation of standard.
Owing to use this special bimodulus divider can obtain best detection performance, will suppose always to be to use this divider in the following discussion.And in actual design, carried out rational assessment if desired and to precision and stability, also might use general bimodulus divider.At this moment the following algorithm of introducing need be made amendment and could be used, but its basic functional principle is constant.
Should be noted that sampling phase S
iQuantization threshold be 0.Can also suppose S
iAlways less than 1, this presets divider in the time of can be by initialization and obtains.
Bit sequence { M like this
iJust will be the single order single-bit delta sigma quantized value of fractional frequency S, and { M
iMean value be exactly S.This means the output bit sequence M of DSFD
I, DSFDCorresponding to the fractional frequency of its input signal, the reason that is called as DSFD (delta sigma frequency discriminator) has been described also.
Though also it is to be noted in discussing to be N and N+1 from succinct consideration with two moduluses supposing the bimodulus divider always here, the difference of two moduluses can be greater than 1 when specific design, its basic functional principle is also constant.
Can visualization ground be described by single order delta sigma accumulator equation with Fig. 3.Real ray from initial point among the figure is called condition line, and its polar angle with respect to vertical 0 ° of line is sampling phase S
iMultiply by 2 π.Notice that all in the following discussion diagram phase places are all so handled and do not indicate 2 π coefficients in the drawings.Through each reference cycle, the condition line S angle that all will turn clockwise.Do not pass through 0 ° of line, corresponding M as condition line in a reference cycle
iTo be 0, opposite then will be 1 as having passed through.Because the cycle of polar angle is 2 π, the anglec of rotation of condition line and single order delta sigma accumulator equation fit like a glove like this.
Digital Signal Processing piecemeal (5) among Fig. 4 will be according to the bit sequence M that receives from DSFD
I, DSFD, produce an error signal by the fractional frequency S and the loop response of required output frequency and reference frequency decision.With conventional frequency synthesizer difference be that this error signal is a digital signal, must just can become suitable analog signal through digital to analog converter D/A (6) and low pass filter (7) and be added to the control end of voltage controlled oscillator (3) again with the correction oscillation error.Here need to prove loop response substantially by Digital Signal Processing piecemeal (5) with digital method control, the major function of low pass filter (7) is the high order harmonic component of filtering digital to analog converter (6), and is less to the influence of loop response function.
Lip-deep weakness of this structure is that the requirement of logarithmic mode transducer (6) is than higher.But in fact be operated in the arrowband feedback control loop owing to this digital to analog converter, therefore very low to the requirement of its linearity and change-over time, be easy in circuit, realize.
The operating state of digital DSFD module (8) analog D SFD among Fig. 5 when input signal has desirable fractional frequency S.Module has two outputs, and one is quantization bit M
i, another is sampling phase S
iModule is not according to the work of single order delta sigma accumulator equation when (reset) end that resets has signal.Notice that modules all among this figure all is with the rhythm work of reference frequency.
The operation principle of system will be described with the diagrammatic representation of condition line for simplicity's sake.The work of numeral DSFD module (8) and DSFD (4) can be represented with their condition line.If the output signal frequency of voltage controlled oscillator (3) work and the digital DSFD module (8) of ideal value and DSFD (4) just is synchronous, then the angle between its two condition lines is 0 and in synchronous rotation.This means that they will cross 0 ° of line when same reference cycle, two bit sequences that therefore arrive Compare Logic (11) will be duplicate.Compare Logic (11) will make switch (9) maintain position A like this, and the error signal of delivering to loop filter (10) also is 0.
If the output signal frequency of voltage controlled oscillator this moment (3) has departed from ideal value, the input fractional frequency of DSFD (4) also will begin to change, then two condition lines separation that is about to begin.But in general the dibit sequence does not just begin to occur different at once.Even this is because two condition lines have separated a low-angle, but the angle that condition line stops when most of reference cycle is all bigger from 0 ° of line, so can not occur that a bar state line has been crossed 0 ° of line and situation that another bar state line did not have.This situation only is parked in comparison at condition line and just might takes place near the reference cycle of 0 ° of line.When two relatively bit is different, show above situation has taken place, that is to say the phase error that has detected output signal.At this moment just should export a suitable error signal goes this phase error is proofreaied and correct.
Owing to can put aside fixing loop gain coefficient, desirable error signal should be the differential seat angle between the two condition line.Regrettably this differential seat angle is not known.Angle between now known is digital DSFD module status line and the 0 ° of line is its sampling phase S
iIn addition since at this moment the two condition line be positioned at the both sides of 0 ° of line, so the differential seat angle between the two condition line is necessarily greater than S
i
Must be noted that at this moment and can not simply get S
iRepeat this testing process as the first approximation of error signal and in the following reference cycle.Even this is because this being similar to can be satisfied required precision, but along with the angle between the accumulation two condition line that detects error probably can become bigger and bigger.The error that detects so also can become bigger and bigger.Accuracy of detection will corrupt to the degree that can't use fast.
The way that addresses this problem is to make detection not with phase demodulation but carry out in the mode of frequency discrimination.The output error signal that frequency discrimination detects should be the difference on the frequency between two signals.If between two signals small difference on the frequency is arranged, then the variation through the angle between the two condition line after the reference cycle will be this difference on the frequency and the product of time in reference cycle.Because the time in reference cycle is a fixing constant, therefore the error signal that is produced also and the angle between the current two condition line be directly proportional.
Because the error signal that is produced all is by the angle representative between the current two condition line, frequency discrimination has nothing different with the phase demodulation mode on the surface.But what the difference of frequency discrimination and phase demodulation mode most critical was the frequency discrimination detection in fact is the variation of the angle between the two condition line rather than the absolute value of angle.Therefore, desirable frequency discrimination process is after different comparison bits occurs, and the output of the angle between the two condition line at this moment as error signal, is moved on to the detection that position overlapped is restarted the next reference cycle again to two bar state lines then.Notice that this also is equivalent to make the direction of another bar state line of bar state alignment to move the angle onesize with error signal.Like this, and phase demodulation detect compare frequency discrimination detect in angle between the two condition line can arbitrarily not increase, will remain on the very little numerical value always.
Owing to be the part angle of known two condition line, i.e. S when actual detected
i, therefore the frequency discrimination that can not realize ideal detects.But at this moment just available S
iFirst approximation as error signal.According to the frequency discrimination principle at this moment needs the condition line of digital DSFD module is moved and S to the direction of DSFD condition line
iSame numerical value.Because all parameters of digital DSFD module all are known and controlled, finish this and move no problem.Though the two condition line is not overlapping when the next reference cycle begins like this, the angle between it did not last time have detected that part of angle value just.The phase error that produces in the next reference cycle will with this part angle addition after be carried out detection again.Therefore, we can say that in a sense those errors that are not detected finally still will be detected, and just have a time-delay on detection time.In fact as long as guarantee that those error angles that have been detected are constantly removed the angle between the two condition line, the two condition line just can rotate with almost synchronous angle, make each detection less than the error angle also very little, thereby guaranteed the accuracy that detects.
The error of this detection method is reflected in above the time-delay of detection time.This time-delay is closely-related with the time in reference cycle.If reference frequency is much larger than loop bandwidth, this delay time error is an acceptable.
After detecting different comparison bits, Compare Logic (11) just exports a control signal among Fig. 5.This signal switches to position B with switch (9).This makes S
iBe used as error signal and deliver to loop filter (10).Control signal is also delivered to digital DSFD module (8) by (reset) end that resets simultaneously.At this moment module will be not operative norm single order delta sigma accumulator equation and carry out following equation:
S
i+1＝S-1+M
i (4)
Next sampling phase will be (be without loss of generality and can suppose that its input fractional frequency also is S) concerning DSFD (4):
S
i+1，DSFD＝S
i，DSFD+S-M
i，DSFD＝S
i，DSFD+S-1+M
i (5)
Because current relatively bit is different, so use 1-M during the derivation following formula
iReplaced M
I, DSFD(
MM during i=1
I, DSFD=0, M
i=0 o'clock M
I, DSFD=1).Relatively this two formula just can see the next one during sample time angle between the two condition line be exactly that part S that is not detected really
I, DSFD, reached the purpose of rotating the condition line of digital DSFD module (8) to the direction of the condition line of DSFD (4).
The condition line of numeral DSFD module (8) and the angle between 0 ° of line are exactly S
iTherefore says that from the angle of diagrammatic representation the operation of rotating its condition line restarts it in fact exactly from 0 ° of line.
Fig. 5 intermediate ring road filter (10) will be delivered to digital to analog converter by required loop response function with the digital filtering technique processing and the result to the error signal that generates.Though it is to be noted that here error-detecting carries out with frequency detection mode, the phase-locked loop response that forms standard if desired then only needs to add the one-level digital integration in loop filter and just can.Must be pointed out also that in addition it is better directly to make loop have a response of FLL in a lot of practical applications.
From above argumentation, as can be seen, among the value of the error function of Sheng Chenging, except that 0, will only contain the sampling phase of accumulator (8) when occurring difference comparison bit in this way.And further analysis also can draw, as long as choose suitable fractional frequency value S and sufficiently high reference frequency f
Ref, the sampling phase of accumulator (8) will be always than 1 little getting much when the appearance difference compared bit.This explanation was mixed in quantizing noise in the output bit sequence of DSFD (4) originally and had been balanced out by this relatively method of bit sequence when certain.
Fig. 5 realizes that just a kind of of this patent method may structure.Fig. 6 has provided the higher structure of another kind of efficient.Below will progressively analyze its operation principle.
Press the operating principle of Fig. 5, the condition line of digital DSFD module (8) is always from 0 ° of line.If S=n/m and n and m are mutual prime rwmbers.If condition line occurs from 0 ° of never different relatively bit in line back, then just get back on 0 ° of line again, and all condition lines do not overlap between this through m reference cycle rotation n circle back.Clearly this m root condition line is equally distributed to the whole circumference angle, that is to say, the angle between any two adjacent condition lines is 1/m (having omitted coefficient 2 π, down together).
The principle of general selection fractional frequency S is to make m big as far as possible, and therefore a lot of different condition lines existence will be arranged.It is very little owing to phase error when loop is in the lock state, therefore the condition line of accumulator (8) is generally all very near from 0 ° of line when different relatively bit occurring, only just can contribution be arranged to detecting output very close to several of 0 ° of line usually like this in this m root condition line.When opposite extreme situations, have only angle be-two ability of 1/m and 1/m are useful.The condition line that should be noted that numeral DSFD module (8) when lock-out state also often is parked on 0 ° of line.And by the structure of making Fig. 5, at this moment owing to the current sampling phase of digital DSFD module (8) be 0 action that makes switch (9) without any effect, that is to say at this moment to not contribution of error-detecting.In fact at this moment be 0 as the output bit of DSFD and show that phase of output signal lags behind, 1 is leading.This illustrates that this state still contains certain detection information.But these information are not carried out utilization in Fig. 5.Owing to have only several condition lines that detection is had contribution usually, if can effectively utilize these information of omitting systematic function will be further improved.
For simplicity's sake, will claim later on when the condition line of the not digital simultaneously DSFD module of bit (8) relatively not the state on 0 ° of line be that a class detects, and be that two classes detect when the condition line of digital DSFD module (8) turns to 0 ° of state on the line.
Can only show that phase of output signal is in advance or lags behind because two classes detect, obtain the just necessary relatively result of twice detection of information of output signal frequency error.The phase place of understanding output signal as the output table of bits of DSFD (4) is to lag behind and this is leading when detecting when preceding one-time detection, illustrates that then output signal frequency is higher than ideal value.At this moment just can send a suitable perturbation error signal to arrive loop filter to reduce frequency of oscillation.As being last time to be to lag behind in advance and specifically, then can send an opposite perturbation signal.If but the output bit of DSFD (4) is the same when detecting for twice, then can not determine the output signal frequency direction of error, does not at this moment just preferably add perturbation.
If the intensity of this perturbation signal is proper, make in m the reference cycle that adds after the perturbation angle between two condition lines be in always+1/m between, then next the detection also will be two classes.This just can continue and last time detect relatively to determine correct perturbation signal.
If the random fluctuation of oscillator frequency is less than the intensity of perturbation, the then very possible detection that occurs continuously all is two classes.So just can utilize perturbation method to make phase error remain on very little numerical value always.
But the angle that also probably occurs between the two condition line become greater to the situation that makes a class detect generation.This is if system has preserved the perturbation record since last one one class detects, and what the error signal that then can make generation was a normal class error signal with respect to totalling perturbation sum is poor.So just can make add perturbation and do not disturb algorithm a class detection of error signals, thereby stability problem can not appear.
In sum, when two classes occurring and detect with the small perturbation of opposite in sign to reduce residual phase error, detect the generation that then returns to a normal class error signal now when a class.Might return to less numerical value again through phase error after the correction of class detection, two classes detect and just can reappear at that time.Utilizing the detection of two classes to apply perturbation so just can make average phase error be reduced.
Because the error signal absolute value of minimum was 1/m when a class detected, a proper perturbation intensity is 1/2m.Often average phase error can be reduced half with this perturbation intensity.
Identical among the course of work of the digital DSFD module (8) among Fig. 6 and Fig. 5.When two relatively bits not simultaneously, the Compare Logic among Fig. 6 (14) produces the reset terminal (reset) that a control signal is delivered to DSFD module (8) at its port one.When taking place without any detection, switch (12) will be in position A.When the detection of any class or two classes occurring, Compare Logic (14) will produce a control signal at port 2 make switch (12) be transformed into position B.Compare Logic (14) makes switch (13) be in position A when a class detects by port 3, is in position B at two time-likes.And Compare Logic (11) different be that Compare Logic (14) need to detect sampling phase S
iWhether be on 0 ° of line with the condition line of judging digital DSFD module (8).
Dibit memory BR
1And BR
2Be used for storing perturbation history.Produced after the error signal of class detection, Compare Logic (14) all will deposit current DSFD output bit in BR at every turn
1And BR
2Note BR
2The small circle of output is to take advantage of-1 the meaning.Therefore, BR when having only a class to detect
1And BR
2Cancelled each other, the work of Fig. 6 structure at this moment is the same with Fig. 5.
When two classes detect now, the value of perturbation signal will be by BR
2Current output bit decision with DSFD.Only at BR
2Just can not produce the perturbation signal of non-zero simultaneously with the current output bit of DSFD.The intensity of perturbation signal is set by the value of δ.After having produced the error perturbation signal of two classes detections, Compare Logic (14) will deposit the current bit of DSFD in BR separately at every turn
2
Replacing owing to the perturbation signal is always positive and negative, is not that δ is zero so two classes that apply detect perturbation signal summation.When after any two classes detect, occurring class machines meeting again, only need the output bit BR of DSFD when relatively last class of front detects
1The output bit BR of DSFD when detecting with last two class
2Whether the same two classes that just can have been applied detect perturbation signal summation.As can see from Figure 6, the perturbation summation that calculates will be deducted from a normal class detection of error signals, can not influence the algorithm that a class detects to guarantee perturbation.
What need statement is the example how above structure all only implements design philosophy of the present invention.Also can construct many other structures according to basic principle.For example in Fig. 5, generate to a class machines can error signal always less than the angle between the two condition line.As error signal is suitably also rotated with the same angle of error signal greater than the current sampling phase of digital DSFD module (8) and at the condition line that makes accumulator (8) thereafter can obtain better phase error performance therefore.This algorithm is more complicated than Fig. 5, but it is also not too large to implement difficulty concerning the modern digital treatment circuit.The improvement of this class also should belong to the invention category of this patent.
Therefore an advantage of structure of the present invention can dynamically change loop bandwidth and other loop parameters at an easy rate owing to loop response is to be controlled by digital processing technology basically.Can adopt big loop bandwidth to accelerate as the lock stage of going into, and after loop locks substantially, just switch to narrow bandwidth to improve output performance into lock speed at loop.
For a class machines can, when the angle between the two condition line can not generate the error signal of any non-zero during less than 1/m.No matter therefore how other loop parameter is chosen, average phase error can be not a lot of less than 1/m.So when the design loop, choose suitable fractional frequency so that m is a bigger numerical value because of this.Though for the application that can not freely choose output frequency and reference frequency, this appears to a serious restriction, by following argumentation this problem anything but concerning the overwhelming majority uses as can be seen.
The reference frequency of General System obtains by crystal oscillator.Any crystal oscillator, no matter how accurate, frequency of oscillation is not infinitely accurately.As the nominal value fractional frequency of establishing according to reference frequency should be 0.x, is 0.xyyyy but often should make fractional frequency according to the actual oscillation frequency of crystal oscillator.General so all can have a bigger m value.This adds another advantage of understanding according to the frequency synthesizer of this patent design, the accuracy that promptly often can come digitlization ground to proofread and correct output frequency by calibration to crystal oscillator, thereby very low to the absolute frequency accuracy requirement of use crystal oscillator.This also is a significant advantage when large-scale commercial applications production.
From another point of view, even reference frequency is an absolutely accurate, the numerical value that also can change fractional frequency enough distant places behind decimal point artificially is so that m is enough big.Output frequency also can have a small difference with required frequency like this.But concerning most electronic equipments, as long as the enough urine of difference always can meet the demands.
Therefore, the controllability of the frequency resolution of this frequency synthesizer is good.It is chosen enough under the prerequisite of big m really, and its frequency resolution and phase error performance are by the ratio decision of reference frequency and loop bandwidth substantially.The big more then performance of ratio is good more.
An important feature of this patent invention structure makes and can more easily with digital method information be added on the output signal that is produced with frequency or phase modulation method.Utilize these characteristics that the design of many signal sources or transmitter is simplified greatly, performance is improved and reduces cost.
Less than loop bandwidth, this needs will required frequency shift (FS) function to deliver to after the fractional frequency merging with Fig. 5 after with reference frequency normalization the input of digital DSFD module (8) again as the modulation signal bandwidth.Its principle is the same with traditional analog-modulated ring except the characteristics of digital realization.
Can realize wide-band modulation in the modulation signal bandwidth with two-point method during greater than loop bandwidth.Frequency shift (FS) function Δ f in Fig. 7 after the normalization of usefulness reference frequency
mNot only be added on the input of digital DSFD module (8), also added loop filter. in the output signal of (10) with direct modulation voltage controlled oscillator (3).Because second modulation is added in after the loop filter, its modulation bandwidth just can not be subjected to the restriction of loop bandwidth.As modulation is accurately, and then digital DSFD module (8) and DSFD (4) implement the single order delta sigma to the signal frequency that contains same modulation product to quantize.This means that modulation will can not destroy the detection of phase error, thereby loop feedback can not make modulation produce distortion.
Directly the modulation signal amplitude of modulation voltage controlled oscillator (3) must be carried out normalization with the modulation gain coefficient of voltage controlled oscillator.This just must calibrate gain coefficient earlier.Calibration can be carried out when system initialization or before transmitting each packet.The method of calibration has several.Be added on the fractional frequency input of accumulator as the less low-frequency sweep signal that is lower than loop bandwidth that then can use of modulation amplitude.Because loop feedback will be followed the tracks of this low frequency modulations, the intensity that reads this output that is modulated at loop filter (10) just can calculate the modulation gain of voltage controlled oscillator (3).Then the calibration speed of this method might be too slow greatly as modulation amplitude, at this moment can calibrate to several Frequency points by making the loop quick lock in.Because can utilize the method for switching loop bandwidth to accelerate into lock speed, the calibration time can accomplish very short.
The very long or system requirements energy continuous operation as packet, then requirement can be implemented dynamic compensation to the modulation gain coefficient drift of voltage controlled oscillator (3).Fig. 7 has comprised a kind of method of dynamic compensation.A low-frequency sweep signal (16) that is positioned at loop bandwidth has superposeed in the modulation signal that directly is added to voltage controlled oscillator (3).But owing to not having this low frequency component in the modulation signal that is added to digital DSFD module (8), loop feedback will produce this low frequency component from the output of loop filter (10) to eliminate the distortion of modulation.Like this, the low frequency signal (16) of voltage controlled oscillator gain detecting unit (15) low frequency signal that just can measure the output from loop filter (10) and this stack is compared and is monitored the modulation gain coefficient drift of voltage controlled oscillator (3) and the intensity of direct modulation signal is carried out dynamic compensation.It should be noted that often the modulation gain coefficient of voltage controlled oscillator (3) can change with modulating frequency, but because compensation is implemented with digital form, this variation also becomes more readily available compensation.
Claims (10)
1. one kind can frequency synthesis be non-integral multiple loop reference frequency f
RefThe fraction N frequency synthesizer of output signal in comprise the voltage-controlled oscillator (3) that is used to produce output signal;
The single order delta sigma frequency discriminator DSFD (4) that a double modulus divider (1) and a d type flip flop (2) constitute; And
Output bit sequence M to DSFD (4)
I, DSFDHandle and according to required output frequency f
sProduce the digital and analog circuit of an error signal with the frequency error of correction voltage control generator (3); It is characterized in that
Above error signal be not by directly the output bit sequence of single order delta sigma frequency discriminator DSFD (4) be used as incoming frequency after delta sigma quantizes numerical value but the phase quantization noise that adopts digital method that single order delta sigma frequency discriminator is produced obtain indirectly after compensating.
2. frequency synthesizer as claimed in claim 1 is characterized in that
With digital DSFD module (8) to by output frequency and loop reference frequency f
RefThe fractional frequency S of decision implements the quantification of single order delta sigma and exports bit sequence M with its phase state with by DSFD (4)
I, DSFDThe phase state of the DSFD (4) of reflection is compared, and the characteristics of utilizing this two states to have basic identical phase quantization noise balance out the phase quantization noise and error signal is extracted.
3. as the frequency synthesizer of claim 2, it is characterized in that
The phase state that the mode of utilizing frequency discrimination to detect makes the phase state of digital DSFD module (8) tightly follow the tracks of DSFD (4) can not accumulate gradually to guarantee the detection error that the unknown phase difference maintains on the less numerical value and this unknown phase difference causes.
4. as the frequency synthesizer of claim 3, it is characterized in that
Quantization bit M when digital DSFD module (8)
iAnd the output bit M of DSFD (4)
I, DSFDThe error signal that outputs to loop filter (10) when identical is zero, and works as the quantization bit M of digital DSFD module (8)
iAnd the output bit M of DSFD (4)
I, DSFDNot simultaneously with the sampling phase S of digital DSFD module (8)
iAs the first approximation value of error signal output to loop filter (10) and the digital accumulator that resets (8) to zero-phase lines so that the frequency discrimination detection mode be achieved.
5. frequency synthesizer as claimed in claim 4 is characterized in that
(detection of two classes) is according to the output bit M of corresponding DSFD (4) when the phase state of digital DSFD module (8) is transferred to the zero phase state
I, DSFDThe perturbation error signal that one of the phase state output of the DSFD (4) that shows has a proper strength δ to be further reducing the output phase error of frequency synthesizer, and when the phase state that occurs digital DSFD module (8) is once more transferred to nonzero phase its quantization bit M
iThe output bit M that is different from DSFD (4)
I, DSFDSituation under (class detection) deduct the perturbation signal summation that is applied in the non-perturbation frequency error amount so that non-perturbation detects the interference that is not subjected to perturbation.
6. frequency synthesizer as claimed in claim 1 is characterized in that
The digital error signal that is produced will be added to voltage-controlled oscillator (3) by one after being become analog control voltage and the low pass filter (7) by a filtering high order harmonic component by a digital to analog converter D/A (6) again behind the digital loop filters (10) of required loop response characteristic structure.
7. frequency synthesizer as claimed in claim 6 is characterized in that
By Digital Signal Processing the feedback control loop bandwidth can dynamically be switched to obtain the fastest go into the lock speed and the highest loop error performance simultaneously.
8. frequency synthesizer as claimed in claim 1 is characterized in that
Above DSFD (4) have a reset circuit so that the initial phase of double modulus divider (1) less than 1 to accelerate lock speed.
9. frequency synthesizer as claimed in claim 2 is characterized in that
By with normalized frequency shift (FS) function Δ f
mMix with the fractional frequency S of its digital accumulator of input (8) respectively and from the control port of the direct input voltage control generator of the output of loop filter (10) (3) so that above frequency shift (FS) function can be modulated onto the signal that is synthesized in the mode of some narrowband modulation or 2 wide-band modulation.
10. frequency synthesizer as claimed in claim 9 is characterized in that
To the calibration of the modulation gain coefficient of voltage-controlled oscillator (3) is by in the control signal of its loop filter of monitoring (10) output the fractional frequency S of a low-frequency sweep signal and its digital accumulator of input (8) being mixed or loop quick lock in to several different frequencies are carried out, and can rely on voltage-controlled oscillator (3) input and introduce an amount of low-frequency sweep signal (16) and monitoring and come to carry out dynamic compensation to modulating gain coefficient by the compensating signal of loop filter (10) output.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101221230B (en) * | 2007-12-26 | 2010-10-06 | 西安华迅微电子有限公司 | Multichannel common phase noise restraining device and method thereof |
| WO2012083709A1 (en) * | 2011-08-19 | 2012-06-28 | 华为技术有限公司 | Phase discriminator implementation circuit and phase discriminator clock generation method |
| CN101345783B (en) * | 2008-08-22 | 2013-03-27 | 北京中星微电子有限公司 | System and method for noise elimination |
| CN110045399A (en) * | 2019-04-30 | 2019-07-23 | 中国人民解放军国防科技大学 | Zero crossing point deviation suppression method based on selective non-equivalent sampling |
-
2005
- 2005-02-23 CN CN 200510008583 patent/CN1825769A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101221230B (en) * | 2007-12-26 | 2010-10-06 | 西安华迅微电子有限公司 | Multichannel common phase noise restraining device and method thereof |
| CN101345783B (en) * | 2008-08-22 | 2013-03-27 | 北京中星微电子有限公司 | System and method for noise elimination |
| WO2012083709A1 (en) * | 2011-08-19 | 2012-06-28 | 华为技术有限公司 | Phase discriminator implementation circuit and phase discriminator clock generation method |
| CN110045399A (en) * | 2019-04-30 | 2019-07-23 | 中国人民解放军国防科技大学 | Zero crossing point deviation suppression method based on selective non-equivalent sampling |
| CN110045399B (en) * | 2019-04-30 | 2020-11-27 | 中国人民解放军国防科技大学 | Zero crossing point deviation suppression method based on selective non-equivalent sampling |
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