CN1819058A

CN1819058A - Memory outputting circuit and data outputting method

Info

Publication number: CN1819058A
Application number: CN 200510131405
Authority: CN
Inventors: 黄超圣
Original assignee: Via Technologies Inc
Current assignee: Via Technologies Inc
Priority date: 2005-12-12
Filing date: 2005-12-12
Publication date: 2006-08-16
Anticipated expiration: 2025-12-12
Also published as: CN100573712C

Abstract

A memorizer output stage circuit, including: the first pre-charging circuit, couple with the reading position line, the reading position line couple with the output end of some memorizer units, the first pre-charging circuit charge the reading position line to high electric potential before read some memorizers at the some level; the sensing amplifier couple with the reading position line, use to test the pressure of the reading position line, and output the result signal to the two output nodes after comparing with the high electric potential.

Description

The method of storer output-stage circuit and memory data output

Technical field

The invention relates to the output-stage circuit of storer, particularly relevant for static RAM (static random access memory, output-stage circuit SRAM).

Background technology

In storer, data are binary digit (binary bit) mostly, and each need have a circuit unit to be responsible for storing its state is 0 or 1, and this circuit unit is called storage unit, and they are arranged in rectangular array, constitute the main body of storer.In storer, selected storage unit can writing and reading by the output signal determination data of control circuit.Write fashionable, can be by input and output selecting circuit selected memory cell, again the position of desiring to write is deposited in the storage unit.Otherwise, when reading, can be by input and output selecting circuit selected memory cell, the position state that it is stored is sent out via output-stage circuit in the curtage mode.Because the curtage of reading from storage unit is very little,, make it become output again after the standard digital signals (digital signal) so will strengthen its curtage through output amplifier.

(as long as static random access memory SRAM) does not interrupt for a kind of power supply supply static RAM, just can be in the random access memory that wherein retains stored data bit.(dynamic random access memory DRAM) differently is that SRAM does not need periodically to refresh (refresh), and the data access speed of SRAM is fast than DRAM also with dynamic RAM.Therefore SRAM often is used to do the high-speed cache (cache memory) of computing machine, or as digital part random access memory to analog signal converter in the video card.

The access time of SRAM has determined the usefulness of SRAM, because should determine the speed of Collaboration between storer and control module or CPU (central processing unit) the access time.Owing to have thousands of sram cells to be coupled to output-stage circuit among the SRAM, cause and coupled a large amount of stray capacitances on the output-stage circuit, because the driving force (driving ability) of sram cell is very weak, and these stray capacitances can cause the delay in the output, just form the key factor that influences the SRAM time for reading.Therefore how to design output-stage circuit to shorten the time for reading of SRAM, just become the emphasis problem that promotes SRAM usefulness.

Summary of the invention

The invention provides a kind of storer output-stage circuit, to solve the problem that prior art exists.In one embodiment, this storer output-stage circuit comprises: first pre-charge circuit, be coupled to reading bit line, this reading bit line is coupled to the output terminal of a plurality of memory cells, and this first pre-charge circuit charges to noble potential with this reading bit line before the Destination Storage Unit in selected these a plurality of memory cells when being used to read these a plurality of memory cells.Sense amplifier, be coupled to this reading bit line, when being used to read these a plurality of memory cells, detect this in the chosen back of this Destination Storage Unit and read the online voltage in position, and with after this noble potential is compared, the output compare result signal in the inversion signal of first output node and this compare result signal in second output node.

The present invention also provides a kind of method of memory data output, is used for the data read of Destination Storage Unit is come out.The output intent of this memory data comprises the following step: at first, the precharge reading bit line is to noble potential, and this reading bit line is coupled to this Destination Storage Unit.Secondly selected this Destination Storage Unit, to read the position to this online to discharge the current potential that stores in this target reading unit.Then detect this reading bit line voltage and with the high-potential voltage source relatively.Then export compare result signal in first output node, the inversion signal of exporting this compare result signal simultaneously is in second output node.

For above and other objects of the present invention, feature and advantage can be become apparent, several preferred embodiments cited below particularly, and cooperate appended diagram, be described in detail below.

Description of drawings

Fig. 1 is the circuit diagram of a SRAM cell;

Fig. 2 is the output-stage circuit of a static RAM;

Fig. 3 is the output-stage circuit of static RAM of the present invention;

Fig. 4 a is precharging signal and the sequential chart that reads the voltage of character line;

Fig. 4 b is the sequential chart of the voltage of reading bit line;

Fig. 4 c is the sequential chart of the voltage of sensing amplifier control signal;

Fig. 4 d is the sequential chart of output signal.

[label simple declaration]

100～static RAM (SRAM) unit;

112,116～pulled transistor;

114,118～draw and fall transistor;

122,124～channel gate transistor;

126,128～read the port transistor;

WWL～write character line;

WBL～write bit line; The anti-phase bit line of WBL～write;

RWL～read character line; RBL～reading bit line;

Vdd～voltage source;

130～node;

The output-stage circuit of the static RAM of 200～correlation technique (SRAM);

202～stray capacitance;

204～pre-charge circuit (pre-charge circuit);

206～data storing circuit;

208～negative circuit (inverter);

PRE～precharging signal;

OUT～output signal;

212,214,218,222～PMOS transistor;

216,220,224～nmos pass transistor;

The output-stage circuit of 300～static RAM (SRAM);

302～stray capacitance;

304～the first pre-charge circuits;

308～the second pre-charge circuits;

306～sense amplifier (sense amplifier);

310～latch cicuit (latch);

311～phase inverter (inverter);

312,314,318,330,332,334～PMOS transistor;

316,320,322,324,326～nmos pass transistor;

336,338～NOT-AND gate;

SAC～sensing amplifier control signal;

342,344～node;

Embodiment

Fig. 1 is the circuit diagram of a SRAM cell 100.SRAM cell 100 is the storage unit of 8 transistors (8T) structure of a dual-port (dual port), and it has single output terminal.These 8 transistors comprise pulled transistor 112 and 116, draw and

fall transistor

114 and 118,

channel gate transistor

122 and 124 and read port transistor 126 and 128.Wherein pulled transistor 112 and 116 is the PMOS transistor, falls

transistor

114 and 118,

channel gate transistor

122 and 124 and read

port transistor

126 and 128 and be nmos pass transistor and draw.But still other NMOS and the transistorized configuration of PMOS of tolerable of the present invention.

Pulled transistor 112 and 116 source electrode are coupled to voltage source V dd.The drain electrode of pulled transistor 112 be coupled to channel gate transistor 124 source electrode, draw the drain electrode of falling transistor 114, with the grid of pulled transistor 116.Similarly, the drain electrode of pulled transistor 116 be coupled to channel gate transistor 122 source electrode, draw the drain electrode of falling transistor 118, with the grid of pulled transistor 112.The grid of pulled transistor 112 also is coupled to and draws the grid that falls transistor 114.Similarly, the grid of pulled transistor 116 also is coupled to and draws the grid that falls transistor 118, and the grid of reading port transistor 126.Draw the source ground that falls transistor 114 and 118.The source electrode of reading port transistor 126 is ground connection also.

Channel gate transistor

122 and 124 drain electrode are coupled to respectively and write bit line WBL (write bit line) and write anti-phase bit line WBL (write bit bar line).The grid of channel gate transistor 122,124 is coupled to and writes character line WWL (write word line).Read

port transistor

126 and 128 and couple between ground voltage and reading bit line RBL (read bit line), the grid of wherein reading port transistor 128 is coupled to and reads character line RWL (read word line).Write bit line WBL, write anti-phase bit line WBL, write character line WWL, reading bit line RBL, read character line RWL and may extend to other SRAM storage unit or other element, comprise data ranks latch (row and column latch), demoder (decoder), select driver (select driver), control logic circuit, induction amplifier, multiplexer, impact damper or the like.

Fig. 2 is the output-stage circuit 200 of a static RAM.Output-stage circuit 200 comprises pre-charge circuit (pre-charge circuit) 204, data storing circuit 206 and negative circuit (inverter) 208.Wherein transistor 212,214,218 and 222 is the PMOS transistor, and transistor 216,220 and 224 is a nmos pass transistor.The input end of output-stage circuit 200 is reading bit line RBL, and this reading bit line RBL is coupled to the output terminal of a plurality of sram cell 100.Owing to coupled sram cell strong in number via reading bit line RBL, so be equal on the reading bit line RBL and coupled very big stray capacitance, this stray capacitance is to be coupled to stray capacitance 202 expressions between reading bit line RBL and ground voltage.

Sram cell 100 among Fig. 1, wherein stored value may be 0 or 1, so node 130 is also looked the storage values of SRAM and may be noble potential or electronegative potential.If node 130 is a noble potential, then read 126 conductings of port transistor; Otherwise, then read port transistor 126 and close if node 130 is an electronegative potential.Suppose that desire reads this sram cell this moment.Before reading sram cell, must reading bit line RBL be precharged to noble potential Vdd by pre-charge circuit 204; And when charging, earlier pre-charge signal PRE being dropped to electronegative potential, just conducting of PMOS transistor 212 relatedly is precharged to noble potential with reading bit line RBL.After reading bit line RBL charging finishes, just pre-charge signal PRE is promoted to noble potential, to close PMOS transistor 212.Then, the voltage that reads character line RWL of the sram cell 100 that is selected will rise to noble potential, read port transistor 128 with conducting.

Then read

port transistor

126 and 128 and will all be conducting state if node 130 is a noble potential this moment; And because the source ground of transistor 126, therefore the voltage of related whole piece reading bit line RBL also can be pulled down to earth potential gradually.But because the existence of stray capacitance 202, so the voltage of reading bit line RBL will be slow decline, also thereby the time for reading that has prolonged SRAM.Receive the electronegative potential of reading bit line RBL when data storing circuit 206, will export noble potential.Then, the just output of forming by nmos pass transistor 224 and PMOS transistor 222 of reversal data storage circuit 206 of negative circuit 208, and export electronegative potential in output terminal OUT.

If node 130 is an electronegative potential, then read port transistor 126 and will be closed condition, can't drag down the voltage of reading bit line RBL; Therefore the voltage of whole piece reading bit line RBL still is maintained at the noble potential after the precharge.Receive the noble potential that reads character line RWL when data storing circuit 206, will export electronegative potential.Then, negative circuit 208 is the output of reversal data storage circuit 206 just, and in output terminal OUT output noble potential.

Figure 3 shows that the output-stage circuit 300 of a static RAM of the embodiment of the invention.Output-stage circuit 300 comprises first pre-charge circuit (pre-charge circuit), 304, second pre-charge circuit 308, sense amplifier (sense amplifier) 306, latch cicuit (latch) 310 and phase inverter (inverter) 311.Wherein transistor 312,314,318,330,332 and 334 is the PMOS transistor, and transistor 316,320,322,324 and 326 is a nmos pass transistor.The input end of output-stage circuit 300 is reading bit line RBL, and this reading bit line RBL is coupled to the output terminal of a plurality of sram cell 100.Owing to coupled sram cell strong in number via reading bit line RBL, so be equal on the reading bit line RBL and coupled very big stray capacitance, this stray capacitance is to be coupled to stray capacitance 302 expressions between reading bit line RBL and ground voltage.

First pre-charge circuit 304 comprises the PMOS transistor 312 that is coupled between voltage source V dd and the reading bit line RBL, and its grid is coupled to pre-charge signal PRE.Sense amplifier 306 with the voltage of reading bit line RBL with after noble potential Vdd compares, in node 342 and the anti-phase output signals of 344 outputs two.Sense amplifier 306 comprises nmos pass transistor 316,320,322,324,326 and PMOS transistor 314,318.Wherein the drain electrode of transistor 326 is coupled to the source electrode of

differential input transistor

324 and 322, and the source ground of transistor 326, its grid are coupled to sensing amplifier control signal SAC.The grid of differential input transistor 322 is coupled to reading bit line RBL, and its drain electrode is coupled to the source electrode of transistor 316.The grid of differential input transistor 324 is coupled to voltage source V dd, and its drain electrode is coupled to the source electrode of transistor 320.The grid of PMOS transistor 314 more is coupled to node 342 with the drain electrode of PMOS transistor 318 and the drain electrode of nmos pass transistor 320 with after the grid of nmos pass transistor 316 couples mutually.The grid of PMOS transistor 318 more is coupled to node 344 with the drain electrode of PMOS transistor 314 and the drain electrode of nmos pass transistor 316 with after the grid of nmos pass transistor 320 couples mutually.And the source electrode of PMOS transistor 314 and 318 is coupled to voltage source V dd.

Second pre-charge circuit 308 comprises PMOS transistor 330,332 and 334, and three's grid all is coupled to pre-charge signal PRE.The source electrode of PMOS transistor 330 is coupled to voltage source V dd, and its drain electrode is coupled to node 342.The source electrode of PMOS transistor 332 is coupled to voltage source V dd, and its drain electrode is coupled to node 344.PMOS transistor 334 is coupled between node 342 and 344.Latch cicuit 310 is used to lock and

storage node

342 and 344 voltages of exporting, and comprises NAND (NAND) door 336 and 338.Wherein an input end of NAND door 336 is coupled to node 342, and another input end is coupled to the output terminal of NAND door 338; And an input end of NAND door 338 is coupled to node 344, and another input end is coupled to the output terminal of NAND door 336.Phase inverter 311 is coupled to the output terminal of the NAND door 336 of latch cicuit 310.

Sram cell 100 among Fig. 1, wherein stored value may be 0 or 1, so node 130 is also looked the storage values of SRAM and may be noble potential or electronegative potential.If node 130 is a noble potential, then read 126 conductings of port transistor; Otherwise, then read port transistor 126 and close if node 130 is an electronegative potential.Suppose that desire reads this sram cell this moment.Before reading sram cell, must reading bit line RBL be precharged to noble potential (for example being the noble potential of voltage source V dd) by first pre-charge circuit 304; And when charging, earlier pre-charge signal PRE being dropped to electronegative potential, just conducting of PMOS transistor 312 relatedly is precharged to noble potential with reading bit line RBL.In this simultaneously, the pre-charge signal PRE in second pre-charge circuit 308 also drops to electronegative potential, and PMOS transistor 330,332 and 334 just conductings are to charge to

node

342 and 344 noble potential (for example being the noble potential of voltage source V dd).

Node

342 and 334 coupling a little for two inverting inputs of two reversed-phase outputs of sense amplifier 306 and latch cicuit 310.After reading bit line RBL charging finished, just the pre-charge signal PRE with the grid of PMOS transistor 312 was promoted to noble potential, to close PMOS transistor 312.This moment is because pre-charge signal PRE is promoted to noble potential, and PMOS transistor 330,332 and 334 also is closed, so node 342 does not couple mutually with 344 both mutual independences.Then, the voltage that reads character line RWL of the sram cell 100 that is selected will rise to noble potential, read port transistor 128 with conducting.See Fig. 4 a, wherein pre-charge signal PRE is promoted to noble potential earlier, then reads character line RWL and also rises to noble potential.

Then read

port transistor

126 and 128 and will all be conducting state if node 130 is a noble potential this moment; And because the source ground of transistor 126, therefore the voltage of related whole piece reading bit line RBL also can be pulled down to earth potential gradually.But because the existence of stray capacitance 302, so the voltage of reading bit line RBL will be slow decline, shown in Fig. 4 b.This moment will be by sense amplifier 306, detects the grid voltage of two

differential input transistors

322 and 324 and compares, and the result is exported two anti-phase each other voltages in node 342 and 344.Must get appropriate time point and start sense amplifier 306 because the voltage of reading bit line RBL descends slowlyer this moment, makes the grid voltage slippage of nmos pass transistor 322 enough big exporting the correct result that reads, but time for reading can not delayed long.When sensing amplifier control signal SAC rose to noble potential, just conducting of nmos pass transistor 326 was to start sense amplifier 306.Ask for an interview Fig. 4 c, if when sensing amplifier control signal SAC rises to noble potential as shown in dotted line c1～c3 too early, then sensing amplifier 306 can be in the noble potential of node 342 output errors, shown in the dotted line d1～d3 among Fig. 4 d.If sensing amplifier control signal SAC shown in solid line c4～c8 as when the appropriate time rises to noble potential, then sensing amplifier 306 can be in the correct electronegative potential (shown in the solid line d4～d8 among Fig. 4 d) of node 342 outputs, and in the anti-phase noble potential of node 344 outputs and node 342.

Then, the latch cicuit of being made up of

NAND door

336 and 338 310 just receives the output of sense amplifier 306 in

node

342 and 344, and continues the anti-phase noble potential of output and node 342.At last, the output of phase inverter 311 counter-rotating latch cicuits 310, and in output terminal OUT output electronegative potential.

Otherwise, if node 130 is an electronegative potential, then reads port transistor 126 and will be closed condition, can't drag down the voltage of reading bit line RBL; Therefore the voltage of whole piece reading bit line RBL still is maintained at the noble potential after the precharge.Because the differential input transistor 322 of sensing amplifier 306 and 324 grid voltage are all noble potential at this moment, can't obtain correct output.For solving this problem, the present invention specially strengthens the grid width (gate width) of differential input transistor 322, for example the grid width of differential input transistor 322 can be 1.5 times of grid width of differential input transistor 324, so that transistor 322 has less conducting resistance when making differential input transistor 322 and 324 grid be connected to identical voltage Vdd, so that the drain electrode of differential input transistor 322 produces the drain electrode of more differential input transistors 324 is big current potential pull-down capability, and then making the drain electrode of transistor 316 produce electronegative potential, the drain electrode of transistor 320 produces noble potential.Therefore receive the noble potential that reads character line RWL when sense amplifier 306, will export noble potentials in node 342, and in node 344 output electronegative potentials.Then, the latch cicuit of being made up of NAND door 336 and 338 310 just receives the output of sense amplifier 306 in node 342 and 344, and continues the anti-phase electronegative potential of output and node 342.At last, the output of phase inverter 311 counter-rotating latch cicuits 310, and in output terminal OUT output noble potential.

At last, we can be in Fig. 4 d the output result of correlation technique of the embodiment of the invention of comparison diagram 3 and Fig. 2.If sensing amplifier control signal SAC starts in suitable time point, as the c4～c8 among Fig. 4 c, then the output of its correspondence is shown in the d4～d8 among Fig. 4 d.And the output result of the correlation technique of Fig. 2 is shown in the dotted line that is designated as e among Fig. 4 d.Therefore the output of visible d4～d8 use this circuit to obtain exporting the result sooner in the comparable traditional circuit of the output stage of SRAM than the fast about 1～3ns of output of correlation technique in figure.

The present invention uses sensing amplifier in the output circuit of the SRAM of single-ended output, will amplify for little differential wave by this, to accelerate the reading speed of SRAM.Two input ends of this sensing amplifier connect voltage source V dd and reading bit line respectively.And for fear of when reading the online SRAM output in position also for noble potential, two input ends of sensing amplifier are all noble potential and cause the correctly situation of interpretation, therefore adopt asymmetrical design, the transistor gate widths that is couple to reading bit line in the sensing amplifier is increased, reducing this transistorized conducting resistance, and when being all noble potential, two input ends of sensing amplifier can obtain correct output.Therefore use this circuit can effectively reduce the time for reading of SRAM as the output-stage circuit of SRAM, and the usefulness of promoting this SRAM.

Above-mentioned several embodiment of the present invention described.Those skilled in the art should understand that they can be with embodiment of the invention modification or as the basis of designing, to reach identical purpose or the convenience of being introduced with this paper of embodiment.Those skilled in the art also should understand; above-mentioned equivalent constructions thing does not surmount spirit of the present invention and category; even those skilled in the art make various forms of modifications, replacement or change, as long as spirit still according to the invention just still belongs to protection category of the present invention.

Claims

1. storer output-stage circuit comprises:

First pre-charge circuit, be coupled to reading bit line, this reading bit line is coupled to the output terminal of a plurality of memory cells, and this first pre-charge circuit charges to noble potential with this reading bit line before the Destination Storage Unit in selected these a plurality of memory cells when being used to read this a plurality of memory cell; And

Sense amplifier, be coupled to this reading bit line, when being used to read these a plurality of memory cells, detect this in the chosen back of this Destination Storage Unit and read the online voltage in position, and with after this noble potential is compared, the output compare result signal in the inversion signal of first output node and this compare result signal in second output node.

2. storer output-stage circuit according to claim 1, wherein this sense amplifier comprises first differential input transistor and second differential input transistor, the grid of this first differential input transistor is coupled to this reading bit line, and the grid of this second differential input transistor is coupled to this noble potential, wherein the grid width of this first differential input transistor is greater than the grid width of this second differential input transistor, use the conducting resistance that reduces this first differential input transistor, so that this makes still exportable this correct compare result signal of this sensing amplifier when reading the online current potential in position for noble potential.

3. storer output-stage circuit according to claim 2, wherein this first and second differential input transistor is all nmos pass transistor.

4. storer output-stage circuit according to claim 2, wherein the grid width of this first differential input transistor is about 1.5 times of grid width of this second differential input transistor.

5. storer output-stage circuit according to claim 2, wherein this sense amplifier also comprises:

The one PMOS transistor is coupled between this noble potential and first output node, and its grid is coupled to second output node;

The 2nd PMOS transistor is coupled between this noble potential and this second output node, and its grid is coupled to this first output node;

First nmos pass transistor is coupled between the drain electrode of this first output node and this first differential input transistor, and its grid is coupled to this second input node;

Second nmos pass transistor is coupled between the drain electrode of this second output node and this second differential input transistor, and its grid is coupled to this first input node; And

The 3rd nmos pass transistor, be coupled between the source electrode and ground voltage of this first and second differential input transistor, its grid is coupled to the sensing amplifier control signal, but and this sensing amplifier control signal conducting the 3rd nmos pass transistor to start this sense amplifier.

6. storer output-stage circuit according to claim 1 also comprises second pre-charge circuit, is coupled to this first and second output node, is used to the chosen preceding current potential with this first and second output node of this Destination Storage Unit and is promoted to noble potential.

7. storer output-stage circuit according to claim 6, wherein this second pre-charge circuit comprises:

The 3rd PMOS transistor is coupled between this noble potential and this second output node, and its grid is coupled to precharging signal, but and this precharging signal conducting the 3rd PMOS transistor this second output node is promoted to noble potential;

The 4th PMOS transistor is coupled between this noble potential and this first output node, and its grid is coupled to this precharging signal, but and this precharging signal conducting the 4th PMOS transistor this first output node is promoted to noble potential; And

The 5th PMOS transistor is coupled between this first and second output node, and its grid is coupled to this precharging signal, but and this precharging signal conducting the 5th PMOS transistor to connect this first and second output node.

8. storer output-stage circuit according to claim 1, wherein this first pre-charge circuit comprises the 6th PMOS transistor, be coupled between this noble potential and this reading bit line, its grid is coupled to precharging signal, but and this precharging signal conducting the 6th PMOS transistor so that this reading bit line is promoted to noble potential.

9. storer output-stage circuit according to claim 1 also comprises latch cicuit, is coupled to this sensing amplifier through this first and second output node, is used to store this compare result signal that this sense amplifier is exported.

10. storer output-stage circuit according to claim 9, wherein this latch cicuit comprises:

First NOT-AND gate, its two input end is coupled to the output terminal of this first output node and second NOT-AND gate respectively; And

This second NOT-AND gate, its two input end is coupled to the output terminal of this second output node and this first NOT-AND gate respectively;

11. storer output-stage circuit according to claim 9 also comprises phase inverter, is coupled to this latch cicuit, is used for this compare result signal is anti-phase and be output in output terminal.

12. storer output-stage circuit according to claim 1, wherein each these a plurality of memory cell all comprises:

First reads the port transistor, be coupled between second reading outbound port transistor drain and this reading bit line, its grid is coupled to and reads character line, this first reads the port transistor so that this reading bit line couples mutually with this second reading outbound port transistor drain and but this reads the character line conducting, and when this voltage that reads character line that is coupled to this SRAM cell rose to noble potential, just can select a memory cell was this Destination Storage Unit; And

This second reading outbound port transistor, its source electrode is coupled to this electronegative potential, and its grid voltage is looked the stored position of this SRAM cell and is noble potential or electronegative potential;

Wherein selected when this SRAM cell, and the transistorized grid voltage of this second reading outbound port is when being noble potential, but conducting this first with this second reading outbound port transistor, and the current potential of drop-down this reading bit line is to electronegative potential.

13. storer output-stage circuit according to claim 1, wherein this circuit is the output-stage circuit of static RAM.

14. the method for a memory data output is used for the data read of Destination Storage Unit is come out, and includes:

The precharge reading bit line is to noble potential, and this reading bit line is coupled to this Destination Storage Unit;

Selected this Destination Storage Unit, to read the position to this online to discharge the current potential that stores in this target reading unit;

Detect this reading bit line voltage and with the high-potential voltage source relatively; And

The output compare result signal is in first output node, and the inversion signal of exporting this compare result signal simultaneously is in second output node.

15. memory data output intent according to claim 14, also be contained in selected this Destination Storage Unit before, the current potential of this first output node and second output node is promoted to this noble potential.

16. memory data output intent according to claim 14 also comprises the anti-phase back output of this compare result signal.

17. memory data output intent according to claim 14, wherein when this memory data is 1, make the voltage of this reading bit line be pulled to electronegative potential, relatively behind the voltage of this reading bit line and this high-potential voltage source, in this first output node output electronegative potential, in this second output node output noble potential.

18. memory data output intent according to claim 14 wherein also comprises and utilizes control signal in appropriate time point relatively voltage and this high-potential voltage source of this reading bit line.

19. memory data output intent according to claim 14, wherein when this memory data is 0, the voltage of reading bit line is pulled to noble potential, relatively behind the voltage of this reading bit line and this high-potential voltage source, in this first output node output noble potential, in this second output node output electronegative potential.

20. memory data output intent according to claim 14, wherein utilize asymmetric sensing amplifier to make, can distinguish the difference of voltage and this voltage source of this reading bit line when the voltage charging of this reading bit line during extremely as the noble potential in this high-potential voltage source.

21. memory data output intent according to claim 14, wherein this method is applicable to static RAM.