CN1808649A - Multilayer chip capacitor - Google Patents
Multilayer chip capacitor Download PDFInfo
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- CN1808649A CN1808649A CNA2005100695251A CN200510069525A CN1808649A CN 1808649 A CN1808649 A CN 1808649A CN A2005100695251 A CNA2005100695251 A CN A2005100695251A CN 200510069525 A CN200510069525 A CN 200510069525A CN 1808649 A CN1808649 A CN 1808649A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 241
- 239000000463 material Substances 0.000 claims description 17
- 239000003086 colorant Substances 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 239000004033 plastic Substances 0.000 claims description 3
- 229920003023 plastic Polymers 0.000 claims description 3
- 239000005315 stained glass Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 description 13
- 239000011248 coating agent Substances 0.000 description 10
- 238000000576 coating method Methods 0.000 description 10
- 230000004907 flux Effects 0.000 description 10
- 230000006872 improvement Effects 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000004069 differentiation Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
- H01G2/02—Mountings
- H01G2/06—Mountings specially adapted for mounting on a printed-circuit support
- H01G2/065—Mountings specially adapted for mounting on a printed-circuit support for surface mounting, e.g. chip capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
- H01G4/08—Inorganic dielectrics
- H01G4/12—Ceramic dielectrics
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
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- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
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- Inorganic Chemistry (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Ceramic Capacitors (AREA)
Abstract
A multilayer chip capacitor, which reduces ESL generated due to current flowing through external electrodes and assures an improved mechanical strength. The multilayer chip capacitor includes an upper dummy layer and a lower dummy layer; a plurality of internal electrodes interposed between the upper and lower dummy layers; and external electrodes connected to the internal electrodes, wherein the thickness of the lower dummy layer is smaller than the thickness of the upper dummy layer.
Description
Related application
The present invention requires korean application 2005-5513 number submitted on January 20th, 2005 and the priority of the korean application submitted on February 28th, 2005 2004-16874 number, and its full content is hereby expressly incorporated by reference.
Technical field
The present invention relates to a kind of multi-layer chip capacitor, more specifically, relate to a kind of multi-layer chip capacitor that in high-frequency circuit, has low equivalent series inductance (ESL).
Background technology
Usually, multi-layer chip capacitor has little size, has realized high electric capacity, and is easy to be installed on the substrate, thereby is widely used in various electronic equipments.Multi-layer chip capacitor is used as the capacity cell of high-frequency circuit, especially is used as the decoupling capacitor in the power circuit that is arranged in LSI.In order to use multi-layer chip capacitor in high-frequency circuit, this multi-layer chip capacitor must have low ESL value.Along with the high frequency and the high electric current trend of electronic equipment, above-mentioned requirements improves constantly.
United States Patent (USP) the 5th, 880 has proposed in cross one another arrangement for No. 925, with each pin configuration of first internal electrode each pin configuration location in abutting connection with second internal electrode, to reduce the ESL of multi-layer chip capacitor.Above-mentioned arrangement has been shown among Fig. 1 a.
Fig. 1 a is the exploded perspective view that the internal electrode shape of traditional multi-layer chip capacitor is shown.Fig. 1 b is a schematic perspective view of utilizing traditional multi-layer chip capacitor that the internal electrode of Fig. 1 a makes.Fig. 1 c is the sectional view that the multi-layer chip capacitor of Fig. 1 b is got X-X ' line.With reference to Fig. 1 a, internal electrode 14 forms on dielectric layer 11a that a plurality of potteries are made and 11b.Internal electrode 14 is divided into first internal electrode 12 and second internal electrode 13 with opposed polarity.The lead-in wire 16 of first internal electrode 12 and the lead-in wire 17 of second internal electrode 13 are connected to (in Fig. 1 b) in the outer electrode 18 respectively.In integrated layout, the lead-in wire 17 of contiguous second internal electrode 13 in lead-in wire 16 positions of first internal electrode 12.Because it is inequality to offer the polarity of voltage of adjacent electrode, so between these contiguous lead-in wires, be cancelled by the magnetic flux that produces from the outer electrode high-frequency current.Therefore, reduced ESL.Yet the reduction of this ESL does not satisfy the desired degree of decoupling capacitor that is used for high-frequency circuit.
Shown in Fig. 1 b and Fig. 1 c, in traditional multi-layer chip capacitor 10, internal electrode 14 is positioned at the core of capacitor main body 20, so that the cross section of capacitor main body 20 has with respect to the laterally zygomorphic structure of center line (L).That is, capacitor main body 20 comprises following virtual level 51, goes up virtual level 52 and the active coating 50 between following virtual level and last virtual level 51 and 52.Lower floor has identical thickness (a) with upper strata 51 and 52.Active coating 50 has a plurality of internal electrodes 14.As shown in Figure 1a, dielectric layer 11a and 11b are placed between the internal electrode 14. Virtual level 51 and 52 is corresponding to having the zone that mainly contains the internal electrode that helps electric capacity.On the contrary, active coating 50 is corresponding to the zone that mainly contains the internal electrode that helps electric capacity. Virtual level 51 and 52 is used to protect internal electrode 14, and is used to guarantee the appointed thickness of multi-layer chip capacitor 10.Following virtual level and last virtual level 51 and 52 are by making with the material identical materials of dielectric layer 11a and 11b.
When internal electrode 14 was positioned at the core of capacitor main body 20, the distance from the bottom surface (being attached to the surface of the liner of substrate) of the multi-layer chip capacitor 10 that is installed on substrate to nethermost internal electrode 14 was elongated.That is, the thickness of following virtual level 51 (a) relatively increases by the core that internal electrode 14 is positioned capacitor main body 20.When increasing the thickness (a) of virtual level 51 down,, electric current partly will increase because flowing through the ESL that the outer electrode 18 that comes from the bottom surface produces.Especially, in the multi-layer chip capacitor that has more than a plurality of terminals of two terminals, above-mentioned ESL has partly occupied the sizable part among the whole ESL of multi-layer chip capacitor.
Fig. 1 d is the sectional view that the multi-layer chip capacitor of Fig. 1 b is got A-A ' line.Fig. 1 e is the schematic diagram of model of equivalent series inductance that the multi-layer chip capacitor of Fig. 1 d is shown.As shown in Fig. 1 e, traditional multi-layer chip capacitor 10 has the inductance (L among the regional H
h) and regional V
1And V
2In inductance (L
v).Thereby the total inductance of multi-layer chip capacitor is L
h+ 2L
vTherefore, along with virtual level 51 thickness (a) increase down, the ESL of capacitor will increase.
In addition, in traditional multi-layer chip capacitor 10, each internal electrode 14 has four lead-in wires, and it has caused less ESR (equivalent series resistance).When each internal electrode 12 or 13 has as shown in Figure 1a four lead-in wires, will be connected in parallel by the resistance that lead-in wire is produced.Therefore, the all-in resistance of capacitor 10 will become very little.If ESR is very little, will be difficult to satisfy target impedance so, and can not stably designs distribution system.
In order to prevent that ESR from reducing too much, United States Patent (USP) the 6th, 441 proposes each internal electrode and has a lead-in wire to increase ESR for No. 459.Yet according to this United States Patent (USP), ESL will increase, and ESR is uncontrollable.
In order to solve the problem that ESL increases, as shown in Figure 2, following virtual level 51 ' and last virtual level 52 ' can have the thickness (b ') that reduces, thereby the multi-layer chip capacitor that obtains approaching.Yet when multi-layer chip capacitor was too thin, the mechanical strength of multi-layer chip capacitor will descend.For example, when multi-layer chip capacitor was designed to thickness less than 0.3mm, capacitor will be easy to fracture or damage in its manufacture process, thereby had reduced the production rate of chip capacitor.Especially, maybe when the multi-layer chip capacitor that will make is installed on the substrate, the above-mentioned mechanical failure of this capacitor will often take place when capacitor main body polishes after sintering.
Summary of the invention
Therefore, to have made the present invention in order addressing the above problem, to have the object of the present invention is to provide a kind of multi-layer chip capacitor, it has reduced owing to electric current flows through the ESL part that outer electrode produces from the bottom surface of capacitor.
Another object of the present invention is to provide a kind of multi-layer chip capacitor, it has enough integral thickness, thereby has reduced mechanical failure and had the product yield of improvement.
Another purpose of the present invention is to provide a kind of multi-layer chip capacitor, and it can prevent that the ESR minimizing is too many and can easily control ESR.
According to an aspect of the present invention, the multi-layer chip capacitor that is provided comprises: go up virtual level and following virtual level; A plurality of internal electrodes place between virtual level and the following virtual level; And outer electrode, be connected with internal electrode, wherein descend the thickness of the thickness of virtual level less than last virtual level.
Preferably, the ratio of the thickness of the thickness of following virtual level and last virtual level is 0.8 or less than 0.8.
Because down the thickness of virtual level is less than the thickness of last virtual level, so multi-layer chip capacitor has the ESL value of decline, and has enough mechanical strengths.
About having, multi-layer chip capacitor of the present invention under the situation of unsymmetrical section structure, must distinguish the upper surface and the lower surface of capacitor, so that this capacitor correctly is installed on the substrate.Realize the differentiation of capacitor upper surface and lower surface by the different colours that upper surface and lower surface presented that detects capacitor.Alternatively, on capacitor, be provided for distinguishing the mark of capacitor upper surface and lower surface.This mark is by making as stained glass.
On the contrary, about having, multi-layer chip capacitor of the present invention under the situation of symmetrical section structure, needn't distinguish the upper surface and the lower surface of capacitor.Therefore, no longer need mark.Need not distinguish upper surface and lower surface just can be installed in this capacitor on the substrate.
According to embodiments of the invention, thin dielectric layer is formed between a plurality of internal electrodes; Last virtual level and following virtual level are by making with the material identical materials of thin dielectric layer.In this case, be used for the thickness of the thickness of virtual level, so improved the mechanical strength of capacitor greater than following virtual level.
According to embodiments of the invention, thin dielectric layer is formed between a plurality of internal electrodes; Last virtual level and following virtual level are by making with the material identical materials of thin dielectric layer; And go up enhancement layer and be formed on the virtual level, and by making with the material of thin dielectric layer material inequality.Last enhancement layer has increased the integral thickness of capacitor, and has improved the mechanical strength of capacitor.Last enhancement layer is to be made by plastics, glass or pottery.
According to still another embodiment of the invention, on last virtual level, can also comprise one or more internal electrodes.In this case, multi-layer chip capacitor can have unsymmetrical section structure or symmetrical section structure up and down up and down.
Multi-layer chip capacitor of the present invention can be the multi-layer chip capacitor with a plurality of outer electrodes of the lead-in wire that is provided with mutual cross arrangement.For example, multi-layer chip capacitor of the present invention can be 8,10 or 12 terminals type multi-layer chip capacitors.Multi-layer chip capacitor of the present invention can also be two terminals type multi-layer chip capacitors.
According to a further aspect in the invention, the multi-layer chip capacitor that is provided comprises: go up virtual level and following virtual level; A plurality of first internal electrodes and second internal electrode place between virtual level and the following virtual level; And the outer electrode that is connected with internal electrode, wherein descending the thickness of the thickness of virtual level less than last virtual level, one or two in first and second internal electrode has one or more grooves.First and second electrode is separately also alternately stacked by dielectric layer.Each first and second electrode has one or more lead-in wires that are connected to outer electrode.
According to one embodiment of present invention, each first and second electrode has a pair of adjacent rectangular conductive pattern.To in the conductive pattern each, towards each conductive pattern, be formed centrally one or more grooves at this, to change sense of current in the conductive pattern from one or more sides.
In this case, electric current flows through this adjacent area to conductive pattern along direction respect to one another.This can have identical polarity to conductive pattern.Alternatively, this can have different polarity to conductive pattern.
According to one embodiment of present invention, electric current can flow in first and second internal electrode along orthogonal direction.
In this case, each first internal electrode can have the first rectangular conductive pattern, and two grooves that extend to the center of first conductive pattern from two opposite sides of first conductive pattern are formed at wherein.Each second internal electrode can have the second rectangular conductive pattern, wherein when the groove that makes second conductive pattern extends from the center of relative two side direction, second conductive pattern of second conductive pattern, in second conductive pattern, form two grooves perpendicular to the groove of first conductive pattern.
Alternatively, each first electrode can have a pair of first conductive pattern that separates by first groove.In this case, each second electrode has rectangle second conductive pattern, wherein when making second groove when extend at the center of relative two side direction, second conductive pattern of second conductive pattern, forms two second grooves perpendicular to first groove in second conductive pattern.
Also alternatively, each first electrode can have first conductive pattern, and each second electrode has a pair of second conductive pattern that separates by groove.
Used in this manual term definition is as follows:
" virtual level (dummy layer) " do not have the zone that electric capacity is had the internal electrode of substantive contribution." active coating (active layer) " has to have substantive contribution electric capacity to be had the zone of the internal electrode of substantive contribution to electric capacity.Therefore, multi-layer chip capacitor can have the active coating more than.
" following virtual level " is arranged on the bottom surface to the virtual level between the minimum internal electrode of multi-layer chip capacitor." go up virtual level " and be arranged on the most close virtual level down and layer virtual level that separates that be activated.Thereby other internal electrode or active coating can be arranged on the virtual level.And other virtual level can be arranged on the virtual level (sees Figure 10 and Figure 11).The bottom surface of capacitor (or lower surface) is the surface that is attached to the substrate liner when being installed in capacitor on the substrate.The upper surface of capacitor is and the bottom surface facing surfaces.
Description of drawings
Carry out following detailed description by the reference accompanying drawing, above-mentioned and other advantage of the present invention will become more apparent, wherein:
Fig. 1 a is the exploded perspective view of shape that the internal electrode of traditional multi-layer chip capacitor is shown;
Fig. 1 b is a schematic perspective view of utilizing traditional multi-layer chip capacitor that the internal electrode of Fig. 1 a makes;
Fig. 1 c is the sectional view that the multi-layer chip capacitor of Fig. 1 b is got X-X ' line;
Fig. 1 d is the sectional view that the multi-layer chip capacitor of Fig. 1 b is got A-A ' line;
Fig. 1 e is the schematic diagram of model of equivalent series inductance that the multi-layer chip capacitor of Fig. 1 d is shown;
Fig. 2 is the sectional view that another traditional multi-layer chip capacitor is shown;
Fig. 3 is the schematic perspective view of multi-layer chip capacitor according to an embodiment of the invention;
Fig. 4 is a sectional view of getting Y-Y ' line of Fig. 3;
Fig. 5 is the schematic perspective view of multi-layer chip capacitor according to another embodiment of the present invention;
Fig. 6 is the stereogram of multi-layer chip capacitor according to another embodiment of the present invention, shows the inside of multi-layer chip capacitor;
Fig. 7 is a sectional view of getting Z-Z ' line of Fig. 6;
Fig. 8 is the sectional view of multi-layer chip capacitor according to still another embodiment of the invention;
Fig. 9 is the schematic perspective view of change embodiment of the multi-layer chip capacitor of Fig. 3;
Figure 10 is the sectional view of multi-layer chip capacitor according to still another embodiment of the invention;
Figure 11 is the sectional view of multi-layer chip capacitor according to still another embodiment of the invention;
Figure 12 is the plane graph that illustrates according to the internal electrode of the multi-layer chip capacitor of the first embodiment of the present invention;
Figure 13 is the plane graph that the internal electrode of multi-layer chip capacitor according to a second embodiment of the present invention is shown;
Figure 14 is the plane graph of internal electrode that the multi-layer chip capacitor of a third embodiment in accordance with the invention is shown;
Figure 15 is the plane graph of internal electrode that the multi-layer chip capacitor of a fourth embodiment in accordance with the invention is shown;
Figure 16 is the plane graph that the internal electrode of multi-layer chip capacitor according to a fifth embodiment of the invention is shown;
Figure 17 is the plane graph that the internal electrode of multi-layer chip capacitor according to a sixth embodiment of the invention is shown; And
Figure 18 to Figure 21 is the plane graph that the arrangement of the outer electrode of multi-layer chip capacitor according to various embodiments of the present invention and internal electrode is shown.
Embodiment
Now, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.Embodiments of the invention can be made various changes.The foregoing description is to understand for convenience the present invention better, and and non-limiting scope of the present invention.Correspondingly, for the sake of clarity, the shape of each element of accompanying drawing and size may be exaggerated, and components identical (it is substantially the same), even it occurs in different accompanying drawings, also will be denoted by the same reference numerals.
Fig. 3 is the schematic perspective view of multi-layer chip capacitor according to an embodiment of the invention.With reference to Fig. 3, multi-layer chip capacitor 100 comprises capacitor main body 120, and a plurality of internal electrodes 114 are formed at wherein; And a plurality of outer electrodes 118, be formed at the outer surface of capacitor main body 120.Internal electrode 114 is divided into first internal electrode 112 and second internal electrode 113, and it has different polarity, and the upper surface that keeps clear of capacitor 100 near the lower surface of capacitor 100 is provided with.Internal electrode 114 has a plurality of leads, it is arranged close to each otherly and crosses one another.The present invention can be applied to have any multi-layer chip capacitor of other internal electrode structures, and the chip capacitor that is applied to have the internal electrode structure shown in Fig. 1 a.
In Fig. 3, outer electrode 118 extends to the upper end of capacitor main body 120 from the bottom surface of capacitor main body 120.Alternatively, outer electrode 118 can only extend to the height of the highest internal electrode 112 from the bottom surface of capacitor main body 120.Fig. 9 shows the foregoing description.With reference to Fig. 9, multi-layer chip capacitor 100 ' outer electrode 118 ' from the bottom surface of capacitor main body 120 extend to position corresponding to the highest internal electrode 112, and be not basically the height of the highest internal electrode 112 of the ratio of capacitor main body 120 outer surfaces more eminence form.
Fig. 4 is a sectional view of getting Y-Y ' line of Fig. 3.With reference to Fig. 4, capacitor main body 120 comprises following virtual level 151, goes up virtual level 152 and a plurality of internal electrode 114 that places down between virtual level and last virtual level 151 and 152.Dielectric layer forms between a plurality of internal electrodes 114.Following virtual level and last virtual level 151 and 152 are by making with the material identical materials of dielectric layer.As shown in Figure 4, the thickness of following virtual level 151 (b) is less than the thickness (a) of last virtual level 152.Thereby capacitor main body 120 has the unsymmetrical section structure with respect to center line (M).Preferably, the ratio of the thickness (a) of the thickness of following virtual level 151 (b) and last virtual level 152 is 0.8 or less than 0.8.
By forming above-mentioned unsymmetrical section structure, reduced the thickness (b) of time virtual level 151, thereby reduced owing to electric current flows through the ESL value that outer electrode 118 produces.In addition, because last virtual level 152 has the thickness (a) bigger than the thickness (b) of following virtual level 151, so multi-layer chip capacitor 100 has enough integral thickness, thereby the mechanical strength that has prevented capacitor 100 descends.
As mentioned above, because multi-layer chip capacitor 100 has the unsymmetrical section structure, so when being installed on capacitor 100 on the substrate, must distinguish the upper surface and the lower surface of capacitor 100.That is, in order to reduce owing to electric current flows through the ESL value that outer electrode 118 produces, capacitor is mounted on the substrate towards the mode of substrate by descending virtual level 151.The differentiation of above-mentioned capacitor 100 upper surfaces and lower surface realizes by the different colours that allows sensor capacitor 100 upper surface and lower surfaces to be presented.
Especially, because the thickness (b) of following virtual level 151 is less than the thickness (c) of last virtual level 152, so when from visual observation capacitor 100, the lower surface of capacitor 100 presents the color darker than the color of the upper surface of capacitor 100.Usually, following virtual level and last virtual level 151 and 152 are to be made by translucent dielectric substance, and internal electrode 114 presents dead color (for example, navy blue).Therefore, because following virtual level 151 has the thickness (b) littler than the thickness (c) of last virtual level 152, so the lower surface of capacitor 100 presents blueness, and the upper surface of capacitor 100 presents light brown.By allowing the color that upper surface and lower surface presented of sensor by capacitor 100, the upper surface and the lower surface of capacitor 100 are distinguished mutually, and the lower surface of capacitor 100 is installed on printed circuit board (PCB) or the receiving belt (receipt tape).
Distinguishing the upper surface of capacitor and the another kind of method of lower surface, is to make marks on the upper surface of capacitor.Fig. 5 shows multi-layer chip capacitor, and it has the mark that is used to distinguish this capacitor upper surface and lower surface.
Except being used to distinguish the mark 130 of capacitor 200 upper and lowers in printing on the upper surface of capacitor 200, multi-layer chip capacitor 200 shown in Figure 5 is identical with multi-layer chip capacitor 100 shown in Figure 3.By typographic(al) mark 130 on multi-layer chip capacitor 200 upper surfaces, can distinguish the upper surface and the lower surface of capacitor 130 easily and exactly.For example, on dielectric layer, form the mark of designated shape, and then dielectric layer is layered on capacitor 200 top, and obtain the mark 130 of multi-layer chip capacitor 200 by utilizing silk screen printing.The mark that utilizes silk screen printing to form is made (for example, presenting navy blue) by the stained glass material.By allowing the mark 130 of sensor, can distinguish the upper surface and the lower surface of capacitor 200 easily and exactly with the capacitor 200 of said process printing.
Although the foregoing description has been described the multi-layer chip capacitor with 8 outer electrodes respectively, the present invention is not limited thereto.For example, as shown in Figure 6, the present invention can be applicable to have the multi-layer chip capacitor of two outer electrodes.
Fig. 6 is the stereogram of multi-layer chip capacitor 300 according to another embodiment of the present invention, show the inside of multi-layer chip capacitor 300, and Fig. 7 is a sectional view of getting Z-Z ' line of Fig. 6.With reference to Fig. 6 and Fig. 7, external terminal 318 and 319 forms in the both sides of capacitor main body 320 respectively, and a plurality of internal electrodes 314 form in capacitor main body 320.Internal electrode 314 is divided into first internal electrode 312 and second internal electrode 313 with opposed polarity.First internal electrode 312 and second internal electrode 313 are connected to outer electrode 318 and 319 respectively, and alternately stacked.
As shown in Figure 7, above-mentioned two terminals type multi-layer chip capacitors 300 have unsymmetrical section structure up and down, and the thickness (d) of following virtual level 351 is less than the thickness (e) of last virtual level 352.In order to be easy to distinguish the upper surface and the lower surface of two terminals type multi-layer chip capacitors 300 shown in Figure 6, on capacitor 300 upper surfaces, be provided with mark.The present invention can be applicable to prepare the multi-layer chip capacitor of the outer electrode that various numbers are arranged, and above-mentioned multi-layer chip capacitor with 8 and 2 outer electrodes.
Fig. 8 is the sectional view of multi-layer chip capacitor according to still another embodiment of the invention.With reference to Fig. 8, multi-layer chip capacitor 400 is included under the inner electrode 414 the following virtual level 451 that forms, and on forming on the internal electrode 414 virtual level 452.Between a plurality of internal electrodes 414, thin dielectric layer is set.Especially, in the present embodiment, last virtual level 452 has double-layer structure.Particularly, last virtual level 452 comprises virtual dielectric layer 454, and on forming on the last virtual dielectric layer 454 enhancement layer 453.Last enhancement layer 453 is used to strengthen the mechanical strength of capacitor 400.For example, last enhancement layer 453 is to be made by plastics, glass or ceramic material.The material identical materials of following virtual level 451 and last virtual dielectric layer 454 usefulness and the dielectric layer between internal electrode 414 is made.
In present embodiment shown in Figure 8, the thickness of following virtual level 451 (f) is less than the thickness (i) of last virtual level 452.That is, the little gross thickness that thickness (g) with the thickness (h) of last enhancement layer 453 of virtual dielectric layer 454 of the thickness of following virtual level 451 (i), thus reduced owing to electric current flows through the ESL value that outer electrode produces.In addition, be layered in the mechanical strength that has improved capacitor 400 on the virtual dielectric layer 454 by going up enhancement layer 453.
Figure 10 and Figure 11 are the sectional views of multi-layer chip capacitor according to still another embodiment of the invention.In these embodiments, on last virtual level 552 and 652, formed additional internal electrode and/or virtual level.
With reference to Figure 10, capacitor 500 comprises following virtual level 551, goes up virtual level 552 and has the active coating of inserting between the virtual level 551 and 552 550.The thickness of following virtual level 551 (j) is less than the thickness (k) of last virtual level 552.In addition, internal electrode 524,534 is arranged on the virtual level 552.This extra play can be used for control capacittance to desirable value.The capacitor of Figure 10 has unsymmetrical section structure up and down.Be used for to distinguish the upper surface and the lower surface of capacitor, preferably, on the upper surface of capacitor, mark be set.
On the contrary, the capacitor of Figure 11 has symmetrical section structure up and down.As shown in figure 11, capacitor 600 comprises following virtual level 651, first active coating 650 and goes up virtual level 652.In addition, capacitor 600 also comprises second active coating 600 and the highest virtual level 661 on last virtual level 652.The thickness of last virtual level 652 (m) is greater than the thickness (1) of following virtual level 651.The highest virtual level 661 has the thickness (1) identical with the thickness of following virtual level 651.First and second active coating 650,660 has a plurality of internal electrodes respectively.Because capacitor 600 has symmetrical section structure up and down, therefore do not need to distinguish the upper surface and the lower surface of capacitor 600.Thereby, need not distinguish upper surface and lower surface, just capacitor can be installed in (not shown) on the substrate.
According to the present invention, capacitor can have the internal electrode structure, and it also can reduce ESL and control ESR, and ESR can not reduced too much.In this electrode structure, form one or more grooves.
Figure 12 to Figure 17 is the plane graph that illustrates according to the shape of the internal electrode that comprises in the capacitor of the present invention.
Figure 12 is the plane graph that illustrates according to the shape of the internal electrode of the capacitor of the first embodiment of the present invention.With reference to Figure 12, each first electrode 1041 and second electrode 1042 have the lead-in wire 1413,1414,1423,1424 (among Fig. 3) that is connected to outer electrode 118.First and second internal electrode has the voltage of opposed polarity, thereby has offset the magnetic flux that produces owing to high-frequency current.
In addition, each first internal electrode 1041 and second internal electrode 1042 have setting first conductive pattern 1411,1421 and second conductive pattern 1412,1422 at grade.A plurality of leads 1413,1414,1423,1424 is connected to the positive pole (+) or the negative pole (-) of outer electrode.
First conductive pattern 1411 on the same plane or 1421 has different polarity with second conductive pattern 1412 or 1422.Adjacent domain in first conductive pattern 1411 or 1421 and second conductive pattern 1412 or 1422, the electric current of flowing opposite direction, thereby offset the magnetic flux that produces owing to this electric current.In addition, because rightabout electric current is mobile in the adjacent domain of first internal electrode 1041 and second internal electrode 1042, so the magnetic flux between first and second internal electrode 1041,1042 has been cancelled.
In each first conductive pattern 1411 or 1421 and second conductive pattern 1412 or 1422, formed respectively from the groove of opposite side towards the conductive pattern center.Thereby in first and second conductive pattern, magnetic flux also has been cancelled.Therefore ESL is further reduced.
In addition, because each groove that extends to the conductive pattern center has prolonged path of current in the conductive pattern, so it is too many to have prevented that ESR from reducing.And by the length of regulating tank, may command ESR is to desirable value.Therefore, the target impedance that is content with very little.In addition, distribution system also can design more stablely.
In the above-described embodiments, in a conductive pattern, only form a groove.Yet, in each conductive pattern, can form two or more than two grooves.In addition, each first internal electrode or second internal electrode can have only conductive pattern.In addition, each internal electrode lead-in wire that can have a varying number maybe can have only lead-in wire.
Figure 13 is the plane graph that the internal electrode of capacitor according to a second embodiment of the present invention is shown.With reference to Figure 13, the groove that forms in first conductive pattern 1511 or 1521 and second conductive pattern 1512 or 1522 is provided with in the opposite direction.Shown in the arrow among Figure 13, rightabout electric current flows between first conductive pattern and second conductive pattern, flows between first and second adjacent internal electrode, and flows between the adjacent domain of each internal electrode.Therefore, the magnetic flux that produces owing to this electric current is cancelled, thereby has also reduced ESL.In addition, can also control ESR by groove.Label 1513,1514,1523 and 1524 expression lead-in wires.
According to the present invention, between first and second internal electrode, electric current can flow along orthogonal direction.Figure 14 to Figure 17 shows these embodiment.
Figure 14 is the plane graph of internal electrode that the multi-layer chip capacitor of a third embodiment in accordance with the invention is shown.With reference to Figure 14, each first internal electrode 1061 and (second) internal electrode 1062 have a conductive pattern 1611,1621 respectively.In each conductive pattern 1611,1621, two grooves 1612,1613 or 1622,1623 are formed by two grooves that are arranged in a straight line.In addition, the groove 1612,1613 in the conductive pattern 1611 of first internal electrode 1061 is perpendicular to the groove in the conductive pattern 1621 of second internal electrode 1,062 1622,1623.In this case, the electric current of vertical direction flows between first internal electrode and second internal electrode, thereby has offset magnetic flux.Label 1614 and 1624 expression lead-in wires.
Figure 15 is the plane graph of internal electrode that the multi-layer chip capacitor of a fourth embodiment in accordance with the invention is shown.With reference to Figure 15, first internal electrode 1071 has a pair of conductive pattern 1711 that separates by groove 1712.Second internal electrode 1072 has one has two grooves 1722,1723 that are arranged as straight line to be formed at wherein conductive pattern 1721.The groove 1712 of first electrode 1071 is perpendicular to the groove 1722,1723 that forms in conductive pattern 1721.Therefore, the electric current of vertical direction is along flowing between first internal electrode and second internal electrode, thereby offset magnetic flux.Label 1713 and 1724 expression lead-in wires.
Figure 16 is the plane graph that the internal electrode of multi-layer chip capacitor according to a fifth embodiment of the invention is shown.With reference to Figure 16, first internal electrode 1081 has one has two grooves 1813,1822 that are arranged as straight line to be formed at wherein conductive pattern 1811.Second internal electrode 1082 has two conductive patterns 1821 that separated by groove 1822.Groove 1813 is perpendicular to groove 1822.Therefore, the electric current of vertical direction is along flowing between first internal electrode and second internal electrode, thereby offset magnetic flux.Label 1812,1814 and 1823 expression lead-in wires.
Figure 17 is the plane graph that the internal electrode of multi-layer chip capacitor according to a sixth embodiment of the invention is shown.With reference to Figure 17, first internal electrode 1091 has a conductive pattern 1912 that does not have groove.Second electrode 1092 has the pair of conductive pattern 1921 that is separated by groove 1922.In this case, the electric current of vertical direction also is along mobile between first internal electrode and second internal electrode, thereby has offset magnetic flux.Label 1912 and 1913 expression lead-in wires.
Figure 18 to Figure 21 is the plane graph that the arrangement of the outer electrode of multi-layer chip capacitor according to various embodiments of the present invention and internal electrode is shown.In Figure 18 to Figure 21, left-hand column shows first internal electrode, and right-hand column shows second internal electrode.According to the embodiment shown in Figure 18 to Figure 21, the electric current of different directions, along mobile between the pair of conductive pattern that is separated by groove and flows among having the conductive pattern of one or more grooves along flowing between first and second internal electrode.In addition, the groove that forms in conductive pattern has prolonged current path, thereby has prevented that ESR from reducing too much.In addition, by selecting the groove of appropriate length, can control ESR.
Embodiment
The applicant has carried out following experiment, the ESL characteristic of traditional multi-layer chip capacitor and multi-layer chip capacitor according to three examples of the present invention (first to the 3rd embodiment) are compared, with the improvement of the ESL characteristic of observing multi-layer chip capacitor of the present invention.The tradition multi-layer chip capacitor has the symmetrical section structure shown in the internal electrode structure shown in Fig. 1 a and Fig. 1 c.The capacitor of first to the 3rd example has internal electrode structure shown in Figure 13.The multi-layer chip capacitor of first embodiment has the structure of unsymmetrical section up and down shown in Figure 4, the capacitor of second embodiment has the structure of unsymmetrical section up and down shown in Figure 10, and the capacitor of the 3rd embodiment has the structure of symmetrical section up and down shown in Figure 11.The multi-layer chip capacitor of all traditional multi-layer chip capacitors and three embodiment of the present invention all has 8 outer electrodes.
The multi-layer chip capacitor of tradition multi-layer chip capacitor and these three embodiment is of a size of 2.0mm * 1.25mm, highly is 0.85mm.Especially, the multi-layer chip capacitor of three embodiment of the present invention comprises that respectively thickness is the following virtual level of 50 μ m.On the other hand, traditional multi-layer chip capacitor comprises following virtual level and the last virtual level of thickness greater than 350 μ m.The multi-layer chip capacitor of tradition multi-layer chip capacitor and three embodiment of the present invention utilizes nickel (Ni) electrode as internal electrode, utilizes copper (Cu) electrode as outer electrode.The electric capacity of the multi-layer chip capacitor of tradition multi-layer chip capacitor and three embodiment of the present invention all is 1 μ F.
Table 1 shows the result of ESL of the multi-layer chip capacitor of traditional multi-layer chip capacitor and three embodiment of the present invention, and it obtains from above-mentioned experiment.
Table 1
| Traditional capacitor | First embodiment | Second embodiment | The 3rd embodiment | |
| Electric capacity | 1μF | 1μF | 1μF | 1μF |
| ESL | 70pH | 25pH | 25pH | 30pH |
As shown in table 1, with traditional multi-layer chip capacitor comparatively speaking, the ESL characteristic of the multi-layer chip capacitor of three embodiment of the present invention has had significant improvement.As shown in table 1, to compare with the ESL value of traditional multi-layer chip capacitor, the ESL value of the multi-layer chip capacitor of first and second embodiment of the present invention has reduced about 65%.Can't obtain to be about the ESL value of 25pH at traditional multi-layer chip capacitor with 8 outer electrodes.Under the situation of using traditional multi-layer chip capacitor,, just can obtain ESL value less than 30pH as long as traditional multi-layer chip capacitor has at least 12 outer electrodes.Yet, under the situation of the quantity of the outer electrode that increases capacitor, will the spacing between the outer electrode be narrowed down, thereby when being installed on capacitor on the substrate, be easy to make between the outer electrode be short-circuited.Therefore, do not adopt the traditional multi-layer chip capacitor with at least 12 outer electrodes, but adopt according to the multi-layer chip capacitor with 8 outer electrodes of the present invention, this benefits.Can be for reference be, multi-layer chip capacitor comprise have than under the situation of following virtual level of the bigger thickness of the thickness of virtual level, the ESL value of this multi-layer chip capacitor is about 100pH.
Can obviously find out from the above description, the invention provides the thickness that wherein descends virtual level multi-layer chip capacitor, thereby reduced the ESL that flows and produce from outer electrode owing to electric current, thereby reduce the ESL of whole capacitor device less than the thickness of last virtual level.In addition, multi-layer chip capacitor of the present invention has enough thickness, thereby has strengthened the mechanical strength of capacitor.Therefore, when this multi-layer chip capacitor is used for high-frequency circuit, can improves the electrical characteristics of this high-frequency circuit and prevent that capacitor from suffering mechanical breaking.
In addition, by form one or more grooves in internal electrode, it is too many to have prevented that ESR from descending, and ESR can be controlled to be required value.So the target impedance that is content with very little, and be provided with distribution system stable.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (20)
1. multi-layer chip capacitor comprises:
Last virtual level and following virtual level;
A plurality of internal electrodes place the described virtual level and described down between the virtual level of going up; And
A plurality of outer electrodes are connected with described internal electrode,
The thickness of wherein said virtual level down is less than the described thickness of going up virtual level.
2. multi-layer chip capacitor according to claim 1, wherein, the thickness of described down virtual level with described on the ratio of thickness of virtual level be 0.8 or less than 0.8.
3. multi-layer chip capacitor according to claim 1, wherein, the upper surface of described capacitor presents different colors with lower surface.
4. multi-layer chip capacitor according to claim 1 wherein, is provided for distinguishing the upper surface of described capacitor and the mark of lower surface on the described upper surface of described capacitor.
5. multi-layer chip capacitor according to claim 4, wherein, described mark is to be made by stained glass.
6. multi-layer chip capacitor according to claim 1, wherein:
Thin dielectric layer is formed between described a plurality of internal electrode; And
Described upward virtual level and described virtual level down are by making with the material identical materials of described dielectric layer.
7. multi-layer chip capacitor according to claim 1, wherein:
Thin dielectric layer is formed between described a plurality of internal electrode; And
The described virtual level of going up comprises:
Go up virtual dielectric layer, by making with the material identical materials of described dielectric layer; And
Last enhancement layer is formed at described going up on the virtual level.
8. multi-layer chip capacitor according to claim 7, wherein, described upward enhancement layer is to be made by plastics, glass or pottery.
9. multi-layer chip capacitor according to claim 1 wherein, also comprises one or more internal electrodes above the virtual level on described.
10. multi-layer chip capacitor according to claim 1 wherein, also comprises one or more virtual levels above the virtual level on described.
11. multi-layer chip capacitor according to claim 1, wherein, described multi-layer chip capacitor has asymmetrical cross section structure up and down.
12. multi-layer chip capacitor according to claim 1, wherein, described multi-layer chip capacitor has laterally zygomorphic cross section structure.
13. a multi-layer chip capacitor comprises:
Last virtual level and following virtual level;
A plurality of first internal electrodes and second internal electrode place the described virtual level and described down between the virtual level of going up; And
Outer electrode is connected with described internal electrode,
The thickness of wherein said down virtual level is less than the described thickness of going up virtual level,
Described first and second internal electrode by dielectric layer separately and alternately stacked, and each described first and second electrode has one or more going between of being connected with described outer electrode, and
In described first and second internal electrode one or two has one or more grooves.
14. multi-layer chip capacitor according to claim 13, wherein, each described first and second internal electrode has a pair of adjacent rectangular conductive pattern,
In described each in the conductive pattern, one or more grooves are formed centrally towards described conductive pattern from one or more sides, changing sense of current in the described conductive pattern, and
Electric current flows through described adjacent area to conductive pattern along direction respect to one another.
15. multi-layer chip capacitor according to claim 14, wherein, described have identical polarity to conductive pattern.
16. multi-layer chip capacitor according to claim 14, wherein, described have different polarity to conductive pattern.
17. multi-layer chip capacitor according to claim 13, wherein, electric current flows in described first and second internal electrode along orthogonal direction.
18. multi-layer chip capacitor according to claim 17, wherein, each described first internal electrode has the first rectangular conductive pattern, in the described first rectangular conductive pattern, form two grooves that extend to the center of described first conductive pattern from two opposite sides of described first conductive pattern, and
Each described second internal electrode has the second rectangular conductive pattern, in the described second rectangular conductive pattern, form two grooves, the groove of described second conductive pattern is extended from the center of described second conductive pattern of relative two side direction of described second conductive pattern perpendicular to the groove of described first conductive pattern.
19. multi-layer chip capacitor according to claim 17, wherein, each described first electrode has a pair of first conductive pattern that separates by first groove, and
Each described second electrode has second conductive pattern of rectangle, wherein in described second conductive pattern, form two second grooves, described second groove is extended to the center of described second conductive pattern from the opposite side of described second conductive pattern perpendicular to described first groove.
20. multi-layer chip capacitor according to claim 17, wherein, each described first electrode has first conductive pattern, and
Each described second electrode has a pair of second conductive pattern that separates by groove.
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| KR20060084770A (en) | 2006-07-25 |
| CN100568426C (en) | 2009-12-09 |
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