CN1801394A - Temperature-Dependent DRAM Self-refresh Circuit - Google Patents
Temperature-Dependent DRAM Self-refresh Circuit Download PDFInfo
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Abstract
一种装置，包括与温度有关的自刷新电路，用于存贮器装置。其中自刷新电路包括：用以提供反映出操作温度的输出之温度传感器电路；用于在自刷新操作期间切换温度传感器电路至低功率状态之手段；用以将来自该输出的温度数据进行编码之编码器；以及响应于已编码数据之可编程振荡器，以于自刷新操作中提供与温度有关的刷新信号。
An apparatus including a temperature-dependent self-refresh circuit for use in a memory device, wherein the self-refresh circuit includes: a temperature sensor circuit for providing an output reflecting an operating temperature; means for switching the temperature sensor circuit to a low power state during a self-refresh operation; an encoder for encoding temperature data from the output; and a programmable oscillator responsive to the encoded data to provide a temperature-dependent refresh signal during a self-refresh operation.
Description
Technical field
The invention relates to a kind of dynamic random access memory self-refresh circuit, and particularly about the invention of the method for a kind of dynamic random access memory self-refresh circuit relevant with temperature and the generation self refresh signal relevant with temperature.
Background technology
Dynamic random access memory (DRAM) device is to continue to become popular memory, in order to data-storing in electronic system.Because their memory cell (memory cell) size, dynamic random access memory can store mass data in very little device.Simultaneously, because the appearance of low power electronics device (for example laptop computer or the like), the demand that reduces power consumption for the deviser of dynamic random access memory just continues to become important target.
But, when visiting the target of two either-ors, must refresh (refresh) operation.At first, refresh operation must recover data values.Frequent refresh operation is desirable, and is destroyed to guarantee that data do not have.Simultaneously, cause the power consumption that increases to the required magnitude of current of memory cell charging.Therefore, frequent refresh operation does not conform with the needs of its consumed power.The target of these either-ors causes refreshing in each memory cell before " time-out " time of maximum hypothesis finishes.
In typical dynamic random access memory array, the memory cell that access should be listed as by starting the common word line (word line) of same column (row).Therefore, to refresh each memory cell by the row mode.In order to guarantee that each row all is refreshed, dynamic random access memory generally includes " a refreshing " counter.This refresh counter is set to the initial column address and causes initial column to be refreshed.Under the control of refreshing frequency, change refresh counter (above usually number or number operation down) then to the next column address.This causes the next column address to be refreshed.In case reach last column address, refresh counter returns the initial column address.So, under the control of refreshing frequency, all row in the refresh counter circulation memory device.Therefore, the decision of the speed of refresh counter refreshes the speed of memory cell.In order to meet maximum time out, refresh counter all column addresss that must in the time out of maximum, circulate usually.The speed of refreshing frequency pilot brush refresh counter.If maximum time out (institute's deposit data as yet not the maximum time of breaking-up) is T and total X row, then counter cycle is T/X.
The dynamic random access memory device can be estimated to operate in a temperature range.This causes the problem with relevant known refresh circuit.When the time out of maximum may be determined value on a certain temperature, it but was different values in another temperature.Can find the every decline 12-15 of temperature ℃, the time out of dynamic random access memory memory cell doubles generally.Therefore, when operating temperature decline, memory cell does not need to refresh so continually.Therefore,, then can reduce the power consumption of dynamic random access memory, especially conform with the needs of battery powdered device if can adjust refresh rate according to temperature.
The patent No. is that 56560164,6281760 and 5278796 United States Patent (USP) (it, is merged by reference hereby at this) is described the circuit of adjusting the dynamic random access memory refresh rate based on environment temperature, to reduce because of refreshing the power consumption of memory cell.The temperature sensor of known circuit continues detected temperatures, always makes temperature sensor keep " unlatching " or " startup " state, so continue consumed power.
Therefore, still exist and improve relevant refresh circuit and make the less demand of power consumption about the method that refreshes memory cell with temperature with temperature.
Summary of the invention
The present invention proposes a kind of device, comprises the self-refresh circuit relevant with temperature, is used for memory device.Wherein self-refresh circuit comprises: in order to the temperature sensor circuit of the output that reflects operating temperature to be provided; Be used for during self refresh operation the switching temperature sensor circuit to the means of low power state; In order to the scrambler that will encode from the temperature data of this output; And in response to the programmable oscillator of coded data, so that the refresh signal relevant with temperature to be provided in self refresh operation.
The present invention reintroduces a kind of method that produces the refresh signal relevant with temperature, is used for the signal memory storage.The step that the method comprises has: provide temperature sensor, in order to provide output to reflect the device operating temperature; The switching temperature sensor is to low power state during self refresh operation; To encode from the temperature data of this output; And utilize coded data programmed settings oscillator to be provided for refresh signal relevant in the self refresh operation with temperature.
State with other purpose, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Embodiment
Fig. 1 is the circuit diagram of refresh signal generator 10 embodiments relevant with temperature.Circuit 10 produces the refresh rate that the refresh signal REF relevant with temperature removes to be controlled at each memory cell in the memory arrays.In exemplary application, refreshing generation circuit 10 is included in the dynamic random access memory, this dynamic random access memory is used in the battery powered device, mancarried device especially, for example notebook computer or other any powered battery and the device of misgivings power consumption is arranged.
Reference signal generator 10 comprises temperature sensor circuit 12, in order to produce the temperature detection output signal and to offer sampling and latch circuit 14 via comparator circuit 16.Refresh signal generator 10 also comprises coding circuit 18, in order to receive and to encode from the data of sampling with 14 samplings of latch circuit and breech lock, and programmable oscillator circuit 20, the clock signal (oscillator 22 is provided) that it is controlled by coded signal (scrambler 18 is provided) and the refresh signal (REF) relevant with temperature is provided.
The operation of sensor circuit 12 should be known by the professional in this field, so this operation will not describe in detail in the present invention.Voltage signal VT1, VT2 and VT3 are the fixed reference potential that is produced by impedance step (comprising reference resistor R3, R2 and R1).This voltage is provided to comparator circuit 16, drops on what scope in order to compare with voltage VD with decision voltage VD.Voltage VD is the voltage relevant with temperature.If this sensor circuit is unlocked, then there is electric current to flow through diode A.Therefore, diode A produces voltage VD.
Fig. 4 is a voltage temperature family curve chart.The slope of VD (being d VD/dT) approximately is-0.0015V/ ℃, and promptly voltage VD increases descend (being learnt by analog result) with temperature.The slope of VTn (for example VT3, VT2 and VT1) satisfies following equation:
Wherein K is a constant, and q is an electric charge, and B is the diode A quantity of diode part BA in the circuit 12 of Fig. 1.B=1,2,3...., B=50 in the present embodiment.Therefore, the impedance of resistor R n (being R1, R2 and R3) can be selected to meet the characteristic requirement of voltage temperature shown in Fig. 4.
When initiating signal ENB transition is a low level, temperature sensor circuit 12 promptly is activated.In one embodiment, 16 li of comparator circuits 3 comparers are arranged, it couples as shown in fig. 1, and its negative (-) voltage input end (Vn) all is connected to the voltage node relevant with temperature receiving voltage VD, and its just (+) voltage input end (Vp) be respectively coupled to VT3, VT2 and VT1.If the Vp＞Vn of comparer, then comparer is output as logic high.On the contrary, if Vp＜Vn, then comparer is output as the logic low level.Fig. 4 illustrates following condition:
(i) if T＞T1, then three comparers output logic high position all in VT3＞VT2＞VT1＞VD and the comparator circuit 16;
If (ii) T1＞T＞T2, VT3＞VT2＞VD＞VT1 and couple the comparer output logic low level of VT1 then, other two comparers are an output logic high position then;
If (iii) T2＞T＞T3, VT3＞VD＞VT2＞VT1 and couple VT1 and the comparer output logic low level of VT2 then, and other comparer output logic high position; And
If (iv) T＜T3, then VD＞VT3＞VT2＞VT1 and the equal output logic low level of whole three comparers.
Fig. 2 shows the demonstration initiating signal (ENB) that is used for temperature sensor 12.ENB during the normal running (being non-self refresh operation) of memory for the logic low level, and self refresh operation to begin the ENB transition be logic high.Back ENB returns low level in the self-refresh circulation.When ENB was low level, PMOS transistor switch 24 was switched on, and this moment, temperature sensor circuit 12 was energized, and therefore produced reference voltage signal VT1, VT2 and VT3 and the voltage signal VD relevant with temperature.When ENB is a high position, with the output of comparer sampling and be latched in sampling and latch circuit 14.P type Metal-Oxide Semiconductor transistor (PMOS) switch 24 cuts out and temperature sensor circuit 12 enters low power state, for example, cut off the electricity supply, therefore save in the self-refresh power consumption of cycle period.Whether optional selecting opens ENB during normal running, is negligible because the power consumption of temperature sensor is compared with the remaining circuit operation.
In one embodiment, during refresh cycle, signal ENB periodically (being each period T p) transition in the cycle in short-term to be low level detect temperature variation during refresh cycle for temperature sensor circuit 12 so that supply electric power again, therefore can during refresh operation, dynamically change the refresh cycle time according to chip temperature.Perhaps, can in whole refresh cycle, make initiating signal keep high-order.
Fig. 3 (a) and 3 (b) illustrate a kind of demonstration methods that is created in initiating signal ENB shown in Figure 2.The self refresh signal SR of fixed frequency (can not the refresh signal REF relevant obscure mutually) with temperature may be provided from, for example, microcontroller.This signal SR is shown in Fig. 3 (b).In one embodiment, may provide fixing self refresh signal SR by microcontroller.Traditional microcontroller is controlled the SR state in order to save electric current.For example, when the holding state of mobile phone, signal SR may be set to maintenance " high position ".In Fig. 3 (a) and 3 (b), period T p can equal, for example, and 126*Tosc, and Tw can equal 2*Tosc.Because Tw control makes the temperature sensor power-on,, Tw do not have time enough to be opened so can not lacking with no-sensor very much.If Tw is too short, sensor can not be activated and remain on the state of power-off, and this moment, sampling may receive misdata with latch circuit 14.Signal X2 to X64 will be described as follows with Fig. 7 and 8.In the present embodiment, Tp=126*Tosc (being periodic signal sum total X2+X4+X8+X16+X32+X64), and Tw=2*Tosc.Tw with signal X2 cycle of minimum period is provided to the circuit of Fig. 3 (a).
Please refer to Fig. 5, this figure shows the example embodiment of sampling/breech lock 50.In the embodiment in figure 1, sampling preferably includes three sampling/latch circuits 50 with latch circuit 14, each is coupled to the output of comparator circuit 16 all separately, and the sampling and the breech lock output SLn (being denoted as output SL1, SL2 and SL3 in Fig. 1) of circuit 14 are provided separately.Each sampling/breech lock 50 comprises transmission gate 52, and transmission gate 52 comprises PMOS transistor and N type Metal-Oxide Semiconductor transistor (NMOS).Transmission gate is opened (i.e. " on ") so that the circuit sampled data, and closes (i.e. " off ") so that circuit breech lock and keep data.Transmission gate 52 is connected to the phase inverter 54 and 56 that pair of cross connects, and is being connected to phase inverter 58 successively.Phase inverter 56 couples ENB and anti-phase ENB simultaneously and works in as ENB during at logic high.Phase inverter 54 and 58 is held open forever.When the ENB transition was low level, sampling/breech lock 50 received the output signal of the comparer that is connected.When ENB transition when being high-order, the output of comparer be uncertain (because temperature sensor circuit such as above-mentioned as be closed), and the output signal breech lock that breech lock 50 will receive the comparer that is connected at last is firmly.Using sampling and latch circuit is because sensor circuit is not to be held open forever.Therefore, when sensor circuit was shut, sampling was pinned last input data and it is sent to coding circuit with latch circuit, is unlocked once again up to sensor circuit.Sampling and latch circuit 14 are by a plurality of sampling/latch circuits 50, from the output probe temperature data of sensor circuit 12, with the explanation of comparator circuit 16, to be encoded by scrambler 18.When temperature sensor is closed condition (promptly when ENB is logic high), sampling is pinned last received temperature data to encode by scrambler 18 with latch circuit 14.
Fig. 6 illustrates the preferred embodiment of coding circuit 18.In the present embodiment, coding circuit comprises circuit 60, this circuit 60 comprises a plurality of Sheffer stroke gates (NAND) circuit, its output OT0, OT1, OT2 and OT3 reflected by temperature sensor 12 is detected and by sampling and latch circuit 14 from the comparator circuit 16 state of temperature T that breech lock also lives that taken a sample.There are 3 samplings and breech lock output SL1, SL2 and SL3 to point out which temperature range is temperature T fall within.As mentioned above, if T1＜T, then all three output SL are logical one (because when temperature sensor is on this state of temperature, whole three comparers outputs all are from comparator circuit 16 generation logical ones), and to have only OT3 be logical one.If T2＜T＜T1, then SL1 and SL2 are that logical one and SL3 are logical zero.Having only OT2 is logical one.If T3＜T＜T2, then SL1 is that logical one and SL2 and SL3 are logical zero.Having only OT1 is logical one.At last, if T＜T3, exporting all then that SL is all logical zero and has only OT1 is logical one.Therefore, reflect range temperature by exporting of circuit 60 with door.
Fig. 7 illustrates the preferred embodiment of programmable oscillator 70.Oscillator 70 comprises a plurality of and non-(NAND) door 72a to 72d, couples control signal OT0 to OT3 respectively.The output of each Sheffer stroke gate 72 all is connected to Sheffer stroke gate 74, and 74 of Sheffer stroke gates are connected to edge-triggered pulse producer 76.Each Sheffer stroke gate 72 connection has the clock signal of different clock period, for example signal X2, X4, X8 and X4 and X8.The clock period T (Xn) of clock signal Xn has following relationship: T (X2)＜T (X4)＜T (X8).Therefore, the frequency of clock signal X2 is greater than the frequency of clock signal X4 or the like.As T1＜T, it is high-order then having only OT3, and edge-triggered pulse producer 76 receives high frequency clock signal X2 from Sheffer stroke gate 72 by Sheffer stroke gate 74.Edge-triggered pulse producer 76 produces relevant refresh signal REF with temperature according to frequency X2 (having the short period but high-frequency), in order to refresh the word line of dynamic random access memory.In essence, because temperature is very high, refreshing frequency must be high.In another example, as T＜T3, it is high-order then having only OT0, and edge-triggered pulse producer 76 received signal X12, and promptly Sheffer stroke gate 72d provides signal X12 to edge-triggered pulse producer 76 from signal OT0 (for high-order), signal X4 and X8.The relevant refresh signal REF that edge-triggered pulse producer 76 produces corresponding to low-frequency clock signal X12 with temperature.In this example, because temperature is lower, so REF has lower frequency.The operation of edge-triggered pulse producer 76 and the design professional in field are for this reason known.
Fig. 9 is the curve map of the refresh cycle of Fig. 1 circuit sampling example data to temperature (T).As shown in the figure, when increasing, temperature reduces the refresh cycle (increasing the meaning of refreshing frequency).
Fig. 8 illustrates the circuit 80 of clocking X2, X4 or the like.The speed of signal X2, X4 or the like can be changed and set by design.Circuit 80 comprises the binary counter of a plurality of series connection, with each signal frequency that receives divided by 2 (embodiment as shown in figure 12).This circuit is connected to oscillator signal OSC, and oscillator signal OSC is provided by oscillator 22 (Fig. 1) in one embodiment.First binary counter receive clock signal OSC and in subordinate with the 1/n frequency output signal Xn of clock signal, shown in Fig. 8 and 12.
As shown in Figure 8, in an embodiment, signal SR also is used as reset signal, in order to the replacement binary counter.When signal SR transition was a high position, binary counter was reset to its original state so that determine new ENB signal (with reference to Fig. 3 (b)), and it depends upon REF, to control this sensor circuit.If binary counter is not reset, output subsequently will shone and be divided by.
Under the temperature regime of selecting, the frequency of the input of Fig. 7 Sheffer stroke gate 72 and Fig. 8 OSC can be selected to provide required frequency control signal to pulse producer 76.For example, if four frequencies of control signal are chosen as X2, X4, X6 and X8, then comparer 72a is connected to X2, and comparer 72b is connected to X4, and comparer 72c is connected to X2 and X4 and comparer 72d and is connected to X8.Can be simultaneously refresh characteristic and temperature range is selected control signal according to required.
Figure 10 is the circuit diagram of demonstration oscillator 100, and it can be contained in the oscillator square 22 of Fig. 1.The design of oscillator 100 professional in field is for this reason known and is not described in detail in this.Oscillator 100 provides constant clock signal OSC to programmable oscillator 20 via feedback circuit.
Please refer to Figure 11, another preferred embodiment of temperature sensor 12A is specified.The sensor circuit 12A of Figure 11 is identical with the sensor circuit 12 of Fig. 1, and difference is to provide starting circuit 114.When the ENB transition was low level, line A was provided voltage (by PMOS transistor switch 24) with start-up temperature sensor 110.But in some cases,, cause temperature sensor not to be unlocked because the stray capacitance that exists can be drawn high designed line B voltage by line A.In this embodiment, starting circuit 114 is provided to drag down the voltage (being logical zero) of line B, closes it then when temperature sensor is opened.When it is input as identity logic (being all a low level or a high position), the output of operational amplifier in the temperature sensor circuit (OP AMP) will be high.At first, the operational amplifier input is all low level and causes operational amplifier output high-order.So, the B point keeps closing for high-order and expression sensor circuit.To force a B transition be low level to starting circuit when starting, to guarantee first turn on sensor circuit.
Though four kinds of possible temperature conditions of the foregoing description explanation, i.e. (i) T＜T3, (ii) T3＜T＜T2＜T1, (iii) T3＜T2＜T＜T1 and (iv) T1＜T, this is just for convenience of description.Can use other many possible temperature combinations by the resistor that adds (perhaps subtracting) temperature sensor 12 middle impedance ladders, and add corresponding comparer at comparator circuit 16, add corresponding sampling/latch circuit 50 at sampling and latch circuit 14, add at scrambler 60 corresponding with door and at the corresponding input nand gate of programmable oscillator 70 interpolations.
Though do not show, the refresh clock signal REF relevant with temperature is provided to start word line and triggers refresh address counter, as described in background technology one joint and known to the ordinary skill of technical field that the present invention belongs to, will be write memory cell (for example dynamic random access memory) again by the data of storage according to refresh clock signal.REF is used to control bit line and refreshes.In addition, in integrated circuit, the refresh clock signal generator is preferred embodiment.
Though the present invention with preferred embodiment openly as above; right its is not in order to limit the present invention; the ordinary skill of any technical field that the present invention belongs to; in thought that does not break away from the present invention and scope; when can doing a little change and improvement, so the present invention's protection domain is as the criterion when looking claims person of defining.
Description of drawings
Fig. 1 is in order to the exemplary circuit diagram of generation with the refresh signal of the relevant memory cell of temperature.
Fig. 2 is used for the sequential chart of initiating signal that Fig. 1 refresh signal produces the temperature sensor of circuit.
Fig. 3 A is the circuit diagram that explanation produces Fig. 2 initiating signal, and Fig. 3 B is the sequential chart that shows the initiating signal, self refresh signal and the clock signal that are produced.
Fig. 4 is the temperature voltage performance plot of Fig. 1 temperature sensor of producing circuit.
Fig. 5 is the circuit diagram of sampling and latch circuit.
Fig. 6 illustrates the embodiment of demonstration coding circuit.
Fig. 7 illustrates the embodiment of demonstration programmable pulse generator.
Fig. 8 explanation is in order to the embodiment of the exemplary electrical circuit of generation clock signals of different frequencies.
Fig. 9 is the demonstration temperature-refresh cycle performance plot of Fig. 1 circuit.
Figure 10 is the circuit diagram of demonstration oscillator circuit.
Figure 11 is the circuit diagram of the selected embodiment of temperature inductor circuit.
Figure 12 is the sequential chart that shows several relevant clock signals.
The main element description of symbols
10: the refresh signal generator relevant with temperature
12,12A: temperature sensor circuit
14: sampling and latch circuit
16: comparator circuit
18: coding circuit
20: the programmable oscillator circuit
22,100: oscillator
24: transistor switch
50: sampling/latch circuit
52: transmission gate
54,56,58: phase inverter
60: coding circuit
70: programmable oscillator
72a ~ 72d, 74: with non-(NAND) door
76: the edge-triggered pulse producer
80: the circuit of clocking
114: starting circuit
Claims (24)
1. device, this device comprises the self-refresh circuit relevant with temperature that is used for memory device, it is characterized in that this self-refresh circuit comprises:
Temperature sensor circuit is in order to provide the output that reflects operating temperature;
Means (means) are in order to switch this temperature sensor circuit to low power state during self refresh operation;
Scrambler will be in order to encoding from the temperature data of this output; And
Programmable oscillator is in order to provide relevant self refresh signal with temperature according to this coded data in this self refresh operation.
2. the device according to claim 1 is characterized in that this self-refresh circuit also comprises:
Sampling and latch circuit, be coupled between this temperature sensor circuit and this scrambler, this sampling and latch circuit are pointing out that the signal of this output of this temperature sensor circuit is taken a sample, to provide this temperature data to this scrambler, when this temperature sensor circuit was switched to this low power state, this sampling and latch circuit also breech lock were lived this temperature data to this scrambler.
3. the device according to claim 2 is characterized in that this temperature sensor circuit comprises the means of the voltage signal that provides relevant with temperature,
This device also comprises comparator circuit, and in order to relatively to be somebody's turn to do voltage signal and a plurality of reference voltage relevant with temperature, this comparator circuit provides this signal of this output of pointing out this temperature sensor circuit whereby.
4. the device according to claim 1 is characterized in that these means of switching comprise switch, is coupled between power supply and this sensor circuit, and this switching response is in initiating signal, and this initiating signal is pointed out this self refresh operation.
5. the device according to claim 4 is characterized in that this switch comprises the Metal-Oxide Semiconductor transistor, by this initiating signal of pointing out this self refresh operation this Metal-Oxide Semiconductor transistor applied bias voltage.
6. the device according to claim 1, these means that it is characterized in that switching are in response to this initiating signal of pointing out this self refresh operation, wherein during above-mentioned self refresh operation, at least switch logic state of this initiating signal reaches cycle time, and these means of feasible switching are opened this sensor circuit and reached this time cycle.
7. the device according to claim 6 is characterized in that also comprising the means that produce this initiating signal.
8. the device according to claim 1 is characterized in that this scrambler comprises a plurality of Sheffer stroke gates, and each above-mentioned these Sheffer stroke gate provides the output of representative this operating temperature in temperature range separately.
9. the device according to claim 1 is characterized in that this programmable oscillator comprises pulse producer and the means in response to this coded data, and this pulse producer one of couples in a plurality of control clock signal.
10. the device according to claim 9 is characterized in that also comprising the means that produce above-mentioned these control clock signal.
11. the device according to claim 1 is characterized in that also comprising the dynamic random access memory array.
12. the method for a generation and the relevant refresh signal of temperature is used for memory device, it is characterized in that this generation comprises the following steps with the method for the relevant refresh signal of temperature
Provide temperature sensor, in order to provide output to reflect the operating temperature of this memory device;
During self refresh operation, switch this temperature sensor to low power state;
To encode from the temperature data of this output; And
Utilize this coded data program setting oscillator that the refresh signal relevant with temperature is provided in this self refresh operation.
13., it is characterized in that also comprising the following steps: according to the method for the described generation of claim 12 with the relevant refresh signal of temperature
To sample of signal, this signal is pointed out this output from this temperature sensor, so that this temperature data in order to coding to be provided; And
When this temperature sensor circuit was switched to this low power state, breech lock was lived this temperature data in order to coding.
14. according to the method for the described generation of claim 12, it is characterized in that comprising the voltage signal relevant that this method also comprises with temperature from this output of this temperature sensor circuit with the relevant refresh signal of temperature:
Relatively be somebody's turn to do voltage signal and a plurality of reference voltage relevant with temperature, feasible this signal of this output of this temperature sensor circuit of pointing out is provided.
15. according to the method for the described generation of claim 12 with the relevant refresh signal of temperature, it is characterized in that this switch step is performed according to initiating signal, this initiating signal is pointed out this self refresh operation.
16. according to the method for the described generation of claim 14 with the relevant refresh signal of temperature, it is characterized in that this initiating signal at least switch logic state during this self refresh operation reaches cycle time, being opened with this this sensor circuit reaches this time cycle.
17., it is characterized in that this memory device comprises the dynamic random access memory device according to the method for the described generation of claim 12 with the relevant refresh signal of temperature.
18. a memory device is characterized in that comprising:
The dynamic random access memory array; And
The self-refresh circuit relevant with temperature is used for this dynamic random access memory array, and this self-refresh circuit comprises:
Temperature sensor circuit, in order to output to be provided, this output reflects the operating temperature of this dynamic random access memory array;
Means (means) are used for switching this temperature sensor circuit to low power state according to initiating signal, and this initiating signal is pointed out self refresh operation;
Scrambler will be in order to encoding from the temperature data of this output;
Sampling and latch circuit, signal in order to this output that will point out this temperature sensor circuit is taken a sample, to provide temperature data to this scrambler, when this temperature sensor circuit was switched to this low power state, this sampling and latch circuit also breech lock were lived this temperature data to this scrambler; And
Programmable oscillator provides the refresh signal relevant with temperature in response to this coded data in this self refresh operation.
19. according to claim 18 a described memory device, it is characterized in that this output of this temperature sensor circuit comprises the voltage signal relevant with temperature,
This memory device also comprises comparator circuit, in order to relatively to be somebody's turn to do voltage signal and a plurality of reference voltage relevant with temperature, provides this signal of this output of pointing out this temperature sensor circuit to this sampling and latch circuit with this this comparator circuit.
20. the memory device according to claim 18 is characterized in that this initiating signal at least switch logic state during this self refresh operation reaches cycle time, opens this sensor circuit with these these means of switching and reaches this time cycle.
21. the memory device according to claim 20 is characterized in that also comprising the means that produce this initiating signal.
22. the memory device according to claim 18 is characterized in that this scrambler comprises a plurality of Sheffer stroke gates, each above-mentioned these Sheffer stroke gate provides the output of representative this operating temperature in temperature range separately.
23. the memory device according to claim 18 is characterized in that this programmable oscillator comprises pulse producer and the means in response to this coded data, this pulse producer one of is coupled in a plurality of control clock signal.
24. the memory device according to claim 23 is characterized in that also comprising the means that produce above-mentioned these control clock signal.
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| CNB2004101035714A CN100440375C (en) | 2004-12-31 | 2004-12-31 | Temperature dependent DRAM self-refresh circuit |
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| CNB2004101035714A CN100440375C (en) | 2004-12-31 | 2004-12-31 | Temperature dependent DRAM self-refresh circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106560894A (en) * | 2015-10-05 | 2017-04-12 | 爱思开海力士有限公司 | Semiconductor device |
| CN107038988A (en) * | 2017-06-19 | 2017-08-11 | 京东方科技集团股份有限公司 | Control circuit, display screen, the driving method of display screen and display device |
| CN107516539A (en) * | 2016-06-15 | 2017-12-26 | 上海磁宇信息科技有限公司 | A kind of MRAM chip and its self-refresh method |
| CN108463807A (en) * | 2015-10-30 | 2018-08-28 | 英特尔公司 | The relevant multi-mode error correction of temperature |
| CN110739013A (en) * | 2018-07-18 | 2020-01-31 | 华邦电子股份有限公司 | Dynamic random access memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5278796A (en) * | 1991-04-12 | 1994-01-11 | Micron Technology, Inc. | Temperature-dependent DRAM refresh circuit |
| KR950010624B1 (en) * | 1993-07-14 | 1995-09-20 | 삼성전자주식회사 | Cell refresh cycle control circuit of semiconductor memory device |
| US6281760B1 (en) * | 1998-07-23 | 2001-08-28 | Texas Instruments Incorporated | On-chip temperature sensor and oscillator for reduced self-refresh current for dynamic random access memory |
| JP2003132676A (en) * | 2001-10-29 | 2003-05-09 | Mitsubishi Electric Corp | Semiconductor memory |
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2004
- 2004-12-31 CN CNB2004101035714A patent/CN100440375C/en not_active Expired - Lifetime
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106560894A (en) * | 2015-10-05 | 2017-04-12 | 爱思开海力士有限公司 | Semiconductor device |
| CN106560894B (en) * | 2015-10-05 | 2020-12-29 | 爱思开海力士有限公司 | Semiconductor device |
| CN108463807A (en) * | 2015-10-30 | 2018-08-28 | 英特尔公司 | The relevant multi-mode error correction of temperature |
| CN107516539A (en) * | 2016-06-15 | 2017-12-26 | 上海磁宇信息科技有限公司 | A kind of MRAM chip and its self-refresh method |
| CN107038988A (en) * | 2017-06-19 | 2017-08-11 | 京东方科技集团股份有限公司 | Control circuit, display screen, the driving method of display screen and display device |
| CN107038988B (en) * | 2017-06-19 | 2019-11-05 | 京东方科技集团股份有限公司 | Control circuit, display screen, the driving method of display screen and display device |
| US10706759B2 (en) | 2017-06-19 | 2020-07-07 | Boe Technology Group Co., Ltd. | Current comparison circuit, display device and driving method thereof |
| CN110739013A (en) * | 2018-07-18 | 2020-01-31 | 华邦电子股份有限公司 | Dynamic random access memory |
| CN110739013B (en) * | 2018-07-18 | 2021-08-10 | 华邦电子股份有限公司 | Dynamic random access memory |
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| CN100440375C (en) | 2008-12-03 |
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