CN1799064A - Image processing device - Google Patents

Abstract

An image processing device applied to a digital camera including: a frame memory (4) for inputting via a bus (11) and storing image data obtained by imaging an optical image of an optical system by a CCD (1); a first data sequence conversion section (5) for reading out the image data from the frame memory (4) in block unit in the row direction and converting it into the column direction for output; an image processing section (6) connected to the first data sequence conversion section (5) in such a manner that pipeline processing can be performed and performing image processing; a distortion correction processing section (7) connected to the image processing section (6) in such a manner that pipeline processing can be performed and performing distortion correction processing; and a second data sequence conversion section (8) connected to the distortion correction processing section (7) in such a manner that pipeline processing can be performed and returning the block data of the column direction into the block data of the row direction for output to the frame memory (4).

Description

Image processing apparatus

Technical field

The present invention relates to image processing apparatus, in more detail, relate to the image processing apparatus that the electronic image data that obtain by the optical system shooting are handled.

Background technology

In electronic image pickup devices such as digital camera, general, by CCD imaging apparatuss such as (charge-coupled image sensors) shot object image by optical system imaging is carried out opto-electronic conversion, obtain camera data, this camera data is carried out various Flame Image Process, compress in JPEG compression modes such as (JPEG (joint photographic experts group)) then, be recorded in the recording mediums such as storage card, electronic image pickup devices such as this digital camera become the equipment that double as is an image processing apparatus.

Figure 32 is the figure of step of the general Flame Image Process of presentation video treating apparatus.

Imaging apparatuss such as CCD carry out opto-electronic conversion to the optics shot object image by optical system imaging, generate electric image pickup signal.This image pickup signal is stored in the frame memory after being carried out pre-service such as the correction of picture element flaw and A/D conversion.

Then, the view data that is stored in the frame memory is read out, by the 1st Flame Image Process, the 2nd Flame Image Process ..., N Flame Image Process etc., be carried out from monolithic signal (single-chipsignal) and emphasize to handle, amplify various Flame Image Process such as dwindling processing to conversion process, low-pass filtering treatment, the edge of 3 signals (three-chip signal).

Picture signal after the Flame Image Process is further compressed by compression modes such as JPEG, is recorded in the storage card as image file.

Figure 33 is the block scheme that expression is used to carry out the structure of the existing image processing apparatus that above-mentioned general pattern shown in Figure 32 handles.

This image processing apparatus has: CCD 91, pretreatment portion 92, frame memory the 94, the 1st image processing part 95a, the 2nd image processing part 95b ..., N image processing part 95n, JPEG handling part 96, storage card etc. 97, connect above-mentioned each circuit and the bus 98 of CPU described later 93 and the CPU 93 that unified control comprises this image processing apparatus of above-mentioned each circuit except above-mentioned CCD 91.

When the image processing apparatus by this structure shown in Figure 33 carries out above-mentioned processing shown in Figure 32, be in particular following step.

At first, will temporarily be stored in frame memory 94 from the view data of pretreatment portion 92 by bus 98.

Then, read view data, be input to the 1st image processing part 95a, carry out the 1st Flame Image Process, the view data after handling is written on the frame memory 94 by bus 98 from this frame memory 94.

Similarly, carry out following processing: read view data after the 1st Flame Image Process from this frame memory 94, be input to the 2nd image processing part 95b by bus 98, carry out the 2nd Flame Image Process, view data after handling is written on the frame memory 94, each image processing part is repeated same processing.

Like this, when carrying out Flame Image Process, the view data bus 98 of repeatedly flowing through, and because the size of data of view data is all bigger generally speaking, so bus 98 has been increased very big load.Give this big load of bus 98, become more remarkable when using the write the two or more syllables of a word together function etc.

According to such viewpoint, for example special opening following technology being disclosed in the 2000-311241 communique: a plurality of image processing parts is connected into can carry out pipeline processes, image from frame memory is carried out pipeline processes, thereby alleviate the load of bus, thus when alleviating the load of bus, can not increase memory span and comprise in real time and amplify the Flame Image Process of dwindling processing.

And, open the spy and also to disclose following technology in the 2000-312327 communique: by reading the image that is stored in the frame memory by predetermined direction (column direction) with block unit, reduce the buffer memory when carrying out pipeline processes, can constitute the image processing apparatus of low power consumption, saving storer.

But, in the optical system of the camera that comprises digital camera and silver halide photography machine, the difference of size is arranged certainly, generally all can produce distorton aberration.For example when taking cancellate subject, this distorton aberration is sighted (with reference to Fig. 3 (A), Fig. 3 (B), Fig. 3 (C) of embodiments of the present invention) such as drum type, pillow types.In addition, the camera of current sale, the machine that can carry out optical zoom is a lot, but so varifocal optical system is when changing focal length in the zooming range from the wide-angle side to the telescope end, and the state of distorton aberration changes under a lot of situations.

For this phenomenon, developed since in the past as the part of Flame Image Process and the technology of carrying out distortion correction as the one example, for example can list the spy and open disclosed technology in the flat 6-181530 communique.In general pattern that this communique is put down in writing is handled, from frame memory for example with the unit's of going sense data.

In addition, as the part of Flame Image Process and other the technology of carrying out distortion correction, for example open and disclose each image processing part in the flat 10-224695 communique frame memory is carried out random-access technology the spy.According to this technology, because impact damper need be set in image processing part, so have the advantage that the circuit scale that can make this image processing part diminishes.

And it is known can producing chromatic aberation in the optical system of above-mentioned camera.This chromatic aberation is because when light incides optical system, owing to the light wavelength difference makes what the refractive index difference produced, when being optical image by optical system imaging, the phenomenon of little deviation occurs being produced by the optical image of each wavelength imaging.Though design of Optical System is become to make this chromatic aberation diminish as far as possible, from configuration space and weight, cost equal angles, the very difficult chromatic aberation of eliminating fully.

Open in the flat 6-181530 communique in the disclosed technology above-mentioned spy, for the 1 capable distortion correction of carrying out as Flame Image Process to the image after proofreading and correct, as shown in figure 34, must read the view data before the needed multirow of distortion correction is proofreaied and correct across the width of the horizontal direction of integral image.This Figure 34 is used to illustrate in the past in order to carry out the figure of the necessary memory span of distortion correction treatment.Because the view data of these multirows is carried out processing after being temporarily stored in the impact damper of the inside that is arranged on image processing part, so in order to obtain the correcting image of 1 row, need bigger capacity, make circuit scale become big as impact damper, manufacturing cost increases, and power consumption also increases.And because the memory buffer capacity in the image processing part, accessible image size is restricted.

In addition, in being disclosed in the technology that above-mentioned spy opens flat 10-224695 communique, if the frame memory that random access is made of SDRAM etc. then transmits with the burst of reading at a high speed from SDRAM (burst) and compares, the delivery time of data becomes the principal element that the whole processing time is increased.

But in image processing apparatus, the processing block by being provided for carrying out above-mentioned distortion correction treatment and be used to amplify processing block two sides that dwindle processing can amplify and dwindle processing and distortion correction treatment two sides.But these processing are accompanied by the interpolation arithmetic of each pixel, and treatment circuit also becomes on a large scale, and therefore in the structure that two treatment circuits are set merely, it is big that circuit structure becomes, and power consumption is risen, and manufacturing cost also increases.

And, preferably need not how to increase cost etc., also can proofread and correct above-mentioned chromatic aberation well.

The present invention is In view of the foregoing and proposes that its purpose is to provide a kind of image processing apparatus, and it can not increase the data conveying capacity of bus and memory span and the Flame Image Process of carrying out.

In addition, the object of the present invention is to provide a kind of image processing apparatus, it can amplify to dwindle handles and distortion correction treatment, and circuit scale is little and power consumption is low.

And, the object of the present invention is to provide a kind of image processing apparatus, it can carry out distortion correction treatment and chromatic aberation treatment for correcting, and circuit scale is little and power consumption is low.

Summary of the invention

The present invention is a kind of image processing apparatus, the electronic image data that obtain making a video recording through optical system are handled, the pixel data of described view data is two-dimensionally arranged on line direction and column direction, this image processing apparatus comprises: storer, it is the described view data of storage before carrying out Flame Image Process at least, and also can carry out the described view data of storage after the Flame Image Process; The 1st data orders converter section, its piece with the described two-dimensional arrangements of described view data is a unit, reads pixel data this piece in by bus by line direction from described storer, then, exports pixel data in this piece by column direction; Image processing part, it is connected into described the 1st data order converter section by the information communicating path different with described bus can carry out pipeline processes, input is pressed the view data that column direction is exported from the 1st data order converter section, has carried out after the Flame Image Process, by this column direction output; And the 2nd data orders converter section, it is connected into described image processing part can carry out pipeline processes, will be converted to the view data of line direction by the view data of column direction output and exports from this image processing part.

In addition, the present invention is a kind of image processing apparatus, the electronic image data that can obtain to making a video recording through optical system, comprise distortion correction treatment and amplify the Flame Image Process of dwindling processing, this image processing apparatus has distortion correction treatment portion, this distortion correction treatment portion comprises: the interpolated coordinates generating unit, it is used to generate and has carried out comprising distortion correction treatment and amplified the coordinate data of dwindling before the corresponding interpolation processing of the location of pixels of processing after the interpolation processing of interior Flame Image Process, i.e. interpolated coordinates data; Storage part, it is used to store at least a portion of described view data; Memory controller, it carries out the part of described view data is written to the control of described storage part and the control of reading from this storage part based on described interpolated coordinates data; And interpolation arithmetic unit, it generates the view data of having carried out the location of pixels after the interpolation processing by the view data of reading from described storage part according to the control of described memory controller is carried out interpolation arithmetic.

And, the present invention is a kind of image processing apparatus, the electronic image data that obtain making a video recording through optical system are handled, described view data is made of a plurality of compositions, this image processing apparatus has the distortion correction treatment unit, this distortion correction treatment unit comprises: the distortion correction coefficient calculation unit, and it calculates the distortion correction coefficient that is used to proofread and correct the distorton aberration that is caused by described optical system according to the distance from the center of distortion position at described each composition; And the distortion correction arithmetic element, the distortion correction coefficient that it uses each composition of calculating by described distortion correction coefficient calculation unit carries out distortion correction according to each composition to described view data.

Description of drawings

Fig. 1 is the block scheme of structure of the image processing apparatus of expression the 1st embodiment of the present invention.

Fig. 2 is the block scheme of structure of the distortion correction treatment portion of above-mentioned the 1st embodiment of expression.

Fig. 3 is illustrated in above-mentioned the 1st embodiment figure of the example of the distorton aberration when having taken cancellate subject by optical system.

Fig. 4 is used for illustrating the figure of summary that comprises the interpolation processing of distortion correction at above-mentioned the 1st embodiment.

Fig. 5 is the figure that is used for illustrating in the processing of 16 point interpolations of above-mentioned the 1st embodiment.

Fig. 6 is the figure that reads order of the view data of above-mentioned the 1st embodiment of expression.

Fig. 7 is the block scheme of structure of the data orders converter section of above-mentioned the 1st embodiment of expression.

Fig. 8 is the corresponding relation that is illustrated in correcting image and photographed images in above-mentioned the 1st embodiment, and the figure that handles needed buffer memory.

Fig. 9 is illustrated in described the 1st embodiment according to the distance from center of distortion, makes the figure of the different in a longitudinal direction example of the width of the view data of reading.

Figure 10 is illustrated in above-mentioned the 1st embodiment according to the distance from center of distortion, makes the size of the view data of reading and the figure that reads the different example in starting position.

Figure 11 is the block scheme of the 1st variation of structure of the image processing apparatus of above-mentioned the 1st embodiment of expression.

Figure 12 is the block scheme of the 2nd variation of structure of the image processing apparatus of above-mentioned the 1st embodiment of expression.

Figure 13 is the block scheme of the 3rd variation of structure of the image processing apparatus of above-mentioned the 1st embodiment of expression.

Figure 14 is the block scheme of the 4th variation of structure of the image processing apparatus of above-mentioned the 1st embodiment of expression.

Figure 15 is the block scheme of structure of the image processing apparatus of expression the 2nd embodiment of the present invention.

Figure 16 is the block scheme of more detailed structure of the distortion correction treatment portion of above-mentioned the 2nd embodiment of expression.

Figure 17 is the block scheme of an example of structure of the distortion correction coefficient calculation circuit of above-mentioned the 2nd embodiment of expression.

Figure 18 is the block scheme of other example of structure of the distortion correction coefficient calculation circuit of above-mentioned the 2nd embodiment of expression.

Figure 19 is the sequential chart of the situation when generating location of interpolation at every in above-mentioned the 2nd embodiment of expression.

Figure 20 is the sequential chart of the situation when generating location of interpolation according to per 3 ratios of 1 time in above-mentioned the 2nd embodiment of expression.

Figure 21 is the block scheme of summary of structure of the distortion correction treatment portion of above-mentioned the 3rd embodiment of expression.

Figure 22 is the figure of an example of the chromatic aberation that produces when being illustrated in above-mentioned the 3rd embodiment by the optical system photographic images.

Figure 23 is illustrated in above-mentioned the 3rd embodiment, is stored in the figure of the situation of the view data in the storage inside portion in the moment that can calculate the interpolated data relevant with B.

Figure 24 is illustrated in described the 3rd embodiment, is stored in the figure of the situation of the view data in the storage inside portion in each the moment of interpolated data that can calculate R, G, B.

Figure 25 is the block scheme of more detailed structure of the distortion correction treatment portion of above-mentioned the 3rd embodiment of expression.

Figure 26 is the block scheme of structure of the distortion correction coefficient calculation circuit of above-mentioned the 3rd embodiment of expression.

Figure 27 is the block scheme apart from the structure of interdependence coefficient counting circuit of above-mentioned the 3rd embodiment of expression.

Figure 28 is other routine block scheme of structure of the distortion correction coefficient calculation circuit of above-mentioned the 3rd embodiment of expression.

Figure 29 is the block scheme of the Ch.0 of above-mentioned the 3rd embodiment of expression with the structure of distortion correction circuit.

Figure 30 is the block scheme of structure of the allowance synchronizing circuit of above-mentioned the 3rd embodiment of expression.

Figure 31 is the sequential chart of action that is used to illustrate the allowance synchronizing circuit of above-mentioned the 3rd embodiment.

Figure 32 is the figure of the step handled of the general pattern of presentation video treating apparatus.

Figure 33 is the block scheme that expression is used to carry out the structure of the conventional images treating apparatus that above-mentioned general pattern shown in Figure 32 handles.

Figure 34 is used to illustrate the figure of the memory span of needs in order to carry out distortion correction treatment in the past.

Embodiment

Below, with reference to the description of drawings embodiments of the present invention.

Be the figure of expression the 1st embodiment of the present invention from Fig. 1 to Figure 14, Fig. 1 is the block scheme of the structure of presentation video treating apparatus.

This image processing apparatus comprises with the lower part and constitutes: the optics shot object image by optical system imaging is carried out opto-electronic conversion, generate the imaging apparatus CCD 1 of electric image pickup signal; Image pickup signal from this CCD1 output is carried out pretreated pretreatment portions 2 such as the correction of picture element flaw and A/D conversion; The frame memory 4 of the two field picture after storage is handled by this pretreatment portion 2; Read the view data that is stored in this frame memory 4 by bus 11 described later by each predetermined block, and temporary transient storage, the 1st data order converter section 5 of order and output is read in change then; To implementing the image processing part 6 that predetermined picture is handled as image processing part from the view data of the 1st data order converter section 5 outputs; View data after handling by this image processing part 6 is carried out the distortion correction treatment portion 7 as image processing part of distortion correction treatment; To temporarily storing from every view data of this distortion correction treatment portion 7 outputs, the 2nd data order converter section 8 of reading and exporting by direction identical when from frame memory 4, reading by above-mentioned the 1st data order converter section 5; To view data from 8 outputs of the 2nd data orders converter section, the JPEG handling part 9 that compresses by compression modes such as JPEG; To temporarily write frame memory 4 by bus 11 described later by the view data that this JPEG handling part 9 has carried out compressing, this view data that writes is read and is imported by bus 11, as image file store as storage card of non-volatile memory cells etc. 10; The bus 11 that will above-mentioned each circuit except above-mentioned CCD 1 be connected with CPU 3 described later; And as the unified CPU 3 that controls the control module of this image processing apparatus that comprises above-mentioned each circuit.

Here, from above-mentioned the 1st data order converter section 5 to JPEG handling parts 9, by bus 11, can carry out pipeline processes and connect into by the information communicating path different with this bus 11, the predetermined block unit of arranging with two-dimensional pixel transmits and handles view data.Thereby the view data that data volume is big need repeatedly not be transmitted from bus 11 at each processing, thus can significantly alleviate the load of bus 11, and, the capacity of the internal buffer portion of image processing part is diminished by handling by block unit.

In addition, in this example shown in Figure 1, only be provided with 1 image processing part 6 that carries out Flame Image Process, yet also can on the path of above-mentioned pipeline processes, dispose a plurality of image processing parts corresponding with a plurality of Flame Image Process.Here, as the example of Flame Image Process,, can enumerate from the monolithic signal and emphasize to handle, amplify and dwindle processing etc. to conversion process, low-pass filtering treatment, the edge of 3 signals with above-mentioned same.The configuration of image processing part 6 at this moment can be the preceding-stage side in above-mentioned distortion correction treatment portion 7, also can be rear-stage side.

Secondly, Fig. 2 is the block scheme of the structure of the above-mentioned distortion correction treatment of expression portion 7.

The processing block reception view data of predetermined block unit from prime pressed by this distortion correction treatment portion 7, carrying out after the distortion correction, output to the processing block of back level, in above-mentioned structure example shown in Figure 1, the processing block of prime is corresponding to image processing part 6, and the processing block of back level is corresponding to the 2nd data order converter section 8.

In this distortion correction treatment portion 7, the control register 7a that is provided with going along with, be set from CPU 3 at the setting value of this distortion correction treatment portion 7 and various data etc., can read the state etc. of result from this CPU 3 simultaneously.

The processing summary of this distortion correction treatment portion 7 also as shown in Figure 4 and Figure 5, and is as described below substantially.Fig. 4 is the figure that is used to illustrate the summary of the interpolation processing that comprises distortion correction, and Fig. 5 is the figure that is used to illustrate the processing of 16 point interpolations.

At first, shown in Fig. 4 (B), prepare in advance the image after the distortion correction treatment coordinate system (X, Y).This coordinate system (before the beginning distortion correction treatment, do not obtain whatever by X, the Y) view data in.

Set this coordinate system (X, Y) impact point in (concerned pixel) (coordinate of each pixel of its image after corresponding to distortion correction treatment, be expressed as equally (X, Y).), obtain corresponding to this impact point (X, the coordinate of view data Y) (interpolated coordinates data) (X ', Y ') (with reference to Fig. 4 (A)) by coordinate transform.Be somebody's turn to do (X, Y) and (X ', Y ') corresponding relation is determined by the optical property that is used for to the optical system of above-mentioned CCD 1 imaging shot object image, according to the Design for optical system value or the inspection of the optical system after making obtain the parameter etc. of this corresponding relation having been carried out definition in advance, be stored in the not shown nonvolatile memory etc.And above-mentioned CPU 3 reads parameter from this nonvolatile memory etc., be set among the above-mentioned control register 7a.

Like this, when obtaining coordinate (X ', Y ') by corresponding relation, for the coordinate of the view data of the view data of obtaining this coordinate (X ', Y ') around needed is determined.For example, under the situation of carrying out the Cubic interpolation processing, as shown in Figure 5, and for this coordinate (X ', Y ') (view data of Fig. 5 becomes the point of Dout), 16 coordinate around the decision.

Therefore, according to the view data D0～D15 of this coordinate of 16, the view data Dout of the coordinate by using predetermined interpolation formula to obtain to represent (X ', Y ') point with white circle, it becomes impact point (X, view data Y) of the image after the distortion correction treatment.

(X Y) moves, Yi Bian calculate all images data of necessary scope, the view data after the generation distortion correction by making above-mentioned impact point on one side.

The distortion correction treatment portion 7 that is used to carry out this processing comprises with the lower part and constitutes as shown in Figure 2: the coordinate (X, the location of interpolation generating unit 21 Y) that are used to generate impact point; (X Y), calculates the distortion correction coordinate converting section 22 of the coordinate (X ', Y ') of the view data before the distortion correction treatment to be used for coordinate according to the impact point that is generated by this location of interpolation generating unit 21; Selector switch 23 is not carrying out under the situation of distortion correction treatment, and it is selected from the coordinate (X of above-mentioned location of interpolation generating unit 21 outputs, Y), under the situation of carrying out distortion correction treatment, the coordinate that selection is exported from above-mentioned distortion correction coordinate converting section 22 (X ', Y '); Memory controller 24, its control is read from the view data of the processing block of prime, and controls storage inside described later portion 25 so that send the view data of carrying out the needed surrounding pixel of interpolation processing for correspondence from the coordinate of above-mentioned selector switch 23 outputs; Storage inside portion 25, its storage is exported the view data of the needed surrounding pixel of interpolation from the view data of the processing block of prime to interpolation arithmetic unit 26 described later according to the control of above-mentioned memory controller 24; Interpolation arithmetic unit 26, it is according near the view data the impact point of this storage inside portion 25 outputs with from the coordinate of the impact point of above-mentioned selector switch 23 outputs, for example by the Cubic interpolation, obtain the view data of this impact point as described above, the processing block of level output backward.

Above-mentioned location of interpolation generating unit 21, distortion correction coordinate converting section 22 and selector switch 23 in these block structures becomes the key element that constitutes interpolated coordinates generating unit 20.

Above-mentioned location of interpolation generating unit 21 is used the interpolation starting position set by above-mentioned CPU 3 in above-mentioned control register 7a (XST YST) and interpolation step-length (Δ X, Δ Y), shown in following formula 1, calculates the impact point (X, coordinate Y) that carry out interpolation.

[formula 1]

$\left\{\begin{array}{c}X=X_{\mathrm{ST}}+k\×\mathrm{\ΔX}\\ Y=Y_{\mathrm{ST}}+l\×\mathrm{\ΔY}\end{array}\right.$

Here, k is the variable that is increased when making impact point at the only mobile Δ X of directions X, the 1st, and the variable that impact point is increased when the only mobile Δ Y of Y direction.

And (XST YST) can be set at the interior optional position of image in above-mentioned interpolation starting position.In addition, by suitably setting above-mentioned interpolation step-lengths (Δ X, Δ Y), can carry out the amplification of image or dwindle by above-mentioned CPU 3.

Above-mentioned distortion correction coordinate converting section 22 according to the coordinate of the impact point after the distortion correction treatment of above-mentioned location of interpolation generating unit 21 outputs (X, Y), coordinate of calculating the impact point before the distortion correction treatment as follows (X ', Y ').

Promptly, at first use the coordinate (Xd of center of distortion position of the image of process object, Yd), off-centring correcting value (the Xoff that proofread and correct position when being used for the subject offset that caused by this distortion correction after distortion correction treatment shooting, Yoff), and carry out in the parameter of the optical property of using the expression optical system being used under the situation of distortion correction treatment the image after proofreading and correct exceeded as necessary scope of view data or not enough scope of proofreading and correct and proofread and correct multiplying power M, obtain (the X (point) of the intermediate computations value shown in the following formula 2, Y (point)) (in article, will on character, be expressed as (point) by institute's target point here.)。

[formula 2]

$\left\{\begin{array}{c}\stackrel{\·}{X}=M\·(X-X_d)+(X_d+X_{\mathrm{off}})\\ \stackrel{\·}{Y}=M\·(Y-Y_d)+(Y_d+Y_{\mathrm{off}})\end{array}\right.$

And (Xd Yd) is the coordinate that is equivalent to the position on the image that optical axis intersected of the optical system of imaging subject optics picture on the above-mentioned CCD 1 to the coordinate of above-mentioned center of distortion position.

In addition, the coordinate of above-mentioned center of distortion position (Xd, Yd), the off-centring correcting value (Xoff, Yoff), scope proofreaies and correct multiplying power M and be set among the above-mentioned control register 7a by above-mentioned CPU 3.

Below, the calculated value that use is obtained (X (point), Y (point)), the coordinate (Xd of above-mentioned center of distortion position, Yd) and be used under the situation that is taken at interval view data at the longitudinal direction of image and different coefficient (SX that proofread and correct of space samples in a lateral direction, SY), by calculating the Z of expression from the distance of center of distortion (more precisely Z square) shown in the following formula 3.

[formula 3]

${\mathrm{<figure-callout\; id="2"\; label="Z"\; filenames="A200480015452.100571.png,A200480015452.100631.png"\; state="\{\{state\}\}">Z</figure-callout>}}^2={\{S_X\&CenterDot;(\stackrel{\&CenterDot;}{X}-X_d)\}}^2+{\{S_Y\&CenterDot;(\stackrel{\&CenterDot;}{Y}-Y_d)\}}^2$

The parameter that use the Z calculate like this, is set to the relevant optical property of the distorton aberration of the expression optical system among the above-mentioned control register 7a by above-mentioned CPU 3 is distortion correction coefficient A, B, C, D, E and aforementioned calculation value (X (point), coordinate (the Xd of (Y (point)) and above-mentioned center of distortion position, Yd), by shown in the following formula 4, calculate with distortion correction treatment after the coordinate (X of impact point, Y) coordinate of the impact point before the Dui Ying distortion correction treatment (X ', Y ').

[formula 4]

$\left\{\begin{array}{c}{X}^{\&prime;}=(\stackrel{\&CenterDot;}{X}-X_d)\&CenterDot;[1+A\&CenterDot;{\mathrm{<figure-callout\; id="2"\; label="Z"\; filenames="A200480015452.100571.png,A200480015452.100631.png"\; state="\{\{state\}\}">Z</figure-callout>}}^2+B\&CenterDot;{\mathrm{<figure-callout\; id="4"\; label="Z"\; filenames="A200480015452.100571.png,A200480015452.100611.png"\; state="\{\{state\}\}">Z</figure-callout>}}^4+C\&CenterDot;{\mathrm{<figure-callout\; id="6"\; label="Z"\; filenames="A200480015452.100571.png,A200480015452.100611.png"\; state="\{\{state\}\}">Z</figure-callout>}}^6+D\&CenterDot;{\mathrm{<figure-callout\; id="8"\; label="Z"\; filenames="A200480015452.100571.png,A200480015452.100631.png"\; state="\{\{state\}\}">Z</figure-callout>}}^8+E\&CenterDot;{\mathrm{<figure-callout\; id="10"\; label="Z"\; filenames="A200480015452.100571.png,A200480015452.100631.png"\; state="\{\{state\}\}">Z</figure-callout>}}^{10}+\&CenterDot;\&CenterDot;\&CenterDot;]+X_d\\ Y^{\&prime;}=(\stackrel{\&CenterDot;}{Y}-Y_d)\&CenterDot;[1+A\&CenterDot;{\mathrm{<figure-callout\; id="2"\; label="Z"\; filenames="A200480015452.100571.png,A200480015452.100631.png"\; state="\{\{state\}\}">Z</figure-callout>}}^2+B\&CenterDot;{\mathrm{<figure-callout\; id="4"\; label="Z"\; filenames="A200480015452.100571.png,A200480015452.100611.png"\; state="\{\{state\}\}">Z</figure-callout>}}^4+C\&CenterDot;{\mathrm{<figure-callout\; id="6"\; label="Z"\; filenames="A200480015452.100571.png,A200480015452.100611.png"\; state="\{\{state\}\}">Z</figure-callout>}}^6+D\&CenterDot;{\mathrm{<figure-callout\; id="8"\; label="Z"\; filenames="A200480015452.100571.png,A200480015452.100631.png"\; state="\{\{state\}\}">Z</figure-callout>}}^8+E\&CenterDot;{\mathrm{<figure-callout\; id="10"\; label="Z"\; filenames="A200480015452.100571.png,A200480015452.100631.png"\; state="\{\{state\}\}">Z</figure-callout>}}^{10}+\&CenterDot;\&CenterDot;\&CenterDot;]+Y_d\end{array}\right.$

Here, Fig. 3 is the figure of the example of the distorton aberration of expression when taking cancellate subject by optical system.At first, Fig. 3 (A) is the example of the cancellate subject of expression.In the past, because only consider 2 items of Z, though so can be when taking the subject shown in Fig. 3 (A) by optical system the distorton aberration of the distorton aberration of producible drum type shown in Fig. 3 (B) or the pillow type shown in Fig. 3 (C) carry out to a certain degree correction, can not proofread and correct the straw hat type distorton aberration shown in Fig. 3 (D).But in this 1st embodiment, shown in this formula 4, because consider to the number of times of 2 items that surpass Z, i.e. for example 4 items or 6 items are so also can proofread and correct the aberration of this more high order accurately.And, also can consider item to high order more.

(X, Y), or the coordinate of calculating by distortion correction coordinate converting section 22 (X ', Y ') is imported into selector switch 23 to the coordinate of calculating by above-mentioned location of interpolation generating unit 21, selects needed coordinate according to whether carrying out distortion correction.

In addition, above-mentioned interpolation arithmetic unit 26 is according to the coordinate from above-mentioned selector switch 23 outputs, read near the view data D0～D15 of the pixel this coordinate from above-mentioned storage inside portion 25, by using following formula 5, calculate the view data Dout after the relevant distortion correction treatment of this impact point, and output to back level piece.

[formula 5]

D _out＝k _x0(k _y0D ₀+k _y1D ₄+k _y2D ₈+k _y3D ₁₂)

+k _x1(k _y0D ₁+k _y1D _s+k _y2D ₉+k _y3D ₁₃)

+k _x2(k _y0D ₂+k _y1D ₆+k _y2D ₁₀+k _y3D ₁₄)

+k _x3(k _y0D ₃+K _y1D ₇+k _y2D ₁₁+k _y3D ₁₅)

Here, kx0～kx3, ky0～ky3 are the predetermined interpolation coefficients that is prescribed when for example carrying out the Cubic interpolation.

Then, Fig. 6 is the figure that reads order of the view data of this 1st embodiment of expression.

View data is read by following direction usually, all is the view data of carrying out all reading earlier 1 row repeatedly generally, then all reads the such action of view data of next adjacent lines.

Relative therewith, the image processing apparatus of this 1st embodiment is only read predetermined length at line direction, move to next line and equally only read predetermined length, after the predetermined line number that gathered together enough, press the output of column direction order, thereby the data order is changed, so that read view data at longitudinal direction by predetermined block unit.The width that can read at a high speed from frame memory 4 decides predetermined length at this line direction as unit.

Thereafter the piece that continues to read is at the piece of line direction adjacent (in Fig. 6, becoming right adjacent), when having arrived the right-hand member of view data, offsets downward a little and reads next piece group, makes and repeats at longitudinal direction with a series of group of reading up to now.The view data that needs for the data that generate the adjacent lines of being exported by the 2nd data order converter section 8 (horizontal direction) respectively has part to repeat.Therefore, at the 1st data order converter section 5, this part is read to need consideration.

Because the sense command of view data is sent continuously, thus reading of in fact this block unit carried out continuously, in the data in the elongated rectangular on the line direction among Fig. 6 shown in the solid line arrow, in longitudinal direction continuous stream mistake.

Explanation is used to make reading of such view data to become the structure of possible the 1st data order converter section 5 and the 2nd data order converter section 8 with reference to Fig. 7.Fig. 7 is the block scheme of the structure of expression data order converter section.

The 1st data order converter section 5 is shown in Fig. 7 (A), but the storer with view data of a plurality of storage block units has 2 herein, is storer 5a and storer 5b.Frame memory 4 switchably is connected in these storeies 5a and storer 5b, and image processing part 6 also switchably is connected in these storeies 5a and storer 5b, when frame memory 4 and storer 5a when a side among the storer 5b is connected, this storer 5a is switched with image processing part 6 with the opposing party among the storer 5b and is connected.That is, storer 5a, 5b are switched make them not be connected with image processing part 6 both sides with frame memory 4 simultaneously.

A part that is stored in the two field picture in the frame memory 4 is read at line direction by block unit, and is stored in one of them storer, for example is storer 5a here.

Parallel therewith, the view data of the block unit that is read out and stores from frame memory 4 is called over by column direction (longitudinal direction) from storer 5b, outputs to image processing part 6.

When from frame memory 4 to storer 5a write and from storer 5b when reading of image processing part 6 finished, switch the switch that writes the switch of side and read side, then begin to carry out to storer 5b the writing of view data of next block unit, and begin reading to the view data of the block unit of image processing part 6 from storer 5a from frame memory 4.

The 2nd data order converter section 8 almost similarly constitutes with above-mentioned the 1st data order converter section 5 shown in Fig. 7 (B), also almost similarly moves.

That is, the 2nd data orders converter section 8 has storer 8a and storer 8b and constitutes.

And, when the 2nd data order converter section 8 moves, side storer 8a and the storer 8b is write at column direction (longitudinal direction) from distortion correction treatment portion 7, the opposing party from storer 8a and storer 8b reads at line direction (horizontal direction), outputs to JPEG handling part 9.

In addition, as shown in Figure 8 as the storage inside portion 25 needed buffer memories of Fig. 2.Fig. 8 is expression correcting image and the corresponding relation of photographed images and the figure that handles needed buffer memory.

The dotted line of Fig. 8 point intersected with each other is represented from image processing part 6 to the view data of distortion correction treatment portion 7 input (view data before promptly carrying out distortion correction treatment, and be the view data of reading from frame memory 4).In addition, stain is represented according to the coordinate of the impact point after the distortion correction treatment (X, the coordinate of the impact point before the distortion correction treatment of Y) calculating (X ', Y '), expression becomes a plurality of points (in example shown in Figure 8, by the point of horizontal 4 * vertical 5 formations) of process object.These points are used to for example carry out distortion correction treatment with 5 some units of arranging at longitudinal direction, for the vertical needed buffer memory of 5 points (5 points that dispose on heavy line among Fig. 8) of handling the rightmost side in for example horizontal piece at 4 * vertical 5 is the scope shown in the arrow among Fig. 8, promptly (wherein by the input image data piece of indulging 9 * horizontal 7 formations, this be need when carrying out the Cubic interpolation impact point around 16 the situation of view data, if the change interpolation method, then needed buffer memory can change).

And,, must guarantee 4 angle parts of the image of distorton aberration maximum are carried out the size of interpolation processing about the size (memory capacity) of impact damper (storage inside portion 25).

In addition, in example shown in Figure 6, any position in the frame picture all equally obtains the pixel count of reading at longitudinal direction, but is not limited thereto, also can be as shown in Figure 9, make the pixel count difference of reading according to the position at longitudinal direction.Fig. 9 is expression according to make the width of the view data of reading at the figure of the different example of longitudinal direction from the distance of center of distortion.That is, the distortion that is caused by distorton aberration is then big more away from center of distortion, then more little the closer to center of distortion on the contrary more.Therefore, if in the position away from center of distortion, then the pixel count of reading at longitudinal direction is more, and is then less at the pixel count that longitudinal direction is read in the position near center of distortion, can make like this and handle more high speed.

And Figure 10 represents to make the size of the view data of reading and the figure that reads the different example in starting position according to the distance of distance center of distortion.In this example shown in Figure 10, change the pixel count of reading at longitudinal direction, and also read the starting position of view data with the block unit change according to the position of horizontal direction.

That is, if center of distortion is positioned at picture substantial middle portion situation as an example, even then on delegation, central portion is then the closer to center of distortion, about end then more away from center of distortion.Therefore, the pixel count of reading at longitudinal direction near the central portion of center of distortion is few, and the pixel count of reading at longitudinal direction away from the left and right end portions of center of distortion is many.And, under the situation that illustrated drum type distorton aberration takes place, corresponding to curve shape based on this aberration, about end with the downside slightly of longitudinal direction starting position as the view data of reading block unit, at central portion with the upside slightly of longitudinal direction starting position as the view data of reading block unit.Here, show the situation of the distorton aberration that drum type takes place, but under the situation of the distorton aberration that pillow type or straw hat type take place, also can be corresponding to the distortion shape that has taken place, the pixel count that change is read.

And, in the piece of reading, not only can make the pixel count of reading in the longitudinal direction difference, also can make it in the horizontal direction difference.

In addition, above-mentioned in, the view data after handling by image processing part 6 is carried out distortion correction, but is not limited thereto.

Figure 11 is the block scheme of the 1st variation of the structure of presentation video treating apparatus.Figure 11 shows will be from the camera data of CCD 1 output (for example, the Bayer data) after temporarily being stored in the frame memory 4, carried out the structure example of distortion correction before 3 changes, compare with above-mentioned structure shown in Figure 1, the position of image processing part 6 and distortion correction treatment portion 7 is exchanged.In above-mentioned Fig. 1, for example the view data of having been undertaken by image processing part 6 after 3 changes is handled according to every kind of color, but be not limited thereto, as shown in Figure 11, also can carry out distortion correction treatment Bayer data from CCD 1 output with color filter that Bayer arranges.Under this situation, be not to use adjacent a plurality of pixels (for example 16 pixels) to carry out interpolation processing, and the homochromy neighbor that uses Bayer to arrange carry out interpolation processing.According to this structure, compare with the view data after 3 changes, can reduce the data volume of carrying out distortion correction.

Below, Figure 12 is the block scheme of the 2nd variation of the structure of presentation video treating apparatus.This Figure 12 has represented to carry out the structure example of distortion correction treatment to being recorded in view data in storage card etc. 10.In this structure example, dispose JPEG handling part 9 in the prime of the 1st data orders converter section 5, the compression mode such as JPEG of passing through of reading from storage card etc. 10 has been carried out the view data of compression decompressed.View data after the decompression is handled by distortion correction treatment portion 7 in a manner described via the 1st data order converter section 5 and image processing part 6, is converted into original data order in the 2nd data order converter section 8.And, under the situation in be recorded in storage card etc. 10 as TIFF unpacked datas such as (Tag image fileformat), also can not carry out decompression especially, comprise distortion correction in interior Flame Image Process and carry out.

Then, Figure 13 is the block scheme of the 3rd variation of the structure of presentation video treating apparatus.This Figure 13 has represented the view data after the distortion correction treatment not to be compressed, but for image demonstration etc. and the structure example of output.The view data that is converted into original data order by the 2nd data orders converter section 8 is not utilized compression mode such as JPEG and compresses, but is written into video memory 12 by bus 11, is shown as image.

Further, Figure 14 is the block scheme of the 4th variation of the structure of presentation video treating apparatus.This Figure 14 has represented that the range information that will use (above-mentioned from the center of distortion to the location of interpolation apart from Z) also is used for the structure example of other Flame Image Process in distortion correction treatment.In this structure example, the back level at image processing part 6 has disposed on the pipeline processes path: the shadow correction portion 14 as image processing part that is used to proofread and correct the ambient light quantity not sufficient that is caused by above-mentioned optical system in the following order; Be used to cut the low-pass filtering as image processing part (LPF) handling part 15 of radio-frequency component not; Above-mentioned distortion correction treatment portion 7; And handling part 16 is emphasized at the edge as image processing part that is used for emphasizing the marginal portion of image.And range information emphasized handling part 16 output from distortion correction treatment portion 7 to shadow correction portion 14, low-pass filtering (LPF) handling part 15, edge, in handling, these use this range information as required.

Thereby shadow correction portion 14 can suitably proofread and correct the ambient light quantity not sufficient that produces according to the distance from center of distortion.In addition, at the distorton aberration that produces according to the distance from center of distortion for example is under the situation of drum type, when having proofreaied and correct distorton aberration, the periphery of image is elongated, the sharpness of image might descend, and emphasizes that by low-pass filtering treatment portion 15 and edge handling part 16 can carry out suitable correction to this.And, because these shadow correction portions 14, low-pass filtering treatment portion 15, edge emphasize that handling part 16 does not need individually to calculate respectively range information, so can dwindle circuit scale.

And, in the diagram from distortion correction treatment portion 7 to shadow correction portion 14 and the low-pass filtering treatment portion 15 output range informations that are positioned on the pipeline processes path in the prime of this distortion correction treatment portion 7, but consider processing sequence, also can be configured for calculating processing block in addition, and it is configured in the preceding-stage side of each piece of service range information apart from Z.

And, in above-mentioned, the example that uses image processing apparatus in digital camera be illustrated, but be not limited thereto, can be special-purpose image processing apparatus, also can be the image processing apparatus of the type that provides as the expander board of computing machine etc.

In addition, object as Flame Image Process, be not limited in digital camera or video camera, by image units such as CCD the subject by optical system imaging is carried out the view data that opto-electronic conversion obtains as imaging apparatus, perhaps this view data is handled the non-compressing image data that obtains, the compressing image data of perhaps this view data being handled back compression and obtaining also can be with for example by being taken into the film of taking with the silver halide photography machine with image units such as scanners, or printed article and view data of obtaining etc. are as the object of above-mentioned distortion correction treatment.

And, be not limited to pixel data as the object of Flame Image Process and be arranged in view data on line direction and the column direction fully.For example, even the captured view data of imaging apparatus of arranging with the pixel with honeycomb type can be carried out the substantive view data of handling at line direction and column direction as long as become, then also can carry out above-mentioned distortion correction treatment.

According to this 1st embodiment, transmission to the view data of image processing part and distortion correction treatment portion is undertaken by the information communicating path that is different from bus, so that can carry out pipeline processes, and because carry out the data transmission by block unit, and prepare it and read direction, so need not increase the data conveying capacity and the memory span of bus, can comprise distortion correction in interior Flame Image Process.

And, because considered 4 items of the distance from the center of distortion to the location of interpolation, 6 items or calculated the coordinate of the impact point before the distortion correction treatment corresponding, so the distorton aberration etc. that also can the proofread and correct the straw hat type accurately aberration of high order more with the coordinate of impact point after the distortion correction treatment than its higher high-order term.

In addition, because can select the coordinate that generated by the location of interpolation generating unit and by the coordinate of distortion correction coordinate converting section institute conversion, so can be as required select whether to carry out distortion correction according to desirable by selector switch.Like this, can the time not carry out distortion correction treatment, and view data etc. temporarily is stored in the storage card etc., read view data from this storage card again in the moment of back and carry out distortion correction treatment in shooting.If carry out this selection, then because when shooting, can omit distortion correction treatment, so can carry out processing more at a high speed.

And, will output to shadow correction portion and low-pass filter by the range information that distortion correction treatment portion calculates, handling part is emphasized at the edge, thereby can suitably proofread and correct ambient light quantity not sufficient or correcting image unintelligible suitably, and can not increase circuit scale.

In addition, according to because of size from the different distorton aberration of the distance of center of distortion, the suitable at least one side the size of the size of the line direction of the view data of the block unit read from storer of change and column direction, handle needed minimal data thereby can read, therefore can make the processing high speed.

Figure 15～Figure 20 is the figure of expression the 2nd embodiment of the present invention, and Figure 15 is the block scheme of the structure of presentation video treating apparatus.

In the 2nd embodiment, omit the explanation of the part identical, mainly describe with regard to difference with above-mentioned the 1st embodiment.

The image processing apparatus of the 2nd embodiment has been removed the 1st data order converter section 5 and the 2nd data order converter section 8 from the image processing apparatus of above-mentioned the 1st embodiment shown in Figure 1.

In addition, the image processing part of the 2nd embodiment, not only the view data after being handled by above-mentioned image processing part 6 is carried out distortion correction treatment, dwindle processing but also amplify as the distortion correction treatment portion 7 of distortion correction treatment unit.

And same as described above is that above-mentioned image processing part 6, distortion correction treatment portion 7, JPEG handling part 9 are connected to by the information communicating path that is different from bus 11 can carry out pipeline processes.At this moment, can be above-mentioned storage inside portion 25 shown in Figure 2 or 2 port SRAMs (static memory) 25a shown in Figure 16 by the internal buffer of handling the image processing part that the capacity that makes reduces by block unit.

In addition, the structure of distortion correction treatment portion 7 with reference to above-mentioned Fig. 2 illustrated identical.

And in above-mentioned structure example shown in Figure 15, the processing block of the prime of distortion correction treatment portion 7 is corresponding to image processing part 6, and the processing block of back level is corresponding to JPEG handling part 9.

Here, describe to the fundamental formular of in above-mentioned location of interpolation generating unit 21 and distortion correction coordinate converting section 22, calculating coordinate time and by the Practical Formula that can dwindle circuit scale to its distortion.

At first, fundamental formular is described.

Above-mentioned location of interpolation generating unit 21 is to use substantially by above-mentioned CPU 3 and is set to interpolation starting position (XST among the above-mentioned control register 7a, YST) and interpolation step-length (Δ X, Δ Y), shown in above-mentioned formula 1 like that, calculate the impact point that carries out interpolation coordinate (X, Y).

Above-mentioned distortion correction coordinate converting section 22 be substantially according to the coordinate of the impact point after the distortion correction treatment of above-mentioned location of interpolation generating unit 21 outputs (X, Y), by coordinate of calculating the impact point before the distortion correction treatment as follows (X ', Y ').

That is, distortion correction coordinate converting section 22 is at first obtained the intermediate computations value shown in the above-mentioned formula 2 (X (point), Y (point)) (will be on character in article institute's target point be expressed as (point)) here.

Then, distortion correction coordinate converting section 22 is by calculating the Z of expression from the distance of center of distortion (more precisely Z square) shown in the above-mentioned formula 3.

Distortion correction coordinate converting section 22 is used the Z that calculates like this, the parameter that is set to the optical property relevant with distorton aberration of the expression optical system among the above-mentioned control register 7a by above-mentioned CPU 3 is distortion correction coefficient A, B, C, aforementioned calculation value (X (point), Y (point)), and the coordinate (Xd of above-mentioned center of distortion position, Yd), by shown in the following formula 6, calculate with distortion correction treatment after the coordinate (X of impact point, Y) coordinate of the impact point before the Dui Ying distortion correction treatment (X ', Y ').

[formula 6]

$\left\{\begin{array}{c}{X}^{\&prime;}=(\stackrel{\&CenterDot;}{X}-X_d)\&CenterDot;[1+A\&CenterDot;{\mathrm{<figure-callout\; id="2"\; label="Z"\; filenames="A200480015452.100571.png,A200480015452.100631.png"\; state="\{\{state\}\}">Z</figure-callout>}}^2+B\&CenterDot;{\mathrm{<figure-callout\; id="4"\; label="Z"\; filenames="A200480015452.100571.png,A200480015452.100611.png"\; state="\{\{state\}\}">Z</figure-callout>}}^4+C\&CenterDot;Z^6]+X_d\\ Y^{\&prime;}=(\stackrel{\&CenterDot;}{Y}-Y_d)\&CenterDot;[1+A\&CenterDot;{\mathrm{<figure-callout\; id="2"\; label="Z"\; filenames="A200480015452.100571.png,A200480015452.100631.png"\; state="\{\{state\}\}">Z</figure-callout>}}^2+B\&CenterDot;{\mathrm{<figure-callout\; id="4"\; label="Z"\; filenames="A200480015452.100571.png,A200480015452.100611.png"\; state="\{\{state\}\}">Z</figure-callout>}}^4+C\&CenterDot;Z^6]+Y_d\end{array}\right.$

In the 2nd embodiment, shown in this formula 6, because considered the number of times of 2 items that surpass Z, i.e. so for example 4 items or 6 items are the distorton aberration etc. that also can proofread and correct the straw hat type shown in above-mentioned Fig. 3 (D) the accurately aberration of high order more.And, show the example of considering 6 items here, but also can be shown in above-mentioned formula 4, to 8 items, 10 items etc. more the aberration of high order proofread and correct.

Above-mentioned coordinate of calculating by location of interpolation generating unit 21 (X, Y), or the coordinate of calculating by distortion correction coordinate converting section 22 (X ', Y ') be imported into selector switch 23, according to whether carrying out distortion correction, select needed coordinate.

Below, the Practical Formula that can dwindle circuit scale is described.

At first, formula 2 and formula 1 are updated in the above-mentioned formula 3, are deformed into shown in the following formula 7.

[formula 7]

${\mathrm{<figure-callout\; id="2"\; label="Z"\; filenames="A200480015452.100571.png,A200480015452.100631.png"\; state="\{\{state\}\}">Z</figure-callout>}}^2={\mathrm{<figure-callout\; id="2"\; label="M"\; filenames="A200480015452.100571.png,A200480015452.100631.png"\; state="\{\{state\}\}">M</figure-callout>}}^2\&CenterDot;({[S_X\&CenterDot;\{(X-X_d)+\frac{X_{\mathrm{off}}}{M}\left\}\right]}^2+{[S_Y\&CenterDot;\{(Y-Y_d)+\frac{Y_{\mathrm{off}}}{M}\left\}\right]}^2)$

$={\mathrm{<figure-callout\; id="2"\; label="M"\; filenames="A200480015452.100571.png,A200480015452.100631.png"\; state="\{\{state\}\}">M</figure-callout>}}^2\&CenterDot;({[S_X\&CenterDot;\{(X_{\mathrm{ST}}+\mathrm{k\&Delta;X}-X_d)+\frac{X_{\mathrm{off}}}{M}\left\}\right]}^2+{[S_Y\&CenterDot;\{(Y_{\mathrm{ST}}+\mathrm{l\&Delta;Y}-Y_d)+\frac{Y_{\mathrm{off}}}{M}\left\}\right]}^2)$

And, introduce the new constant expression shown in the formula 8, above-mentioned formula 7 is deformed into shown in the formula 9.

[formula 8]

$\left\{\begin{array}{c}{\stackrel{\&CenterDot;\&CenterDot;}{X}}_{\mathrm{ST}}=S_X\&CenterDot;\{(X_{\mathrm{ST}}-X_d)+\frac{X_{\mathrm{off}}}{M}\}\\ {\stackrel{\&CenterDot;\&CenterDot;}{Y}}_{\mathrm{ST}}=S_Y\&CenterDot;\{(Y_{\mathrm{ST}}-Y_d)+\frac{Y_{\mathrm{off}}}{M}\}\\ \mathrm{\&Delta;}\stackrel{\&CenterDot;\&CenterDot;}{X}=S_X\&times;\mathrm{\&Delta;X}\\ \mathrm{\&Delta;}\stackrel{\&CenterDot;\&CenterDot;}{Y}=S_Y\&times;\mathrm{\&Delta;Y}\end{array}\right.$

[formula 9]

${\mathrm{<figure-callout\; id="2"\; label="Z"\; filenames="A200480015452.100571.png,A200480015452.100631.png"\; state="\{\{state\}\}">Z</figure-callout>}}^2=M^2{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^2={\mathrm{<figure-callout\; id="2"\; label="M"\; filenames="A200480015452.100571.png,A200480015452.100631.png"\; state="\{\{state\}\}">M</figure-callout>}}^2\&CenterDot;\{{({\stackrel{\&CenterDot;\&CenterDot;}{X}}_{\mathrm{ST}}+\mathrm{k\&Delta;}\stackrel{\&CenterDot;\&CenterDot;}{X})}^2+{({\stackrel{\&CenterDot;\&CenterDot;}{Y}}_{\mathrm{ST}}+\mathrm{l\&Delta;}\stackrel{\&CenterDot;\&CenterDot;}{Y})}^2\}$

Here, the Z in the formula 9 (2 point) is defined as shown in following formula 10, and X2, Y2 (interpolated coordinates data) are defined as shown in following formula 11.

[formula 10]

$\stackrel{\&CenterDot;\&CenterDot;}{Z}=\frac{Z}{M}$

[formula 11]

$\left\{\begin{array}{c}\mathrm{<figure-callout\; id="2"\; label="X"\; filenames="A200480015452.100571.png,A200480015452.100631.png"\; state="\{\{state\}\}">X</figure-callout>}2={\stackrel{\&CenterDot;\&CenterDot;}{X}}_{\mathrm{ST}}+\mathrm{k\&Delta;}\stackrel{\&CenterDot;\&CenterDot;}{X}\\ \mathrm{<figure-callout\; id="2"\; label="Y"\; filenames="A200480015452.100571.png,A200480015452.100631.png"\; state="\{\{state\}\}">Y</figure-callout>}2={\stackrel{\&CenterDot;\&CenterDot;}{Y}}_{\mathrm{ST}}+\mathrm{l\&Delta;}\stackrel{\&CenterDot;\&CenterDot;}{Y}\end{array}\right.$

If use the Z (2 point) by definition shown in this formula 10 and the formula 11, then above-mentioned formula 6 is deformed into shown in following formula 12.

[formula 12]

$\left\{\begin{array}{c}{X}^{\&prime;}=[1+\left({\mathrm{AM}}^2\right){\stackrel{\&CenterDot;\&CenterDot;}{Z}}^2+\left({\mathrm{BM}}^4\right){\stackrel{\&CenterDot;\&CenterDot;}{Z}}^4+\left({\mathrm{CM}}^6\right){\stackrel{\&CenterDot;\&CenterDot;}{Z}}^6]\&CenterDot;(\stackrel{\&CenterDot;}{X}-X_d)+X_d\\ =[1+\stackrel{\&CenterDot;}{A}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^2+\stackrel{\&CenterDot;}{B}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^4+\stackrel{\&CenterDot;}{C}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^6]\&CenterDot;(\stackrel{\&CenterDot;}{X}-X_d)+X_d\\ =[1+\stackrel{\&CenterDot;}{A}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^2+\stackrel{\&CenterDot;}{B}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^4+\stackrel{\&CenterDot;}{C}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^6]\&CenterDot;\{M(X_{\mathrm{ST}}-X_d)+X_{\mathrm{off}}+M\&CenterDot;\mathrm{k\&Delta;X}\}+X_d\\ =[1+\stackrel{\&CenterDot;}{A}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^2+\stackrel{\&CenterDot;}{B}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^4+\stackrel{\&CenterDot;}{C}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^6]\&CenterDot;(\stackrel{\&CenterDot;\&CenterDot;\&CenterDot;}{X}+\mathrm{k\&Delta;}\stackrel{\&CenterDot;\&CenterDot;\&CenterDot;}{X})+X_d\\ =F\&CenterDot;X1+X_d\\ Y^{\&prime;}=[1+\left({\mathrm{AM}}^2\right){\stackrel{\&CenterDot;\&CenterDot;}{Z}}^2+\left({\mathrm{BM}}^4\right){\stackrel{\&CenterDot;\&CenterDot;}{Z}}^4+\left({\mathrm{CM}}^6\right){\stackrel{\&CenterDot;\&CenterDot;}{Z}}^6]\&CenterDot;(\stackrel{\&CenterDot;}{Y}-Y_d)+Y_d\\ =[1+\stackrel{\&CenterDot;}{A}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^2+\stackrel{\&CenterDot;}{B}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^4+\stackrel{\&CenterDot;}{C}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^6]\&CenterDot;(\stackrel{\&CenterDot;}{Y}-Y_d)+Y_d\\ =[1+\stackrel{\&CenterDot;}{A}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^2+\stackrel{\&CenterDot;}{B}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^4+\stackrel{\&CenterDot;}{C}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^6]\&CenterDot;\{M(Y_{\mathrm{ST}}-Y_d)+Y_{\mathrm{off}}+M\&CenterDot;\mathrm{l\&Delta;Y}\}+Y_d\\ =[1+\stackrel{\&CenterDot;}{A}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^2+\stackrel{\&CenterDot;}{B}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^4+\stackrel{\&CenterDot;}{C}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^6]\&CenterDot;(\stackrel{\&CenterDot;\&CenterDot;\&CenterDot;}{Y}+\mathrm{l\&Delta;}\stackrel{\&CenterDot;\&CenterDot;\&CenterDot;}{Y})+Y_d\\ =F\&CenterDot;Y1+Y_d\end{array}\right.$

Here, in this formula 12, used by the constant expression or the variable expression that define shown in following formula 13～formula 16.

[formula 13]

$\left\{\begin{array}{c}\stackrel{\&CenterDot;}{A}=A{M}^2\\ \stackrel{\&CenterDot;}{B}=B{M}^4\\ \stackrel{\&CenterDot;}{C}=\mathrm{<figure-callout\; id="6"\; label="C\; M"\; filenames="A200480015452.100571.png,A200480015452.100611.png"\; state="\{\{state\}\}">C</figure-callout>}{M}^{}{}^6\end{array}\right.$

[formula 14]

$\left\{\begin{array}{c}\stackrel{\&CenterDot;\&CenterDot;\&CenterDot;}{X}=M(X_{\mathrm{ST}}-X_d)+X_{\mathrm{off}}\\ \mathrm{\&Delta;}\stackrel{\&CenterDot;\&CenterDot;\&CenterDot;}{X}=M\&CenterDot;\mathrm{\&Delta;X}\\ \stackrel{\&CenterDot;\&CenterDot;\&CenterDot;}{Y}=M(Y_{\mathrm{ST}}-Y_d)+Y_{\mathrm{off}}\\ \mathrm{\&Delta;}\stackrel{\&CenterDot;\&CenterDot;\&CenterDot;}{Y}=M\&CenterDot;\mathrm{\&Delta;Y}\end{array}\right.$

[formula 15]

$\left\{\begin{array}{c}\mathrm{<figure-callout\; id="1"\; label="X"\; filenames="A200480015452.100581.png,A200480015452.100591.png"\; state="\{\{state\}\}">X</figure-callout>}1=\stackrel{\&CenterDot;\&CenterDot;\&CenterDot;}{X}+\mathrm{k\&Delta;}\stackrel{\&CenterDot;\&CenterDot;\&CenterDot;}{X}\\ \mathrm{<figure-callout\; id="1"\; label="Y"\; filenames="A200480015452.100581.png,A200480015452.100591.png"\; state="\{\{state\}\}">Y</figure-callout>}1=\stackrel{\&CenterDot;\&CenterDot;\&CenterDot;}{Y}+\mathrm{l\&Delta;}\stackrel{\&CenterDot;\&CenterDot;\&CenterDot;}{Y}\end{array}\right.$

[formula 16]

$F=[1+\stackrel{\&CenterDot;}{A}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^2+\stackrel{\&CenterDot;}{B}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^4+\stackrel{\&CenterDot;}{C}{\stackrel{\&CenterDot;\&CenterDot;}{Z}}^6]$

Carrying out under the situation of computing according to the fundamental formular shown in above-mentioned formula 1～formula 3 and the formula 6, coefficient is 14, and the multiplying number of times is 13 times.That is, coefficient be the center of distortion position (Xd, Yd), off-centring correcting value (Xoff, Yoff), scope proofread and correct multiplying power M, coefficient (Sx, Sy), distortion correction coefficient A, B, C, interpolation starting position (XST, YST), interpolation step-length (Δ X, Δ Y), add up to 14.In addition, the multiplying number of times is: with the multiplying of M in the formula 22 times; Respectively with formula 3 in the multiplying of Sx, Sy and 2 square operations totally 4 times; With the multiplying of distortion correction coefficient A in the formula 6, B, C 3 times; Multiplying was 2 times during 4 powers of Z and 6 powers calculated; The multiplying of braces and round bracket 2 times adds up to 13 times.

Relative therewith, carrying out under the situation of computing according to the Practical Formula shown in above-mentioned formula 7～formula 16, coefficient is 13, the multiplying number of times is 9 times.That is, coefficient is X (2 point) ST, Y (2 point) ST, Δ X (2 point), Δ Y (2 point), X (3 point), Y (3 point), Δ X (3 point), Δ Y (3 point), A (point), B (point), C (point), Xd, Yd, adds up to 13.In addition, the multiplying number of times is: 2 square operations in the bracket in the formula 92 times; With the multiplying of A (point), B (point) in the formula 16, C (point) 3 times; Multiplying was 2 times during 4 powers of Z in this formula 16 (point) and 6 powers calculated; With the multiplying of F in the formula 12 2 times, add up to 9 times.

Handled number in this computing, even dynamic range is big, calculation times only increases a little, it is very big that circuit scale also can become, therefore by carrying out computing by the Practical Formula shown in above-mentioned, can reduce the number of multiplier, and can cut down the register that is used to set coefficient, can effectively dwindle circuit scale.

Based on the Practical Formula of having carried out such distortion, use by above-mentioned CPU 3 corresponding to the location of interpolation counting circuit 21a of above-mentioned location of interpolation generating unit 21 (with reference to Figure 16 described later) and to be set in interpolation starting position (X (3 point) among the above-mentioned control register 7a, Y (3 point)) and interpolation step-length (Δ X (3 point), Δ Y (3 point)), shown in above-mentioned formula 15, calculate the impact point that carries out interpolation coordinate (location of interpolation) (X1, Y1).

In addition, the distortion correction coefficient calculation circuit 22a as the distortion correction coefficient calculation unit of above-mentioned distortion correction coordinate converting section 22 (with reference to Figure 16 described later and Figure 17), use is set in A (point), B (point), C (point) among the above-mentioned control register 7a by above-mentioned CPU 3, shown in above-mentioned formula 16, calculate distortion correction coefficient F.And, as hereinafter described, also can calculate distortion correction coefficient F by structure shown in Figure 180, replace this structure shown in Figure 17.

And, the location of interpolation correcting circuit 22b of above-mentioned distortion correction coordinate converting section 22 (with reference to Figure 16 described later) uses distortion correction coefficient F that calculates and the coordinate (Xd that is set in the center of distortion position among the above-mentioned control register 7a by above-mentioned CPU 3, Yd), coordinate (location of interpolation) (X1 according to above-mentioned impact point, Y1), utilize above-mentioned formula 12 to calculate the coordinate (interpolated coordinates data) of the impact point before the distortion correction treatment (X ', Y ').

Then, above-mentioned interpolation arithmetic unit 26 is according to the coordinate from above-mentioned selector switch 23 outputs, read near the view data D0～D15 of the pixel this coordinate from above-mentioned storage inside portion 25, by using above-mentioned formula 5, calculate the view data Dout after the distortion correction treatment relevant, output to the processing block of back level with this impact point.

Figure 16 is the block scheme of the more detailed structure of expression distortion correction treatment portion 7.

Above-mentioned location of interpolation generating unit 21 has and is used for by top described coordinate (X1, location of interpolation counting circuit 21a Y1) that calculates above-mentioned impact point.

Above-mentioned distortion correction coordinate converting section 22 has the distortion correction coefficient calculation circuit 22a that is used for by calculating above-mentioned distortion correction coefficient F shown in the above-mentioned formula 16, and use the distortion correction coefficient F that calculates by this distortion correction coefficient calculation circuit 22a location of interpolation correcting circuit 22b by the coordinate of calculating the impact point before the distortion correction treatment shown in the above-mentioned formula 12 (X ', Y ').

Above-mentioned selector switch 23 under the situation of not carrying out distortion correction treatment (with whether amplify dwindle handle irrelevant), selection is from the coordinate (X1 of above-mentioned location of interpolation counting circuit 21a, Y1), under the situation of carrying out distortion correction treatment (with whether be accompanied by amplify dwindle handle irrelevant), selection is from the coordinate of above-mentioned location of interpolation correcting circuit 22b (X ', Y ').

The coordinate of respectively this selector switch 23 being selected by totalizer 27a, 27b (X1, Y1) or the coordinate of coordinate (X ', Y ') and the center of distortion position of setting by above-mentioned CPU 3 via control register 7a (Xd Yd) carries out addition.

The output of these totalizers 27a, 27b is output to reads address generating circuit 24a and buffer memory burst size counting circuit 24c.

Further, the coordinate of calculating by above-mentioned location of interpolation counting circuit 21a (X1, Y1), also by be imported into this via different other path, the path of above-mentioned selector switch 23 and read address generating circuit 24a.And, this is read address generating circuit 24a and will store and this coordinate (X1, Y1) Guan Lian pixel data is (under the situation of carrying out 16 point interpolations, with this coordinate (X1, Y1) for 16 pixel datas at center) address AD R export to 2 port SRAM 25a, and (for example with interpolation coefficient, interpolation coefficient kx0～kx3 shown in above-mentioned formula 5, the pixel data of ky0～ky3) and expression output are that the serial data control signal of pixel data of which position of D0～D15 outputs to interpolation circuit 26a.And this reads address generating circuit 24a will write the processing block that enabling signal WE_N exports to the back level.

Above-mentioned 2 port SRAM 25a are the circuit parts corresponding to above-mentioned storage inside portion 25 shown in Figure 2.

Interpolation circuit 26a is corresponding to above-mentioned interpolation arithmetic unit shown in Figure 2 26, the view data that this interpolation circuit 26a use is read from above-mentioned 2 port SRAM 25a is carried out the interpolation processing shown in above-mentioned formula 5, the view data after handling is outputed to the processing block of back level.

Above-mentioned buffer memory burst size counting circuit 24c calculates releasable memory capacity (buffer memory burst size) in above-mentioned 2 port SRAM 25a according to from the output of above-mentioned location of interpolation counting circuit 21a and from the output of above-mentioned selector switch 23.

Impact damper vacant capacity monitoring circuit 24d grasps the situation of the vacant capacity of above-mentioned 2 port SRAM 25a with reference to the output of this buffer memory burst size counting circuit 24c.

Write the view data of address generating circuit 24b reception, be recorded among the above-mentioned 2 port SRAM 25a from the processing block of prime.

GRANT_N sends the request signal REQ_N of decision circuit 24e reception from the requested image data of the processing block of back level, according to the above-mentioned output that writes address generating circuit 24b and buffer memory burst size counting circuit 24c, can judgement send view data, under the situation that can send, Ji processing block output enabling signal GRANT_N backward, and also to above-mentioned location of interpolation counting circuit 21a output.This GRANT_N sends decision circuit 24e and also triggers trig to this distortion correction coefficient calculation circuit 22a output, make distortion correction coefficient calculation circuit 22a according to the location of interpolation counting circuit 21a that has received this enabling signal GRANT_N calculate coordinate (X1, Y1) and output timing come output distortion correction coefficient F.

And in the structure of above-mentioned distortion correction treatment portion 7 shown in Figure 16, supply with clock CLK2 to each circuit except above-mentioned distortion correction coordinate converting section 22, and supply with the clock CLK1 that is different from this clock CLK2 to this distortion correction coordinate converting section 22.

Like this, do not carrying out under the situation of distortion correction treatment, promptly for example only amplifying under the situation of dwindling processing, or distortion correction treatment and amplification are dwindled and are handled under the situation that two sides do not carry out, if stop supply clock CLK1, then can suppress power consumption unnecessary to distortion correction coordinate converting section 22.In addition, by reducing or control with returning the clock number of the clock CLK1 that is supplied with, also can control and adjust the number of times that generates the interpolated coordinates data in the time per unit.

Below, the action of this distortion correction treatment portion 7 shown in Figure 16 is described.

Impact damper vacant capacity monitoring circuit 24d monitors the vacant capacity of 2 port SRAM 25a by buffer memory burst size counting circuit 24c, if predetermined vacant capacity is arranged, then the processing block to prime sends request signal REQ, so that the view data of the block unit that transmission is predetermined (below, suitably be called unit capable (UL) data) (step S1).

The processing block of prime receives this request signal REQ, sends enabling signal GRANT in the time can sending view data, and above-mentioned impact damper vacant capacity monitoring circuit 24d receives this enabling signal GRANT (step S2).

This impact damper vacant capacity monitoring circuit 24d is by holding the vacant capacity of 2 port SRAM 25a at the counter that inside kept, when receiving enabling signal GRANT, the value of this internal counter is deducted 1.If this internal counter becomes 0, then this impact damper vacant capacity monitoring circuit 24d moves so that cancel above-mentioned request signal REQ (step S3).

And, write enabling signal WE from the processing block of prime to writing address generating circuit 24b input, then input image data.Corresponding therewith, write address generating circuit 24b to 2 port SRAM 25a output control signal, with view data DATA be written among this 2 port SRAM 25a by the specified zone of address AD DRESS.In addition,, write address generating circuit 24b and just increase BLC counter (being illustrated in the counter that has stored how many data among the 2 port SRAM 25a as internal buffer), export to GRANT_N and send decision circuit 24e (step S4) whenever the 1UL data are transfused to.

When GRANT_N sends decision circuit 24e when the processing block of back level receives request signal REQ_N, whether judgement has the UL data that can send next time in 2 port SRAM 25a, under situation about being judged to be, Ji processing block and above-mentioned location of interpolation counting circuit 21a send enabling signal GRANT_N (step S5) backward.

Location of interpolation counting circuit 21a receives this enabling signal GRANT_N beginning action, when the location of interpolation of the amount of having carried out 1UL is that (X1 during Y1) calculating action, calculates the beginning coordinate of next UL and finishes (step S6) coordinate.

Above-mentioned GRANT_N sends decision circuit 24e and location of interpolation counting circuit 21a begins action and output coordinate (X1, Y1) synchronised, distortion correction coefficient calculation circuit 22a can output distortion correction coefficient F timing, trigger trig (step S7) to this distortion correction coefficient calculation circuit 22a output.

When distortion correction coefficient calculation circuit 22a has received triggering trig, at the pixel in the UL data, calculate distortion correction coefficient F according to above-mentioned formula 16, export to location of interpolation correcting circuit 22b.This distortion correction coefficient calculation circuit 22a is also same with above-mentioned location of interpolation counting circuit 21a, when the action of the amount of having carried out 1UL, calculates next UL beginning coordinate and finishes (step S8).

Location of interpolation correcting circuit 22b uses the distortion correction coefficient F that receives from this distortion correction coefficient calculation circuit 22a and the coordinate that receives from above-mentioned location of interpolation counting circuit 21a, and (X1 Y1), calculates coordinate (X ', Y ') according to above-mentioned formula 12.This location of interpolation correcting circuit 22b, calculates the beginning coordinate of next UL and finishes (step S9) when the action of the amount of having carried out 1UL also according to above-mentioned distortion correction coefficient calculation circuit 22a.

Selector switch 23 is according to the pattern of being set by above-mentioned CPU 3 by above-mentioned control register 7a, under the situation of carrying out distortion correction treatment, selection from the coordinate of above-mentioned location of interpolation correcting circuit 22b (X ', Y '), do not carrying out under the situation of distortion correction treatment, selection is from coordinate (X1, Y1) (the step S10) of above-mentioned location of interpolation counting circuit 21a.

The coordinate that totalizer 27a, 27b will select by this selector switch 23 (X1, Y1) or coordinate (X ', Y ') respectively with coordinate (Xd, the Yd) addition (step S11) of center of distortion position.

Reading address generating circuit 24a will be in order to be used for interpolation, the address AD R of the pixel data of reading according to the coordinate that obtains from totalizer 27a, 27b and from 2 port SRAM 25a exports to this 2 port SRAM 25a, and interpolation coefficient and serial data control signal are exported to interpolation circuit 26a (step S12).

Interpolation circuit 26a uses from reading interpolation coefficient, serial data control signal that address generating circuit 24a obtains and the pixel data that obtains from 2 port SRAM 25a, shown in above-mentioned formula 5, calculate by the pixel data of interpolation, export to the processing block (step S13) of back level.

Buffer memory burst size counting circuit 24c is according to above-mentioned location of interpolation counting circuit 21a and totalizer 27a, the output of 27b, in case having confirmed the UL data has been output at last, the beginning coordinate and the next UL that then calculate the UL of the current processing that is through with start the poor of coordinate, in order to discharge the impact damper (zones in the 2 port SRAM 25a) of having stored unnecessary data, to impact damper vacant capacity monitoring circuit 24d output buffers burst size, and, send decision circuit 24e to above-mentioned GRANT_N and send the information (step S14) that need receive how many data of back in order to carry out next UL to handle from the processing block of prime.

When impact damper vacant capacity monitoring circuit 24d has confirmed to have the vacant situation of storage area in 2 port SRAM 25a as internal buffer in above-mentioned steps S14, then return above-mentioned steps S1, repeat above-mentioned processing (step S15).

GRANT_N sends decision circuit 24e according to from the value of the above-mentioned BLC counter that writes address generating circuit 24b and from the output of buffer memory burst size counting circuit 24c, can judgement send to next UL data the processing block of back level, be judged to be under the situation that can send, carrying out the processing (step S16) of above-mentioned steps S5.

Figure 17 is the block scheme of an example of the structure of the above-mentioned distortion correction coefficient calculation circuit 22a of expression.This distortion correction coefficient calculation circuit 22a calculates distortion correction coefficient F according to above-mentioned formula 16.

And in this Figure 17, and in the explanation of Figure 17 shown below, Z is meant the Z (2 point) that represents on the left side of formula 10, and coefficient A, B, C are meant A (point), B (point), the C (point) that represents on the left side of formula 13.

Distortion correction coefficient calculation circuit 22a has: when sending decision circuit 24e from above-mentioned GRANT_N and imported triggering trig, the distortion correction of calculating interpolated coordinates X2, Y2 according to above-mentioned formula 11 is with coordinate calculating circuit 31; To be converted to the floating-point decimation circuit 32a of floating-point decimal by the interpolated coordinates X2 that this distortion correction is calculated with coordinate calculating circuit 31; To be converted to the floating-point decimation circuit 32b of floating-point decimal by the interpolated coordinates Y2 that above-mentioned distortion correction is calculated with coordinate calculating circuit 31; To the square calculator 33a that is undertaken square by the interpolated coordinates X2 of floating-point decimation by above-mentioned floating-point decimation circuit 32a; To the square calculator 33b that is undertaken square by the interpolated coordinates Y2 of floating-point decimation by above-mentioned floating-point decimation circuit 32b; By the interpolated coordinates X2 that will calculate by above-mentioned square calculator 33a square with the summed square of the interpolated coordinates Y2 that calculates by above-mentioned square calculator 33b, calculate Z and (more precisely, be Z (2 point) as mentioned above.Below identical) square totalizer 34; By the output of this totalizer 34 being carried out square, calculate the square calculator 33c of 4 powers of Z; The delay circuit 35b that output from above-mentioned totalizer 34 is postponed; By 4 powers of the Z that will calculate by above-mentioned square calculator 33c, and postponed by this delay circuit 35b and, calculate the multiplier 36d of 6 powers of Z according to square the multiplying each other of the Z of regularly output; Output from above-mentioned totalizer 34 is postponed, and the delay circuit 35a that the output from above-mentioned square calculator 33c is postponed; To be postponed by above-mentioned delay circuit 35a and according to the Z of regularly output square, and be set in coefficient A among the control register 7a by above-mentioned CPU 3 and (more precisely, be A (point) as mentioned above.Below identical) the multiplier 36a that multiplies each other; To be postponed by above-mentioned delay circuit 35a and according to 4 powers of the Z of output regularly, and and be set in coefficient B among the control register 7a by above-mentioned CPU 3 and (more precisely, be B (point) as mentioned above.Below identical) the multiplier 36b that multiplies each other; Will be from 6 powers of the Z of above-mentioned multiplier 36d output, and be set in coefficient C among the control register 7a by above-mentioned CPU 3 and (more precisely, be C (point) as mentioned above.Below identical) the multiplier 36c that multiplies each other; To give output by the symbol signA that above-mentioned CPU 3 is set in the above-mentioned coefficient A among the control register 7a, and be converted to the fractional fixed point circuit 37a of fractional fixed point to above-mentioned multiplier 36a; To give output by the symbol signB that above-mentioned CPU 3 is set in the above-mentioned coefficient B among the control register 7a, and be converted to the fractional fixed point circuit 37b of fractional fixed point to above-mentioned multiplier 36b; To give output by the symbol signC that above-mentioned CPU 3 is set in the above-mentioned coefficient C among the control register 7a, and be converted to the fractional fixed point circuit 37c of fractional fixed point to above-mentioned multiplier 36c; By will be from the output of above-mentioned fractional fixed point circuit 37a, from the output of above-mentioned fractional fixed point circuit 37b, from the output of above-mentioned fractional fixed point circuit 37c, with constant 1.0 additions that are set in by above-mentioned CPU 3 among the control register 7a, calculate totalizer 38 based on the distortion correction coefficient F of above-mentioned formula 16.

And in this Figure 17, the part of representing with two-wire is the part of carrying out the calculation process of floating-point decimal, handles as the floating-point decimal by the X2 that dynamic range is wide, Y2 and Z etc., has dwindled circuit scale when keeping precision.

In addition, Figure 18 is other routine block scheme of the structure of the above-mentioned distortion correction coefficient calculation circuit 22a of expression.

This distortion correction coefficient calculation circuit 22a shown in Figure 180 has: above-mentioned distortion correction coordinate calculating circuit 31, above-mentioned floating-point decimation circuit 32a, above-mentioned floating-point decimation circuit 32b, above-mentioned square calculator 33a, above-mentioned square calculator 33b, above-mentioned totalizer 34, LUT (look-up table) 39, this LUT39 uses from what this totalizer 34 was exported and (more precisely, is aforesaid Z (2 point) by the Z of floating-point decimation.Below identical) square carry out reference, thereby output is by the distortion correction coefficient F of fractional fixed pointization.

In this Figure 18, the part that two-wire is represented also is the part of carrying out the calculation process of floating-point decimal.

Like this, this structure example shown in Figure 180 has shortened the processing time that is used for calculated distortion correction coefficient F by using look-up table, has reduced the power consumption of circuit.

And under the situation of using this structure example, above-mentioned coefficient A, B, C are not set by CPU 3, but fixed value.Certainly,, can prepare the corresponding look-up table of a plurality of combinations with above-mentioned coefficient A, B, C, use suitable look-up table even become under the big situation that also it doesn't matter in the scale of look-up table.

Then, Figure 19 is the sequential chart of the situation when being illustrated in each clock and generating location of interpolation, the sequential chart of the situation of Figure 20 when to be expression in the ratio of per 3 clocks 1 time generate location of interpolation.

The situation of the action when Figure 19 is illustrated in each clock generation location of interpolation, when from the processing block of back level when GRANT_N sends decision circuit 24e input request signal REQ_N, this GRANT_N sends decision circuit 24e in can output image data, sends enabling signal GRANT_N to processing block of this back level.

This enabling signal GRANGT_N also is transfused to location of interpolation counting circuit 21a, generates location of interpolation X1, Y1 and output.In this example shown in Figure 19, location of interpolation X1, Y1 are output at each clock.

And after having passed through the suitable processing time, from the above-mentioned interpolation circuit 26a view data after the processing block output interpolation of level backward, read address generating circuit 24a output and write enabling signal WE_N from above-mentioned this moment.

The figure of the situation of the action when in addition, Figure 20 represents that ratio in per 3 clocks 1 time generates location of interpolation.

Identical to the action that enabling signal GRANT_N is imported into till the location of interpolation counting circuit 21a with situation shown in Figure 19, and this location of interpolation counting circuit 21a generates location of interpolation X1, Y1 and output in the ratio of per 3 clocks 1 time afterwards.

In addition, also the situation with shown in Figure 19 is identical to be generated to needed time of processing till the view data after the above-mentioned interpolation circuit 26a output interpolation from location of interpolation X1, Y1, but because the generation of location of interpolation X1, Y1 is per 3 clocks 1 time, so the output of the view data after the interpolation is per 3 clocks 1 time too, corresponding therewith, the output that writes enabling signal WE_N also becomes per 3 clocks 1 time.

And, here show each clock or per 3 examples that clock carries out the generation of 1 location of interpolation, but be not limited thereto, also can carry out the generation of 1 location of interpolation by whenever suitable a plurality of clocks, perhaps, also can carry out (n 〉=m) generation of (for example, per 3 clocks 2 times) location of interpolation, the also available location of interpolation of frequency generation arbitrarily of pressing m time by every n clock.In addition, also can dynamically change the ratio of the generation number of this location of interpolation with respect to clock number.

According to this 2nd embodiment, obtain and the above-mentioned almost same effect of the 1st embodiment, and,, dwindle circuit scale so can shorten the processing time because can carry out distortion correction treatment and amplification simultaneously by 1 circuit dwindles processing.Thereby can constitute the high speed image treating apparatus with low cost.

In addition, when not carrying out distortion correction treatment,, promptly, can reduce power consumption by stopping to offer the clock of distortion correction coefficient calculation circuit and location of interpolation correcting circuit by stopping to offer the clock of distortion correction coordinate converting section.

And, by not carrying out the coordinate Calculation of these location of interpolation counting circuits as required, can on time orientation, disperse power consumption at each clock (be not each clock but across clock).By the number of times of coordinates computed in this unit interval of suitable change, can realize the dispersion of more effective power consumption.Thereby the temperature that can suppress treatment circuit rises, and has reduced the moment power consumption (peak value power consumption) of image processing apparatus integral body.

And because generate the interpolated coordinates data according to the Practical Formula after the distortion, make and compare the number of times that has reduced multiplying based on the situation of fundamental formular, therefore the number that can cut down the multiplier that is arranged at location of interpolation generating unit or distortion correction coordinate converting section inside can realize dwindling of circuit scale.

In addition, with the concerned pixel (X in the image after the distortion correction, Y) Dui Ying position (promptly, to (X, Y) consider the position of Xoff, Yoff, M, SX, SY etc.) and center of distortion position (Xd, Yd) between is the wide number of dynamic range apart from Z (or Z (2 point)), they square, 4 powers, 6 powers etc. further become the wide number of dynamic range, but because they are handled as the floating-point decimal, carry out computing and calculate the distortion correction coefficient, so can when guaranteeing precision, dwindle circuit scale.

In addition, when obtaining the distortion correction coefficient, apart from Z (or Z (2 point)) (or it square), under the situation of the look-up table that use can reference, can when shortening the processing time, dwindle circuit scale according to above-mentioned.

From Figure 21 to Figure 31, represent the 3rd embodiment of the present invention.In the 3rd embodiment, the part identical with above-mentioned the 1st, the 2nd embodiment omitted explanation, mainly only difference is described.

The structure of the major part of the image processing apparatus of the 3rd embodiment and above-mentioned the 2nd embodiment shown in Figure 15 identical.

In addition, in the 3rd embodiment, can be above-mentioned storage inside portion 25 shown in Figure 2 or 2 port SRAM 25a shown in Figure 29 by the internal buffer that reduces capacity by predetermined block unit transmitted image data.

Figure 21 is the block scheme of summary of the structure of the above-mentioned distortion correction treatment of expression portion 7.

Color image data is broken down into independently signal content such as RGB or YCbCr 3 (or more than them) usually, handles respectively at each composition.Here, independently the processed path (passage) of signal content difference is made as Ch.0, Ch.1 with 3, Ch.2 describes, and specifically, for example the signal of handling by Ch.0 becomes R, the signal of handling by Ch.1 becomes G, and the signal of handling by Ch.2 becomes B etc.

In this distortion correction treatment portion 7, the distortion correction treatment portion of each passage sends request to the processing block of the passage of the correspondence of prime, receive the view data of sending from the processing block of prime according to this request by predetermined block unit, carried out after the distortion correction processing block of the passage of the correspondence of level after exporting to.Specifically, the distortion correction treatment portion that is used to handle the Ch.0 data becomes 7A, the distortion correction treatment portion that is used to handle the Ch.1 data becomes 7B, and the distortion correction treatment portion that is used to handle the Ch.2 data becomes 7C, and they all are contained in the above-mentioned distortion correction treatment portion 7.And, when the 7A of these distortion correction treatment portions, 7B, 7C when the piece of back level receives the request of the intention of wishing to send view data, in the stage that can send, send view data to the piece of this back level by predetermined block unit.

And in above-mentioned structure example shown in Figure 15, the processing block of prime is corresponding to image processing part 6, and the processing block of back level is corresponding to JPEG handling part 9, and the processing block of these primes and back level also constitutes according to each passage to be handled.

In distortion correction treatment portion 7, set up control register 7a, from CPU 3 be set to the above-mentioned distortion correction treatment 7A of portion, 7B, 7C at the setting value of this distortion correction treatment portion 7 and various data etc., can read the state etc. of result simultaneously from CPU 3.

The summary of the processing of 1 channel part of above-mentioned distortion correction treatment portion 7 with illustrated much at one with reference to above-mentioned Fig. 4 and Fig. 5.

And the distortion correction treatment portion 7 of 1 passage that is used to carry out this processing is with above-mentioned shown in Figure 2 identical.

In addition, thereby in above-mentioned location of interpolation generating unit 21 and distortion correction coordinate converting section 22, calculate the fundamental formular and the Practical Formula of coordinate time by dwindling circuit scale to its distortion, with in the above-described 2nd embodiment with reference to formula 1～formula 3 and formula 5～formula 16 illustrated identical.

At this moment, carry out the calculating of the distortion correction coefficient F shown in above-mentioned formula 16 by the distortion correction coefficient calculation circuit 22a as the distortion correction coefficient calculation unit shown in Figure 26, above-mentioned distortion correction coordinate converting section 22 described later, but also can use structure shown in Figure 28 described later to replace this structure shown in Figure 26.

And, calculate the coordinate (interpolated coordinates data) (X ', Y ') of the impact point before the distortion correction treatment according to above-mentioned formula 12 by the location of interpolation correcting circuit 22b of above-mentioned distortion correction coordinate converting section 22 shown in Figure 29 as described later.

Figure 22 is the figure of an example of the chromatic aberation that takes place during by the optical system photographic images of expression.

In this example shown in Figure 22, the distorton aberration of pillow type has taken place, and red R observes in the inboard of green G from center of distortion, blue B observes in the outside of green G from center of distortion, and the chromatic aberation of skew has respectively taken place.And the skew that this chromatic aberation causes is far away more then big more from the distance of center of distortion.

Like this, because chromatic aberation at every kind of color and difference so interpolation processing also as shown in figure 21, is carried out according to every kind of color.Figure 25 is the block scheme of the more detailed structure of the above-mentioned distortion correction treatment of expression portion 7.

The above-mentioned distortion correction treatment 7A of portion has Ch.0 and uses distortion correction circuit 7A1 as the distortion correction arithmetic element, the above-mentioned distortion correction treatment 7B of portion has Ch.1 and uses distortion correction circuit 7B1 as the distortion correction arithmetic element, and the above-mentioned distortion correction treatment 7C of portion has Ch.2 and uses distortion correction circuit 7C1 as the distortion correction arithmetic element.

In addition, the distortion correction coefficient calculation circuit 22a that is used to calculate distortion correction coefficient F constitutes the part of above-mentioned distortion correction coordinate converting section 22, because can be shared in the 7A of distortion correction treatment portion, 7B, 7C, so as 3 shared single circuit of passage are provided with, calculate Ch.0 with distortion correction coefficient F0, Ch.1 distortion correction coefficient F1, Ch.2 distortion correction coefficient F2, export to above-mentioned Ch.0 distortion correction circuit 7A1, Ch.1 distortion correction circuit 7B1, Ch.2 distortion correction circuit 7C1 respectively.

In addition, after having carried out distortion correction treatment or amplification and dwindling the interpolation processing of processing, backward during the processing block output image data of level, the contents processing according to the processing block of this back level needs 3 channel image data sometimes simultaneously.Yet, as above-mentioned shown in Figure 22, having under the situation of chromatic aberation, the position of concerned pixel is different because of color, exports so not necessarily will collect complete 3 data simultaneously.

Be explained with reference to Figure 23 and Figure 24.Figure 23 is illustrated in the figure that the moment that can calculate the interpolated data relevant with B is stored in the situation of the view data in the storage inside portion, and Figure 24 is illustrated in to calculate respectively the figure that is stored in the situation of the view data in the storage inside portion with the moment of R, G, interpolated data that B is relevant.

Begin simultaneously at 3 passages under the situation of computing of interpolated data, be stored in order in the storage inside portion 25 (2 port SRAM 25a shown in Figure 29 described later) of each passage from the view data of the processing block of prime.At this moment, as data and stored part is the part of representing with oblique line.In the moment shown in Figure 23,, also do not reach the amount of the calculating that can carry out the interpolated data relevant with green G and red R though the savings of view data has reached the amount that can carry out the calculating of the interpolated data relevant with blue B.

In addition, in the moment shown in Figure 24, the savings of view data has proceeded to the degree that can carry out with the calculating of red R, green G, interpolated data that blue B is relevant.

Like this, in the moment that becomes the interpolated data that to calculate 3 passages, by carrying out synchronously as the allowance synchronizing circuit 27 of permitting lock unit so that permit the processing block transmit image data of level backward.

If with Ch.0 is that R, Ch.1 are that G, Ch.2 are that the situation of B is an example, when becoming when as above stating state shown in Figure 23, above-mentioned Ch.0 begins the request signal trok_0 of distortion correction treatment with distortion correction circuit 7A1 output request, though it is not shown, but Ch.1 with distortion correction circuit 7B1 in the moment that can carry out distortion correction treatment, the request signal trok_1 of output request beginning distortion correction treatment, when becoming when as above stating state shown in Figure 24, Ch.2 is with the request signal trok_2 of distortion correction circuit 7C1 output request beginning distortion correction treatment.

Permit synchronizing circuit 27 and all collecting these request signals trok_0 complete, trok_1, behind the trok_2, promptly when whole transmission interpolated data that can be by 3 passages, the part output enabling signal GRANT_N0 of the processing that the carrying out in Ji the processing block is relevant with Ch.0 backward, to the part output enabling signal GRANT_N1 that carries out the processing relevant with Ch.1, to the part output enabling signal GRANT_N2 that carries out the processing relevant with Ch.2, and to Ch.0 distortion correction circuit 7A1, Ch.1 distortion correction circuit 7B1, Ch.2 controls with distortion correction circuit 7C1, so that begin distortion correction treatment as hereinafter described simultaneously.

And whether this permits synchronizing circuit 27 as hereinafter described, has switch in inside, can to the output of 3 passages being switched synchronously.

Figure 26 is the block scheme of the structure of the above-mentioned distortion correction coefficient calculation circuit 22a of expression.

This distortion correction coefficient calculation circuit 22a is the distortion correction coefficient calculation unit that is used for calculating according to above-mentioned formula 16 distortion correction coefficient F, the A of the optical property of the reflection optical system in this formula 16 (point), B (point), C (point) quilt are at each passage, promptly, be set among the control register 7a by above-mentioned CPU 3 at each color component of for example RGB.

And, in the figure of this Figure 26 and Figure 27 described later, Figure 28, and at Figure 26 shown below in the explanation of Figure 28, Z is meant the Z (2 point) shown in the left side of formula 10, coefficient A, B, C are meant A (point), B (point), the C (point) shown in the left side of formula 13.

Distortion correction coefficient calculation circuit 22a has: when when above-mentioned allowance synchronizing circuit 27 has been imported enabling signal e_grant, the distortion correction of calculating interpolated coordinates X2, Y2 according to above-mentioned formula 11 is with coordinate calculating circuit 31; To be converted to the floating-point decimation circuit 32a of floating-point decimal by the interpolated coordinates X2 that this distortion correction is calculated with coordinate calculating circuit 31; To be converted to the floating-point decimation circuit 32b of floating-point decimal by the interpolated coordinates Y2 that this distortion correction is calculated with coordinate calculating circuit 31; The square calculator 33a that the interpolated coordinates X2 that has carried out the floating-point decimation by above-mentioned floating-point decimation circuit 32a is carried out square; The square calculator 33b that the interpolated coordinates Y2 that has carried out the floating-point decimation by above-mentioned floating-point decimation circuit 32b is carried out square; The summed square of square interpolated coordinates Y2 that calculates with above-mentioned square calculator 33b by interpolated coordinates X2 that above-mentioned square calculator 33a is calculated is calculated Z and (more precisely, is above-mentioned Z (2 point).Below identical) square totalizer 34; By the output of this totalizer 34 being carried out square, calculate the square calculator 33c of 4 powers of Z; The delay circuit 35b that output from above-mentioned totalizer 34 is postponed; By 4 powers of the Z that will calculate by above-mentioned square calculator 33c, and be delayed by this delay circuit 35b and, calculate the multiplier 36 of 6 powers of Z according to square the multiplying each other of the Z of regularly output; Output from above-mentioned totalizer 34 is postponed, and the delay circuit 35a that the output from above-mentioned square calculator 33c is postponed; Use is from 4 powers of this delay circuit 35a according to the quadratic sum Z of the Z that regularly exports, and from 6 powers of the Z of above-mentioned multiplier 36 outputs, calculate respectively distortion correction coefficient F0 that Ch.0 uses with, Ch.2 with, Ch.1, F1, F2 apart from interdependence coefficient counting circuit 40a, 40b, 40c.

Figure 27 is expression as above-mentioned block scheme apart from any 1 structure apart from interdependence coefficient counting circuit 40 among interdependence coefficient counting circuit 40a, 40b, the 40c.

This has apart from interdependence coefficient counting circuit 40: will be postponed by above-mentioned delay circuit 35a, according to the Z of regularly output square, (more precisely, be above-mentioned A (point) with the coefficient A that is set in by above-mentioned CPU 3 among the control register 7a.Below identical) the multiplier 41a that multiplies each other; To (more precisely, be above-mentioned B (point) with the coefficient B that is set in by above-mentioned CPU 3 among the control register 7a by above-mentioned delay circuit 35a delay, according to 4 powers of the Z that regularly exports.Below identical) the multiplier 41b that multiplies each other; To (more precisely, be above-mentioned C (point) with the coefficient C that is set in the control register 7a by above-mentioned CPU 3 from 6 powers of the Z of above-mentioned multiplier 36 outputs.Below identical) the multiplier 41c that multiplies each other; To give to output by the symbol signA that above-mentioned CPU 3 is set in the above-mentioned coefficient A among the control register 7a, and be converted to the fractional fixed point circuit 42a of fractional fixed point from above-mentioned multiplier 41a; To give to output by the symbol signB that above-mentioned CPU 3 is set in the above-mentioned coefficient B among the control register 7a, and be converted to the fractional fixed point circuit 42b of fractional fixed point from above-mentioned multiplier 41b; To give to output by the symbol signC that above-mentioned CPU 3 is set in the above-mentioned coefficient C among the control register 7a, and be converted to the fractional fixed point circuit 42c of fractional fixed point from above-mentioned multiplier 41c; By will be from the output of above-mentioned fractional fixed point circuit 42a, from the output of above-mentioned fractional fixed point circuit 42b, from the output of above-mentioned fractional fixed point circuit 42c, be set in constant 1.0 additions among the control register 7a by above-mentioned CPU 3, calculate the totalizer 43 of the distortion correction coefficient F (that is any one among distortion correction coefficient F0, F1, the F2) based on above-mentioned formula 16.

And in Figure 26 and Figure 27, the part of representing with two-wire is the part of carrying out the calculation process of floating-point decimal, handles as the floating-point decimal by the X2 that dynamic range is wide, Y2 and Z, has dwindled circuit scale when keeping precision.

At this moment, as above-mentioned shown in Figure 26, the part of distortion correction coefficient calculation circuit 22a, be distortion correction coordinate calculating circuit 31, floating-point decimation circuit 32a, 32b, square calculator 33a, 33b, 33c, totalizer 34, delay circuit 35a, 35b, multiplier 36, constitute the shared part that does not rely on passage.Like this, can further realize dwindling of circuit scale, reduce power consumption.

In addition, Figure 28 is other routine block scheme of the structure of the above-mentioned distortion correction coefficient calculation circuit 22a of expression.

This distortion correction coefficient calculation circuit 22a shown in Figure 28 has with the lower part and constitutes: above-mentioned distortion correction is with coordinate calculating circuit 31; Above-mentioned floating-point decimation circuit 32a; Above-mentioned floating-point decimation circuit 32b; Above-mentioned square calculator 33a; Above-mentioned square calculator 33b; Above-mentioned totalizer 34; By using from 34 outputs of this totalizer, (more precisely, being above-mentioned Z (2 point) by the Z of floating-point decimation.Below identical) square and carry out reference, export respectively by LUT (look-up table) 39a, 39b, the 39c of the distortion correction coefficient F0 of fractional fixed pointization, F1, F2.

In this Figure 28, the part of representing with two-wire also is the part of carrying out the calculation process of floating-point decimal.

Like this, this structure example shown in Figure 28 has shortened the processing time that is used to calculate distortion correction coefficient F0, F1, F2 by using look-up table, has reduced the power consumption of circuit.

And under the situation of using this structure example, the above-mentioned coefficient A of each passage, B, C are not set by CPU 3, but become fixed value.Certainly, even become under the big situation that also it doesn't matter, also can use suitable look-up table at the corresponding look-up table of a plurality of combinations of each passage preparation with above-mentioned coefficient A, B, C in the scale of look-up table.

Below, Figure 29 is the block scheme of the above-mentioned Ch.0 of expression with the structure of distortion correction circuit 7A1.Because Ch.1 is also identical with the structure of distortion correction circuit 7A1 with this Ch.0 with the structure of distortion correction circuit 7C1 with distortion correction circuit 7B1, Ch.2, so only Ch.0 is described with distortion correction circuit 7A1 here.

Location of interpolation counting circuit 21a is used for calculating as described above the coordinate of above-mentioned impact point, and (X1 Y1), is the circuit part corresponding to above-mentioned location of interpolation generating unit 21.

Location of interpolation correcting circuit 22b is used to use the distortion correction coefficient F0 that calculates by above-mentioned distortion correction coefficient calculation circuit 22a, such shown in above-mentioned formula 12, calculate the impact point before the distortion correction treatment coordinate (X ', Y '), become the part of above-mentioned distortion correction coordinate converting section 22.

Above-mentioned selector switch 23 (dwindles processing no matter whether amplify) under the situation of not carrying out distortion correction treatment, selection is from the coordinate (X1 of above-mentioned location of interpolation counting circuit 21a, Y1), under the situation of carrying out distortion correction treatment, (dwindle processing) no matter whether follow to amplify, selection is from the coordinate of above-mentioned location of interpolation correcting circuit 22b (X ', Y ').

By totalizer 27a, 27b, respectively the coordinate that will select by this selector switch 23 (X1, Y1) or the coordinate of coordinate (X ', Y ') and the center of distortion position of setting by above-mentioned CPU 3 by control register 7a (Xd Yd) carries out additive operation.

The output of these totalizers 27a, 27b is output to reads address generating circuit 24a and buffer memory burst size counting circuit 24c.

And, the coordinate of calculating by above-mentioned location of interpolation counting circuit 21a (X1, Y1) also by be imported into this via different path, the path of above-mentioned selector switch 23 and read address generating circuit 24a.And, this is read address generating circuit 24a and will store and this coordinate (X1, Y1) Guan Lian pixel data is (under the situation of carrying out 16 point interpolations, be with this coordinate (X1, Y1) for 16 pixel datas at center) address AD R export to 2 port SRAM 25a, and (for example with interpolation coefficient, interpolation coefficient kx0～kx3 shown in above-mentioned formula 5, ky0～ky3) and the pixel data of indicating to export are that the serial data control signal of pixel data of which position of D0～D15 is exported to interpolation circuit 26a.And then this reads address generating circuit 24a will write the processing block corresponding with Ch.0 that enabling signal WE_N0 exports to the back level.

Above-mentioned 2 port SRAM 25a are circuit parts corresponding with above-mentioned storage inside portion shown in Figure 2 25.

Interpolation circuit 26a is corresponding with above-mentioned interpolation arithmetic unit shown in Figure 2 26, uses the view data of reading from above-mentioned 2 port SRAM 25a, carries out the interpolation processing shown in above-mentioned formula 5, the view data after handling is exported to the processing block of back level.

Above-mentioned buffer memory burst size counting circuit 24c calculates releasable memory capacity (buffer memory burst size) in above-mentioned 2 port SRAM 25a according to from the output of above-mentioned location of interpolation counting circuit 21a with via the output from above-mentioned selector switch 23 of above-mentioned totalizer 27a, 27b.

Impact damper vacant capacity monitoring circuit 24d holds the situation of the vacant capacity of above-mentioned 2 port SRAM 25a with reference to the output of this buffer memory burst size counting circuit 24c.

Write with the Ch.0 relevant view data of address generating circuit 24b reception, and be recorded among the above-mentioned 2 port SRAM 25a from the processing block of prime.

Data could send the request signal REQ_N0 of decision circuit 24f reception from the requested image data of the processing block of the back level relevant with Ch.0, according to the above-mentioned output that writes address generating circuit 24b and buffer memory burst size counting circuit 24c, can judgement carry out the transmission of view data, can situation under, request signal trok_0 is exported to above-mentioned allowance synchronizing circuit 27.

Below, the action of this distortion correction treatment portion 7 shown in Figure 29 is described.

Impact damper vacant capacity monitoring circuit 24d monitors the vacant capacity of 2 port SRAM 25a by buffer memory burst size counting circuit 24c, if predetermined vacant capacity is arranged, then the processing block to the prime relevant with Ch.0 sends request signal REQ_0, so that the view data of the block unit that transmission is predetermined (below, suitably be called unit capable (UL) data) (step S21).

The processing block of the prime relevant with Ch.0 receives this request signal REQ_0, in the time can sending view data, sends enabling signal GRANT_0, and above-mentioned impact damper vacant capacity monitoring circuit 24d receives this enabling signal GRANT_0 (step S22).

This impact damper vacant capacity monitoring circuit 24d holds the vacant capacity of 2 port SRAM 25a by remaining in inner counter, when receiving enabling signal GRANT, the value of this internal counter is subtracted 1.In case this internal counter has become 0, then this impact damper vacant capacity monitoring circuit 24d moves, to cancel above-mentioned request signal REQ_0 (step S23).

And, write enabling signal WE_0 from the processing block of the prime relevant to writing address generating circuit 24b input, then input image data with Ch.0.Corresponding therewith, write address generating circuit 24b to 2 port SRAM 25a output control signal, with view data DATA be written among this 2 port SRAM 25a by the specified zone of address AD DRESS.In addition, whenever being transfused to the 1UL data, write address generating circuit 24b and just increase BLC counter (being illustrated in the counter that stores how many data among the 2 port SRAM 25a as internal buffer), and export to data and could send decision circuit 24f (step S24).

When data could send decision circuit 24f when the processing block of relevant with Ch.0 back level receives request signal REQ_N0, whether judgement exists the UL data that next can send in 2 port SRAM 25a, be judged to be under the situation of existence, sending request signal trok_0 (step S25) to above-mentioned allowance synchronizing circuit 27.

As hereinafter described, permit synchronizing circuit 27 when having possessed the transmission condition of view data, to the processing block of the back level relevant and location of interpolation counting circuit 21a output enabling signal GRANT_N0, GRANT_N1, the GRANT_N2 relevant with each passage with each passage.

The location of interpolation counting circuit 21a relevant with Ch.0 receives this enabling signal GRANT_N0, begins action, when the location of interpolation of the amount of having carried out 1UL is that (X1 during Y1) calculating action, calculates the beginning coordinate of next UL and finishes (step S26) coordinate.

Above-mentioned allowance synchronizing circuit 27 begins action and output coordinate (X1 with location of interpolation counting circuit 21a, Y1) synchronised ground distortion correction coefficient calculation circuit 22a can output distortion correction coefficient F0 timing, to this distortion correction coefficient calculation circuit 22a output enabling signal e_grant (step S27).

When distortion correction coefficient calculation circuit 22a receives enabling signal e_grant, calculate distortion correction coefficient F0, F1, the F2 relevant according to above-mentioned formula 16 with each passage, export to the location of interpolation correcting circuit 22b of each passage.This distortion correction coefficient calculation circuit 22a is also identical with above-mentioned location of interpolation counting circuit 21a, when the action of the amount of having carried out 1UL, calculates next UL beginning coordinate and finishes (step S28).

The location of interpolation correcting circuit 22b relevant with Ch.0 uses distortion correction coefficient F0 that obtains from this distortion correction coefficient calculation circuit 22a and the coordinate (X1 that obtains from above-mentioned location of interpolation counting circuit 21a, Y1), calculate coordinate (X ', Y ') based on above-mentioned formula 12.This location of interpolation correcting circuit 22b, calculates next UL beginning coordinate and finishes (step S29) when the action of the amount of having carried out 1UL also according to above-mentioned distortion correction coefficient calculation circuit 22a.

Selector switch 23 is according to the pattern of being set by above-mentioned CPU 3 by above-mentioned control register 7a, under the situation of carrying out distortion correction treatment, selection from the coordinate of above-mentioned location of interpolation correcting circuit 22b (X ', Y '), do not carrying out under the situation of distortion correction treatment, selection is from coordinate (X1, Y1) (the step S30) of above-mentioned location of interpolation counting circuit 21a.

The coordinate that totalizer 27a, 27b will select by this selector switch 23 (X1, Y1) or coordinate (X ', Y ') respectively with coordinate (Xd, the Yd) addition (step S31) of center of distortion position.

Reading address generating circuit 24a will be in order to be used for interpolation, the address AD R of the pixel data of reading according to the coordinate that obtains from totalizer 27a, 27b and from 2 port SRAM 25a exports to this 2 port SRAM 25a, and interpolation coefficient and serial data control signal are exported to interpolation circuit 26a output (step S32).

Interpolation circuit 26a uses from reading interpolation coefficient and the serial data control signal that address generating circuit 24a obtains, and the pixel data that obtains from 2 port SRAM 25a, shown in above-mentioned formula 5, calculate by the pixel data after the interpolation, and export to the processing block (step S33) of the back level relevant with Ch.0.

Buffer memory burst size counting circuit 24c is based on above-mentioned location of interpolation counting circuit 21a and totalizer 27a, the output of 27b, in case confirmed to export the UL data until last situation, the UL beginning coordinate and the next UL that then calculate current end process start the poor of coordinate, in order to discharge the impact damper (zones in the 2 port SRAM 25a) of storing unwanted data, the buffer memory burst size is exported to impact damper vacant capacity monitoring circuit 24d, and, will send to above-mentioned data about the information that need receive how many data of back in order to carry out next UL to handle and could send decision circuit 24f (step S34) from the processing block of the prime relevant with Ch.0.

When impact damper vacant capacity monitoring circuit 24d has confirmed to have storage area vacant at above-mentioned steps S34 in 2 port SRAM 25a as internal buffer, return above-mentioned steps S21, carry out above-mentioned processing (step S35) repeatedly.

Data could send decision circuit 24f according to from the value of the above-mentioned BLC counter that writes address generating circuit 24b with from the output of buffer memory burst size counting circuit 24c, can judgement send to next UL data the processing block of back level, be judged to be under the situation that can send, carrying out the processing (step S36) of above-mentioned steps S25.

Figure 30 is the block scheme that the structure of synchronizing circuit 27 is permitted in expression, and Figure 31 is the sequential chart that is used to illustrate the action of permitting synchronizing circuit 27.

At first, by the DT_ON that obtains with reference to above-mentioned control register 7a is to preserve the data whether expression carries out the Boolean of distortion correction, constitute in the following manner: under the situation of 0 (vacation), be taken as low level signal, under the situation of 1 (very), be taken as high level signal.

This allowance synchronizing circuit 27 has with the lower part and constitutes: be used to obtain from Ch.0 with the request signal trok_0 of distortion correction circuit 7A1, from Ch.1 with the request signal trok_1 of distortion correction circuit 7B1 with from the "AND" circuit 51 of Ch.2 with the logic product of the request signal trok_2 of distortion correction circuit 7C1; Be used to detect the differentiating circuit 52 of rising edge of the output of above-mentioned request signal trok_0, trok_1, trok_2 and "AND" circuit 51; Be carried out and switch make the outgoing side that when DT_ON is low level, is connected to the differentiating circuit 52 relevant, when this DT_ON is high level, be connected to the switch 53a of the outgoing side of the differentiating circuit 52 relevant with above-mentioned "AND" circuit 51 with request signal trok_0; Be carried out and switch make the outgoing side that when DT_ON is low level, is connected to the differentiating circuit 52 relevant, when this DT_ON is high level, be connected to the switch 53b of the outgoing side of the differentiating circuit 52 relevant with above-mentioned "AND" circuit 51 with request signal trok_1; Be carried out and switch make the outgoing side that when DT_ON is low level, is connected to the differentiating circuit 52 relevant, when this DT_ON is high level, be connected to the switch 53c of the outgoing side of the differentiating circuit 52 relevant with above-mentioned "AND" circuit 51 with request signal trok_2; Obtain the output of the differentiating circuit 52 relevant and the logic product of DT_ON, export to the "AND" circuit 54 of the distortion correction of above-mentioned distortion correction coefficient calculation circuit 22a with coordinate calculating circuit 31 as enabling signal e_grant with above-mentioned "AND" circuit 51.

The action of such allowance synchronizing circuit 27 is as described below.

At first, when DT_ON was low level, when promptly not carrying out distortion correction, above-mentioned switch 53a, 53b, 53c were switched to the outgoing side of the differentiating circuit 52 that is used to detect request signal trok_0, trok_1, trok_2 respectively.

At this moment, shown in the left side of Figure 31, when high level signal is imported into request signal trok_0, detect its rising edge, export as GRANT_N0 by differentiating circuit 52.Then, when high level signal is imported into request signal trok_1, detect its rising edge by differentiating circuit 52, export as GRANT_N1, and afterwards when high level signal is imported into request signal trok_2, detect its rising edge by differentiating circuit 52, export as GRANT_N2.Like this, when DT_ON is low level, each passage is carried out according to timing separately from the output needle of 3 channel image data.

In addition, when DT_ON becomes low level, no matter the output of "AND" circuit 51 how, the output of "AND" circuit 54 maintains low level state, enabling signal e_grant is not output (or become disapprove output), so above-mentioned distortion correction coefficient calculation circuit 22a does not carry out the calculating of distortion correction coefficient F0, F1, F2.Therefore, the location of interpolation correcting circuit 22b relevant with each passage also is failure to actuate, and the result does not carry out the distortion interpolation processing.

Then, when DT_ON was high level, when promptly carrying out distortion correction, above-mentioned switch 53a, 53b, 53c were switched to the outgoing side of the differentiating circuit 52 relevant with "AND" circuit 51.

At this moment, shown in the right side of Figure 31, even to request signal trok_0 input high level signal, at this constantly, because request signal trok_1, trok_2 are maintained at low level state, so the output of this "AND" circuit 51 still maintains low level state.

Thereafter, be high level and request signal trok_1 when becoming high level at request signal trok_0, during request signal trok_2 was low level, the output of "AND" circuit 51 still was maintained at low level state.

And when request signal trok_0, trok_1, trok_2 all became high level, the output of "AND" circuit 51 became high level, detected its rising edge by differentiating circuit 52.

The output of this differentiating circuit 52 is output simultaneously as enabling signal GRANT_N0, GRANT_N1, GRANT_N2, and also export to "AND" circuit 54, obtain and the logic product that becomes the DT_ON of high level, be input to above-mentioned distortion correction coefficient calculation circuit 22a as enabling signal e_grant.

Like this, when DT_ON is high level, carry out output from 3 channel image data according to synchronous timing.

According to this 3rd embodiment, obtained and the above-mentioned almost same effect of the 1st, the 2nd embodiment, and, can realize carrying out that distortion correction and chromatic aberation are proofreaied and correct, circuit scale is little and the image processing apparatus of low power consumption.

Especially,, can effectively reduce circuit scale, realize low power consumption by at least a portion to the shared distortion correction coefficient calculation circuit of a plurality of passages.At this moment, because handling as the floating-point decimal, the number that dynamic range is wide carries out computing, so can when guaranteeing precision, dwindle circuit scale.And, obtain at the reference look-up table under the situation of distortion correction coefficient, can when shortening the processing time, dwindle circuit scale.

In addition,, can carry out simultaneously, so can the corresponding well situation that in the processing block of back level, needs a plurality of channel image data simultaneously from each channel image data output because be provided with the allowance synchronizing circuit.At this moment, permit synchronizing circuit and can handle, so can select as required in the mode of a plurality of channel image data being exported according to timing separately by switch.

In addition, because generate the interpolated coordinates data according to the Practical Formula after the distortion, make and to have reduced the multiplication number of times with comparing based on the situation of fundamental formular, so can cut down the number of the multiplier of the inside that is arranged at location of interpolation generating unit or distortion correction coordinate converting section, can realize dwindling of circuit scale.

And, have and can amplify the advantage of dwindling processing and distortion correction treatment simultaneously by same circuit.

And, the invention is not restricted to above-mentioned embodiment, certainly in the scope of the purport that does not break away from invention, carry out various distortion and application.

According to image processing apparatus of the present invention as described above, can not increase the data conveying capacity and the memory span of bus, and carry out Flame Image Process.

In addition, realized amplifying dwindle processing and distortion correction treatment, circuit scale is little and the image processing apparatus of low power consumption.

And, realized carrying out that distortion correction and chromatic aberation are proofreaied and correct, circuit scale is little and the image processing apparatus of low power consumption.

Claims (71)

1. image processing apparatus, the electronic image data that obtain making a video recording through optical system are handled, and described view data has the pixel data that is arranged in two-dimensionally on line direction and the column direction, it is characterized in that, has:

Storer, it is the described view data of storage before carrying out Flame Image Process at least, and also can carry out the described view data of storage after the Flame Image Process;

The 1st data orders converter section, its piece with the described two-dimensional arrangements of described view data is a unit, reads pixel data this piece in by bus by line direction from described storer, then, exports pixel data in this piece by column direction;

Image processing part, it is connected into described the 1st data order converter section by the information communicating path different with described bus can carry out pipeline processes, input is pressed the view data that column direction is exported from the 1st data order converter section, has carried out after the Flame Image Process, by this column direction output; And

The 2nd data orders converter section, it is connected into described image processing part can carry out pipeline processes, will be converted to the view data of line direction by the view data of column direction output and exports from this image processing part.

2. image processing apparatus according to claim 1 is characterized in that, it is at least one side the size of the size of line direction of view data of unit and column direction with the piece that described the 1st data order converter section can change what read from described storer.

3. image processing apparatus according to claim 1, it is characterized in that, carry out view data before the described Flame Image Process and be any one in the following data: the subject optics by optical system imaging is looked like to carry out the camera data that opto-electronic conversion is exported by image unit; As required to the non-compressing image data after the predetermined process of this camera data enforcement except compression is handled; As required described camera data is implemented after compressing the predetermined process handling, carried out the compressing image data that compression is handled again.

4. image processing apparatus according to claim 2, it is characterized in that, carry out view data before the described Flame Image Process and be any one in the following data: the shot object image by optical system imaging is carried out the camera data that opto-electronic conversion is exported by image unit; As required this camera data is implemented the non-compressing image data of the predetermined process except compression is handled; As required described camera data is implemented after compressing the predetermined process handling, carried out the compressing image data that compression is handled again.

5. image processing apparatus according to claim 1 is characterized in that, described image processing part constitutes has distortion correction treatment portion, and this distortion correction treatment portion is used to proofread and correct the distorton aberration that is caused by described optical system.

6. image processing apparatus according to claim 4 is characterized in that, described image processing part constitutes has distortion correction treatment portion, and this distortion correction treatment portion is used to proofread and correct the distorton aberration that is caused by described optical system.

7. image processing apparatus according to claim 5 is characterized in that, described distortion correction treatment portion has:

Generate the interpolated coordinates generating unit of interpolated coordinates;

Be used to store the storage inside portion of the part of described view data; And

Interpolation arithmetic unit, it is according to the interpolated coordinates that is generated by described interpolated coordinates generating unit, and according to the view data that is stored in the described storage inside portion, generates the pixel data of this interpolated coordinates.

8. image processing apparatus according to claim 6 is characterized in that, described distortion correction treatment portion has:

Generate the interpolated coordinates generating unit of interpolated coordinates;

Be used to store the storage inside portion of the part of described view data; And

Interpolation arithmetic unit, it is according to the interpolated coordinates that is generated by described interpolated coordinates generating unit, and according to the view data that is stored in the described storage inside portion, generates the pixel data of this interpolated coordinates.

9. image processing apparatus according to claim 7 is characterized in that, described interpolated coordinates generating unit has:

The location of interpolation generating unit, it generates in the image after distortion correction the coordinate as the interpolation object pixels; And

The distortion correction coordinate converting section, it obtains the coordinate in the image before the distortion correction corresponding with the coordinate that is generated by this location of interpolation generating unit.

10. image processing apparatus according to claim 8 is characterized in that, described interpolated coordinates generating unit has:

The location of interpolation generating unit, it generates in the image after distortion correction the coordinate as the interpolation object pixels; And

The distortion correction coordinate converting section, it obtains the coordinate in the image before the distortion correction corresponding with the coordinate that is generated by this location of interpolation generating unit.

11. image processing apparatus according to claim 9, it is characterized in that, described interpolated coordinates generating unit also has selector switch, this selector switch select the coordinate that generates by described location of interpolation generating unit and the coordinate obtained by described distortion correction coordinate converting section in any one and export to described interpolation arithmetic unit.

12. image processing apparatus according to claim 10, it is characterized in that, described interpolated coordinates generating unit also has selector switch, this selector switch select the coordinate that generates by described location of interpolation generating unit and the coordinate obtained by described distortion correction coordinate converting section in any one and export to described interpolation arithmetic unit.

13. image processing apparatus according to claim 9, it is characterized in that, described distortion correction coordinate converting section uses the integer power that comprises the distance from the center of distortion to the location of interpolation to carry out linear combination and the polynomial predetermined correction formula that obtains, obtain with by the coordinate in the preceding image of the corresponding distortion correction of the coordinate of described location of interpolation generating unit generation.

14. image processing apparatus according to claim 10, it is characterized in that, described distortion correction coordinate converting section uses the integer power that comprises the distance from the center of distortion to the location of interpolation to carry out linear combination and the polynomial predetermined correction formula that obtains, obtain with by the coordinate in the preceding image of the corresponding distortion correction of the coordinate of described location of interpolation generating unit generation.

15. image processing apparatus according to claim 11, it is characterized in that, described distortion correction coordinate converting section uses the integer power that comprises the distance from the center of distortion to the location of interpolation to carry out linear combination and the polynomial predetermined correction formula that obtains, obtain with by the coordinate in the preceding image of the corresponding distortion correction of the coordinate of described location of interpolation generating unit generation.

16. image processing apparatus according to claim 12, it is characterized in that, described distortion correction coordinate converting section uses the integer power that comprises the distance from the center of distortion to the location of interpolation to carry out linear combination and the polynomial predetermined correction formula that obtains, obtain with by the coordinate in the preceding image of the corresponding distortion correction of the coordinate of described location of interpolation generating unit generation.

17. image processing apparatus according to claim 13 is characterized in that, described polynomial expression comprises the high-order term of 2 items that surpassed described distance.

18. image processing apparatus according to claim 14 is characterized in that, described polynomial expression comprises the high-order term of 2 items that surpassed described distance.

19. image processing apparatus according to claim 15 is characterized in that, described polynomial expression comprises the high-order term of 2 items that surpassed described distance.

20. image processing apparatus according to claim 16 is characterized in that, described polynomial expression comprises the high-order term of 2 items that surpassed described distance.

21. image processing apparatus according to claim 13 is characterized in that, described image processing part also comprises described distortion correction treatment portion other image processing part in addition,

Described distortion correction coordinate converting section is exported to described other image processing part with the information relevant with the distance from described center of distortion to location of interpolation.

22. image processing apparatus according to claim 14 is characterized in that, described image processing part also comprises described distortion correction treatment portion other image processing part in addition,

Described distortion correction coordinate converting section is exported to described other image processing part with the information relevant with the distance from described center of distortion to location of interpolation.

23. image processing apparatus according to claim 15 is characterized in that, described image processing part also comprises described distortion correction treatment portion other image processing part in addition,

Described distortion correction coordinate converting section is exported to described other image processing part with the information relevant with the distance from described center of distortion to location of interpolation.

24. image processing apparatus according to claim 16 is characterized in that, described image processing part also comprises described distortion correction treatment portion other image processing part in addition,

Described distortion correction coordinate converting section is exported to described other image processing part with the information relevant with the distance from described center of distortion to location of interpolation.

25. image processing apparatus according to claim 17 is characterized in that, described image processing part also comprises described distortion correction treatment portion other image processing part in addition,

Described distortion correction coordinate converting section is exported to described other image processing part with the information relevant with the distance from described center of distortion to location of interpolation.

26. image processing apparatus according to claim 18 is characterized in that, described image processing part also comprises described distortion correction treatment portion other image processing part in addition,

Described distortion correction coordinate converting section is exported to described other image processing part with the information relevant with the distance from described center of distortion to location of interpolation.

27. image processing apparatus according to claim 19 is characterized in that, described image processing part also comprises described distortion correction treatment portion other image processing part in addition,

Described distortion correction coordinate converting section is exported to described other image processing part with the information relevant with the distance from described center of distortion to location of interpolation.

28. image processing apparatus according to claim 20 is characterized in that, described image processing part also comprises described distortion correction treatment portion other image processing part in addition,

Described distortion correction coordinate converting section is exported to described other image processing part with the information relevant with the distance from described center of distortion to location of interpolation.

29. image processing apparatus according to claim 21 is characterized in that, described other image processing part comprise shadow correction portion, low-pass filtering treatment portion, edge emphasize among the handling part more than 1.

30. image processing apparatus according to claim 22 is characterized in that, described other image processing part comprise shadow correction portion, low-pass filtering treatment portion, edge emphasize among the handling part more than 1.

31. image processing apparatus according to claim 23 is characterized in that, described other image processing part comprise shadow correction portion, low-pass filtering treatment portion, edge emphasize among the handling part more than 1.

32. image processing apparatus according to claim 24 is characterized in that, described other image processing part comprise shadow correction portion, low-pass filtering treatment portion, edge emphasize among the handling part more than 1.

33. image processing apparatus according to claim 25 is characterized in that, described other image processing part comprise shadow correction portion, low-pass filtering treatment portion, edge emphasize among the handling part more than 1.

34. image processing apparatus according to claim 26 is characterized in that, described other image processing part comprise shadow correction portion, low-pass filtering treatment portion, edge emphasize among the handling part more than 1.

35. image processing apparatus according to claim 27 is characterized in that, described other image processing part comprise shadow correction portion, low-pass filtering treatment portion, edge emphasize among the handling part more than 1.

36. image processing apparatus according to claim 28 is characterized in that, described other image processing part comprise shadow correction portion, low-pass filtering treatment portion, edge emphasize among the handling part more than 1.

37. an image processing apparatus, the electronic image data that can obtain making a video recording through optical system comprise distortion correction treatment and amplify the Flame Image Process of dwindling processing, it is characterized in that,

This image processing apparatus has distortion correction treatment portion, and this distortion correction treatment portion comprises:

The interpolated coordinates generating unit, it is used to generate and has carried out comprising distortion correction treatment and amplified the coordinate data of dwindling before the corresponding interpolation processing of the location of pixels of processing after the interpolation processing of interior Flame Image Process, i.e. interpolated coordinates data;

Storage part, it is used to store at least a portion of described view data;

Memory controller, it carries out the part of described view data is written to the control of described storage part and the control of reading from this storage part based on described interpolated coordinates data; And

Interpolation arithmetic unit, it generates the view data of having carried out the location of pixels after the interpolation processing by the view data of reading from described storage part according to the control of described memory controller is carried out interpolation arithmetic.

38., it is characterized in that described interpolated coordinates generating unit comprises according to the described image processing apparatus of claim 37:

The location of interpolation generating unit, its generation comprises the coordinate data before the corresponding interpolation processing of the location of pixels of processing after the interpolation processing of interior Flame Image Process is dwindled in amplification, i.e. location of interpolation with having carried out not comprising distortion correction treatment;

The distortion correction coordinate converting section, it uses the location of interpolation that is generated by described location of interpolation generating unit, generate with carried out comprising the corresponding interpolation processing of the location of pixels of distortion correction treatment after the interpolation processing of interior Flame Image Process before coordinate data, i.e. interpolated coordinates data; And

Selector switch, it is not carrying out selecting the output of described location of interpolation generating unit under the situation of distortion correction treatment, under the situation of carrying out distortion correction treatment, select the output of described distortion correction coordinate converting section, and described memory controller is exported in selected output.

39., it is characterized in that described distortion correction coordinate converting section comprises according to the described image processing apparatus of claim 38:

The distortion correction coefficient calculation circuit, it calculates the coefficient of the changes in coordinates that expression causes by the distorton aberration of described optical system, i.e. distortion correction coefficient; And

The location of interpolation correcting circuit, it uses the distortion correction coefficient of calculating by described distortion correction coefficient calculation circuit, proofreaies and correct the location of interpolation that is generated by described location of interpolation generating unit, thereby generates described interpolated coordinates data.

40. according to the described image processing apparatus of claim 38, it is characterized in that, described distortion correction treatment portion moves by being supplied to clock, the described distortion correction coordinate converting section of this distortion correction treatment portion be supplied to this distortion correction coordinate converting section that offers this distortion correction treatment portion beyond the different clock of clock of part.

41. according to the described image processing apparatus of claim 39, it is characterized in that, described distortion correction treatment portion moves by being supplied to clock, the described distortion correction coordinate converting section of this distortion correction treatment portion be supplied to this distortion correction coordinate converting section that offers this distortion correction treatment portion beyond the different clock of clock of part.

42. according to the described image processing apparatus of claim 38, it is characterized in that,

Described distortion correction treatment portion moves by being supplied to clock,

Described location of interpolation generating unit, perhaps this location of interpolation generating unit and described distortion correction coordinate converting section are not according to each clock but carry out the generation of location of interpolation across clock, the perhaps generation of the generation of location of interpolation and interpolated coordinates data.

43. according to the described image processing apparatus of claim 39, it is characterized in that,

Described distortion correction treatment portion moves by being supplied to clock,

Described location of interpolation generating unit, perhaps this location of interpolation generating unit and described distortion correction coordinate converting section are not according to each clock but carry out the generation of location of interpolation across clock, the perhaps generation of the generation of location of interpolation and interpolated coordinates data.

44. according to the described image processing apparatus of claim 40, it is characterized in that,

Described distortion correction treatment portion moves by being supplied to clock,

Described location of interpolation generating unit, perhaps this location of interpolation generating unit and described distortion correction coordinate converting section are not according to each clock but carry out the generation of location of interpolation across clock, the perhaps generation of the generation of location of interpolation and interpolated coordinates data.

45. according to the described image processing apparatus of claim 41, it is characterized in that,

Described distortion correction treatment portion moves by being supplied to clock,

Described location of interpolation generating unit, perhaps this location of interpolation generating unit and described distortion correction coordinate converting section are not according to each clock but carry out the generation of location of interpolation across clock, the perhaps generation of the generation of location of interpolation and interpolated coordinates data.

46. according to the described image processing apparatus of claim 38, it is characterized in that,

The Practical Formula of described distortion correction coordinate converting section after according to distortion generates the interpolated coordinates data, makes to have reduced the multiplication number of times with comparing based on the situation of fundamental formular.

47. according to the described image processing apparatus of claim 39, it is characterized in that,

The Practical Formula of described distortion correction coordinate converting section after according to distortion generates the interpolated coordinates data, makes to have reduced the multiplication number of times with comparing based on the situation of fundamental formular.

48. according to the described image processing apparatus of claim 40, it is characterized in that,

The Practical Formula of described distortion correction coordinate converting section after according to distortion generates the interpolated coordinates data, makes to have reduced the multiplication number of times with comparing based on the situation of fundamental formular.

49. according to the described image processing apparatus of claim 41, it is characterized in that,

The Practical Formula of described distortion correction coordinate converting section after according to distortion generates the interpolated coordinates data, makes to have reduced the multiplication number of times with comparing based on the situation of fundamental formular.

50. according to the described image processing apparatus of claim 42, it is characterized in that,

The Practical Formula of described distortion correction coordinate converting section after according to distortion generates the interpolated coordinates data, makes to have reduced the multiplication number of times with comparing based on the situation of fundamental formular.

51. according to the described image processing apparatus of claim 43, it is characterized in that,

The Practical Formula of described distortion correction coordinate converting section after according to distortion generates the interpolated coordinates data, makes to have reduced the multiplication number of times with comparing based on the situation of fundamental formular.

52. according to the described image processing apparatus of claim 44, it is characterized in that,

The Practical Formula of described distortion correction coordinate converting section after according to distortion generates the interpolated coordinates data, makes to have reduced the multiplication number of times with comparing based on the situation of fundamental formular.

53. according to the described image processing apparatus of claim 45, it is characterized in that,

The Practical Formula of described distortion correction coordinate converting section after according to distortion generates the interpolated coordinates data, makes to have reduced the multiplication number of times with comparing based on the situation of fundamental formular.

54. according to the described image processing apparatus of claim 39, it is characterized in that, described distortion correction coefficient calculation circuit according to distortion correction after image in corresponding position and the described distortion correction coefficient of the distance calculation between the center of distortion position of concerned pixel, carry out at least a portion of the calculation process in this calculating by the floating-point fractional arithmetic.

55., it is characterized in that described distortion correction coefficient calculation circuit has look-up table according to the described image processing apparatus of claim 54, the square value of the described distance of this look-up table stores and the corresponding relation of described distortion correction coefficient,

Obtain the square value of this distance by described floating-point fractional arithmetic, come to obtain described distortion correction coefficient with reference to this look-up table by square value according to the distance of obtaining.

56. image processing apparatus, the electronic image data that obtain making a video recording through optical system are handled, and described view data is made of a plurality of compositions, it is characterized in that, this image processing apparatus has distortion correction treatment portion, and this distortion correction treatment portion comprises:

Distortion correction coefficient calculations portion, it calculates the distortion correction coefficient that is used to proofread and correct the distorton aberration that is caused by described optical system according to the distance from the center of distortion position at described each composition; And

The distortion correction operational part, the distortion correction coefficient that it uses each composition of calculating by described distortion correction coefficient calculations portion carries out distortion correction according to each composition to described view data.

57., it is characterized in that described distortion correction operational part is provided with a plurality of with all the components that constitutes described view data according to the described image processing apparatus of claim 56 one to one correspondingly.

58. according to the described image processing apparatus of claim 57, it is characterized in that,

Described distortion correction operational part constitutes has the internal buffer that is used for storing image data, and has stored in this internal buffer the stage of carrying out the needed view data of distortion correction treatment, and the output distortion treatment for correcting begins request,

Also has the synchronous portion of allowance, this permits synchronous portion after collecting complete from the distortion correction treatment of whole distortion correction operational parts of described a plurality of distortion correction operational parts to begin request, and these whole distortion correction operational parts are controlled so that begin distortion correction treatment.

59. according to the described image processing apparatus of claim 58, it is characterized in that,

The synchronous portion of described allowance is used to permit the enabling signal of the computing of distortion correction coefficient to the output of described distortion correction coefficient calculations portion, the calculating of the distortion correction coefficient relevant that is undertaken by this distortion correction coefficient calculations portion with beginning with all the components, thereby whole distortion correction operational parts is controlled, so that beginning distortion correction treatment.

60., it is characterized in that at least a portion of described distortion correction coefficient calculations portion is as when calculating the distortion correction coefficient of described each composition the shared part of all the components being constituted according to the described image processing apparatus of claim 56.

61., it is characterized in that at least a portion of described distortion correction coefficient calculations portion is as when calculating the distortion correction coefficient of described each composition the shared part of all the components being constituted according to the described image processing apparatus of claim 57.

62., it is characterized in that at least a portion of described distortion correction coefficient calculations portion is as when calculating the distortion correction coefficient of described each composition the shared part of all the components being constituted according to the described image processing apparatus of claim 58.

63., it is characterized in that at least a portion of described distortion correction coefficient calculations portion is as when calculating the distortion correction coefficient of described each composition the shared part of all the components being constituted according to the described image processing apparatus of claim 59.

64. according to the described image processing apparatus of claim 60, it is characterized in that,

The square value from the distance of described center of distortion position is calculated by described distortion correction coefficient calculations portion, obtains described distortion correction coefficient according to this square value by each composition,

To the shared part of described all the components is the part that is used to calculate from the square value of the distance of this center of distortion position.

65. according to the described image processing apparatus of claim 61, it is characterized in that,

The square value from the distance of described center of distortion position is calculated by described distortion correction coefficient calculations portion, obtains described distortion correction coefficient according to this square value by each composition,

To the shared part of described all the components is the part that is used to calculate from the square value of the distance of this center of distortion position.

66. according to the described image processing apparatus of claim 62, it is characterized in that,

The square value from the distance of described center of distortion position is calculated by described distortion correction coefficient calculations portion, obtains described distortion correction coefficient according to this square value by each composition,

To the shared part of described all the components is the part that is used to calculate from the square value of the distance of this center of distortion position.

67. according to the described image processing apparatus of claim 63, it is characterized in that,

The square value from the distance of described center of distortion position is calculated by described distortion correction coefficient calculations portion, obtains described distortion correction coefficient according to this square value by each composition,

To the shared part of described all the components is the part that is used to calculate from the square value of the distance of this center of distortion position.

68. according to the described image processing apparatus of claim 64, it is characterized in that,

Described distortion correction coefficient calculations portion all has look-up table at described each composition, and this look-up table stores is from the square value of the distance of described center of distortion position and the corresponding relation of described distortion correction coefficient,

Described distortion correction coefficient calculations portion by the look-up table with reference to described each composition, obtains described distortion correction coefficient at each composition according to the square value of the described distance of calculating.

69. according to the described image processing apparatus of claim 65, it is characterized in that,

Described distortion correction coefficient calculations portion all has look-up table at described each composition, and this look-up table stores is from the square value of the distance of described center of distortion position and the corresponding relation of described distortion correction coefficient,

Described distortion correction coefficient calculations portion by the look-up table with reference to described each composition, obtains described distortion correction coefficient at each composition according to the square value of the described distance of calculating.

70. according to the described image processing apparatus of claim 66, it is characterized in that,

Described distortion correction coefficient calculations portion all has look-up table at described each composition, and this look-up table stores is from the square value of the distance of described center of distortion position and the corresponding relation of described distortion correction coefficient,

Described distortion correction coefficient calculations portion by the look-up table with reference to described each composition, obtains described distortion correction coefficient at each composition according to the square value of the described distance of calculating.

71. according to the described image processing apparatus of claim 67, it is characterized in that,

Described distortion correction coefficient calculations portion all has look-up table at described each composition, and this look-up table stores is from the square value of the distance of described center of distortion position and the corresponding relation of described distortion correction coefficient,

Described distortion correction coefficient calculations portion by the look-up table with reference to described each composition, obtains described distortion correction coefficient at each composition according to the square value of the described distance of calculating.

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