CN1798980A

CN1798980A - Delay-fault testing method,Related system and circuit

Info

Publication number: CN1798980A
Application number: CNA2004800153976A
Authority: CN
Inventors: N·T·温根; G·E·埃曼
Original assignee: Koninklijke Philips Electronics NV
Current assignee: Koninklijke Philips NV
Priority date: 2003-06-03
Filing date: 2004-05-28
Publication date: 2006-07-05
Also published as: WO2004106958A1; TW200508637A; EP1634089A1; KR20060019565A

Abstract

A testing approach involves selective application of clock signals to target circuitry. In an example embodiment ( 300 ), a target circuit ( 332 ) having logic circuitry that processes data in response to an operational clock signal ( 308 ) having at least one clock period, is analyzed for delay faults. Test signals are applied to the logic circuitry while the logic circuitry is clocked with a high-speed test clock ( 309 ) having several clock-state transitions that occur during at least one clock period of the operational clock ( 308 ). An output from the logic circuitry is analyzed for its state (e.g., as affected by delay in the circuitry). Delay faults are detected as a difference in state of the output of the logic circuitry. With this approach, circuits are tested using conventional testers ( 340 ) that operate at normal (e.g., slow) speeds while selectively clocking selected portions of the circuit at higher speeds for detecting speed-related faults therein.

Description

Delay fault testing method, related system and circuit

The present invention relates in general to a kind of test circuit, and relates more specifically to comprise the circuit testing method and the device of test signal (comprising timing signal).

Electronics industry continues to rely on the development of semiconductor technology aspect, so that realize having the device of higher function in compacter zone.For many application, realize that the device with higher function need be integrated into a large amount of electronic installations in the single silicon wafer.When the number of electronic devices on each given area of silicon wafer increased, it is difficult more that the Computer-Assisted Design, Manufacture And Test process becomes.

Had multiple technologies to be used for electronic-circuit device, in case to guarantee to have made these electronic-circuit devices, they will be comply with their predetermined design and implementation specification fully and operate.Yet, when the operating speed of circuit increases when satisfying the needs of the device with higher function, because defective and other fault can appear in high operating speed.In this respect, when the operating speed of circuit increased, many circuit showed the suspicious defective that occurs with higher rate.

A kind of like this defective that together occurs with the high speed operation of the circuit position of the defective that shows speed sensitive is that resistive is electrically connected.Aspect production, Performance And Reliability, the resistive interconnection has been main circuit manufacturing issue, and when interconnection level quantity and operating frequency increase, expects that this problem can become more important.This resistive connects often slower than the reaction of other circuit part, thereby causes at circuit position the delay in the response of input signal (for example delay fault).This delay for example can cause providing misdata, switching delay or other problem.Yet, in order to analyze these delay faults, operation (clock) circuit under high relatively frequency of having to.Though detecting the ability of these defective interconnection may be extremely useful for diagnosing the IC fault and carrying out corrective action, this detection usually needs high-frequency operation to produce functional fault.

Traditionally, by utilizing the test vector function circuit to attempt detecting the fault of delay type in the mode that causes the fault generation.Yet the clock that this electrical testing typically need use in test vector application (test clock or TCK) process increases to the speed that tends to occur delay fault.This method has typically needed for example to have the tester of high speed test clock, perhaps such as other method of multiplier.Yet, these methods have its limitation: traditional tester is not operated under high speed, the tester of employing high speed test device clock is generally comparatively expensive and need carry out all tests under high speed, and multiplier is confined to the multiple of test clock aspect frequency application.

These and other difficulty has proposed challenge to the design that is used for multiple application.

Various aspect of the present invention comprises the method for testing that is used for multiple circuit, such as those circuit that comprise memory circuitry and other circuit.With multiple implementation with should be used for illustration the present invention, summarize wherein some below.

According to one exemplary embodiment of the present invention, utilize the operating clock comprise relative low speed and the method for the high speed test clock realized for clock objective circuit selectivity is come test circuit.Input and operating clock that the high speed test clock is suitable for being used to the self-test signal generator come logical circuit is operated or clock, simultaneously the test signal input are provided to objective circuit.Detection is from the output of objective circuit, and the delay in will exporting (for example delay of exporting with respect to expection) detection is delay fault.Utilize this method, traditional tester can be used to analysis circuit, also utilizes the high-frequency clock that can separate control with the operating clock of traditional test device to come circuit is carried out clock simultaneously.

Circuit tester with control signal is used to utilize operating clock operational objective circuit under test pattern more specifically in the exemplary embodiment at one of the present invention, meanwhile utilizes test clock signals to come logical circuit in the operational objective circuit.This operation clock signal has at least one clock period, and this test clock signals has at least four clock status transition that come across in this at least one clock period.In one implementation, described operating clock has a frequency, and described test clock signals to have one be the fast frequency of this operational clock frequency twice at least.In response to test clock signals, logical circuit produces an output that is received and handled by circuit tester, so that detect the delay fault in the objective circuit.

In another exemplary embodiment, described circuit arrangement comprises (on-board) high-speed clock circuit on the plate that can programme in combination with the external circuit tester and operate.This high-speed clock circuit is suitable for optionally being used to from the high-speed clock signal of a high-frequency clock with from the test signal of this external circuit tester, so that optionally high-speed clock signal is applied to the logical circuit in this circuit arrangement during acquisition mode.During non-acquisition mode, this high-speed clock circuit is by the operating speed clock signal from this external circuit tester.In a kind of situation, this high-speed clock circuit is carried out a delayed sequence when starting acquisition mode, and utilizes this high-speed clock signal to come this logical circuit of clock in the center section process in the cycle of catching after starting this delayed sequence.This high-speed clock circuit forbade applying this high-speed clock signal subsequently before catching end cycle.

Summary above of the present invention does not attempt to describe each embodiment of the present invention or each implementation.Summary above of the present invention does not attempt to describe each illustrated embodiment or each implementation.Below drawings and detailed description more specifically illustration these embodiment.

Consider the following detailed description of the various embodiment of the present invention that combine with accompanying drawing, can understand the present invention more up hill and dale, wherein:

Fig. 1 is the process flow diagram that is used for test circuit according to an illustrative embodiment of the invention;

Fig. 2 A shows the circuit testing method that comprises the signal Synchronization of utilizing phase-locked loop (PLL) of another exemplary embodiment according to the present invention;

Fig. 2 B shows the circuit testing method that comprises the delay fault test of another exemplary embodiment according to the present invention; And

Fig. 3 shows being included as the delay fault test of according to the present invention another exemplary embodiment and the circuit arrangement that is used for circuit test of a clock signal is provided.

Shown detail of the present invention and will describing in detail by the example in the accompanying drawing, but can carry out various modifications and the present invention can have various alternatives the present invention to it.Yet should be appreciated that, do not attempt to limit the invention to described specific embodiment.On the contrary, the present invention covers whole modifications, equivalents and the alternative that falls in the scope of the invention that is limited by appended claims.

The present invention is applicable to multiple circuit and the method that comprises and/or benefit from test, and is specially adapted to comprise the test of timing method and circuit.Though the invention is not restricted to this application, in this environment by the various exemplary cases various aspects that the present invention may be better understood are discussed.

According to one exemplary embodiment of the present invention, utilize a kind of method of high-speed clock circuit that comprises to come test electronic circuits, so that during test pattern, optionally a high-speed clock signal is applied to this electronic circuit.For example, can realize this high-speed clock circuit in combination with the circuit tester of the traditional type of operating clock with relatively slow speed.In one implementation, this high-speed clock circuit is the part of tested electronic circuit.In another implementation, this high-speed clock circuit is a part that also has the circuit tester of slower operating clock as discussed above.In another implementation, this high-speed clock circuit and tested electronic circuit be used to apply the circuit tester of test signal and separate to this electronic circuit.In each of these situations, detect output, and use one of them regularly relevant variation to detect the regularly existence of type cases, such as resistance circuit or delay fault from this electronic circuit.Utilize this method, needn't revise the operation of circuit tester by detecting the output that produces in response to the test clock signals of being implemented, this circuit tester can be in traditional mode (low velocity just) operation down, to be used to operate this electronic circuit.

At one more specifically in the implementation, described high-speed clock circuit is suitable for being used to the input from circuit tester, so that optionally apply this high-speed clock signal during the center section of the acquisition mode of this circuit tester.During the single cycle of described operation clock signal, produce several clock status transition by this high-speed clock circuit.An initial input (for example scan enable input) is used to start acquisition mode and a timed events sequence, and this timed events sequence postpones one or more clock status transition with applying of this high-speed clock signal after starting acquisition mode.Utilize this logical circuit to carry out this timed events sequence, this logical circuit is this high-speed clock signal of forbidding before acquisition mode stops also.

Fig. 1 shows the process flow diagram of the delay fault testing method that is used for electronic circuit according to an illustrative embodiment of the invention.At square 110 places, enable circuit tester, and this circuit tester produces the clock signal (for example utilizing automatic test pattern to produce the clock signal of JTAG (joint test access group) tester of (ATPG)) of a relative low speed.At square 120 places, produce a fast clock signal (for example utilizing the clock generation circuit on this electronic circuit).Enable a test scan at square 130 places, so that utilize the clock signal of this relative low speed to test this electronic circuit.At delayed sequence that utilizes this electronic circuit to postpone the enforcement of this quick clock of square 140 places (for example in acquisition mode) beginning, and keep a times selected amount.After postponing, in order to detect delay fault, the quick clock that will be used for the clock objective circuit at square 150 places applies cycle short period (for example several clock status transition), and at square 160 places this quick clock of forbidding.In the output of square 170 places reception, for example can be in the process of forbidding this fast clock signal and detect described output at least in part at square 160 from the objective circuit that passes through this quick clock operation.Assess this output at square 180 places whether delay fault is arranged.If there is not additional delay (be square 150 during), then with this input for not representing defectiveness.Yet,, should postpone to detect for the defective circuit of expression, such as circuit with resistive connection if in this output signal (during square 150), have additional delay.In order to detect after delay fault implemented described quick clock, can repeat to apply this clock, for example to be used in new test vector displacement and to restart the sequence that begins at square 110 places.

Utilization is used to detect the several different methods of the signal that is delayed can implement method discussed above.A kind of method like this comprises utilizes phase-locked loop (PLL) to produce the clock of catching that is used for output signal, such as the clock signal of 110 places of the square in Fig. 1 generation.For example utilize the circuit on the objective circuit to implement this PLL, so that produce system frequency.For example, when with respect to the output of the known analyzed objective circuit of input clock signal (for example, it is " locked " the clock status transition to input clock signal), the accident in the output changes can be used to detect the response that is delayed.

Utilization is at the quick clock that is used to operate this objective circuit that produces on the objective circuit (for example clock on the chip), and Fig. 2 A has illustrated the other method of implementing in conjunction with an illustrative embodiment of the invention that is used to lock.In the method shown in Fig. 2 A at a kind of three-mode delay fault test process, and can for example implement in combination, and also can implement in combination with following signal and the method for in Fig. 2 B, further discussing with the method shown in the Fig. 1 that discusses in the above.The different tester states of circuit tester comprise init state 200, displaced condition 210 (wherein using first shift vector), trapped state 215 (during apply a high-frequency clock) and output state 220 (during first shift vector shift out, and use second shift vector).Two signals 230,240 shown in it are respectively at test controll block (TCB) circuit signal and phase-locked loop (PLL) signal.Utilize TCB signal 230, for evaluating objects circuit (for example circuit board) is implemented this TCB, to be used for delay fault enable (DFE) test.Utilization is at rising transition (low paramount) input clock afterwards of TCB signal 230, and PLL signal 240 begins locking or synchronous.Line 235 shows the delay between the initial sum end of PLL locking, and described PLL signal locked before trapped state 215.In trapped state 215, be used subsequently from the output clock of PLL,, thereby easily detect variation in the timing of this output signal so that analyze the output signal of being caught at a benchmark (locking phase) from the output of tested circuit.

Fig. 2 B shows the method for utilizing a high frequency clock to come the clock objective circuit, meanwhile utilize a tester with clock of relative low speed to test this objective circuit according to another exemplary embodiment of the present invention.For example under the situation of using the jtag test signal, utilize a tester (such as circuit tester shown in Figure 3 340) to operate an objective circuit (such as the objective circuit 332 of Fig. 3), three test patterns shown in it comprise first shift mode 250, acquisition mode 260 and second shift mode 270.Comprise the test clock signals (TCK) 280 that is used to operate this objective circuit, the scan enable signals (SE) 282 that is used to start a scan period, high frequency clock input signal (CLKI) 284 and clock signal (CLKO) 286 at the signal shown in Fig. 2 B.CLKI 284 can for example come from a source of separating with this objective circuit, or from the PLL circuit on this objective circuit, for example as discussing in conjunction with Fig. 2 A.What go out as shown is such, along with the time applies these signals (what for example go out as shown is such, is the time on the horizontal direction, is signal voltage on the vertical direction).Implement CLKO 286 as the one or more function in the middle of TCK 280, SE 282 and the CLKI 284, and apply described CLKO 286 with operation (clock) this objective circuit.During shift mode 250, signal corresponding to TCK 280 of CLKO 286 outputs begins until acquisition mode 260.In one implementation, before entering acquisition mode 260, carry out a checking and check, lock to guarantee PLL, as being discussed in conjunction with Fig. 2 A.

When acquisition mode 260 beginning, implements the catching of weak point of three clock status transition that are approximately CLKI 284, CLKO 286 remains height therebetween, until the 4th the clock status change of CLKI.After this weak point was caught delay, the high extremely low transition in times 287 place began (wherein per two this clock status transition have the cycle (T), and it was illustrated by the cycle 290), and CLKI is applied about two cycles (comprising that four clock status change transition).After the described clock status of finishing CLKI 284 changed transition, CLKO 286 remained height (" 1 ") for the remainder of acquisition mode 260.

After finishing acquisition mode 260, forbidding SE 282 (transferring height to), and enter second shift mode 270, and in this case, signal of CLKO 286 outputs corresponding to TCK280.Detection is from the lag characteristic of the output of objective circuit, and described lag characteristic is to utilize CLKI 286 (being during the times 287 clock status transition that begins of place) by the function of this objective circuit of clock.If the output from objective circuit demonstrates delay, for example compare and combine with Fig. 2 A with PLL method as discussed above, detect resistive and/or delay type fault in the objective circuit.

Method and other method of utilizing multiple circuit arrangement and method to discuss in conjunction with the accompanying drawings above can be embodied in.Fig. 3 shows the sort circuit device 300 of another exemplary embodiment according to the present invention.Following table 1 will be discussed various signals and the element of realizing in conjunction with Fig. 3.

Table 1

STM	Scan testing mode; A control bit that is used for this signal is positioned at the test controll block of implementing in conjunction with Fig. 3 (TCB).
STM		SE	Scan enable; For example control from an external source or circuit tester by a device pin.

DFE	Delay fault enable; A control bit that is used for this signal also is positioned at TCB.
DFE		TCK	The test clock input.This input for example is used to the scan chain that is shifted, and for example controls from an external source or circuit tester by a device pin.
CLKI	The clock input; It for example is the functional clock that produces on the tested circuit in a tester, perhaps controls from the external source that is coupled to a device pin.	TCK
CLKI		CLKO	Clock output; It is to connect to the clock of tested one or more circuit, and in response to the type (for example functional mode or test pattern) of the pattern of circuit tester.
U1	During sweep test, detect initial (not being scanned) of acquisition mode.	CLKO
U1		U2, U3	In the CLKI territory, carry out (not being scanned) synchronously to catching initiation event.
U4, U5, U6	When SE shows that acquisition mode is carrying out, produce " being back to 1 (RTO) " clock with two pulses and forward direction by this clock (not being scanned).	U2, U3
U4, U5, U6		U7	Selection will be used catches clock; If DFE=1, then forward direction is by the RTO CLKI of these two pulses; Otherwise use TCK.
U8	Selection is still to catch the clock CLKI of TCK or one two pulse version (itself or) by shift clock (it is TCK always).	U7
U8		U9	Selection is by functional clock (it is CLKI always) or DFT clock (from the clock output of U8).

There is shown circuit 300, the input of this circuit 300 comprises scan testing mode (STM) 302, scan enable (SE) 304, delay fault enable (DFE) 306, test clock (TCK) 308 and quick clock CLKI 309.Output from circuit 300 is CLKO330, and CLKO 330 is used to the operation (clock) of objective circuit 332.Circuit tester 340 such as the jtag test device is used to provide the operation input of importing STM 302, SE 304, DFE 306 and TCK 308 and arriving objective circuit 332.Also detect the output of objective circuit 332, and described output is used to detect the delay fault in the objective circuit by circuit tester 340.Circuit 300 is supported at least four operator schemes, further discusses below in conjunction with table 2.

Circuit 300 comprises five flip-flop circuits 310,312,314,316 and 318, wherein has by the trigger 310 of TCK 308 clocks with by the trigger 312,314,316 and 318 of CLKI 309 clocks.Do not scan each in these flip-flop circuits, so as during the delay fault sweep test as predetermined ground (just as following the discussion) move these triggers.Circuit 300 also comprises logical circuit, this logical circuit is that the form with two to one multiplexers 322,324 and 326 presents in this example, and it is used for selecting to be used for the signal that forward direction is passed to CLKO 330 based on being provided with of input signal DFE 306, SE 304 and STM 302 respectively.For example, multiplexer 322 is by TCK 308, unless DFE 306 is " 1 " (forward direction is by the output from NAND door 320 in this case).When SE 304 was " 1 ", multiplexer 324 was by TCK 308, and when SE is " 0 " (for example during the acquisition mode shown in Fig. 2 B), multiplexer 324 forward directions are by the output from multiplexer 322.Multiplexer 326 in scan testing mode (when STM is " 1 ") by from the output of multiplexer 324, (when STM is " 0 ") is then by CLKI 309 when not in scan testing mode.In brief, flip-flop circuit 310-318 and NAND door 320 produce " being back to 1 " output with two pulses in combination with SE 304, TCK 308 and CLKI 309.When STM 302 is enabled (height), when SE 304 is enabled (height) for low and DFE 306, be passed to CLKO 330 and objective circuit 332 from " being back to one " output of NAND door 320 by forward direction.

At (for example during shift mode) before the acquisition mode, when SE 304 was high (" 1 "), for example during shift mode, a logical zero was provided to trigger 310 (SE 304 turn to " 0 " from " 1 ").Should zero by trigger 310,312,314,316 and 318 clocks, and with it as providing to NAND door 320 from " 1 " (through overturning) of trigger 318 with from " 0 " of node 315.NAND door 320 also receives CLKI 309, and it carries out clock status transition between " 1 " and " 0 ".Because the input to NAND door 320 all is not " 1 ", is " 1 " so be provided to the output of selector circuit 322, for example as shown during the first of the acquisition mode among Fig. 2 B 260.

For example as shown in conjunction with the SE among Fig. 2 B 282 and acquisition mode 260, when SE 304 transferred low (" 0 ") to, a logical one was provided to trigger 310 (SE 304 turn to " 1 " from " 0 ").Transfer to lowly equally in response to SE 304, select output at multiplexer 324 places, and its forward direction is passed to multiplexer 326 from multiplexer 322.When utilizing TCK 308 clocked flip-flops 310, logical one is provided to trigger 312, and trigger 312 is by CLKI 309 clocks.After the clock status transition of CLKI 309, " 1 " at trigger 312 places is passed to trigger 314.After another clock status transition of CLKI 309, be passed to node 315 and trigger 316 in " 1 " at trigger 314 places, wherein node 315 (and therefore " 1 ") is coupled to the input end of NAND door 320.At this moment, trigger 318 (turning to " 1 ") provides one " 0 ", and switches between clock signal clk I 309 high (" 1 ") and low (" 0 ").In this respect, when " 1 " passes through trigger 316 and 318, during following two clock status transition of CLKI, when CLKI 309 is " 1 ", the upset output of NAND door 320 is " 1 ", and when CLKI 309 was " 0 ", the upset of NAND door 320 output was " 0 ".Therefore, for example shown in the cycle among Fig. 2 B 290, CLKI 309 is followed in the output of NAND door 320.

Afterwards, become " 1 " from the output of trigger 318, and provide corresponding energizing signal " 0 " at NAND door 320 places by trigger 316 and 318 clocks these " 1 ".Therefore, as the part of CLKI 284 signals after cycle among Fig. 2 B 290 is shown, be back to 1 from the output of NAND door 320.Be back to " 1 " (end of the acquisition mode 260 that example is as shown in fig. 2B) afterwards at SE 304, multiplexer 324 forward directions are by TCK 308.

According to an exemplary embodiment more specifically of the present invention, table 2 shows the method that is used to realize circuit 300 as shown in Figure 3.

Table 2

STM	DFE	CLKO	Pattern
STM	DFE	CLKO	Pattern	0	x	CLK1	Function
1	0	TCK	Utilize the normal scan or the delay fault sweep test in external test clock source	0	x	CLK1	Function
1	0	TCK		1	1	SE=1; TCK SE=0; CLKI two pulse RTO	Utilize the delay fault sweep test of internal clocking

With reference to Fig. 3 and table 2, when STM 302 did not enable (for " 0 "), multiplexer 326 was passed to CLKO 330 with CLKI 309 (" function " clock in the top form).When STM302 is " 1 " and DFE 306 when being " 0 ", circuit selector switch 322 is passed to multiplexer 324 with TCK 308, because TCK locates in input " 1 " and " 0 " simultaneously, so this multiplexer 324 passes through TCK.When STM 302, DEF 306 and SE 304 all were " 1 ", TCK 308 was passed to CLKO 330.When STM 302 and DFE 306 are " 1 " and SE 304 when being " 0 ", signal is passed to CLKO 330 " to be back to zero " from two pulses of NAND door 320.

Only the mode by explanation is provided at top the description and various embodiment illustrated in the accompanying drawings, and it is not construed as limiting the invention.Based on top discussion and explanation, those of ordinary skill in the art will readily appreciate that, can not strictly follow in the exemplary embodiment of this explanation and description and application and the present invention is carried out various modifications and change.Implement these methods in conjunction with various exemplary embodiments of the present invention.This modification and change do not break away from true spirit of the present invention and the scope of setting forth in appended claims.

Claims

1, a kind of delay fault testing method that is used for circuit tester, this circuit tester has the control signal that is used at test pattern operational objective circuit, this objective circuit has in response to an operation clock signal with at least one clock period and comes the logical circuit of deal with data, and this method comprises: a test clock signals (110,120,130,140,150,160) with at least four clock status transition that occur in described at least one clock period is provided; Utilize this circuit tester to move this objective circuit simultaneously and utilize this test clock signals to move this logical circuit, thereby make this logical circuit produce an output signal, wherein this circuit tester utilizes this operation clock signal to move this objective circuit; And receive at this circuit tester place and handle this output signal (170), thereby detect the delay fault (180) in this objective circuit.

2, the method for claim 1, wherein provide a test clock signals to comprise and produce a fast clock signal (120), and wherein utilize this test clock signals to move described logical circuit to comprise and optionally this fast clock signal is applied at least four clock status transition (150) with described at least four clock status transition.

3, the method for claim 1 also comprises: an interface circuit is provided, and this interface circuit is optionally by being used for moving the test clock signals of described logical circuit, thereby comes control signal in response to described test clock signals and operation clock signal.

4, method as claimed in claim 3, wherein provide an interface circuit that the interface circuit that provides to have delayed mode and acquisition mode further is provided, this interface circuit during the delayed mode described operation clock signal is passed to described objective circuit and during acquisition mode by described test clock signals to move described logical circuit, make this logical circuit produce an output signal thereby wherein move described logical circuit and make this logical circuit produce during an output signal is included in acquisition mode.

5, method as claimed in claim 3, optionally pass through this test clock signals during wherein optionally being included in acquisition mode by described test clock signals, this be by: at least one cycle that this test clock signals is postponed this test clock signals after acquisition mode begins passes through, and forbids at least one cycle in this test clock signals that before acquisition mode finishes this test clock signals passes through.

6, the method for claim 1 wherein detects delay fault and comprises the detection resistance circuit.

7, method as claimed in claim 6 wherein detects resistance circuit and comprises that detection responds slower circuit owing to the high electrical resistance in the resistance circuit than other circuit in the described objective circuit.

8, the method for claim 1 wherein provides a test clock signals to comprise that the circuit that utilizes in the described objective circuit produces this test clock signals.

9, the method for claim 1, wherein provide a test clock signals to comprise: utilize a computing machine of programming for the frequency of selecting this test clock signals, and utilize this programmed computer select this frequency to be used for the described logical circuit of operation under selected frequency.

10, the method for claim 1, also comprising the phase place that locking receives and handles described output signal before described test clock signals is provided, is from the delay in the output signal of described logical circuit so that the phase change of described output signal can be detected.

11, a kind of delay fault test macro that is used for circuit tester, this circuit tester has the control signal that is used at test pattern operational objective circuit, this objective circuit has in response to an operation clock signal with at least one clock period and comes the logical circuit of deal with data, and this system comprises: the device that provides one to have the test clock signals of at least four clock status transition that occur in described at least one clock period is provided; Thereby be used for utilizing this circuit tester to move this objective circuit simultaneously and utilize this test clock signals to move this logical circuit making this logical circuit produce the device of an output signal, wherein this circuit tester utilizes this operation clock signal to move this objective circuit; Thereby and be used for receiving and handling the device that this output signal detects the delay fault of this objective circuit at this circuit tester place.

12, a kind of delay fault test macro that is used for circuit tester (300), this circuit tester has the control signal (302 that is used at test pattern operational objective circuit, 304,306,308,309), this objective circuit has in response to an operation clock signal (308) with at least one clock period and comes the logical circuit (310 of deal with data, 312,314,317,320,322,324,326), this system comprises: a test clock signals generator, and it has at least four clock status transition that occur in described at least one clock period; An interface circuit, be suitable for utilizing simultaneously this circuit tester (340) to move this objective circuit and utilize this test clock signals (309) thus moving this logical circuit makes this logical circuit produce output signal (330), wherein this circuit tester (340) utilizes this operation clock signal (308) to move this objective circuit (332); And a pick-up unit, detect delay fault in this objective circuit (332) thereby be suitable for receiving and handle this output signal at this circuit tester place.

13, system as claimed in claim 12, wherein said test clock signals generator is arranged in described objective circuit, and this test clock signals generator is coupled to described logical circuit to be used for providing described test clock signals to it.

14, system as claimed in claim 12 wherein can programme to be used to produce a test clock signals with selectable frequency to described test clock signals generator.

15, system as claimed in claim 12, also comprise described circuit tester, wherein said circuit tester is suitable for providing a scan enable signals during acquisition mode, and described interface circuit also is suitable for by entering the operation of described logical circuit being made response to this scan enable signals during acquisition mode.

16, system as claimed in claim 15, wherein said circuit tester also is suitable for providing a delay fault enable signal, wherein, at least one clock status transition that described interface circuit is suitable for postponing to apply by the test clock signals that will be used to move described logical circuit after enabling described scan enable signals this test clock signals comes described delay fault enable signal and scan enable signals are made response, and described interface circuit was suitable for before forbidding described scan enable signals, in at least one clock status transition of this test clock signals, forbid applying this test clock signals that is used to move this logical circuit.

17, system as claimed in claim 15, wherein said circuit tester is suitable for utilizing described test clock signals to provide described control signal to described logical circuit.

18, system as claimed in claim 12, wherein said test clock signals generator comprises a latch circuit that is configured and is arranged to phase locking to one benchmark of described output signal, to be used for being the phase change of described output signal with postponing to detect.

19, system as claimed in claim 18, wherein said latch circuit is suitable for: starting one after the test vector of described objective circuit, and utilize described circuit tester to move this objective circuit simultaneously and utilize described test clock signals to move before thereby described logical circuit makes that this logical circuit produces an output signal at described interface circuit, lock the phase place of this output signal, wherein this circuit tester utilizes described operation clock signal to move described objective circuit.

20, a kind of circuit chip that is used for the delay fault circuit tester, this circuit tester is suitable for utilizing an operating clock with at least one clock period to provide test signal to objective circuit, this circuit chip comprises: an objective circuit is included under the high operating clock speed regularly relevant fault and can be in response to the logical circuit of operating in test pattern from the test signal of this circuit tester easily takes place; The high speed test clock signal that optionally provides one to have at least four clock status transition that occur in described at least one clock period of operating clock is provided for a test clock signals generator circuit, this test clock signals generator circuit; And clock interface circuit, this clock interface circuit is suitable for optionally described operation clock signal and test clock signals one of them is applied to described objective circuit separately to move this objective circuit, during acquisition mode, optionally apply described test clock signals so that one of this objective circuit generation can be by the output signal of this circuit tester detection, to be used for detecting the delay of described output signal, described delay is the function of the relevant fault of the timing in this objective circuit, and this fault is in response to moves by described high speed test clock signal that this objective circuit occurs.