CN1797725A - A kind of transistor and preparing method - Google Patents
A kind of transistor and preparing method Download PDFInfo
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- CN1797725A CN1797725A CN 200510127197 CN200510127197A CN1797725A CN 1797725 A CN1797725 A CN 1797725A CN 200510127197 CN200510127197 CN 200510127197 CN 200510127197 A CN200510127197 A CN 200510127197A CN 1797725 A CN1797725 A CN 1797725A
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Abstract
Using plug with thermal expansion coefficient different from coefficient of substrate, the invention can produce transistors in biaxial or monaxial strain. If thermal expansion coefficient of plug is larger than coefficient of substrate, then transistor with biaxial tensile strain channel can be formed in active region. If thermal expansion coefficient of plug is smaller than coefficient of substrate, then transistor with biaxial compression strain channel can be formed in active region. If insulation plug possessing larger thermal expansion coefficient at one relative edge of active region, and possessing smaller thermal expansion coefficient at another relative edge of active region, then transistor with monaxial strain is formed in active region.
Description
The application is 02147129.0 for application number, and the applying date is on October 22nd, 2002, and denomination of invention is the dividing an application of patent application of a kind of capacitor and a kind of transistor and manufacture method thereof.
Technical field
The present invention relates to a kind of electronic devices and components and manufacture method thereof, refer to the transistor of the biaxial strain that a kind of insulated plug that utilizes thermal coefficient of expansion to be different from substrate constitutes and the transistor and the manufacture method thereof of uniaxial strain especially.
Background technology
(shallow trench isolation STI) is the isolated component of normal use in the CMOS processing procedure below 0.25 micron to fleet plough groove isolation structure.Yet along with the size of fleet plough groove isolation structure continues to be contracted to below 0.15 micron, the electric field that comes from adjacent source/drain junction bias voltage can easy penetration channel district.The negative effect that therefore, can cause for example Vt disturbance etc.In order to eliminate a penetration effect, the someone proposes the fleet plough groove isolation structure of metallic shield, is after the lining oxide layer of isolated groove forms, and inserts one deck conductive material, for example the compound crystal silicon of Can Zaing.Conductive material ground connection with in the above-mentioned groove can provide good shield effectiveness, therefore can eliminate the problem of transistorized narrow width effect (narrow width effect) and Vt disturbance.Yet this kind processing procedure is comparatively complicated.Therefore, be necessary to propose better isolation structure and processing procedure.
In addition,, make metal oxide semiconductcor field effect transistor (MOSFET) element can be under low operating voltage, have high drive current and usefulness at a high speed and be suitable difficulty along with the downsizing of grid element size.Therefore, many people are in the method for making great efforts to seek to improve the usefulness of mos field effect transistor element.
The band structure modification of utilizing stress to cause increases the mobility of electronics, to increase the drive current of field-effect transistor, can improve the usefulness of field effect transistor element, and this kind method has been applied in the various elements.The silicon passage of these elements is the situations that are in biaxial stretch-formed or compression strain.
Traditionally, by building crystal to grow silicon channel layer in lax (relaxed) SiGe (SiGe) layer or substrate, with the silicon layer of preparation elongation strain.Yet, before the silicon channel layer of growth elongation strain, usually need the Si that the growth lattice is out of shape gradually on silica-based
1-xGe
xLayer, wherein the ratio x of germanium increases to 0.2 gradually from 0, with as resilient coating, more then in Si
1-xGe
xThe lax SiGe layer of growth one deck on the resilient coating.This kind method has a lot of shortcomings, and the different not Si of ear ratio grow up
1-xGe
xThe quite difficult control of the processing procedure of layer, quite time-consuming, and cost improves relatively.And when the not ear ratio of Ge will increase, the brilliant Si that builds
1-xGe
xThe gross thickness of layer can increase thereupon, thereby produces many penetrability difference rows (threading dislocation).
Therefore, the someone proposes carbon atom is incorporated in the germanium-silicon layer, reduces the lattice constant of SiGe to utilize carbon atom, makes the lattice constant of SiGe more near silicon, reduces strain whereby, and allows the thicker germanium-silicon layer of growing up and the diffusion that reduces boron.But this kind method has more increased the processing procedure degree of difficulty of silicon germanium buffer.
Increase the mobility of electronics in the situation that existing research is pointed out to utilize the silicon passage to be in biaxial stretch-formed strain, and utilize the SiGe passage is in increases electric hole in the situation of biaxial compressive strain mobility.Yet, be difficult to realize in conjunction with the nmos pass transistor of silicon passage and the transistorized CMOS process technique of PMOS with SiGe passage of biaxial compressive strain with biaxial stretch-formed strain.Have utilization as above to state many strained layer manufacture methods such as thick resilient coating or other complex multilayer in transistorized manufacturing, these a little methods are not readily integrated in traditional CMOS processing procedure.
Therefore, in order to make metal oxide semiconductcor field effect transistor element, demand seeking the road of improvement urgently at the problems referred to above with high drive current and usefulness at a high speed.
Summary of the invention
In view of this, purpose of the present invention provides a kind of processing procedure of fleet plough groove isolation structure of the problem that can eliminate a penetration effect, and manufacturing simultaneously can add the fleet plough groove isolation structure (hereinafter referred to as insulated plug) of high field penetration effect, to be applied to the element of some (coupling) effects that need to be coupled, for example electric capacity, transistor etc.
In addition, another object of the present invention provides the transistor that a kind of simpler method forms the passage with biaxial stretch-formed or compression strain, and the transistor with passage of uniaxial strain.
A further object of the present invention provides a kind of capacitor and transistor and manufacture method thereof of utilizing the insulated plug formation of differing dielectric constant, wherein the insulated plug of low-k is the usefulness as element separation, the insulated plug of high-k is the usefulness as coupling, for example capacitor dielectric or gate insulator.
To achieve these goals, the invention provides a kind of capacitor that utilizes the insulated plug formation of differing dielectric constant, its structure comprises the first low dielectric constant insulation connector and the second high-k insulated plug is arranged in the substrate, wherein the first low dielectric constant insulation connector defines a capacitive region at least, the second high-k insulated plug is arranged in capacitive region, and capacitive region is divided into the first region and second electrode district.And with first battery lead plate and second battery lead plate be located at the first region in the substrate and second electrode district respectively, wherein the degree of depth of depth ratio first and second battery lead plates of the degree of depth of the first low dielectric constant insulation connector and the second high-k insulated plug is dark.
If above-mentioned capacitor n
+To n
+Capacitor, then first and second battery lead plates are to be n
+The bonding land; If p
+To p
+Capacitor, then first and second battery lead plates are to be p
+The bonding land.
The present invention also provides the manufacture method of the capacitor that a kind of insulated plug that utilizes above-mentioned differing dielectric constant constitutes, its manufacture method is summarized as follows: form first groove and second groove in substrate, wherein first groove defines capacitive region at least, second groove is arranged in capacitive region, and capacitive region is divided into the first region and second electrode district.In this first groove and second groove, form the first low dielectric constant insulation connector and the second high-k insulated plug respectively.Form first battery lead plate and second battery lead plate respectively in the first region in substrate and second electrode district simultaneously, wherein the degree of depth of depth ratio first and second battery lead plates of the second high-k insulated plug between first battery lead plate and second battery lead plate is dark.
According to embodiments of the invention, the material of the first low dielectric constant insulation connector of above-mentioned capacitor can be fluorine-containing chemical vapour deposition (CVD) oxide (D
k≈ 3-3.5) or spin-coating low-k dielectric material (D
k≈ 2-3).The material of the second high-k insulated plug of above-mentioned capacitor can be Al
2O
5, Ta
2O
5(D
k≈ 25) or HfO
2(D
k≈ 30).
In addition, the present invention also provides a kind of transistor that utilizes the insulated plug formation of differing dielectric constant, its structure is for to be arranged at the first low dielectric constant insulation connector and the second high-k insulated plug in the substrate, wherein the first low dielectric constant insulation connector defines an active region, the second high-k insulated plug is arranged in active region, and active region is divided into a gate regions and source.Gate electrode is located at the gate regions of substrate, and wherein the degree of depth of the depth ratio gate electrode of the first low dielectric constant insulation connector and the second high-k insulated plug is dark.And, stack the source/drain regions that is arranged at substrate with the drain electrode of first conductivity, the wellblock of second conductivity and the common-source of first conductivity, wherein a channel region is positioned at the sidewall of the second high-k insulated plug of the second conductivity wellblock.
In the above-mentioned transistor, gate electrode is the bonding land with first conductivity, and has the doped region of second conductivity below gate electrode.
The present invention provides a kind of transistorized manufacture method of utilizing the insulated plug formation of above-mentioned differing dielectric constant equally, its manufacture method is summarized as follows: form first groove and second groove in substrate, wherein first groove defines an active region, second groove is arranged in active region, and active region is divided into gate regions and source/drain regions.In first groove and second groove, form the first low dielectric constant insulation connector and the second high-k insulated plug respectively.Form gate electrode in gate regions, wherein the degree of depth of the depth ratio gate electrode of the first low dielectric constant insulation connector and the second high-k insulated plug is dark.And form the drain electrode of the common-source and first conductivity of first conductivity in source/drain regions, and between common-source and drain electrode, form the wellblock of second conductivity, the common-source of the wellblock of the drain electrode of first conductivity, second conductivity and first conductivity is to be stacked and placed on source/drain regions, and a channel region is positioned at the sidewall of the second high-k insulated plug of the wellblock of second conductivity.
According to embodiments of the invention, the material of the above-mentioned transistorized first low dielectric constant insulation connector can be fluorine-containing chemical vapour deposition (CVD) oxide (D
k≈ 3-3.5) or spin-coating low-k dielectric material (D
k≈ 2-3).The material of the above-mentioned transistorized second high-k insulated plug can be Al
2O
5, Ta
2O
5(D
k≈ 25) or HfO
2(D
k≈ 30).
Moreover, the present invention also provides a kind of transistor of the biaxial strain that insulated plug that thermal coefficient of expansion is different from substrate constitutes and the transistor and manufacture method thereof of uniaxial strain utilized, if the thermal coefficient of expansion of insulated plug is bigger than substrate, then can form the transistor of biaxial stretch-formed strained channel in active region; If the thermal coefficient of expansion of insulated plug is littler than substrate, then can form the transistor of biaxial compressive strain passage in active region; If the relative edge at active region forms the bigger insulated plug of thermal coefficient of expansion, another relative edge forms the less insulated plug of thermal coefficient of expansion, then can form the transistor of uniaxial strain in active region.
The transistor of a kind of biaxial strain provided by the invention, its structure is located in the substrate for the insulated plug that a thermal coefficient of expansion is different from substrate, and wherein this insulated plug is so as to defining active region, and transistor is located at above-mentioned active region.
In the transistor of above-mentioned biaxial strain, the thermal coefficient of expansion of the insulated plug in being located at substrate is during greater than substrate, and transistor is the transistor of biaxial stretch-formed strain, perhaps is nmos pass transistor.In the case, if substrate is a silicon base, the material of then above-mentioned insulated plug can be lead oxide (ZrO
2), steatite (MgOSiO
2), aluminium oxide (Al
2O
3), carborundum (SiC) or silicon nitride (SiN).
In the transistor of above-mentioned biaxial strain, the thermal coefficient of expansion of the insulated plug in being located at substrate is during less than substrate, and transistor is the transistor of biaxial compressive strain, perhaps is the PMOS transistor.In the case, if substrate is a silicon base, the material of then above-mentioned insulated plug can be silica (SiO
2).
A kind of above-mentioned insulated plug that utilizes thermal coefficient of expansion to be different from substrate provided by the invention forms the transistorized method with biaxial strain, and its method is summarized as follows: form groove so as to defining an active region in substrate.In groove, form the insulated plug that thermal coefficient of expansion is different from substrate.And in active region formation transistor.
In addition, the invention provides a kind of transistor of uniaxial strain, its structure is for to be located at a pair of first insulated plug and a pair of second insulated plug with second coefficient of expansion with first coefficient of expansion in this substrate, wherein this defines an active region with this to second insulated plug with second coefficient of expansion to first insulated plug with first coefficient of expansion, first insulated plug with first coefficient of expansion is positioned at the relative edge of active region for this and this is positioned at another relative edge of active region to second insulated plug with second coefficient of expansion.And transistor is located at active region.
In the above-mentioned transistor, substrate can be silicon base, and first thermal coefficient of expansion is bigger than silicon, and second thermal coefficient of expansion is littler than silicon.In the case, first insulated plug can be oxidation mistake (ZrO
2), steatite (MgOSiO
2), aluminium oxide (Al
2O
3), carborundum (SiC) or silicon nitride (SiN), the material of second insulated plug can be silica (SiO
2).
A kind of above-mentioned insulated plug that utilizes thermal coefficient of expansion to be different from substrate provided by the invention forms the transistorized method with uniaxial strain, its method is summarized as follows: form a pair of first groove and a pair of second groove in substrate, wherein this defines an active region to first groove and this to second groove, this is positioned at the relative edge of active region to first groove, and this is positioned at another relative edge of active region to second groove.Form a pair of first insulated plug in this in to first groove, and form a pair of second insulated plug in to second groove with second coefficient of expansion in this with first coefficient of expansion.Form transistor in active region.
The invention has the beneficial effects as follows that above-described various elements are to combine with the processing procedure of fleet plough groove isolation structure, and all can with traditional CMOS process-compatible.Those skilled in the art, can be according to the needs on the circuit design, the capacitor that on same wafer, the above-mentioned insulated plug that utilizes differing dielectric constant is constituted, utilize the transistor of the insulated plug formation of differing dielectric constant, the transistor of the biaxial stretch-formed strain that the insulated plug that utilizes thermal coefficient of expansion to be different from substrate constitutes, the transistor of the biaxial compressive strain that the insulated plug that utilizes thermal coefficient of expansion to be different from substrate constitutes, and the transistor of the uniaxial strain that constitutes of the insulated plug that utilizes thermal coefficient of expansion to be different from substrate is done combination in any or collocation.
Therefore, the present invention can be easily in conjunction with the nmos pass transistor of passage and have the transistorized CMOS process technique of PMOS of the SiGe passage of biaxial compressive strain with biaxial stretch-formed strain, and reach drive current and the usefulness at a high speed that on same wafer, promotes PMOS transistor and nmos pass transistor simultaneously.This is beyond one's reach by conventional method.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A and Figure 1B are the schematic diagrames that expression utilizes the manufacture method of the capacitor that the insulated plug of differing dielectric constant constitutes;
Fig. 2 represents the top view of Figure 1A, and wherein Figure 1A is the profile of the I-I line of Fig. 2;
Fig. 3 represents the equivalent circuit diagram of Figure 1B;
Fig. 4 A to Fig. 4 B represents to utilize the schematic diagram of manufacture method of the nmos pass transistor of the vertical-type that the insulated plug of differing dielectric constant constitutes;
Fig. 5 represents to utilize the transistorized schematic diagram of PMOS of the vertical-type that the insulated plug of differing dielectric constant constitutes;
The transistorized top view that the insulated plug that Fig. 6 represents to utilize thermal coefficient of expansion to be different from substrate constitutes with biaxial stretch-formed strain;
Fig. 7 is that Fig. 6 is along VII-VII line profile;
The transistorized top view that the insulated plug that Fig. 8 represents to utilize thermal coefficient of expansion to be different from substrate constitutes with biaxial compressive strain;
Fig. 9 is that expression utilizes thermal coefficient of expansion to be different from the transistorized top view with uniaxial strain of the insulated plug formation of substrate;
Figure 10 A to Figure 10 G is illustrated in the schematic diagram of the method for the insulated plug that utilizes unlike material in the substrate.
Embodiment
The present invention will have differing dielectric constant (D in the shallow trench separation process
k) dielectric material import wherein, and some electronic components are combined with the shallow trench separation process.For example, formation has the insulated plug of differing dielectric constant, and utilizes the insulated plug of differing dielectric constant to constitute capacitor and/or transistor.Following spy does explanation with embodiment 1 and example 2.
In addition, the present invention is in the shallow trench separation process, the dielectric material that will have different heat expansion coefficient (α) imports wherein, utilize thermal coefficient of expansion to be different from the insulated plug of substrate, have the transistor of biaxial stretch-formed strain, the transistor that has the transistor of biaxial compressive strain and have uniaxial strain so as to formation.Following spy does explanation with embodiment 3.
Embodiment 1: capacitor and the manufacture method thereof of utilizing the insulated plug formation of differing dielectric constant:
Please be simultaneously with reference to Figure 1A, Figure 1B, Fig. 2 and Fig. 3, Figure 1B is relevant with the I-I section of Fig. 2, Fig. 3 is the equivalent circuit diagram for the capacitor of Figure 1B.
As shown in the figure, the capacitor that utilizes the insulated plug formation of differing dielectric constant provided by the present invention is to integrate mutually from structure with the shallow ridges block.At first, low dielectric constant insulation connector 112 and high-k insulated plug 114 are arranged in the substrate 100, wherein low dielectric constant insulation connector 112 defines a capacitive region 106 at least, high-k insulated plug 114 is arranged in capacitive region 106, and capacitive region 106 is divided into the first region 108a and the second electrode district 108b.This high-k insulated plug 114 is in order to as capacitor dielectric.
The first battery lead plate 120a and the second battery lead plate 120b are located at the first region 108a and the second electrode district 108b in the substrate 100 respectively, and wherein the degree of depth of the depth ratio first and second battery lead plate 120a of the degree of depth of low dielectric constant insulation connector 112 and high-k insulated plug 114 and 120b is dark.
The above-mentioned first battery lead plate 120a and the second battery lead plate 120b can be n
+Bonding land (n
+Junction) or p
+Bonding land (p
+Junction).If the former, then capacitor is n
+To n
+Capacitor (n
+To n
+Capacitor); If the latter, then capacitor is p
+To p
+Capacitor (p
+To p
+Capacitor), if p
+The bonding land then and between the substrate 100 (being generally the substrate of p type) is separated with a n well (n-well)
Below will illustrate the manufacture method of this capacitor.
Please refer to Figure 1A and Fig. 2, Figure 1A is the I-I profile of Fig. 2.At first, form groove 102 and 104 in substrate 100, wherein groove 102 defines capacitive region 106 at least, and groove 104 is arranged in capacitive region 106, and capacitive region 106 is divided into electrode district 108a and 108b.Then, in groove 102, form low dielectric constant insulation connector 112, and in groove 104, form high-k insulated plug 114.Wherein, low dielectric constant insulation connector 112 is in order to doing the usefulness of electrical isolation, and high-k insulated plug 114 is in order to the usefulness of capacitive coupling (coupling) to be provided, and high-k insulated plug 114 is as capacitor dielectric at this.
Above-mentioned groove 102 is to utilize etching step to be formed at simultaneously in the substrate 100 with 104, formation as for low dielectric constant insulation connector 112 in groove 102 and 104 and high-k insulated plug 114, be successively to form, can form low dielectric constant insulation connector 112 earlier and form high-k insulated plug 114 again, perhaps form high-k insulated plug 114 earlier and form low dielectric constant insulation connector 112 again.This detailed processing procedure partly will be done explanation in the back.
The material of above-mentioned low dielectric constant insulation connector 112 can be fluorine-containing chemical vapour deposition (CVD) oxide (D
k≈ 3-3.5), spin-coating low-k dielectric material (D
k≈ 2-3) or the material of other similar these character.
The material of above-mentioned high-k insulated plug 114 can be Al
2O
5, Ta
2O
5(D
k≈ 25), HfO
2(D
k≈ 30) or the material of other similar these character.
Then please form battery lead plate 120a and 120b respectively among electrode district 108a in substrate 100 and the 108b simultaneously simultaneously with reference to Figure 1B and Fig. 3, the equivalent circuit diagram of formed capacitor as shown in Figure 3.Wherein the degree of depth of the depth ratio battery lead plate 120a of the high-k insulated plug 104 between battery lead plate 120a and 120b and 120b is dark, makes not short circuit mutually of two battery lead plate 120a and 120b.
Above-mentioned battery lead plate 120a and 120b can utilize the formed n of ionic-implantation
+Bonding land or p
+The bonding land.If battery lead plate 120a and 120n are n
+The bonding land, then capacitor is n
+To n
+Capacitor; If battery lead plate 120a and 120b are p
+The bonding land, then capacitor is p
+To p
+If capacitor is p
+The bonding land then and between the substrate 100 (being generally the substrate of p type) is separated with a n well (n-well).
The contact area of the size of the capacitance of formed capacitor and groove 104, the size of dielectric constant of inserting the material in the groove 104 and battery lead plate 120a and 120b and high-k insulated plug 114 is relevant.It should be noted that by n
+Or p
+Battery lead plate 120a that the bonding land constitutes and 120b can be increased the area of battery lead plate 120a and 120b by the energy that increases the admixture implantation.
Embodiment 2: transistor and the manufacture method thereof of utilizing the insulated plug formation of differing dielectric constant
The vertical-type nmos pass transistor
Please refer to Fig. 4 A and Fig. 4 B, it is the structural representation of the nmos pass transistor of vertical-type.
As shown in the figure, the transistor that utilizes the insulated plug formation of differing dielectric constant provided by the present invention is to integrate mutually with fleet plough groove isolation structure.At first, low dielectric constant insulation connector 412 and high-k insulated plug 414 are arranged in the substrate 400, wherein low dielectric constant insulation connector 412 defines an active region AA, high-k insulated plug 414 is arranged in active region AA, and active region AA is divided into a gate regions 408b and source 408a.High-k insulated plug 414 is as transistorized gate insulator at this.
Gate electrode 420 is located at the gate regions 408b of substrate 400, and wherein the degree of depth of the depth ratio gate electrode 420 of low dielectric constant insulation connector 412 and high-k insulated plug 414 is dark.
And the drain electrode 424 of first conductivity, the wellblock 428 of second conductivity and the common-source 426 of first conductivity stacked the source/drain regions 408a that is arranged at substrate 400, wherein a channel region 430 is positioned at the sidewall of the high-k insulated plug 414 of the second conductivity wellblock 428.
In addition, in above-mentioned transistor, the bonding land of gate electrode 420 for having first conductivity, and the doped region 422 that below gate electrode 420, has one second conductivity.
The first above-mentioned conductivity and second conductivity are to refer to n type and p type respectively.
Vertical-type PMOS transistor
Please refer to Fig. 5, be the transistorized structural representation of the PMOS of vertical-type.
As shown in the figure, the transistor that utilizes the insulated plug formation of differing dielectric constant provided by the present invention is to integrate mutually from structure with the shallow ridges block.At first, low dielectric constant insulation connector 512 and high-k insulated plug 514 are arranged in the substrate 500, wherein low dielectric constant insulation connector 512 defines an active region AA, high-k insulated plug 514 is arranged in active region AA, and active region AA is divided into a gate regions 508b and source 508a.High-k insulated plug 514 at this as transistorized gate insulator.
And the drain electrode 524 of first conductivity, the wellblock 528 of second conductivity and the common-source 526 of first conductivity stacked the source/drain regions 508a that is arranged at substrate 500, wherein a channel region 530 is positioned at the sidewall of the high-k insulated plug 514 of the second conductivity wellblock 528.
In addition, in above-mentioned transistor, the bonding land of gate electrode 520 for having first conductivity, and the doped region 522 that below gate electrode 520, has one second conductivity.
The first above-mentioned conductivity and second conductivity are to refer to p type and n type respectively.
Below will illustrate the transistorized manufacture method of vertical-type nmos pass transistor and PMOS.
The vertical-type nmos pass transistor
Below cooperate Fig. 4 A and Fig. 4 B to describe the manufacture method of vertical-type nmos pass transistor in detail.
Please refer to Fig. 4 A, at first, one substrate 400 is provided, it for example is the substrate of p type, then in substrate 400, form groove 402 and 404 simultaneously, wherein groove 402 defines active region (active area) AA, and groove 404 is arranged in active region AA, and active region AA is divided into gate regions 408b and source/drain regions 408a.Then, in groove 402, form low dielectric constant insulation connector 412, and in groove 404, form high-k insulated plug 414.Wherein, low dielectric constant insulation connector 412 is in order to doing the usefulness of electrical isolation, and high-k insulated plug 414 is in order to the usefulness of transistors couple to be provided, and high-k insulated plug 414 is as transistorized gate insulator at this.
Above-mentioned groove 402 is to utilize etching step to be formed at simultaneously in the substrate 400 with 404, formation as for low dielectric constant insulation connector 412 in groove 402 and 404 and high-k insulated plug 414, be successively to form, can form low dielectric constant insulation connector 412 earlier and form high-k insulated plug 414 again, perhaps form high-k insulated plug 414 earlier and form low dielectric constant insulation connector 412 again.
The material of above-mentioned low dielectric constant insulation connector 412 can be fluorine-containing chemical vapour deposition (CVD) oxide (D
k≈ 3-3.5), spin-coating low-k dielectric material (D
k≈ 2-3) or the material of other similar these character.
The material of above-mentioned high-k insulated plug 414 can be Al
2O
5, Ta
2O
5(D
k≈ 25), HfO
2(D
k≈ 30) or the material of other similar these character.
Then, in the substrate 400 that forms low dielectric constant insulation connector 412 and high-k insulated plug 414, form dark n well (deep n well) DNW.
Then please refer to Fig. 4 B, form gate electrode 420 at gate regions 408b, wherein the degree of depth of the depth ratio gate electrode 420 of low dielectric constant insulation connector 412 and high-k insulated plug 414 is dark.This gate electrode 420 is by n
+The bonding land constitutes.In addition, must below gate electrode 420, form a p type doped region 422, in order to gate electrode 420 and dark n well DNW are done electrical isolation.
Aspect source/drain regions 408a, form n
+Drain electrode 424 and p well 428, the common-source 426 of source electrode 426 below p well 428 for constituting by deep-well district DNW.Above-mentioned p well 428 is in order to isolating source electrode 426 and drain electrode 424, and source electrode 426 and the channel region 430 that drains between 424 are the sidewalls that are positioned at the high-k insulated plug 414 of p well 428.
When above-mentioned gate electrode 420, source electrode 426, drain electrode 424 and substrate 400 couple V respectively
G, V
S, V
DBehind voltages such as ground connection, this transistorized switch of may command then.
Above-mentioned nmos pass transistor can be applicable to any common-source circuit design of (common source is called for short CS), for example differentiating amplifier.
Vertical-type PMOS transistor
Similarly, the processing procedure of above-mentioned nmos pass transistor also can be used on the PMOS transistor that forms vertical-type.Below will cooperate Fig. 5 to summarize the transistorized manufacture method of vertical-type PMOS, the processing procedure similar to above-mentioned nmos pass transistor then omits.
In the p type substrate 500 that provides, form low dielectric constant insulation connector 512 and high-k insulated plug 514.Wherein, low dielectric constant insulation connector 512 is in order to do the usefulness of electrical isolation, so as to defining active region AA.In addition, high-k insulated plug 514 is arranged in active region AA, and active region AA is divided into gate regions 508b and source/drain regions 508a, and in order to the usefulness of transistors couple to be provided, is as transistorized gate insulator at this.
The material of above-mentioned low dielectric constant insulation connector 512 can be gassiness chemical vapour deposition (CVD) oxide (D
k≈ 3-3.5), spin-coating low-k dielectric material (D
k≈ 2-3) or the material of other similar these character.
The material of above-mentioned high-k insulated plug 514 can be Al
2O
5, Ta
2O
5(D
k≈ 25), HfO
2(D
k≈ 30) or the material of other similar these character.
Then, form gate electrode 520 in gate regions, and the degree of depth of low dielectric constant insulation connector 512 and high-k insulated plug 514 must be darker than the degree of depth of gate electrode 520.This gate electrode 520 is by p
+The bonding land constitutes.In addition, must form a n type doped region 522, in order to gate electrode 520 and p type substrate 500 are done electrical isolation in gate electrode 520 belows.
As for aspect the source/drain regions, form drain electrode 524 and n well 528, the common-source 526 of the source electrode 526 below n well 528 for being connected by p type substrate 500.Above-mentioned n well 528 is in order to isolating source electrode 526 and drain electrode 524, and source electrode 526 and the channel region 530 that drains between 524 are the sidewalls that are positioned at the high-k insulated plug 514 of n well 528.
Embodiment 3: transistor with strain and manufacture method thereof that the insulated plug that utilizes thermal coefficient of expansion to be different from substrate constitutes.
1. the transistor that has biaxial stretch-formed strain (tensile stress)
Please refer to Fig. 6 and Fig. 7, wherein Fig. 7 is the VII-VII profile of Fig. 6.At first, providing substrate 600, for example is monocrystal silicon substrate, and forms groove 602 in substrate 600, and this groove 602 defines active region AA.Then, thermal coefficient of expansion is inserted formation insulated plug 612 in the groove 602 than substrate 600 big insulation materials.Available insulation material can be zirconia (ZrO
2), steatite (MgOSiO
2), aluminium oxide (Al
2O
3), the material of carborundum (SiC), silicon nitride (SiN) or other similar these character, its character please refer to table one.
Then, form transistor T in active region AA.
Owing to the thermal coefficient of expansion of the material of inserting groove 602 is bigger than substrate 600, make after through high temperature deposition or hot tempering manufacturing process required in the manufacture of semiconductor, the contraction speed of insulated plug 612 when high temperature is lowered the temperature can be faster than silicon base 600, so lattice of insulated plug 612 meeting stretching active region AA, shown in the arrow among the figure, and cause the twin shaft of lattice to be out of shape.According to research, the lattice of the biaxial stretch-formed distortion of this kind, pair nmos transistor can promote the mobility (mobility) of n type admixture in channel region.
The thermal coefficient of expansion and the young's modulus of some insulation materials of table one
| Thermalexpansioncoefficient (K -1 ) | Young's modulus E (GPa) | |
| Zirconia (zirconium oxide) | 1.1×10 -5 | 200 |
| Steatite (steatite; MgOSiO 2) | 8.0×10 -6 | - |
| Aluminium oxide (aluminum oxide) | 7.7×10 -6 | 390 |
| Aluminium nitride (aluminum mitride) | 5.1×10 -6 | 380 |
| Carborundum (silicon carbide) | 4.3×10 -6 | 400 |
| Silicon nitride (silicon nitride) | 2.8×10 -6-3.6× 10 -6 | 306 |
| Silicon (silicon) | 2.0×10 -6 | 156 |
| Silica (silicon oxide) | 5.0×10 -7 | - |
2. the transistor that has biaxial compressive strain (compressive stress)
Please refer to Fig. 8, substrate 800 is provided, for example is monocrystal silicon substrate, and forms groove 802 in substrate, and this groove 802 defines active region AA.Then, thermal coefficient of expansion is inserted formation insulated plug 812 in the groove 802 than substrate 800 little insulation materials.Available insulation material can be the material of silica (SiO2) or other similar these character, and its character please refer to table one.
Then, form transistor at active region AA.
Owing to the thermal coefficient of expansion of the material of inserting groove 802 is littler than substrate 800, make after through high temperature deposition or hot tempering manufacturing process required in the manufacture of semiconductor, the contraction speed of insulated plug 812 when high temperature is lowered the temperature can be slower than silicon base 100, therefore insulated plug 812 can push the lattice of active region AA, shown in the arrow among the figure, and cause the twin shaft of lattice to be out of shape.According to research, the lattice of this kind twin shaft compression, pair pmos transistor can promote p type admixture in the mobility of channel region.
3. the transistor that has uniaxial strain
As shown in Figure 9, substrate 900 is provided, it for example is monocrystal silicon substrate, and in substrate 900, form first pair of groove 902 and second pair of groove 904, these grooves 902 and 904 define active region AA, wherein the first pair of groove 902 is positioned at the relative edge of active region AA, and second pair of groove 904 is positioned at another relative edge of active region AA.
Then, in first pair of groove 902, form an insulated plug 912 with first coefficient of expansion (for example the coefficient of expansion than silicon is big).And in second pair of groove 904, form an insulated plug 914 with second coefficient of expansion (for example the coefficient of expansion than silicon is little).Therefore, form insulated plug 912 available insulation materials and can be zirconia (ZrO
2), steatite (MgOSiO
2), aluminium oxide (Al
2O
3), the material of carborundum (SiC), silicon nitride (SiN) or other similar these character, form insulated plug 914 available insulation materials and can be silica (SiO
2) or the material of other similar these character.
Then, form transistor T in active region AA.
Owing to the thermal coefficient of expansion of the material of inserting groove 902 is bigger than substrate 900, make after through high temperature deposition or hot tempering manufacturing process required in the manufacture of semiconductor, the contraction speed of insulated plug 912 when high temperature is lowered the temperature can be faster than silicon base 900, so lattice of insulated plug 912 meeting stretching active region AA, shown in the arrow among the figure, and cause the x axle stretcher strain of lattice.Relatively, owing to the thermal coefficient of expansion of the material of inserting groove 904 is bigger than substrate 900, make after through high temperature deposition or hot tempering manufacturing process required in the manufacture of semiconductor, the contraction speed of insulated plug 914 when high temperature is lowered the temperature can be slower than silicon base 900, therefore insulated plug 914 can push the lattice of active region AA, shown in the arrow among the figure, and cause the y axial compression compression deformation of lattice.
Above-described various element is to combine with the processing procedure of fleet plough groove isolation structure, and all can with the CMOS process-compatible.Those skilled in the art, can be according to the needs on the circuit design, the capacitor that on same wafer, the above-mentioned insulated plug that utilizes differing dielectric constant is constituted, utilize the transistor of the insulated plug formation of differing dielectric constant, the transistor of the biaxial stretch-formed strain that the insulated plug that utilizes thermal coefficient of expansion to be different from substrate constitutes, the transistor of the biaxial compressive strain that the insulated plug that utilizes thermal coefficient of expansion to be different from substrate constitutes, and the transistor of the uniaxial strain that constitutes of the insulated plug that utilizes thermal coefficient of expansion to be different from substrate is done combination in any or collocation.
Therefore, the present invention can be easily in conjunction with the nmos pass transistor of passage and have the transistorized CMOS process technique of PMOS of the SiGe passage of biaxial compressive strain with biaxial stretch-formed strain, and reach drive current and the usefulness at a high speed that on same wafer, promotes PMOS transistor and nmos pass transistor simultaneously.This is beyond one's reach by conventional method.
Embodiment 4: shape is used the method for the insulated plug of unlike material in substrate
In the above embodiments 1,2 and 3, all need in groove, to insert the insulation material of unlike material, for example have the insulation material of differing dielectric constant or/and have the insulation material of different heat expansion coefficient, below will cooperate Figure 10 A to the 10G figure to describe the manufacture method that to integrate mutually with the CMOS processing procedure in detail.Be to be example in this embodiment, yet the present invention is not limited to insert two kinds of materials, can according to need following processing procedure be inserted instead the material more than three kinds or four kinds with the insulation material of inserting two kinds of differing dielectric constants.
At first please refer to Figure 10 A, one substrate 300 is provided, it for example is the semiconductor-based end, preferably silicon base, form one deck mask layer 302 on substrate 300 surfaces, and on this mask layer 302, cover one deck photoresist layer 308, and with the design transfer of this photoresist layer 308 to mask layer 302 and substrate 300, in substrate 300, to form groove 310a and 310b.Remove photoresist layer 308 afterwards.
Wherein above-mentioned mask layer 302 is preferably by pad oxide 304 and silicon nitride layer 306 and is constituted, and pad oxide 304 preferable thickness are about the 80-150 dust, and silicon nitride layer 306 preferable thickness are about 800～1500 dusts.Wherein the degree of depth in substrate 300 formed groove 310a and 310b is about the 0.3-0.5 micron.
Then please refer to Figure 10 B, substrate in groove 310a and 310b 300 surfaces form one deck linings 312, and its material for example is the oxide layer of the about 100-200 dust of thickness.
Then in the substrate 300 that forms lining 312, deposit first dielectric layer 314 that one deck has first dielectric constant, this first dielectric constant for example is a low relative dielectric constant, the material of first dielectric layer 314 of this low-k for example is the material of silica (dielectric constant is about 3.9, and deposition process for example is CVD, SACVD, HDP-CVD etc.), fluorine-containing CVD silica (dielectric constant is about 3.0-3.5), spin-coating low dielectric material (dielectric constant is about 2-3) or other similar these character.After having deposited first dielectric layer 314 of above-mentioned low-k, carry out tempering manufacturing process, so that first dielectric layer, 314 densifications of the low-k of deposition.
Then please refer to Figure 10 C, carry out the cmp processing procedure, and with mask layer 302 as stop layer, in groove 310a and 310b, to form first fleet plough groove isolation structure 314a and the 314b.
Then please refer to Figure 10 D, on the first fleet plough groove isolation structure 314a and 314b and mask layer 302, form one deck patterned light blockage layer 316, carry out micro image etching procedure, to remove the partly first fleet plough groove isolation structure 314b in zone, and exposing the surface of this regional groove 310b, remaining first fleet plough groove isolation structure is denoted as 314a.Then remove photoresist layer 316.
Then please refer to Figure 10 E, after removing photoresist layer 316, form one deck lining 322 in the groove 310b that exposes surface, its material for example is the oxide layer of the about 40-80 dust of thickness.
Then deposit second dielectric layer 324 that one deck has second dielectric constant in the substrate 300 that forms lining 322, this second dielectric constant for example is relative high-k, and the material of second dielectric layer 324 of this high-k for example is Al
2O
5, Ta
2O
5(dielectric constant is about 25), HfO
2The material of (dielectric constant is about 30) or other similar these character.After having deposited second dielectric layer 324 of above-mentioned high-k, carry out tempering manufacturing process, so that second dielectric layer, 324 densifications of the high-k of deposition.
Then please refer to Figure 10 F, carry out the cmp processing procedure, and with mask layer 302 as stop layer, in groove 310b, to form the second fleet plough groove isolation structure 324a.
Then please refer to Figure 10 G, remove mask layer 302.Afterwards and carry out follow-up processing procedure.
According to the foregoing description 4, its processing procedure can be summarized as:
(1) mask layer of formation patterning in substrate;
(2) with the design transfer of the mask layer of patterning to substrate, in substrate, to form groove;
(3) in groove, form first insulated plug;
(4) remove first part, first insulated plug; And
(5) in groove, form first insulated plug that second insulated plug replaces first part that removes,
If must insert insulation material more than two kinds, then heavily be covered with as required and state step (4) and (5) get final product.Meaning even must be inserted the third insulation material, then increases following step (6) and (7):
(6) remove second part, first insulated plug; And
(7) in groove, form first insulated plug that the 3rd insulated plug replaces second part that removes.
Though the present invention discloses as above with preferred embodiment, be not in order to restriction the present invention, those skilled in the art, without departing from the spirit and scope of the present invention, the equivalent structure transformation of making all is included in the claim of the present invention.
Claims (19)
1. a connector formation of utilizing thermal coefficient of expansion to be different from substrate has the transistorized manufacture method of biaxial strain, it is characterized in that, comprising:
One substrate is provided;
In this substrate, form a groove so as to defining an active region;
In this groove, form the connector that a thermal coefficient of expansion is different from this substrate; And
Form a transistor at this active region.
2. the connector formation of utilizing thermal coefficient of expansion to be different from substrate as claimed in claim 1 has the transistorized manufacture method of biaxial strain, it is characterized in that, described substrate is a silicon base, and the coefficient of expansion of this connector is bigger than silicon, and this transistor is a nmos pass transistor.
3. the connector formation of utilizing thermal coefficient of expansion to be different from substrate as claimed in claim 1 has the transistorized manufacture method of biaxial strain, it is characterized in that the material of described this connector of formation is to be selected from by zirconia (ZrO
2), steatite (MgOSiO
2), aluminium oxide (Al
2O
3), in the group that formed of carborundum (SiC) and silicon nitride (SiN).
4. the connector formation of utilizing thermal coefficient of expansion to be different from substrate as claimed in claim 1 has the transistorized manufacture method of biaxial strain, it is characterized in that, described substrate is a silicon base, and the coefficient of expansion of this connector is littler than silicon, and this transistor is the PMOS transistor.
5. the connector formation of utilizing thermal coefficient of expansion to be different from substrate as claimed in claim 4 has the transistorized manufacture method of biaxial strain, it is characterized in that the material of described this connector of formation is silica (SiO
2).
6. a connector formation of utilizing thermal coefficient of expansion to be different from substrate has the transistorized manufacture method of uniaxial strain, it is characterized in that, comprising:
One substrate is provided;
Form a pair of first groove and a pair of second groove in this substrate, wherein should and should define an active region to second groove to first groove, this is positioned at the relative edge of this active region to first groove, and this is positioned at another relative edge of this active region to second groove;
Form a pair of first connector at this in to first groove with first coefficient of expansion;
Form a pair of second connector at this in to second groove with second coefficient of expansion; And
Form a transistor at this active region.
7. the connector formation of utilizing thermal coefficient of expansion to be different from substrate as claimed in claim 6 has the transistorized manufacture method of uniaxial strain, it is characterized in that described substrate is a silicon base, and first thermal coefficient of expansion is bigger than silicon, and second thermal coefficient of expansion is littler than silicon.
8. the connector formation of utilizing thermal coefficient of expansion to be different from substrate as claimed in claim 7 has the transistorized manufacture method of uniaxial strain, it is characterized in that this material to first connector of described formation is to be selected from by zirconia (ZrO
2), steatite (MgOSiO
2), aluminium oxide (Al
2O
3), in the group that formed of carborundum (SiC) and silicon nitride (SiN), forming this material to second connector is silica (SiO
2).
9. a transistor that utilizes the biaxial strain that connector that thermal coefficient of expansion is different from substrate constitutes is characterized in that, comprising:
One substrate;
Two thermal coefficient of expansions are different from the connector of this substrate, are located in this substrate, and wherein this connector is so as to defining an active region; And
One transistor is located at this active region of this substrate.
10. the transistor of the biaxial strain that the connector that utilizes thermal coefficient of expansion to be different from substrate as claimed in claim 9 constitutes, it is characterized in that, the thermal coefficient of expansion of this connector in being located at this substrate is during greater than this substrate, and this transistor is the transistor of biaxial stretch-formed strain.
11. the transistor that utilizes the biaxial strain that connector that thermal coefficient of expansion is different from substrate constitutes as claimed in claim 9 is characterized in that, the thermal coefficient of expansion of this connector in being located at this substrate is during greater than this substrate, and this transistor is a nmos pass transistor.
12. the transistor of the biaxial strain that the connector that utilizes thermal coefficient of expansion to be different from substrate as claimed in claim 9 constitutes, it is characterized in that, described substrate is a silicon base, and the thermal coefficient of expansion of being located at this connector in this substrate is greater than this substrate, and the material of this connector is to be selected from by lead oxide (ZrO
2), steatite (MgOSiO
2), aluminium oxide (Al
2O
3), in the group that formed of carborundum (SiC) and silicon nitride (SiN).
13. the transistor of the biaxial strain that the connector that utilizes thermal coefficient of expansion to be different from substrate as claimed in claim 9 constitutes, it is characterized in that, the thermal coefficient of expansion of this connector in being located at this substrate is during less than this substrate, and this transistor is the transistor of biaxial compressive strain.
14. the transistor that utilizes the biaxial strain that connector that thermal coefficient of expansion is different from substrate constitutes as claimed in claim 9 is characterized in that, the thermal coefficient of expansion of this connector in being located at this substrate is during less than this substrate, and this transistor is the PMOS transistor.
15. the transistor of the biaxial strain that the connector that utilizes thermal coefficient of expansion to be different from substrate as claimed in claim 9 constitutes is characterized in that described substrate is a silicon base, the coefficient of expansion of this connector is littler than silicon, and this transistor is the PMOS transistor.
16. the transistor of the biaxial strain that the connector that utilizes thermal coefficient of expansion to be different from substrate as claimed in claim 9 constitutes, it is characterized in that, described substrate is a silicon base, and the thermal coefficient of expansion of being located at this connector in this substrate is less than this substrate, and the material of this connector is silica (SiO
2).
17. a transistor that utilizes the uniaxial strain that connector that thermal coefficient of expansion is different from substrate constitutes is characterized in that, comprising:
One substrate;
A pair of first connector and a pair of second connector with second coefficient of expansion with first coefficient of expansion, be located in this substrate, wherein should define an active region with being somebody's turn to do to second connector to first connector with first coefficient of expansion with second coefficient of expansion, should be positioned at the relative edge of this active region and be somebody's turn to do another relative edge that be positioned at this active region to second connector first connector with first coefficient of expansion with second coefficient of expansion; And
One transistor is located at this active region.
18. the transistor of the uniaxial strain that the connector that utilizes thermal coefficient of expansion to be different from substrate as claimed in claim 17 constitutes is characterized in that described first thermal coefficient of expansion is bigger than silicon, second thermal coefficient of expansion is littler than silicon.
19. the transistor of the uniaxial strain that the connector that utilizes thermal coefficient of expansion to be different from substrate as claimed in claim 18 constitutes is characterized in that this material to first connector is to be selected from by cobalt oxide (ZrO
2), steatite (MgOSiO
2), aluminium oxide (Al
2O
3), in the group that formed of carborundum (SiC) and silicon nitride (SiN), this material to second connector is silica (SiO
2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101271976A CN100419975C (en) | 2002-10-22 | 2002-10-22 | A kind of transistor and preparing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101271976A CN100419975C (en) | 2002-10-22 | 2002-10-22 | A kind of transistor and preparing method |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02147129 Division CN1263111C (en) | 2002-10-22 | 2002-10-22 | A capacitor and a transistor and the producing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1797725A true CN1797725A (en) | 2006-07-05 |
| CN100419975C CN100419975C (en) | 2008-09-17 |
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ID=36818650
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2005101271976A Expired - Lifetime CN100419975C (en) | 2002-10-22 | 2002-10-22 | A kind of transistor and preparing method |
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|---|---|
| CN (1) | CN100419975C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101937848B (en) * | 2009-07-03 | 2012-06-06 | 中芯国际集成电路制造(上海)有限公司 | MOS (Metal-oxide Semiconductor) transistor and making method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS535971A (en) * | 1976-07-06 | 1978-01-19 | Mitsubishi Electric Corp | Semiconductor device |
| JP2000277715A (en) * | 1999-03-25 | 2000-10-06 | Matsushita Electric Ind Co Ltd | Semiconductor substrate, its manufacture and semiconductor device |
| US6391732B1 (en) * | 2000-06-16 | 2002-05-21 | Chartered Semiconductor Manufacturing Ltd. | Method to form self-aligned, L-shaped sidewall spacers |
| KR100378190B1 (en) * | 2000-12-28 | 2003-03-29 | 삼성전자주식회사 | Method for fabricating trench isolation having sidewall oxide layers with a different thickness |
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2002
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101937848B (en) * | 2009-07-03 | 2012-06-06 | 中芯国际集成电路制造(上海)有限公司 | MOS (Metal-oxide Semiconductor) transistor and making method thereof |
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| CN100419975C (en) | 2008-09-17 |
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