CN1797708A - Method for fabricating inner connecting lines in insulating layer of wafer, and structure - Google Patents
Method for fabricating inner connecting lines in insulating layer of wafer, and structure Download PDFInfo
- Publication number
- CN1797708A CN1797708A CN 200410011590 CN200410011590A CN1797708A CN 1797708 A CN1797708 A CN 1797708A CN 200410011590 CN200410011590 CN 200410011590 CN 200410011590 A CN200410011590 A CN 200410011590A CN 1797708 A CN1797708 A CN 1797708A
- Authority
- CN
- China
- Prior art keywords
- insulating barrier
- wafer
- intraconnections
- mask
- indicia patterns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The method includes steps: first, a wafer is provided, multiple strips of connecting wire are formed on the wafer already, and an insulating layer is covered on the connecting wires; next, forming two holes on the insulating layer to expose two strips of connecting wire; then, filling first conductive layer in the holes in order to form two patterns of marker, and forming mask on wafer for conformal covering the insulating layer and the two patterns of marker; afterwards, removing mask at least on and between the two patterns of marker to form channel in order to expose the two patterns of marker and the insulating layer; forming second conductive layer on mask to cover the exposed two patterns of marker and the insulating layer; finally, removing the mask and divesting out the second conductive layer on the mask.
Description
Technical field
The present invention relates to a kind of semiconductor technology, relate in particular to a kind of manufacture method and structure of wafer insulating barrier intraconnections.
Background technology
The high-tech industry that integrated circuit (integrated circuit) industry is made up of integrated circuit (IC) design, wafer manufacturing, wafer sort and wafer package four big trunk systems basically.General integrated circuit all must be through a series of test after manufacturing is finished, the quality of the wafer of being produced to guarantee, even can pass through the technology of the result of these tests with the correction integrated circuit.And, after the wafer manufacturing is finished, all can carry out many wafer sorts usually.If find that flaw appears in circuit on the wafer or when undesirable through test; usually can carry out one and repair (repair) action to form a repairing circuit (repair circuit); and such operating mode can be omitted recast mask and otherwise cost, and can promote the yield of wafer widely.
In 1988, a kind of focused ion beam (focus ion beam that is called as is used in the researcher Li Wen Gourde(G) (Richard Liven-good) of Ying Daier company, FIB) device, with on one 486 microprocessor wafer " deposition " circuit of one section omission, but and this wafer normal operation of back after tested, therefore opened the technology of utilizing the focus plasma beam mending circuit.With the circuit of repairing on the wafer flaw or undesirable part appear with this kind technology now, yet, use the focused ion beam technology repairing circuit to still have some shortcomings, because the device of focused ion beam is quite expensive machine, so utilize focused ion beam technology to repair on the wafer, can make and to expend higher cost on the technology at a distance of the circuit of longer distance.In addition, the action that utilizes focused ion beam technology to carry out circuit mending is a time-consuming step, and is same, if when repairing the circuit at a distance of longer distance, needs especially to expend that many times just are accomplished.
Summary of the invention
In view of this, the purpose of this invention is to provide a kind of manufacture method of wafer insulating barrier intraconnections, can repair the circuit on the wafer, and can solve the consuming time and expensive problem of existing line repairing technique.
Another object of the present invention provides a kind of structure of wafer insulating barrier intraconnections, can avoid on the wafer influencing when flaw or undesirable circuit occurring the problem of the yield of wafer.
The present invention proposes a kind of manufacture method of wafer insulating barrier intraconnections, and the method is that a wafer is provided earlier, has been formed with many leads on the wafer, and is coated with insulating barrier on the lead.Then, in insulating barrier, form two holes, to expose wherein two leads respectively.Then, in hole, insert first conductive layer, forming two indicia patterns, and on wafer, form mask, conformal insulating barrier and the two above-mentioned indicia patterns of covering.Afterwards, remove on two indicia patterns at least and the mask between two indicia patterns to form irrigation canals and ditches, to expose two indicia patterns and insulating barrier.Then, on mask, form second conductive layer, cover two indicia patterns and the insulating barrier that are exposed out.Afterwards, remove mask, and divest second conductive layer of mask top simultaneously.
According to the preferred embodiments of the present invention, the material of above-mentioned mask comprises silica.In addition, the method for formation silicon oxide mask comprises method of spin coating on wafer.In addition, the material of above-mentioned mask also comprises titanium dioxide, acetic acid resin or silica gel.
According to the preferred embodiments of the present invention, above-mentionedly remove on two indicia patterns at least and the mask between two indicia patterns comprises prior to cutting out a zone on the mask with the step that forms irrigation canals and ditches, divest the mask in the zone again.In addition, be set forth in the method that cuts out the zone on the mask on and comprise focused ion beam technology or laser technology.
According to the preferred embodiments of the present invention, the material of above-mentioned first conductive layer comprises tungsten, platinum, gold, copper, aluminium or its combination.
According to the preferred embodiments of the present invention, on be set forth in the insulating barrier method that forms hole and comprise focused ion beam technology or laser technology.
According to the preferred embodiments of the present invention, on be set forth in the method for inserting first conductive layer in the hole and comprise the use focused ion beam.
According to the preferred embodiments of the present invention, the material of above-mentioned second conductive layer comprises tungsten, platinum, gold, copper, aluminium or its combination.
According to the preferred embodiments of the present invention, the formation method of above-mentioned second conductive layer comprises utilizes a sputter (Sputter) method or galvanoplastic.
According to the preferred embodiments of the present invention, above-mentioned insulating barrier is a protective layer.
According to the preferred embodiments of the present invention, the material of above-mentioned insulating barrier comprises silicon nitride or silica.
The present invention proposes a kind of structure of wafer insulating barrier intraconnections again, and this structure is made up of wafer, insulating barrier, two indicia patterns and conductor layer.Wherein have many leads on the wafer.In addition, above-mentioned insulating barrier is disposed at wafer surface and covers above-mentioned lead, wherein is formed with two holes in the insulating barrier, to expose wherein two leads.Wherein, two indicia patterns are disposed in the hole and with two leads and electrically contact, and the upper surface of two indicia patterns is higher than the upper surface of insulating barrier.Wherein, above-mentioned conductor layer covers on the surface of two indicia patterns and on the insulating barrier between two indicia patterns at least, so that two leads electrically connect.
From the above, the manufacture method of wafer insulating barrier intraconnections of the present invention is not to use focused ion beam to form internal connection-wire structure in the insulating barrier.Therefore utilize method of the present invention to carry out the repairing of circuit, particularly for the repairing of long distance line, more existing focused ion beam technology can significantly be saved time and cost.In addition, utilize method of the present invention, can significantly save time, therefore can improve the production capacity (throughput) of wafer, and higher success rate is arranged for the repairing of circuit to carry out the circuit mending on the wafer.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 be have on the wafer two leads to be repaired on look schematic diagram;
Fig. 2 A to Fig. 2 F is the flow process top view of manufacture method of the wafer insulating barrier intraconnections of the preferred embodiment of the present invention;
Fig. 3 A to Fig. 3 F is the profile that illustrates respectively among Fig. 2 A to Fig. 2 F along I-I ' line.
Embodiment
Generally repairing the technology of being carried out in the enterprising line of wafer road is that focused ion beam (grow and cost is higher but focused ion beam technology is used for for focus ionbeam, FIB) technology by the required time of repairing circuit.Particularly, as shown in Figure 1, when in the time of need repairing action, existing focused ion beam technology can expend the considerable time and cost can be too high at a distance of the circuit of longer distance (as the distance 106 of lead 102 and lead 104 at a distance of surpassing hundreds of microns (μ m) approximately) on the wafer 100.
Fig. 2 A to Fig. 2 F is the flow process top view of manufacture method of the wafer insulating barrier intraconnections of the preferred embodiment of the present invention.Fig. 3 A to Fig. 3 F is for illustrating among Fig. 2 A to Fig. 2 F the profile along I-I ' line respectively.
At first, please provide a wafer 300 earlier, be formed with several wires 302 on the wafer 300, and be coated with insulating barrier 304 on the several wires 302 simultaneously with reference to Fig. 2 A and Fig. 3 A.Wherein, the material of insulating barrier 304 for example is silicon nitride or silica, and the formation method for example is chemical vapor deposition method (CVD).In one embodiment, it is the protective layer of wafer that this insulating barrier 304 also can be used as, and it can protect the substrate 300 and the several wires 302 of below, avoids causing damage because of exogenous impurity and mechanical injury.
Then, please in insulating barrier 304, form two hole 306a and 306b, to expose two lead 302a and 302b respectively simultaneously with reference to Fig. 2 B and Fig. 3 B.Wherein, the method for formation two hole 306a and 306b for example is focused ion beam technology or laser technology in insulating barrier 304.
Afterwards, please in hole 306a and hole 306b, insert a conductive layer, to form two indicia patterns 308a and 308b simultaneously with reference to Fig. 2 C and Fig. 3 C.Then, on wafer 300, form mask 310, conformal insulating barrier 304 and two indicia patterns 308a and the 308b of covering.Wherein, the material of above-mentioned conductive layer (being indicia patterns 308a and 308b) for example is tungsten, platinum, gold, copper, aluminium or its combination, and the method that forms conductive layer for example is to use focused ion beam technology.In one embodiment, the material of mask 310 for example is a silica, and its formation method for example is a method of spin coating.In another embodiment, the material of mask 310 for example is titanium dioxide, acetic acid resin or silica gel, and its formation method for example is directly titanium dioxide, acetic acid resin or pellosil to be positioned on the wafer 300 to cover insulating barrier 304 and indicia patterns 308a, 308b get final product.
Then, please be simultaneously with reference to Fig. 2 D and Fig. 3 D, at least remove that two indicia patterns 308a and 308b go up and two indicia patterns 30ga and 308b between mask 310 to form irrigation canals and ditches 312, it exposes two indicia patterns 308a and 308b and the insulating barrier 304 between two indicia patterns 308a and 308b.Wherein, the step of above-mentioned formation irrigation canals and ditches 312 for example is prior to cutting out a zone 314 on the mask 310, and this zone 314 comprises the zone at two indicia patterns 308a and 308b place and the zone between two indicia patterns 308a and the 308b at least, and then divests the mask 310 in the zone 314.In one embodiment, on mask 310, cut out zone 314 method and for example be to use focused ion beam technology or laser technology.In another embodiment, if the material of mask 310 is titanium dioxide, acetic acid resin or silica gel, be the action that can utilize cutter on mask 310, to cut then in the method that cuts out zone 314 on the mask 310.
Afterwards, please on mask 310, form conductive layer 316, cover the two indicia patterns 308a and 308b and the insulating barrier 304 that are exposed out simultaneously with reference to Fig. 2 E and Fig. 3 E.Wherein, the material of conductive layer 316 for example is tungsten, platinum, gold, copper, aluminium or its combination, and the formation method for example is to utilize sputter (sputter) method or galvanoplastic.
Afterwards, please remove mask 310, and divest the conductive layer 316 of mask 310 tops simultaneously simultaneously with reference to Fig. 2 F and Fig. 3 F.Thus, lead 302a and 302b promptly can see through the conductive layer 316 stay and indicia patterns 308a and 308b and electrically connect, to finish the technology of wafer insulating barrier intraconnections.
It should be noted that the present invention can be applied to the repairing of circuit on the wafer especially.Wherein, utilizing the present invention is that circuit to be repaired is considered as lead 302a and 302b among Fig. 2 B and Fig. 3 B with the method for repairing the circuit on the wafer, and then carry out the technology of wafer insulating barrier intraconnections of the present invention, form internal connection-wire structure (for example being indicia patterns 308a and 308b) and conductor layer 316, circuit to be repaired can be electrically connected, and reach the purpose of circuit mending.
More than be the manufacture method of explanation wafer insulating barrier intraconnections of the present invention, the structure of wafer insulating barrier intraconnections of the present invention then is described.
Please refer to Fig. 3 F, the structure after wafer of the present invention is repaired is made up of with 308b and conductor layer 316 wafer 300, insulating barrier 304, two indicia patterns 308a.Wherein has several wires 302 on the wafer 300.In addition, above-mentioned insulating barrier 304 is disposed at wafer 300 surfaces and covers above-mentioned several wires 302, wherein is formed with two hole 306a and 306b in the insulating barrier 304, to expose wherein two lead 302a and 302b.Two indicia patterns 308a and 308b are disposed in two hole 306a and the 306b and with two lead 302a and electrically contact with 302b, and the upper surface of two indicia patterns 308a and 308b is the upper surface that is higher than insulating barrier 304.Wherein, above-mentioned conductor layer 316 covers on the surface of two indicia patterns 308a and 308b and on the insulating barrier 304 between two indicia patterns 308a and the 308b at least, so that two lead 302a and 302b electrically connect.
From the above, the present invention forms two indicia patterns 308a and 308b respectively on two lead 302a and 302b, and it is electrically to contact with 302b with two lead 302a.Two lead 302a and 302b go up in two indicia patterns 308a and 308b more afterwards and form conductive layer 316, so that can electrically connect by conductive layer 316 and two indicia patterns 308a and 308b.If two lead 302a and 302b are replaced to circuit to be repaired, then the present invention also can be applicable to the repairing of circuit on the wafer, so that circuit to be repaired can reach the purpose of electric connection.
In brief, the manufacture method of wafer insulating barrier intraconnections of the present invention also can be applicable to repairing circuit, and the present invention uses focused ion beam to form internal connection-wire structure (being indicia patterns 308a and 308b) in the insulating barrier, so the present invention can solve the existing mode of focused ion beam of using and comes repairing circuit to have shortcoming expensive and consuming time.In addition, the manufacture method of wafer insulating barrier intraconnections of the present invention also can improve the production capacity of wafer and for the repairing of circuit higher success rate be arranged.Particularly, the present invention is applied to repair when the circuit that surpasses between hundreds of microns two leads, except the purpose that can reach repairing circuit, in saving time and there is bigger effect the cost aspect than prior art.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; under the premise without departing from the spirit and scope of the present invention; can do various modifications and variation, so protection scope of the present invention is as the criterion when looking the claims person of defining.
Claims (18)
1. the manufacture method of a wafer insulating barrier intraconnections comprises:
One wafer is provided, has been formed with many leads on this wafer, and be coated with an insulating barrier on those leads;
In this insulating barrier, form two holes, to expose wherein two leads of those leads respectively;
In those holes, insert one first conductive layer, to form two indicia patterns;
On this wafer, form a mask, conformal this insulating barrier and those indicia patterns of covering;
At least remove this mask on those indicia patterns and between those indicia patterns to form irrigation canals and ditches, expose those indicia patterns and this insulating barrier;
On this mask, form one second conductive layer, cover those indicia patterns and this insulating barrier that are exposed out; And
Remove this mask, and divest this second conductive layer of this mask top simultaneously.
2. the manufacture method of wafer insulating barrier intraconnections as claimed in claim 1, wherein the material of this mask comprises silica.
3. the manufacture method of wafer insulating barrier intraconnections as claimed in claim 2, the method that wherein forms this silicon oxide mask on this wafer comprises method of spin coating.
4. the manufacture method of wafer insulating barrier intraconnections as claimed in claim 1, wherein the material of this mask comprises titanium dioxide, acetic acid resin or silica gel.
5. the manufacture method of wafer insulating barrier intraconnections as claimed in claim 1, this mask that wherein removes at least on those indicia patterns and between those indicia patterns comprises with the step that forms these irrigation canals and ditches:
On this mask, cut out a zone; And
Divest this mask in this zone.
6. the manufacture method of wafer insulating barrier intraconnections as claimed in claim 5 wherein cuts out this regional method and comprises focused ion beam technology or laser technology on this mask.
7. the manufacture method of wafer insulating barrier intraconnections as claimed in claim 1, wherein the material of this first conductive layer comprises tungsten, platinum, gold, copper, aluminium or its combination.
8. the manufacture method of wafer insulating barrier intraconnections as claimed in claim 1, the method that wherein forms those holes in this insulating barrier comprises focused ion beam technology or laser technology.
9. the manufacture method of wafer insulating barrier intraconnections as claimed in claim 1, the method for wherein inserting this first conductive layer in those holes comprises the use focused ion beam.
10. the manufacture method of wafer insulating barrier intraconnections as claimed in claim 1, wherein the material of this second conductive layer comprises tungsten, platinum, gold, copper, aluminium or its combination.
11. the manufacture method of wafer insulating barrier intraconnections as claimed in claim 1, wherein the formation method of this second conductive layer comprises and utilizes a sputtering method or galvanoplastic.
12. the manufacture method of wafer insulating barrier intraconnections as claimed in claim 1, wherein this insulating barrier is a protective layer.
13. the manufacture method of wafer insulating barrier intraconnections as claimed in claim 1, wherein the material of this insulating barrier comprises silicon nitride or silica.
14. the structure of a wafer insulating barrier intraconnections comprises:
One wafer has many leads on this wafer;
One insulating barrier is disposed at this wafer surface and covers those leads, wherein is formed with two holes in this insulating barrier, exposes wherein two leads of those leads;
Two indicia patterns are disposed in those holes and electrically contact with this two lead, and the upper surface of those indicia patterns is higher than the upper surface of this insulating barrier; And
One conductor layer covers on the surface of those indicia patterns and on this insulating barrier between those indicia patterns at least, so that this two lead electrically connects.
15. the structure of wafer insulating barrier intraconnections as claimed in claim 14, wherein the material of those indicia patterns comprises tungsten, platinum, gold, copper, aluminium or its combination.
16. the structure of wafer insulating barrier intraconnections as claimed in claim 14, wherein the material of this conductive layer comprises tungsten, platinum, gold, copper, aluminium or its combination.
17. the structure of wafer insulating barrier intraconnections as claimed in claim 14, wherein this insulating barrier is a protective layer.
18. the structure of wafer insulating barrier intraconnections as claimed in claim 14, wherein the material of this insulating barrier comprises silicon nitride or silica.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100115904A CN100392809C (en) | 2004-12-21 | 2004-12-21 | Method for fabricating inner connecting lines in insulating layer of wafer, and structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100115904A CN100392809C (en) | 2004-12-21 | 2004-12-21 | Method for fabricating inner connecting lines in insulating layer of wafer, and structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1797708A true CN1797708A (en) | 2006-07-05 |
| CN100392809C CN100392809C (en) | 2008-06-04 |
Family
ID=36818639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100115904A Expired - Fee Related CN100392809C (en) | 2004-12-21 | 2004-12-21 | Method for fabricating inner connecting lines in insulating layer of wafer, and structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100392809C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104280967A (en) * | 2014-10-31 | 2015-01-14 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate, display panel and display device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950003244B1 (en) * | 1986-12-17 | 1995-04-06 | 더 폭스보로 컴패니 | Multilayer circuit board fabrication process |
| US6303423B1 (en) * | 1998-12-21 | 2001-10-16 | Megic Corporation | Method for forming high performance system-on-chip using post passivation process |
| US6417094B1 (en) * | 1998-12-31 | 2002-07-09 | Newport Fab, Llc | Dual-damascene interconnect structures and methods of fabricating same |
-
2004
- 2004-12-21 CN CNB2004100115904A patent/CN100392809C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104280967A (en) * | 2014-10-31 | 2015-01-14 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate, display panel and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100392809C (en) | 2008-06-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1206726C (en) | Semiconductor device and method of mfg. the same | |
| CN1210798C (en) | Semiconductor device and making method | |
| CN2726108Y (en) | Multi-layer semiconductor wafer structure | |
| EP0075926B1 (en) | Semiconductor integrated circuit device | |
| US7638411B2 (en) | Semiconductor wafer, semiconductor chip and dicing method of a semiconductor wafer | |
| EP0678904A1 (en) | Multicut wafer saw process | |
| CN1110842C (en) | Semiconductor IC device having discontinuous insulating regions and manufacturing method thereof | |
| CN1095197C (en) | Semiconductor wafer, semiconductor device and manufacturing method of semiconductor device | |
| EP2223336B1 (en) | Led chip with discharge protection | |
| EP0107515B1 (en) | Methods of making josephson junction devices | |
| KR20090034788A (en) | Integrated circuit package system including die having relieved active region | |
| US7211500B2 (en) | Pre-process before cutting a wafer and method of cutting a wafer | |
| CN1282242C (en) | Chip ratio package and manufacturing method thereof | |
| CN1797708A (en) | Method for fabricating inner connecting lines in insulating layer of wafer, and structure | |
| CN101034683A (en) | Method for forming integrated circuit and structure | |
| TW201003878A (en) | Fuse part of semiconductor device and method of fabricating the same | |
| CN1574320A (en) | Semiconductor package device and method for fabricating the same | |
| CN1866509A (en) | Semiconductor device | |
| US7888770B2 (en) | Fuse box for semiconductor device and method of forming same | |
| CN1212663C (en) | Metal washer structure on semiconductor substrate | |
| US7253093B2 (en) | Method for fabricating interconnection in an insulating layer on a wafer | |
| CN1494134A (en) | Semiconductor device | |
| CN1314113C (en) | Leadframe for preventing pin from short circuit and method for making semiconductor package having same | |
| KR100850585B1 (en) | Method for fabricating liquid crystal display device | |
| KR100390045B1 (en) | Method for forming the pad in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080604 Termination date: 20111221 |