CN1794330A - Current driver, data driver, and display device - Google Patents

Current driver, data driver, and display device Download PDF

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Publication number
CN1794330A
CN1794330A CN200510134789.0A CN200510134789A CN1794330A CN 1794330 A CN1794330 A CN 1794330A CN 200510134789 A CN200510134789 A CN 200510134789A CN 1794330 A CN1794330 A CN 1794330A
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China
Prior art keywords
voltage
transistor
current
grid
cascode amplifier
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CN200510134789.0A
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CN100495504C (en
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大森哲郎
小嶋宽
水木诚
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Craib Innovations Ltd
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松下电器产业株式会社
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3283—Details of drivers for data electrodes in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/34—Dc amplifiers in which all stages are dc-coupled
    • H03F3/343—Dc amplifiers in which all stages are dc-coupled with semiconductor devices only
    • H03F3/345—Dc amplifiers in which all stages are dc-coupled with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Abstract

In a current driver, a gate of a first generating transistor, gates of K driving transistors, and a gate of a second generating transistor are connected to a gate line in this order. A first differential amplifier outputs a voltage determined according to the difference between a voltage from a first supply node and a voltage at the drain of the first generating transistor. A second differential amplifier outputs a voltage determined according to the difference between a voltage from a second supply node and a voltage at the drain of the second generating transistor. The gate of the first generating transistor receives the output of the first differential amplifier. The gate of the second generating transistor receives the output of the second differential amplifier.

Description

Current driver, data driver and display device
The cross reference of related application
The application requires the right of priority of the Japanese patent application No.2004-368740 that submitted on Dec 21st, 2004, at this its full content is incorporated herein by reference.
Technical field
The present invention relates to current driver, specifically, relate to current driver as the display driver of organic EL (electroluminescence) panel etc.
Background technology
The structure of＜conventional current driver 〉
Figure 11 shows the general structure of conventional current driver 20.Conventional current driver 20 relates to reference current Iref, as the input from outside (for example, from current source).Conventional current driver 20 comprises reference transistor T201L is set, supply reference transistor T201RA and T201RB, be used for the cascode amplifier and connect transistor T 202L, the T202RA of (cascode connection) and T202RB (hereinafter, " the cascode amplifier connects transistor "), bias voltage produces transistor T 204A and T204B, and K driving transistors T205-1 is to T205-K (K is a natural number).
Reference transistor T201L is set is connected power supply node and cascode amplifier and connects between the transistor T 202L, and grid and drain electrode that reference transistor T201L is set are connected to each other.Cascode amplifier connection transistor T 202L is connected and is provided with between reference transistor T201L and the input/output terminal N201, and grid and the drain electrode of cascode amplifier connection transistor T 202L are connected to each other.
Supply reference transistor T201RA is connected power supply node and the cascode amplifier connects between the transistor T 202RA, and the grid of supply reference transistor T201RA is connected on the grid that reference transistor T201L is set.The cascode amplifier connects transistor T 202RA and is connected between supply reference transistor T201RA and the bias voltage generation transistor T 204A, and the grid of cascode amplifier connection transistor T 202RA is connected on the grid of cascode amplifier connection transistor T 202L.Bias voltage produces transistor T 204A and is connected between cascode amplifier connection transistor T 202RA and the ground node, and grid and the drain electrode of bias voltage generation transistor T 204A are connected to each other.
Supply reference transistor T201RB is connected power supply node and the cascode amplifier connects between the transistor T 202RB, and the grid of supply reference transistor T201RB is connected on the grid that reference transistor T201L is set.The cascode amplifier connects transistor T 202RB and is connected between supply reference transistor T201RB and the bias voltage generation transistor T 204B, and the grid of cascode amplifier connection transistor T 202RB is connected on the grid of cascode amplifier connection transistor T 202L.Bias voltage produces transistor T 204B and is connected between cascode amplifier connection transistor T 202RB and the ground node, and grid and the drain electrode of bias voltage generation transistor T 204B are connected to each other.
Bias voltage produces the grid of transistor T 204A and the grid of bias voltage generation transistor T 204B is connected on the bias voltage line G204.The per unit length of bias voltage line G204 has the resistance value that is represented as " conductor resistance R ".
Driving transistors T205-1 each in the T205-K all is connected between the output node OUT and ground node with output current Iout output.The grid of driving transistors T205-1 each in the T205-K all is connected on the bias voltage line G204 at an arbitrary position.Driving transistors T205-1 is arranged continuously to T205-K, so that farthest apart on driving transistors T205-1 and the driving transistors T205-K entity.Driving transistors T205-1 and bias voltage produce transistor T 204A and are arranged to adjacent one another are.Driving transistors T205-K and bias voltage produce transistor T 204B and are arranged to adjacent one another are.
Reference transistor T201L is set, supply reference transistor T201RA is connected transistor T 202L, T202RA and T202RB, bias voltage generation transistor T 204A and T204B with T201RB, cascode amplifier, and driving transistors T205-1 each in the T205-K is all formed by one or more transistors.
＜conventional operation 〉
Next the operation of the current driver 20 shown in Figure 11 is described.
At first, by reference transistor T201L being set, supplying the current mirror that reference transistor T201RA and T201RB and bias voltage produce transistor T 204A and T204B formation, producing bias voltage VbiasA on the grid of bias voltage generation transistor T 204A and on the grid of bias voltage generation transistor T 204B, producing bias voltage VbiasB.Bias voltage VbiasA has the definite magnitude of voltage of transistor characteristic (being applied to the relation between the current value of the magnitude of voltage of the grid voltage on the grid and drain current) that produces transistor T 204A according to the current value of reference current Iref and bias voltage.Bias voltage VbiasB has the magnitude of voltage of determining according to the transistor characteristic of the current value of reference current Iref and bias voltage generation transistor T 204B.
Relation between＜gate lines G 204 and the driving transistors 〉
Driving transistors T205-1 is physically farthest apart with driving transistors T205-K and have different transistor characteristics.Therefore, in some cases, driving transistors T205-1 need have different grid voltages with driving transistors T205-K, with the electric current that allows identical size from wherein flowing through.Usually, driving transistors T205-1 changes on gate line 204 linearly to the transistor characteristic of T205-K.
Produce transistor T 204A at bias voltage and be arranged to adjacently with driving transistors T205-1, and bias voltage produces transistor T 204B and is arranged to when adjacent with driving transistors T205-K, and these transistorized transistor characteristics become comparatively approaching.By such arrangement, can produce the bias voltage VbiasA and bias voltage VbiasB of magnitude of voltage with the characteristic that is suitable for driving transistors T205-1 with magnitude of voltage of the characteristic that is suitable for driving transistors T205-K.
Gate line 204 with conductor resistance R has the current potential that obtains by linear interpolation between the bias voltage VbiasA at the two ends that put on gate line 204 and bias voltage VbiasB.Like this, have the output current Iout of the current value of determining according to the linear interpolation current potential of gate lines G 204, flow through each in the T205-K of the driving transistors T205-1 that is connected on the gate lines G 204.Therefore, offset the current potential that driving transistors T205-1 changes to the linearity of the variation of the transistor characteristic of T205-K and gate line.Like this, flow through driving transistors T205-1 and have identical current value to the output current Iout of T205-K.
Yet in the conventional current driver, grid and drain electrode that bias voltage produces transistor T 204A are connected to each other, and grid and the drain electrode of bias voltage generation transistor T 204B also are connected to each other.Bias voltage produces the grid of transistor T 204A and the grid of bias voltage generation transistor T 204B is coupled together by the bias voltage line with conductor resistance R.Therefore, if the magnitude of voltage of bias voltage VbiasA is different with the magnitude of voltage of bias voltage VbiasB, then the electric current Δ Idr that determines according to this voltage difference flows through gate lines G 204.Like this, for example, if the magnitude of voltage of bias voltage VbiasA is less than the magnitude of voltage of bias voltage VbiasB, then flowing through the electric current that bias voltage produces transistor T 204B is to deduct the electric current Δ Idr (Idrs-Δ Idr) that flows through gate lines G 204 from the drain current Idrs that supply reference transistor T201RB flows out, and to flow through the electric current that bias voltage produces transistor T 204A be to add the electric current Δ Idr (Idrs+ Δ Idr) that flows through gate lines G 204 from the drain current Idrs that supply reference transistor T201RA flows out.Like this, owing to produce the electric current of transistor T 204A and flow through bias voltage and produce the error that produces between the electric current of transistor T 204B flowing through bias voltage, the magnitude of voltage of bias voltage VbiasA and VbiasB might can't be set at desired value.
In the case, although reduce to flow through the electric current Δ Idr of gate lines G 204 by the conductor resistance R that increases gate lines G 204, driving transistors T205-1 is to the capacity coupled influence increase of T205-K.
Summary of the invention
According to an aspect of the present invention, a kind of current driver comprises: first I/O part, first bias voltage produce transistor, second I/O part, second bias voltage generation transistor, a K driving transistors (K is a natural number), first grid polar curve, first voltage supply node, first differential amplifier circuit, second voltage supply node and second differential amplifier circuit.First electric current partly is transfused to by this first I/O or exports.This first bias voltage produces transistor and is connected between this first I/O part and first reference mode.Second electric current partly is transfused to by this second I/O or exports.This second bias voltage produces transistor and is connected between this second I/O part and this first reference mode.This K driving transistors is connected by it and inputs or outputs between the output node and this first reference mode of output current.This first bias voltage produces the grid of transistorized grid, this K driving transistors and this second bias voltage and produces transistorized grid and be connected in proper order on this first grid polar curve with this.This first voltage supply node receives first voltage.This first differential amplifier circuit output tertiary voltage, this tertiary voltage has the magnitude of voltage that produces second voltage on transistorized first interconnecting nodes according to this first I/O part and first bias voltage, and the definite magnitude of voltage of difference between first magnitude of voltage of first voltage that is received by this first voltage supply node.This second voltage supply node receives the 4th voltage with the 4th magnitude of voltage.This second differential amplifier circuit is exported the 6th voltage, the 6th voltage has the magnitude of voltage that produces the 5th voltage on transistorized second interconnecting nodes according to this second I/O part and second bias voltage, and the definite magnitude of voltage of difference between the 4th magnitude of voltage of the 4th voltage that is received by this second voltage supply node.This first bias voltage produces transistor and receives the tertiary voltage of being exported by this first differential amplifier circuit at its grid.This second bias voltage produces transistor and receives the 6th voltage of being exported by this second differential amplifier circuit at its grid.
In above-mentioned current driver, the current potential of this first grid polar curve has by producing the tertiary voltage on the transistorized grid and put on this second bias voltage and produce the value that linear interpolation obtains between the 6th voltage on the transistorized grid putting on this first bias voltage.Like this, each in this K driving transistors all receives at its grid and has according to the distance that produces transistor (or second bias voltage produces transistor) from this first bias voltage and the bias voltage of definite magnitude of voltage.Because this first differential amplifier circuit is connected this first bias voltage and produces between transistorized grid and the drain electrode, and this second differential amplifier circuit is connected this second bias voltage and produces between transistorized grid and the drain electrode, flows through this first bias voltage and produces transistor drain electric current and flow through this second bias voltage and produce that neither one flows in this first grid polar curve in transistor drain electric current.Therefore, offset the variation of the gradient of current potential of this first grid polar curve and the transistor characteristic of this K driving transistors (at the magnitude of voltage of the voltage that grid receives and flow through relation between the current value of transistor drain electric current), thus, the output current Iout that flows through this K driving transistors has identical current value.
Because this first and second differential amplifier circuit has low output impedance, the pressure drop in this first and second differential amplifier circuit is less.Thereby, compare with the conventional current driver, effectively utilized energy.Because this first and second differential amplifier circuit has high input impedance, put near the electric loading on the circuit (for example, this first and second I/O part) before this first and second differential amplifier circuit little.By produce the negative-feedback circuit that transistor (second bias voltage produces transistor) forms by this first differential amplifier circuit (second differential amplifier circuit) and first bias voltage, eliminate the variation of the current potential of possible this first grid polar curve that causes owing to transistorized capacity coupled influence.
Preferably, this first grid polar curve has first node and Section Point.This first bias voltage produces on the first node that transistorized grid is connected to this first grid polar curve.This second bias voltage produces on the Section Point that transistorized grid is connected to this first grid polar curve.The grid of each in this K transistor all is connected between the first node and Section Point of this first grid polar curve.
Preferably, this current driver further comprises transistor is set.This is provided with transistor and is connected second reference mode and inputs or outputs between the I/O node of reference current by it, and transistorized grid is set for this and drain electrode is connected to each other.This first I/O partly comprises first supply transistor.This first supply transistor is connected between this second reference mode and this first interconnecting nodes, and the grid of this first supply transistor is connected to this and is provided with on the transistorized grid.This second I/O partly comprises second supply transistor.This second supply transistor is connected between this second reference mode and second interconnecting nodes, and the grid of this second supply transistor is connected to this and is provided with on the transistorized grid.
In above-mentioned current driver, have the drain current of the current value of determining according to the current value of this reference current, flow through this first bias voltage and produce transistor and second bias voltage generation transistor.Thereby, produce bias voltage with current value of determining according to the current value of this reference current.Have the output current of the current value of determining according to the current value of this reference current, flow through each in this K driving transistors.
Preferably, this is provided with transistor and first and second supply transistors are connected by the cascode amplifier.
In above-mentioned current driver, this drain voltage that the transistor and first and second supply transistors are set has identical magnitude of voltage.Utilize this characteristic, have the drain current of the current value of determining according to the current value of this reference current, flow through this first and second bias voltage and produce transistor, and be not subjected to that drain voltage is dependent to be influenced.
Preferably, this current driver comprises that further the 3rd I/O part, the 3rd bias voltage produce transistor, tertiary voltage supply node and the 3rd differential amplifier circuit.Partly input or output the 3rd electric current by the 3rd I/O.The 3rd bias voltage produces transistor and is connected between the 3rd I/O part and first reference mode.This tertiary voltage supply node receives the 7th voltage.The 3rd differential amplifier circuit is exported the 9th voltage, the 9th voltage has the magnitude of voltage that produces the 8th voltage on transistorized the 3rd interconnecting nodes according to the 3rd I/O part and the 3rd bias voltage, and the definite magnitude of voltage of difference between the 7th magnitude of voltage of the 7th voltage that is received by this tertiary voltage supply node.This first bias voltage produces first in transistorized grid, this driving transistors and produces (H+1) in transistorized grid, this driving transistors to H grid, the 3rd bias voltage and produce transistorized grid to K grid and this second bias voltage and be connected in proper order on this first grid polar curve with this, and wherein H is the natural number that satisfies 1≤H≤K-1.The 3rd bias voltage produces transistor and receives the 9th voltage of being exported by the 3rd differential amplifier circuit at its grid.
In above-mentioned current driver, putting on this first grid polar curve is not two voltages (tertiary voltage and the 6th voltages), but three voltages (tertiary voltage, the 6th voltage and the 9th voltage).Therefore, the current potential of this first grid polar curve is set to according to the variation of the transistor characteristic in this K the driving transistors and definite current potential.Utilize this feature, the output current that flows through this K driving transistors is controlled to be accurately has identical current value.
Preferably, this first grid polar curve further comprises first node, Section Point and the 3rd node.The 3rd node is between this first node and Section Point.The 3rd bias voltage produces on the 3rd node that transistorized grid is connected to this first grid polar curve.In this K driving transistors, first grid to H driving transistors (H driving transistors) is connected on the first grid polar curve between this first node and the 3rd node (H is a natural number).On (H+1) is connected to first grid polar curve between the 3rd node and the Section Point to the grid of K driving transistors (K-H driving transistors).
Preferably, this current driver further comprises K output voltage limit transistor and second grid line.This K output voltage limit transistor is connected between this K driving transistors and the output node.The grid of this K output voltage limit transistor is connected on this second grid line.This second grid line receives the deboost with scheduled voltage.
In above-mentioned current driver, the drain voltage of this K driving transistors has identical magnitude of voltage.Utilize this feature, reduced the dependent influence of drain voltage, and the output current that flows through this K driving transistors is controlled to be accurately and is had identical current value.
Preferably, this current driver further comprises the first voltage limit transistor and the second voltage limit transistor.This first voltage limit transistor is connected this first interconnecting nodes and first bias voltage produces between the transistor.This second voltage limit transistor is connected this second interconnecting nodes and second bias voltage produces between the transistor.The grid of the transistorized grid of this first voltage limit, this K output voltage limit transistor and the transistorized grid of this second voltage limit are connected on this second grid line in proper order with this.
In above-mentioned current driver, this first bias voltage produces transistor, this K driving transistors and this second bias voltage generation transistor drain voltage and has identical magnitude of voltage.Utilize this feature, reduced the dependent influence of drain voltage, and the output current that flows through this K driving transistors is controlled to be accurately and is had identical current value.
Preferably, this second grid line further comprises the 3rd node and the 4th node.The transistorized grid of this first voltage limit is connected on the 3rd node of this second grid line.The transistorized grid of this second voltage limit is connected on the 4th node of this second grid line.The grid of each in this K output voltage limit transistor all is connected on the second grid line between the 3rd node and the 4th node.
Preferably, this current driver further comprises the 3rd I/O part and the first and second cascode amplifier transistors.Partly input or output the 3rd electric current by the 3rd I/O.This first and second cascodes amplifier transistor is connected in series between the 3rd I/O part and first reference mode.This first cascode amplifier transistor is connected between the 3rd I/O part and the second cascode amplifier transistor, and the grid of this first cascode amplifier transistor and drain electrode are connected to each other.This second cascode amplifier transistor is connected between this first cascode amplifier transistor and this first reference mode, and the grid of this second cascode amplifier transistor and drain electrode are connected to each other.The second grid line is received in the primary grid voltage of the grid generation of this first cascode amplifier transistor.
In above-mentioned current driver, this first bias voltage produces transistor, this K driving transistors and this second bias voltage and produces transistorized grid and be applied in identical voltage (in the primary grid voltage of the grid generation of this first cascode amplifier transistor).Utilize this feature, reduced the dependent influence of drain voltage, and the output current that flows through this K driving transistors is controlled to be accurately and is had identical current value.
Preferably, this first and second voltage supply node is received in the primary grid voltage of the grid generation of this first cascode amplifier transistor.
In above-mentioned current driver, needn't produce this first voltage and second voltage respectively.Therefore, the voltage generation circuit that is used to produce this first and second voltage is optional, thereby has reduced circuit scale.
Preferably, this current driver further comprises voltage follower circuit.This second grid line receives the output of this voltage follower circuit.
In above-mentioned current driver, this voltage follower circuit has low output impedance.Therefore, reduced the variation of this second grid line current potential of causing owing to capacitive coupling.
Preferably, this second grid line has the 3rd node and the 4th node.The grid of this K output voltage limit transistor is connected on the second grid line between the 3rd node and the 4th node.This second grid line any in the 3rd node and the 4th node receives the output of this voltage follower circuit.
Preferably, this current driver further comprises the first voltage limit transistor, the 3rd I/O part and the first and second cascode amplifier transistors.This first voltage limit transistor is connected this first interconnecting nodes and first bias voltage produces between the transistor.Partly input or output the 3rd electric current by the 3rd I/O.This first and second cascodes amplifier transistor is connected in series between the 3rd I/O part and first reference mode.This first cascode amplifier transistor is connected between the 3rd I/O part and the second cascode amplifier transistor, and the grid of this first cascode amplifier transistor and drain electrode are connected to each other.This second cascode amplifier transistor is connected between this first cascode amplifier transistor and this first reference mode, and the grid of this second cascode amplifier transistor and drain electrode are connected to each other.The transistorized grid of this first voltage limit and this voltage follower circuit are received in the primary grid voltage of the grid generation of this first cascode amplifier transistor.
Preferably, this current driver further comprises the second voltage limit transistor, the 4th I/O part and the third and fourth cascode amplifier transistor.This second voltage limit transistor is connected this second interconnecting nodes and second bias voltage produces between the transistor.Partly input or output the 4th electric current by the 4th I/O.This third and fourth cascode amplifier transistor is connected in series between the 4th I/O part and first reference mode.The 3rd cascode amplifier transistor is connected between the 4th I/O part and the 4th cascode amplifier transistor, and the grid of the 3rd cascode amplifier transistor and drain electrode are connected to each other.The 4th cascode amplifier transistor is connected between the 3rd cascode amplifier transistor and this first reference mode, and the grid of the 4th cascode amplifier transistor and drain electrode are connected to each other.This second voltage limit transistor is received in the second grid voltage of the grid generation of the 3rd cascode amplifier transistor at its grid.
Preferably, this first voltage supply node is received in the primary grid voltage of the grid generation of this first cascode amplifier transistor.The second grid voltage that the grid that this second voltage supply node is received in the 3rd cascode amplifier transistor produces.
Preferably, this current driver further comprises K switching transistor, a K control section and second grid line.This K switching transistor is connected between this K driving transistors and the output node.This K control section is one to one corresponding to this K switching transistor.This second grid line receives the deboost with scheduled voltage.In this K control section each all has first pattern and second pattern, and comprises the first terminal that is connected on this second grid line and second terminal that is connected on this first reference mode.In this first pattern, the voltage on this first terminal is provided on the grid corresponding to the switching transistor of this control section.In this second pattern, the voltage on this second terminal is applied on the grid corresponding to the switching transistor of this control section.
In above-mentioned current driver, be used to be provided with this K driving transistors drain voltage structure and be used to produce the structure of drive current with any grey level, share the element of crossover.Therefore, reduced the circuit scale of this current driver.
Preferably, this first supply transistor is formed by P current-voltage conversioning transistor, and wherein P is a natural number.This P current-voltage conversioning transistor is connected in parallel between this second reference mode and first interconnecting nodes.In this P current-voltage conversioning transistor each all is received in this at its grid the grid voltage that transistorized grid produces is set.
In above-mentioned current driver, reduced the influence of the variation in the transistor characteristic of this first supply transistor.
Preferably, above-mentioned current driver further comprises control section and coupling part.This control section is selected N current-voltage conversioning transistor from this P current-voltage conversioning transistor, wherein N is the natural number that satisfies N≤P.In N the current-voltage conversioning transistor that this coupling part will be selected by this control section each all is connected on this first interconnecting nodes.
In above-mentioned current driver, selected to be received in the number of the current-voltage conversioning transistor of the grid voltage that the grid of this supply transistor produces.Utilize this feature, flow through this first bias voltage and produce transistor drain electric current and be controlled as and have the optimal current value.
Preferably, this is provided with transistor and is formed by P current-voltage conversioning transistor, and wherein P is a natural number.This P current-voltage conversioning transistor is connected in parallel between this second reference mode and the I/O node.In this P current-voltage conversioning transistor each all has by grid connected to one another and drain electrode.In this first and second supply transistor each all is received in the grid voltage that this P current-voltage conversioning transistor produces at its grid.
In above-mentioned current driver, reduced the influence of the variation in the transistor characteristic of this supply transistor.
Preferably, above-mentioned current driver further comprises control section and coupling part.This control section is selected N current-voltage conversioning transistor from this P current-voltage conversioning transistor, wherein N is the natural number that satisfies N≤P.In each in N the current-voltage conversioning transistor of selecting by this control section of this coupling part, grid and drain electrode are connected to each other.In this first and second supply transistor each all is received in the grid voltage of the grid generation of this N current-voltage conversioning transistor at its grid, in this N current-voltage conversioning transistor, grid is connected by this coupling part with drain electrode.
In above-mentioned current driver, selected generation is imposed on the number of current-voltage conversioning transistor of grid voltage of the grid of this first and second supply transistor.Utilize this feature, flow through this first bias voltage and produce transistor drain electric current and be controlled as and have the optimal current value.
Preferably, above-mentioned current driver further comprises storage area.This storing section stores is represented the number of transistors purpose information selected by this control section from this P current-voltage conversioning transistor.This control section is selected N current-voltage conversioning transistor according to canned data in this storage area from this P current-voltage conversioning transistor.
In above-mentioned current driver, as long as make flow through this first and or second bias voltage produce the number that the transistor drain electric current has the current-voltage conversioning transistor of optimal current value and be stored in this storage area, flow through this first and or second bias voltage produce the transistor drain electric current and just be retained as and have the optimal current value.
Preferably, this storage area comprises a plurality of fuses.This control section has rigid condition pattern and simulation model.When this control section moved in the rigid condition pattern, this control section was selected N current-voltage conversioning transistor according to the state of these a plurality of fuses from this P current-voltage conversioning transistor.When this control section moved under simulation model, this control section was simulated the state of these a plurality of fuses, came to select from this P current-voltage conversioning transistor N current-voltage conversioning transistor.
Preferably, this be provided with in transistor, this first supply transistor and second supply transistor each all form by a plurality of transistors.Forming these a plurality of transistors that transistorized a plurality of transistor are set, form a plurality of transistors of this first supply transistor and form this second supply transistor is distributed evenly on the chip.
In above-mentioned current driver, reduced to be provided with the influence of the variation of transistor characteristic in transistor, first supply transistor and second supply transistor.
According to a further aspect in the invention, a kind of data driver comprises: above-mentioned current driver, selection part and drive current lead-out terminal.This selection portion is divided video data X the output current of selection from K the output current of being exported by this current driver according to the outside input, and wherein X is the natural number that satisfies X≤K.By the summation of X output current of this selection portion component selections as drive current from this drive current lead-out terminal output.This video data is represented grey level.
In above-mentioned data driver, the output current that this current driver output has the same current value.Like this, this selection part produces the drive current with current value that the grey level represented according to this video data determines accurately.
According to another aspect of the invention, a kind of display device comprises: above-mentioned data driver and display panel.This display panel is driven by the drive current from this data driver output.
In above-mentioned display device, the drive current of the current value that the grey level that with good grounds this video data of this data driver output device is represented is determined.Like this, this display panel is driven accurately.
Description of drawings
Fig. 1 illustrates the general structure according to the current driver 1 of the embodiment of the invention 1.
Fig. 2 illustrates the general structure according to the current driver 2 of the embodiment of the invention 2.
Fig. 3 illustrates the general structure according to the current driver 3 of the embodiment of the invention 3.
Fig. 4 illustrates the general structure according to the current driver 4 of the embodiment of the invention 4.
Fig. 5 illustrates the general structure according to the current driver 5 of the embodiment of the invention 5.
Fig. 6 illustrates the general structure according to the current driver 6 of the embodiment of the invention 6.
Fig. 7 A illustrates the inner structure that is included in according to the current-voltage conversion portion 700a in the current driver of the embodiment of the invention 7.
Fig. 7 B illustrates the inner structure that is included in according to the current-voltage conversion portion 700b in the current driver of the variation of the embodiment of the invention 7.
Fig. 8 illustrates the inner structure that is included in according to the bias voltage adjustment member 800 in the current driver of the embodiment of the invention 8.
Fig. 9 illustrates the inner structure that is included in according to the grid voltage adjustment member in the current driver of the embodiment of the invention 9.
Figure 10 illustrates the general structure according to the display device of the embodiment of the invention 10.
Figure 11 illustrates the general structure of conventional current driver.
Embodiment
Hereinafter, describe embodiments of the invention with reference to the accompanying drawings in detail.Should be noted that in whole accompanying drawings, identical or equal parts are represented with identical Reference numeral, and do not repeated its explanation.
(embodiment 1)
＜general structure 〉
Fig. 1 illustrates the general structure according to the current driver 1 of the embodiment of the invention 1.Current driver 1 comprises: be provided with reference transistor T101L, supply reference transistor T101RA with T101RB, be used for transistor T 102L, T102RA and T102RB (hereinafter being " the cascode amplifier is connected transistor "), reference voltage supplies node N102A and N102B, differential amplifier circuit D103A and D103B, bias voltage generation transistor T 104A and T104B that the cascode amplifier is connected, and K driving transistors T105-1 is to T105-K (K is a natural number).Current driver 1 receives reference current Iref at reference current input node N101.Current driver 1 can allow drain current Idrs to flow through bias voltage and produce transistor T 104A and T104B, and this drain current has with the current value of importing reference current Iref and equates or proportional current value.Current driver 1 is exported to a plurality of display element circuit (not shown) to output current, and this output current has with the current value of drain current Idrs and equates or proportional current value.
Reference transistor T101L and cascode amplifier connection transistor T 102L is set to be connected in series between power supply node and the reference current input node 101.The grid that reference transistor T101L is set is connected on the grid of supplying reference transistor T101RA and the grid of the supplying reference transistor T101RB.The grid that the grid of cascode amplifier connection transistor T 102L is connected to cascode amplifier connection transistor T 102RA is connected on the grid of transistor T 102RB with the cascode amplifier.
Supply reference transistor T101RA, cascode amplifier connect transistor T 102RA and bias voltage generation transistor T 104A is connected in series between power supply node and the ground node.The grid that bias voltage produces transistor T 104A is connected on the gate lines G 104.Differential amplifier circuit D103A has to be connected to and connects transistor T 102RA and bias voltage at the cascode amplifier and produce non-inverting input on the node N103A between the transistor T 104A, be connected to the reversed input terminal on the reference voltage supplies node N102A and be connected to lead-out terminal on the gate lines G 104.
Supply reference transistor T101RB, cascode amplifier connect transistor T 102RB and bias voltage generation transistor T 104B is connected in series between power supply node and the ground node.The grid that bias voltage produces transistor T 104B is connected on the gate lines G 104.Differential amplifier circuit D103B has to be connected to and connects transistor T 102RB and bias voltage at the cascode amplifier and produce non-inverting input on the node N103B between the transistor T 104B, be connected to the reversed input terminal on the reference voltage supplies node N102B and be connected to lead-out terminal on the gate lines G 104.
Driving transistors T105-1 each in the T105-K all is connected on output node OUT and the ground node.Driving transistors T105-1 is connected in series in bias voltage to T105-K and produces between transistor T 104A and the bias voltage generation transistor T 104B.Driving transistors T105-1 is connected on the gate lines G 104 with this order to the grid of T105-K.Like this, in driving transistors T105-1 each in the T105-K, all have output current Iout flowing, this output current Iout has according to the definite current value of the magnitude of voltage that is applied to the voltage on the transistor gate (current potential at the tie point place of grid and gate lines G 104).
Here should be noted that, suppose that driving transistors T105-1 is disposed in each other neighbouring (for example, supposing that driving transistors T105-1 is formed on the chip continuously to T105-K) to T105-K.
Be to be further noted that here all transistors all move in the saturation region.
Here, suppose that supply reference transistor T101RA and T101RB present and the identical or essentially identical transistor characteristic of reference transistor T101L (, be applied to the magnitude of voltage of the voltage on the transistor gate and flow through relation between the current value of this transistor drain electric current) is set here.
Suppose that also the cascode amplifier connects transistor T 102RA and T102RB and presents and send out common-base amplifier together and be connected the identical or essentially identical transistor characteristic of transistor T 102L.Like this, the cascode amplifier connects the performance ratio between transistor T 102L and the cascode amplifier connection transistor T 102RA, equals to be provided with the performance ratio between reference transistor T101L and the supply reference transistor T101RA.Performance between cascode amplifier connection transistor T 102L and the cascode amplifier connection transistor T 102RB is than the performance ratio that equals to be provided with between reference transistor T101L and the supply reference transistor T101RB.
Suppose that also bias voltage produces transistor T 104A and presents identical with driving transistors T105-1 or essentially identical transistor characteristic.Suppose that also putting voltage generation transistor T 104B presents identical with driving transistors T105-K or essentially identical transistor characteristic.
＜current mirror structure 〉
Reference transistor T101L and supply reference transistor T101RA and T101RB are set constitute current mirror circuit.Grid and source electrode that reference transistor T101L is set are connected to each other.At the grid that reference transistor T101L is set, produce grid voltage Vid with magnitude of voltage of determining according to the current value of reference current Iref.Supply reference transistor T101RA receives the grid voltage Vid of the grid generation that reference transistor T101L is set at grid.Like this, the drain current Idrs that has according to the definite current value of the magnitude of voltage of grid voltage Vid flows through supply reference transistor T101RA.
As supply reference transistor T101RA, supply reference transistor T101RB is at grid receiving grid pole tension Vid, and drain current Idrs flows through supply reference transistor T101RB, and this drain current Idrs has the current value of determining according to the magnitude of voltage of grid voltage Vid.
Like this, current mirror circuit produces drain current Idrs, and this drain current Idrs has according to the current value of reference current and reference transistor T101L is set and supplies the current value that the performance ratio between reference transistor T101RA and the T101RB is determined.
＜cascode amplifier connects 〉
Grid and source electrode that the cascode amplifier connects transistor T 102L are connected to each other.Grid at cascode amplifier connection transistor T 102L produces grid voltage Vidc, and this grid voltage Vidc has the magnitude of voltage of determining according to the current value of reference current Iref.Each that connects at the cascode amplifier that grid voltage Vidc that the grid of transistor T 102L produces connects among transistor T 102RA and the T102RB by the cascode amplifier receives at grid.
Since supply reference transistor T101RA with reference transistor T101L cascode amplifier be set be connected, the magnitude of voltage of supplying the drain voltage of reference transistor T101RA equals to be provided with the magnitude of voltage of the drain voltage of reference transistor T101L.
Since supply reference transistor T101RB with reference transistor T101L cascode amplifier be set be connected, the magnitude of voltage of supplying the drain voltage of reference transistor T101RB equals to be provided with the magnitude of voltage of the drain voltage of reference transistor T101L.
Like this, reduced the dependent influence of drain voltage by the connection of cascode amplifier, and also can reduce the error of the current value of drain current Idrs with respect to the current value of reference current Iref.
＜be formed on a characteristics of transistor on the chip 〉
Usually, being formed on a plurality of transistors on the chip has at the magnitude of voltage of the grid voltage that transistor gate receives and flows through linear changing relation between the current value (transistor characteristic) of transistor drain electric current.For example, in a plurality of transistors that series connection forms continuously, when from the transistor of front end when the transistor of tail end is measured, transistorized threshold voltage increases (or reducing) gradually.Therefore, when when a plurality of transistorized grids apply the grid voltage with identical magnitude of voltage, flow through current value (flowing through the current value of driving transistors the T105-1 here) linear change of each transistor drain electric current to the output current Iout of T105-K.
The current potential of＜gate lines G 104 〉
The magnitude of voltage that produces the bias voltage VbiasA that the grid of transistor T 104A produces at bias voltage is set to produce the transistor characteristic of transistor T 104A and the magnitude of voltage that drain current Idrs determines according to bias voltage.Driving transistors T105-1 has the identical transistor characteristic with bias voltage generation transistor T 104A, therefore, has the output current Iout of the current value that equates with the drain current that flows through bias voltage generation transistor T 104A, flows through driving transistors T105-1.
The magnitude of voltage that produces the bias voltage VbiasB that the grid of transistor T 104B produces at bias voltage is set to produce the transistor characteristic of transistor T 104B and the magnitude of voltage that drain current Idrs determines according to bias voltage.Driving transistors T105-K has the identical transistor characteristic with bias voltage generation transistor T 104B, therefore, has the output current Iout of the current value that equates with the drain current that flows through bias voltage generation transistor T 104B, flows through driving transistors T105-K.
The bias voltage VbiasA that produces the grid generation of transistor T 104A at bias voltage is at one end received by gate lines G 104.The bias voltage VbiasB that produces the grid generation of transistor T 104B at bias voltage is received at the other end by gate lines G 104.
Here, suppose that driving transistors T105-1 increases (driving transistors T105-1 reduces gradually to the magnitude of voltage of the threshold voltage of T105-K) gradually to the transistor characteristic of T105-K from driving transistors T105-1 to driving transistors T105-K.In other words, when from driving transistors T105-1 when driving transistors T105-K measures, each driving transistors all has the transistor characteristic bigger than the driving transistors that is close to previously (each driving transistors all has the threshold voltage lower than the driving transistors that is close to previously).In the case, the magnitude of voltage of bias voltage VbiasA is less than the magnitude of voltage of bias voltage VbiasB.
Because the resistance value of gate lines G 104 is not " 0 ", then gate lines G 104 has between the magnitude of voltage of the magnitude of voltage of the bias voltage VbiasA that receives by the end in gate lines G 104 and bias voltage VbiasB and carries out the current potential that linear interpolation obtains.With from driving transistors T105-1 when the direction of driving transistors T105-K is measured, the current potential of gate lines G 104 increases to the magnitude of voltage of bias voltage VbiasB from the magnitude of voltage linearity of bias voltage VbiasA.
The grid of driving transistors T105-1 each in the T105-K all is applied in bias voltage, and this bias voltage has according to the definite magnitude of voltage of the distance that produces transistor T 104A from bias voltage (perhaps producing the distance of transistor T 104B from bias voltage).
Like this, the gradient of the current potential of gate lines G 104 and driving transistors T105-1 cancel each other out to the variation of the transistor characteristic of T105-K, and the output current Iout of output has identical current value from driving transistors T105-1 to T105-K thus.
＜negative feedback structure 〉
Differential amplifier circuit D103A and bias voltage produce transistor T 104A and constitute negative-feedback circuit.The reference voltage supplies node N102A provide reference voltage VcA.Differential amplifier circuit D103A is to gate lines G 104 output offset voltage VbiasA, and the magnitude of voltage of determining according to the magnitude of voltage of the reference voltage VcA that provides from reference voltage supplies node N102A and the difference between the magnitude of voltage of the drain voltage VrbA that node N103A produces is provided bias voltage VbiasA.Bias voltage produces transistor 104A and receives the bias voltage VbiasA that is exported by differential amplifier circuit D103A at grid.Therefore, the resistance value of the channel resistance of bias voltage generation transistor T 104A changes according to the variation of the magnitude of voltage of bias voltage VbiasA.Utilize this structure, the drain voltage VrbA at node N103A place the reference voltage VcA that provides with reference voltage supplies node N102A is provided equates.
It is such that aberration divides amplifier circuit D103A and bias voltage to produce transistor T 104A, and differential amplifier circuit D103B and bias voltage produce transistor T 104B and also constitute negative-feedback circuit.The reference voltage supplies node N102B provide reference voltage VcB.Differential amplifier circuit D103B is to gate lines G 104 output offset voltage VbiasB, and the magnitude of voltage of determining according to the magnitude of voltage of the reference voltage VcB that provides from reference voltage supplies node N102B and the difference between the magnitude of voltage of the drain voltage VrbB that node N103B produces is provided bias voltage VbiasB.Bias voltage produces transistor T 104B and receives the bias voltage VbiasB that is exported by differential amplifier circuit D103B at grid.Therefore, the resistance value of the channel resistance of bias voltage generation transistor T 104B changes according to the variation of the magnitude of voltage of bias voltage VbiasB.Utilize this structure, the drain voltage VrbB at node N103B place the reference voltage VcB that provides with reference voltage supplies node N102B is provided equates.
The grid voltage that connects transistor T 102RA (T102RB) at the cascode amplifier is under the identical voltage condition with the drain voltage that bias voltage produces transistor T 104A (T104B), for example, reference voltage VcA (VcB) is in and makes cascode amplifier connection transistor T 102RA (T102RB) and bias voltage produce the level that transistor T 104A (T104B) can move in the saturation region.
＜operation 〉
Next the operation of current driver 1 is described with reference to Fig. 1.
At first, flow through at the reference current Iref of reference current input node N101 input and reference transistor T101L is set is connected transistor T 102L with the cascode amplifier.Like this, produce grid voltage Vid, and connect the grid generation grid voltage Vidc of transistor T 102L at the cascode amplifier at the grid that reference transistor T101L is set.
Then, supply reference transistor T101RA is at grid receiving grid pole tension Vid, and the cascode amplifier connects transistor T 102RA at grid receiving grid pole tension Vidc.Like this, drain current Idrs flows through supply reference transistor T101RA, the cascode amplifier connects transistor T 102RA and bias voltage produces transistor T 104A, and this drain current Idrs has the magnitude of voltage according to grid voltage Vid, the magnitude of voltage of grid voltage Vidc and the definite current value of magnitude of voltage of bias voltage VbiasA.Meanwhile, produce drain voltage VrbA at node N103A with magnitude of voltage of determining according to the current value of drain current Idrs.
Then, the reference voltage VcA that provides from reference voltage supplies node N102A is provided at reversed input terminal differential amplifier circuit D103A, be received in the drain voltage VrbA that node N103A produces at non-inverting input, and bias voltage VbiasA is outputed to gate lines G 104, and this bias voltage VbiasA has the magnitude of voltage of determining according to the difference between the magnitude of voltage of the magnitude of voltage of reference voltage VcA and drain voltage VrbA.
Then, output to the bias voltage VbiasA of gate lines G 104 by bias voltage generation transistor T 104A reception.Like this, the resistance value of the channel resistance of bias voltage generation transistor T 104A is determined according to the magnitude of voltage of bias voltage VbiasA.
Produce the operation of carrying out among transistor T 104B, reference voltage supplies node N102B and the differential amplifier circuit D103B at supply reference transistor T101RB, cascode amplifier connection transistor T 102RB, bias voltage, identical with the operation that produces transistor T 104A, reference voltage supplies node N102A and differential amplifier circuit D103A execution at supply reference transistor T101RA, cascode amplifier connection transistor T 102RA, bias voltage.Like this, drain current Idrs flows through supply reference transistor T101RB, the cascode amplifier connects transistor T 102RB and bias voltage produces transistor T 104B, and this drain current Idrs has the current value of determining according to the magnitude of voltage of grid voltage Vid, grid voltage Vidc and bias voltage VbiasB.Differential amplifier circuit D103B outputs to gate lines G 104 to bias voltage VbiasB, and this bias voltage VbiasB has according to the magnitude of voltage of the reference voltage VcB that provides from reference voltage supplies node N102B and the definite magnitude of voltage of the difference between the magnitude of voltage of the drain voltage VrbB that node N103B produces.Like this, the resistance value of the channel resistance of bias voltage VbiasB is determined according to the magnitude of voltage of the bias voltage VbiasB that exports from differential amplifier circuit D103B.
Then, the current potential of gate lines G 104 has by carry out the value that linear interpolation obtains between the magnitude of voltage of the magnitude of voltage of bias voltage VbiasA and bias voltage VbiasB.Like this, output current Iout flows in driving transistors T105-1 each in the T105-K, and this output current Iout has according to the definite current value of the magnitude of voltage that is applied to voltage on the transistorized grid (current potential at the tie point place of grid and gate lines G 104).
[(current value of drain current Idrs)＜(current value of reference current Iref)]
Consider to flow through the situation of the current value of the drain current Idrs that supplies reference transistor T101RA now less than the current value that flows through the reference current Iref that reference transistor T101L is set.
Compare with the situation that the current value of the current value of drain current Idrs and reference current Iref equates, in the case, bias voltage produces the resistance value of the channel resistance of transistor T 104A and wants big.Therefore, the magnitude of voltage of the drain voltage VrbA that produces at node N103A is higher than the magnitude of voltage of reference voltage VcA.Therefore, the magnitude of voltage that is higher than the bias voltage VbiasA that when drain voltage VrbA equals reference voltage VcA, exports from the magnitude of voltage of the bias voltage VbiasA of differential amplifier circuit D103A output.Like this, the resistance value that bias voltage produces the channel resistance of transistor T 104A diminishes, thus, flowing through supply reference transistor T101RA, cascode amplifier connects the current value that transistor T 102RA and bias voltage produce the drain current Idrs of transistor T 104A and becomes big.Further, because bias voltage produces the small resistor value of the channel resistance of transistor T 104A, the magnitude of voltage step-down of the drain voltage VrbA that produces at node N103A.
[(current value of drain current Idrs)＞(current value of reference current Iref)]
Consider to flow through the situation of the current value of the drain current Idrs that supplies reference transistor T101RA now greater than the current value that flows through the reference current Iref that reference transistor T101L is set.
Compare with the situation that the current value of the current value of drain current Idrs and reference current Iref equates, in the case, the resistance value of channel resistance that bias voltage produces transistor T 104A is little.Therefore, the magnitude of voltage of the drain voltage VrbA that produces at node N103A is lower than the magnitude of voltage of reference voltage VcA.Therefore, be lower than the magnitude of voltage of the bias voltage VbiasA that when drain voltage VrbA equals reference voltage VcA, exports from the magnitude of voltage of the bias voltage VbiasA of differential amplifier circuit D103A output.Like this, the resistance value that bias voltage produces the channel resistance of transistor T 104A becomes big, thus, flowing through supply reference transistor T101RA, cascode amplifier connects the current value that transistor T 102RA and bias voltage produce the drain current Idrs of transistor T 104A and diminishes.Further, because bias voltage produces the big resistance value of the channel resistance of transistor T 104A, the magnitude of voltage of the drain voltage VrbA that produces at node N103A uprises.
Although only illustrated that flowing through supply reference transistor T101RA, cascode amplifier connects the control that transistor T 102RA and bias voltage produce the drain current Idrs of transistor T 104A, flow through drain current Idrs that supply reference transistor T101RB, cascode amplifier connect transistor T 102RB and bias voltage generation transistor T 104B with a kind of mode Be Controlled.
＜flow through the electric current of gate lines G 104 〉
Differential amplifier circuit D103A is connected bias voltage and produces between the grid and drain electrode of transistor T 104A, and differential amplifier circuit D103B is connected between the grid and drain electrode of bias voltage generation transistor T 104B.Therefore, flow through bias voltage and produce the drain current Idrs of transistor T 104A and flow through among the drain current Idrs that bias voltage produces transistor T 104B, none flows to gate lines G 104.
＜effect 〉
As mentioned above, in the current driver of embodiment 1, flow through driving transistors T105-1 and be controlled as to the output current Iout of T105-K and have identical current value, and do not allow electric current to flow through gate lines G 104.
Because differential amplifier circuit D103A and D103B have low output impedance, the pressure drop in differential amplifier circuit D103A and D103B is less.Therefore, compared with the current driver of routine, more effectively utilized energy.
Because differential amplifier circuit D103A and D103B have high input impedance, it is little to put on the electric load that is provided with on reference transistor T101L and supply reference transistor T101RA and the T101RB.
May be because the change of the current potential of the gate lines G 104 that causes of transistorized capacity coupled influence, the negative-feedback circuit elimination that is formed by differential amplifier circuit D103A (or D103B) and bias voltage generation transistor T 104A (or T104B).
Be provided with reference transistor T101L and supply reference transistor T101RA and T101RB preferably be disposed in each other near.The cascode amplifier connect transistor T 102L, T102RA and T102RB preferably be disposed in each other near.Utilize such structure, the current value that flows through the drain current Idrs of supply reference transistor T101RA and T101RB becomes and approaches to flow through the current value of the reference current Iref that reference transistor T101L is set.
Bias voltage produce transistor T 104A and driving transistors T105-1 preferably be disposed in each other near.Utilize such structure, the current value that flows through the output current Iout of driving transistors T105-1 becomes and approaches to flow through the current value that bias voltage produces the drain current Idrs of transistor T 104A.Bias voltage produce transistor T 104B and driving transistors T105-K preferably be disposed in each other near.Utilize such structure, the current value that flows through the output current Iout of driving transistors T105-K becomes and approaches to flow through the current value that bias voltage produces the drain current Idrs of transistor T 104B.
Preferably, the magnitude of voltage of reference voltage VcA and VcB equates to the magnitude of voltage of the drain voltage of T105-K substantially with driving transistors T105-1.Utilize such structure, produce the current mirror circuit that transistor T 104A and T104B and driving transistors T105-1 form to T105-K by bias voltage and repeatedly produce the output current Iout that the drain voltage dependence with reduction influences (early effect), for example generation has the output current of the current value identical with drain current Idrs.
(embodiment 2)
＜be formed on a characteristics of transistor on the chip 〉
Be formed on the threshold voltage that a plurality of transistors on the chip can have linear change.Alternately, in the transistor of a plurality of arrangements, the transistor that provides in the central area has less than the transistorized threshold voltage that is positioned at two ends.In the case, these transistorized transistor characteristics variations are inverted " V " shape pattern.
＜general structure 〉
Fig. 2 illustrates the general structure according to the current driver 2 of the embodiment of the invention 2.Except that the element of the current driver shown in Fig. 11, current driver 2 comprises: supply reference transistor T101RC, cascode amplifier connect transistor T 102RC, reference voltage supplies node N103C, differential amplifier circuit D103C and bias voltage and produce transistor T 104C.That is to say that current driver 2 comprises that another set of supply reference transistor, cascode amplifier connect transistor, reference voltage supplies node, differential amplifier circuit and bias voltage and produce transistor.
Supply reference transistor T101RC, cascode amplifier connect transistor T 102RC and bias voltage generation transistor T 104C is connected in series between power supply node and the ground node.The grid of supply reference transistor T101RC is connected on the grid that reference transistor T101L is set.The grid that the cascode amplifier connects transistor T 102RC is connected on the grid of cascode amplifier connection transistor T 102L.Differential amplifier circuit D103C has to be connected to and connects transistor T 102RC and bias voltage at the cascode amplifier and produce non-inverting input on the node N103C between the transistor T 104C, be connected to the reversed input terminal of reference voltage supplies node N102C and be connected to the lead-out terminal of gate lines G 104.Bias voltage produces transistor T 104C and is connected (H is the natural number that satisfies 1≤H≤K-1) between driving transistors T105-(H) and the driving transistors T105-(H+1).The grid that bias voltage produces transistor T 104C is connected on the gate lines G 104.
Suppose that supply reference transistor T101RC presents and the identical or essentially identical transistor characteristic of reference transistor T101L is set.Suppose that the cascode amplifier connects transistor T 102RC and presents and send out common-base amplifier together and connect the identical or essentially identical transistor characteristic of transistor T 102L.Suppose that bias voltage produces transistor T 104C and presents and driving transistors T105-(H) and/or the identical or essentially identical transistor characteristic of driving transistors T105-(H+1).Suppose that supply reference transistor T101RC, cascode amplifier connect transistor T 102RC and bias voltage generation transistor T 104C moves in the saturation region.
＜current mirror structure 〉
Reference transistor T101L is set and supplies reference transistor T101RC and constituted current mirror circuit.As supply reference transistor T101RA, supply reference transistor T101RC receives the grid voltage Vid of the grid generation that reference transistor T101L is set at grid.Drain current Idrs with current value of determining according to the magnitude of voltage of grid voltage Vid flows through supply reference transistor T101RC.
＜cascode amplifier connects 〉
As supply reference transistor T102RA, the cascode amplifier connects transistor T 102RC receives the grid generation that reference transistor T101L is set at grid grid voltage Vidc.Since supply reference transistor T101RC with reference transistor T101L cascode amplifier be set be connected, the magnitude of voltage of supplying the drain voltage of reference transistor T101RA equals to be provided with the magnitude of voltage of the drain voltage of reference transistor T101L.
＜negative-feedback circuit 〉
The reference voltage supplies node N102C provide reference voltage VcC.Aberration divides amplifier circuit D103A such, differential amplifier circuit D103C is to gate lines G 104 output offset voltage VbiCsC, and reference voltage VcC and the definite magnitude of voltage of the voltage difference between the drain voltage VrbC that node N103C produces that provides according to reference voltage supplies node N102C is provided this bias voltage VbiCsC.It is such that kine bias is put voltage generation transistor T 104A, and bias voltage produces transistor 104C and receives the bias voltage VbiasC that is exported by differential amplifier circuit D103C at grid.Therefore, the resistance value of the channel resistance of bias voltage generation transistor T 104C changes according to the variation of the magnitude of voltage of bias voltage VbiCsC.Utilize this structure, the drain voltage VrbC at node N103C place the reference voltage VcC that provides with reference voltage supplies node N102C is provided equates.
Connecting the grid voltage of transistor T 102RC and drain voltage that bias voltage produces transistor T 104C at the cascode amplifier is under the identical voltage condition, for example, reference voltage VcC is in and makes cascode amplifier connection transistor T 102RC and bias voltage produce the level that transistor T 104C can move in the saturation region.
＜operation 〉
Next the operation of the current driver shown in the key diagram 22.Produce the performed operation of transistor T 104C except that connecting transistor T 102RC, reference voltage supplies node N102C, differential amplifier circuit D103C and bias voltage by supply reference transistor T101RC, cascode amplifier, the operation of current driver 2 is identical with the current driver 1 shown in Fig. 1.
At first, supply reference transistor T101RC receives the grid voltage Vid that grid that reference transistor T101L is set produces at grid, and the cascode amplifier connects transistor T 102RC and receives the grid voltage Vidc that grid that the cascode amplifier connects transistor T 102L produces at grid.Like this, drain current Idrs flows through supply reference transistor T101RC, the cascode amplifier connects transistor T 102RC and bias voltage produces transistor T 104C, and this drain current Idrs has the magnitude of voltage according to grid voltage Vid, the magnitude of voltage of grid voltage Vidc and the definite current value of magnitude of voltage of bias voltage VbiasC.Meanwhile, produce drain voltage VrbC at node N103C with magnitude of voltage of determining according to the current value of drain current Idrs.
Then, the reference voltage VcC that provides from reference voltage supplies node N102C is provided at reversed input terminal differential amplifier circuit D103C, be received in the drain voltage VrbC that node N103C produces at non-inverting input, and bias voltage VbiasC is outputed to gate lines G 104, and this bias voltage VbiasC has the magnitude of voltage of determining according to the difference between the magnitude of voltage of the magnitude of voltage of reference voltage VcC and drain voltage VrbC.The bias voltage VbiasC that outputs to gate lines G 104 produces transistor T 104C by bias voltage and receives.Like this, the resistance value of the channel resistance of bias voltage generation transistor T 104C is determined by the magnitude of voltage according to bias voltage VbiasC.Like this, adjust the resistance value that bias voltage produces the channel resistance of transistor T 104C by bias voltage VbiasC, the feasible current value that flows through the drain current Idrs of bias voltage generation transistor T 104C becomes and approaches the current value of reference current Iref.
Then, produce transistor T 104A and bias voltage produces the part of extending between the transistor T 104C at bias voltage, the current potential of gate lines G 104 has by carry out the value that linear interpolation obtains between the magnitude of voltage of the magnitude of voltage of bias voltage VbiasA and bias voltage VbiasC.Produce transistor T 104C and bias voltage produces the part of extending between the transistor T 104B at bias voltage, the current potential of gate lines G 104 has by carry out the value that linear interpolation obtains between the magnitude of voltage of the magnitude of voltage of bias voltage VbiasC and bias voltage VbiasB.
Like this, output current flows in driving transistors T105-1 each in the T105-K, and this output current has according to the definite current value of the magnitude of voltage that is applied to voltage on the transistorized grid (current potential at the tie point place of grid and gate lines G 104).
Here, suppose that driving transistors T105-1 presents inverted " V " shape characteristic to the transistor characteristic of T105-K, wherein driving transistors T105-H is positioned at the summit (part between driving transistors T105-1 and T105-(H) and the part between driving transistors T105-(H) and T105K, transistor characteristic linear change) of " V ".In the case, the variation of the transistor characteristic of the part between driving transistors T105-1 and the T105-(H) is biased voltage VbiasA and bias voltage VbiasB offsets, and the variation of the transistor characteristic of the part between driving transistors T105-(H) and the T105K is biased voltage VbiasC and bias voltage VbiasB offsets.
As mentioned above, not only provide basis at the driving transistors T105-1 at K driving transistors two ends and definite bias voltage VbiasA and the bias voltage VbiasB of transistor characteristic of T105K to gate lines G 104, also provide according to being positioned at gate lines G 104 centre positions (here, the bias voltage (bias voltage VbiasC here) that the transistor characteristic of the driving transistors driving transistors T105-(H)) is determined.Utilize this structure, the current potential of gate lines G 104 is set to according to the variation of the transistor characteristic of driving transistors T105-1 in the T105K and definite current potential.
＜effect 〉
As mentioned above, not only to the two ends of gate lines G 104, also provide bias voltage (here to the centre position of gate line, VbiasC is applied on the centre position), make the current potential of gate lines G 104 have and definite value according to the variation of the transistor characteristic of driving transistors T105-1 in the T105K.Like this, flowing through driving transistors T105-1 is controlled to be accurately to the output current Iout of T105-K and is had identical current value.
As supply reference transistor T101RA, supply reference transistor T101RC preferably be disposed in be provided with reference transistor T101L near.As supply reference transistor T102RA, the cascode amplifier connect transistor T 102RC preferably be disposed in the cascode amplifier connect transistor T 102L near.Bias voltage produce transistor T 104C preferably be disposed in driving transistors T105-(H) and/or driving transistors T105-(H+1) near.
In the example of the embodiment 2 of above-mentioned explanation, produce transistor although only inserted a cover supply reference transistor, cascode amplifier connection transistor, reference voltage supplies node, differential amplifier circuit and bias voltage, can insert two cover and these elements of more covers.Utilize this structure, flow through driving transistors T105-1 and be controlled to be more accurately to the output current Iout of T105-K and have identical current value.
(embodiment 3)
＜general structure 〉
Fig. 3 illustrates the general structure according to the current driver 3 of the embodiment of the invention 3.Except that the element of the current driver shown in Fig. 11, current driver 3 comprises: cascode amplifier transistor T301CA, T302CA, T303CA and T304CA, voltage limit transistor T 103A and T103B and K output voltage limit transistor T305-1 are to T305-K.
Cascode amplifier transistor T301CA is connected in series between power supply node and the ground node to T304CA.Cascode amplifier transistor T301CA is connected between power supply node and the cascode amplifier transistor T302CA, and has the grid that is connected on the grid that reference transistor T101L is set.Cascode amplifier transistor T302CA is connected between cascode amplifier transistor T301CA and the cascode amplifier transistor T303CA, and has the grid on the grid that is connected to cascode amplifier connection transistor T 102L.Cascode amplifier transistor T303CA is connected between cascode amplifier transistor T302CA and the cascode amplifier transistor T304CA, and has the grid on the drain and gate line G304 that is connected to cascode amplifier transistor T303CA.Cascode amplifier transistor T304CA is connected between cascode amplifier transistor T303CA and the ground node, and the grid of cascode amplifier transistor T304CA is connected to each other with drain electrode.
Voltage limit transistor T 103A is connected node N103A and bias voltage produces between the transistor T 104A, and has the grid on gate lines G of being connected to 304.Voltage limit transistor T 103B is connected node N103B and bias voltage produces between the transistor T 104B, and has the grid on gate lines G of being connected to 304.
Output voltage limit transistor T305-1 is connected output node OUT and driving transistors T105-1 between the T105-K to T305-K.Output voltage limit transistor T305-1 is connected on the gate lines G 304 to the grid of T305-K.
Suppose that cascode amplifier transistor T301CA presents and the identical or essentially identical transistor characteristic of reference transistor T101L is set.Suppose also that cascode amplifier transistor T302CA presents and send out common-base amplifier together and connect the identical or essentially identical transistor characteristic of transistor T 102L.Suppose that also cascode amplifier transistor T303CA, voltage limit transistor T 103A, output voltage limit transistor T305-1 present identical or essentially identical transistor characteristic to T305-K with voltage limit transistor T 103B.Suppose that also cascode amplifier transistor T304CA presents the identical or essentially identical transistor characteristic with bias voltage generation transistor T 104A.
＜current mirror structure 〉
Reference transistor T101L is set and cascode amplifier transistor T301CA has constituted current mirror circuit.As supply reference transistor T101RA, cascode amplifier transistor T301CA receives the grid voltage Vid of the grid generation that reference transistor T101L is set at grid.Like this, drain current Idb flows through cascode amplifier transistor T301CA, and this drain current Idb has the current value of determining according to the magnitude of voltage of grid voltage Vid.
＜cascode amplifier connects 〉
As supply reference transistor T102RA, cascode amplifier transistor T302CA receives the grid voltage Vidc of the grid generation that reference transistor T101L is set at grid.Because cascode amplifier transistor T301CA sends out common-base amplifier transistor T 302CA cascode amplifier together and connects, the magnitude of voltage of the drain voltage of cascode amplifier transistor T301CA equals to be provided with the magnitude of voltage of the drain voltage of reference transistor T101L.
Grid at cascode amplifier transistor T304CA produces grid voltage Vido1a.Grid at cascode amplifier transistor T303CA produces grid voltage Vido2a, and this grid voltage Vido2a has the magnitude of voltage of determining according to the current value of drain current Idb.
Voltage limit transistor T 103A receives the grid voltage Vido2a of the grid generation of cascode amplifier transistor T303CA at grid.Output voltage limit transistor T305-1 each in the T305-K all receives the grid voltage Vido2a that the grid of cascode amplifier transistor T303CA produces at grid.Voltage limit transistor T 103B receives the grid voltage Vido2a of the grid generation of cascode amplifier transistor T303CA at grid.
Bias voltage produces transistor T 104A, driving transistors T105-1 and produces each the magnitude of voltage of drain voltage among the transistor T 104B to T105-K and bias voltage, all equals the magnitude of voltage of the grid voltage Vido1a of cascode amplifier transistor T304CA.
＜operation 〉
Next the operation of the current driver shown in the key diagram 33.Except that by cascode amplifier transistor T301CA to T304CA, voltage limit transistor T 103A and T103B and output voltage limit transistor T305-1 to the performed operation of T305-K, the operation of current driver 3 is identical with the current driver 1 shown in Fig. 1.
At first, cascode amplifier transistor T301CA receives the grid voltage Vid that grid that reference transistor T101L is set produces at grid, and cascode amplifier transistor T302CA receives the grid voltage Vidc that grid that the cascode amplifier connects transistor T 102L produces at grid.Like this, have according to the magnitude of voltage of grid voltage Vidc and the drain current Idb of definite current value flows through cascode amplifier transistor T301CA to T304CA.Grid at cascode amplifier transistor T303CA produces grid voltage Vido2a, and produces grid voltage Vido1a at the grid of cascode amplifier transistor T304CA.
Next, gate lines G 304 receives the grid voltage Vido2a of the grid generation of cascode amplifier transistor T303CA.Voltage limit transistor T 103A receives the grid voltage Vido2a that offers gate lines G 304 at grid.As voltage limit transistor T 103A, output voltage limit transistor T305-1 each in T305-K and the voltage limit transistor T 103B is all at grid receiving grid pole tension Vido2a.Because voltage limit transistor T 103A and voltage limit transistor T 103B and output voltage limit transistor T305-1 are provided identical grid voltage Vido2a to the grid of T305-K, then reduced the variation of bias voltage generation transistor T 104A and T104B and driving transistors T105-1 drain voltage in the T105-K.
＜drain voltage is set 〉
For example, by obtaining suitable transistor performance to T305-K, prevent that each the source voltage in these transistors from being changed widely for cascode amplifier transistor T303CA, voltage limit transistor T 103A and T103B and output voltage limit transistor T305-1.
Specifically describe obtaining of transistor performance below.
Ids=(β/2) (Vgs-Vt) 2... (expression formula 1)
Ids wherein: drain current, Vgs: grid voltage, Vt: threshold voltage.
The μ Cox of β=(W/L) ... (expression formula 2)
W wherein: channel length, L: channel width, μ: electron mobility, Cox: grid capacitance.
β/2=500 (μ A/V 2) ... (expression formula 3)
Usually, flow through the current value of transistor drain electric current by expression formula 1 expression.Should be noted that " β " in the expression formula 1 is the parameter by the performance transistor performance of expression formula 2 expressions., suppose that voltage limit transistor T 103A and T103B and output voltage limit transistor T305-1 are provided so that to the transistor performance of T305-K here, as illustrated in the expression formula 3, β/2 approximate 500 (μ A/V greatly 2).In the case, change to " 10 μ A " to the current value of the output current Iout of T105-K from " 1 μ A " even flow through driving transistors T105-1, the voltage Vgs between grid and the source electrode only changes 0.1V.Under the variation of this level, because the variation of the drain current (=output current Iout) that the drain voltage dependence causes is less.
＜effect 〉
As mentioned above, in current driver 3, bias voltage produces transistor T 104A and T104B and the driving transistors T105-1 drain voltage to T105-K, is provided with to T305-K by voltage limit transistor T 103A and T103B and output voltage limit transistor T305-1.Utilize this structure, reduced because the variation of the current value of the output current Iout that the drain voltage dependence causes.Like this, flowing through driving transistors T105-1 is controlled to be accurately to the output current Iout of T105-K and is had identical current value.
(embodiment 4)
The variation of the current potential of＜gate lines G 304 〉
Output voltage limit transistor T305-1 is connected on the display element circuit (not shown) by output node OUT to the drain electrode of T305-K.Therefore, the variation of load capacitance might cause the variation of the drain voltage of output voltage limit transistor T305-1 each in the T305-K in the display element circuit.In the case, by might cause the variation of the current potential of gate lines G 304 to the capacitive coupling of the electric capacity between the drain and gate of T305-K at output voltage limit transistor T305-1.
＜general structure 〉
Fig. 4 illustrates the general structure according to the current driver 4 of the embodiment of the invention 4.Except that the element of the current driver shown in Fig. 33, current driver 4 comprises: cascode amplifier transistor T301CB, T302CB, T303CB and T304CB and differential amplifier circuit D401.Should be noted that the grid of voltage limit transistor T 103B is connected on the grid of cascode amplifier transistor T303CB.Output voltage limit transistor T305-1 is connected on the gate lines G 304 to the grid of T305-K.
Cascode amplifier transistor T301CB is connected in series between power supply node and the ground node to T304CB.
Cascode amplifier transistor T301CB is connected between power supply node and the cascode amplifier transistor T302CB, and has the grid that is connected on the grid that reference transistor T101L is set.Cascode amplifier transistor T302CB is connected between cascode amplifier transistor T301CB and the cascode amplifier transistor T303CB, and has the grid on the grid that is connected to cascode amplifier connection transistor T 102L.
Cascode amplifier transistor T303CB is connected between cascode amplifier transistor T302CB and the cascode amplifier transistor T304CB, and the grid of cascode amplifier transistor T303CB is connected to each other with drain electrode.Cascode amplifier transistor T304CB is connected between cascode amplifier transistor T303CB and the ground node, and the grid of cascode amplifier transistor T304CB is connected to each other with drain electrode.
Differential amplifier circuit D401 is a voltage follower circuit, has non-inverting input on the grid that is connected to cascode amplifier transistor T303CA, and is connected to the lead-out terminal of circuit D401 and the reversed input terminal on the gate lines G 304.
Suppose that cascode amplifier transistor T301CB presents and the identical or essentially identical transistor characteristic of reference transistor T101L is set.Suppose also that cascode amplifier transistor T302CB presents and send out common-base amplifier together and connect the identical or essentially identical transistor characteristic of transistor T 101L.Suppose that also cascode amplifier transistor T303CB presents the identical or essentially identical transistor characteristic with voltage limit transistor T 103B.Suppose that also cascode amplifier transistor T304CB presents the identical or essentially identical transistor characteristic with bias voltage generation transistor T 104B.
＜operation 〉
Next the operation of the current driver shown in the key diagram 44.Except that by cascode amplifier transistor T301CB to the performed operation of T304CB, voltage limit transistor T 103B and differential amplifier circuit D401, the operation of current driver 4 is identical with the current driver 3 shown in Fig. 3.
At first, cascode amplifier transistor T301CB sends out common-base amplifier transistor T 301CA together to T304CB and carries out identical operations to T304CA.Therefore, the grid at cascode amplifier transistor T303CB produces grid voltage Vido2b.
Differential amplifier circuit D401 receives the grid voltage Vido2a that the grid of cascode amplifier transistor T303CA produces, and according to the magnitude of voltage of grid voltage Vido2a, output voltage is outputed on the gate lines G 304.
The output voltage that gate lines G 304 receives from differential amplifier circuit D401.
The variation of＜gate lines G 304 current potentials 〉
Because the output impedance of differential amplifier circuit is low, can reduce because the variation of gate lines G 304 current potentials that capacitive coupling causes.
＜effect 〉
As mentioned above, by the output voltage from differential amplifier circuit D401 is provided on the gate lines G 304, reduced the impedance of gate lines G 304.Thereby reduced the variation of the current potential of gate lines G 304.Like this, flowing through driving transistors T105-1 is controlled to be accurately to the output current Iout of T105-K and is had identical current value.
(embodiment 5)
＜general structure 〉
Fig. 5 illustrates the general structure according to the current driver 5 of the embodiment of the invention 5.Except omitted reference current supply node N102A and N102B from the structure of Fig. 4, current driver 5 has the structure identical with the current driver 4 shown in Fig. 4.Non-inverting input of differential amplifier circuit D103A is connected on the node N401A between cascode amplifier transistor T302CA and the cascode amplifier transistor T303CA.The reversed input terminal of differential amplifier circuit D103B is connected on the node N401B between cascode amplifier transistor T302CB and the cascode amplifier transistor T303CB.
Differential amplifier circuit D103A outputs to bias voltage VbiasA on the gate lines G 104, and this bias voltage VbiasA has according to drain voltage (grid voltage Vido2a) that produces at node N401A and the definite magnitude of voltage of the voltage difference between the drain voltage VrbA that node N103A produces.
Differential amplifier circuit D103B outputs to bias voltage VbiasB on the gate lines G 104, and bias voltage VbiasA has according to drain voltage (grid voltage Vido2b) that produces at node N401B and the definite magnitude of voltage of the voltage difference between the drain voltage VrbB that node N103B produces.
＜operation 〉
Next the operation of the current driver shown in the key diagram 55.Except that by the performed operation of differential amplifier circuit D103A and D103B, the operation of current driver 5 is identical with the current driver 4 shown in Fig. 4.
Differential amplifier circuit D103A outputs to bias voltage VbiasA on the gate lines G 104, and bias voltage VbiasA has according to drain voltage that produces at node N401A and the definite magnitude of voltage of the voltage difference between the drain voltage VrbA that node N103A produces.Bias voltage produces transistor T 104A and receives from the bias voltage VbiasA of differential amplifier circuit D103A output at grid.Therefore, the resistance value of the channel resistance of bias voltage generation transistor T 104A changes according to the variation of the magnitude of voltage of bias voltage VbiasA.Like this, the drain voltage VrbA at node N103A place is controlled as with the drain voltage that produces at node N401A and equates.
Differential amplifier circuit D103B outputs to bias voltage VbiasB on the gate lines G 104, and this bias voltage VbiasB has voltage difference between the drain voltage VrbB that the drain voltage that produces according to node N401B and node N103B produce and definite magnitude of voltage.Bias voltage produces transistor T 104B and receives from the bias voltage VbiasB of differential amplifier circuit D103B output at grid.Therefore, the resistance value of the channel resistance of bias voltage generation transistor T 104B changes according to the variation of the magnitude of voltage of bias voltage VbiasB.Like this, the drain voltage VrbB at node N103B place is controlled as with the drain voltage of node N401B generation and equates.
＜effect 〉
As mentioned above, in current driver 5, under the situation that is not used in the specialized voltages generation circuit that produces reference voltage VcA and VcB, voltage Vido2a (Vido2b) is provided on the reversed input terminal of differential amplifier circuit D103A (D103B).Therefore, the voltage generation circuit that is used to produce reference voltage VcA and VcB is unnecessary, thereby can reduce the scale of circuit.
(embodiment 6)
＜common the current driver that adopts 〉
In order to have the drive current of any grey level to display element circuit (organic EL) output of a pixel, current driver has switch at display element circuit and driving transistors T105-1 between the T105-K.These switches are opened/turned off to grey level according to the video data of a pixel.For example, be under the situation of 4 Bit datas (16 grey levels) at video data, for a pixel provides 15 driving transistorss.Be connected these 15 driving transistors T105-1 to being 15 switches between the display element circuit of a T105-15 and a pixel.Flowing through driving transistors T105-1 in 15 output current Iout of T105-15, the number that offers the output current Iout of display element circuit is determined by opening/turn off 15 switches.Utilize this mechanism, the drive current of 16 grey levels is exported to display element circuit (organic EL).
A kind of alternative structure is arranged, wherein between the corresponding display element circuit of a driving transistors (T105-1) and a pixel, connect switch, at two driving transistors (T105-2, T105-3) and between the corresponding display element circuit connect switch, between the display element circuit of four driving transistorss (T105-4 is to T105-7) and correspondence, connect switch, and between the display element circuit of eight driving transistorss (T105-8 is to T105-15) and correspondence, connect switch.Yet, the explanation of omitting this alternative structure here.
＜general structure 〉
Fig. 6 illustrates the general structure according to the current driver 6 of the embodiment of the invention 6.Except current driver 6 comprise switching transistor T605-1 to T605-K and replace output voltage limit transistor T305-1 shown in Fig. 4 to phase inverter (inverter) the circuit 606-1 of T305-K to 606-K, current driver 6 has the structure identical with the current driver 4 shown in Fig. 4.Switching transistor T605-1 each in the T605-K all is connected corresponding output node OUT and driving transistors T105-1 in the T105-K between the corresponding transistor, and has the grid on the lead-out terminal that is connected to inverter circuit 606-1 corresponding inverter circuit in the 606-K.Inverter circuit 606-1 each in the 606-K all has two voltage input end, and one (H-level voltage input terminal) is connected on the gate lines G 304, and another (L-level voltage input terminal) is connected on the ground node.Inverter circuit 606-1 each in the 606-K is all according to from the control signal output H-level signal of external unit and any in the L-level signal.Control signal is represented ON or OFF.The current potential of H-level signal equals the current potential (current potential at the H-level voltage input terminal of inverter circuit and gate lines G 304 tie point places) of H-level voltage input terminal here.The current potential of L-level signal equals the current potential (current potential of ground node) of L-level voltage input terminal here.
Should be noted that, suppose that switching transistor T605-1 presents identical with T103B with voltage limit transistor T 103A or essentially identical transistor characteristic to T605-K.
＜operation 〉
Next the operation of the current driver shown in the key diagram 66.Except that by switching transistor T605-1 to T605-K and inverter circuit 606-1 to the performed operation of 606-K, the operation of current driver 6 is identical with the current driver 4 shown in Fig. 4.Because switching transistor T605-1 has identical structure to same structure and the inverter circuit 606-1 that T605-K has to 606-K, describe as example with the operation of carrying out by switching transistor T605-1 and inverter circuit 606-1 below.
[if control signal is represented " ON "]
At first the control signal of explanation expression " ON " inputs to the situation of inverter circuit 606-1.
In the case, inverter circuit 606-1 outputs to the H-level signal on the grid of switching transistor T605-1.That is to say that the grid of switching transistor T605-1 is provided to the H-level voltage input terminal of inverter circuit and the current potential (=grid voltage Vido2a) at gate lines G 304 tie point places.Like this, the magnitude of voltage of the drain voltage of driving transistors T105-1 equals the magnitude of voltage that bias voltage produces the drain voltage of transistor T 104A.
[if control signal is represented " OFF "]
Next the control signal of explanation expression " OFF " is transfused to the situation to inverter circuit 606-1.
In the case, inverter circuit 606-1 outputs to the L-level signal on the grid of switching transistor T605-1.Therefore, switching transistor T605-1 is not activated.
Like this, in T605-K, the transistor of activation has and is set to " Vido2b-Vt (Vt: " the source voltage threshold voltage of switching transistor) at switching transistor T605-1.
＜effect 〉
As mentioned above, in T105-K, be set to identical magnitude of voltage at driving transistors T105-1 from the drain voltage of the driving transistors of wherein exporting output current Iout.Utilize this structure, reduced because the variation of the current value of the output current Iout that the drain voltage dependence causes.Like this, flowing through driving transistors T105-1 is controlled to be accurately to the output current Iout of T105-K and is had the same electrical flow valuve.
The structure that is used to be provided with the drive current that driving transistors T105-1 offers display element circuit (organic EL) to the structure and the generation of the drain voltage of T105-K is shared the element that repeats.Therefore, reduced the circuit scale of current driver.
(embodiment 7)
＜general structure 〉
Replace current-voltage converter (inverter) 700a supply reference transistor T101RA shown in Fig. 1, shown in Fig. 7 except that the current driver of embodiment 7 comprises, have the structure identical with the current driver 1 shown in Fig. 1 according to the current driver of the embodiment of the invention 7.Current-voltage converter 700a comprises that P current-voltage conversioning transistor T701-1 is to T701-P (P is a natural number).Current-voltage conversioning transistor T701-1 each in the T701-P all is connected between power supply node and the node N103A (Fig. 1), and has the grid that is connected on the grid that reference transistor T101L (Fig. 1) is set.
＜operation 〉
Next the operation of the current-voltage converter 700a shown in the key diagram 7A.
Current-voltage conversioning transistor T701-1 each in the T701-P all receives at grid the grid voltage Vid that produces on the grid of reference transistor T101L (Fig. 1) is set.Therefore, the drain current I701-1 that has according to the definite current value of the magnitude of voltage of grid voltage Vid flows through current-voltage conversioning transistor T701-1 respectively to T701-P to I701-P.Therefore, drain current I701-1 flows through bias voltage generation transistor T 104A to the summation of I701-P.
＜effect 〉
As mentioned above, supply reference transistor T101RA is formed by a plurality of transistors.Utilize this structure, the influence that the transistorized transistor characteristic that has reduced to comprise among the supply reference transistor T101RA changes.Further, current-voltage conversioning transistor T701-1 to T701-P be disposed in each other near, further reduced the variation of transistor characteristic thus.
Should be noted that current-voltage conversioning transistor T701-1 can have or not have identical transistor characteristic to T701-P.
Even also can obtain above-mentioned effect when replacing current-voltage converter 700a supply reference transistor T101RB, shown in Fig. 7 A when the current driver shown in Fig. 1 comprises.In the case, current-voltage conversioning transistor T701-1 each in the T701-P all is connected between power supply node and the node N103B, and has the grid that is connected on the grid that reference transistor T101L is set.
＜distortion 〉
Also have a kind of structure also to be fine, wherein the current driver shown in Fig. 11 comprises and replaces being provided with current-voltage converter 700b reference transistor T101L, shown in Fig. 7 B.Current-voltage converter 700b comprises that Q current-voltage conversioning transistor T702-1 is to T701-Q (Q is a natural number).Current-voltage conversioning transistor T702-1 each in the T701-Q all is connected between power supply node and the reference current input node N101 (Fig. 1), and the grid of each current-voltage conversioning transistor and source electrode are connected to each other.The drain electrode (grid) of current-voltage conversioning transistor T702-1 each in the T701-Q all is connected on the grid of reference current input node N101 and supply reference transistor T101RA and T101RB.Utilize this structure, reduced to be provided with the influence that the transistor characteristic of reference transistor T101L changes.
A kind of alternative structure also is fine, and wherein the current driver shown in Fig. 11 comprises the supply reference transistor T101RA and current-voltage converter 700a T101RB, Fig. 7 A that current-voltage converter 700b reference transistor T101L, Fig. 7 B are set and replace Fig. 1 that replaces Fig. 1.That is to say, Fig. 1 be provided with among reference transistor T101L and supply reference transistor T101RA and the T101RB each all form by a plurality of transistors.In the case, preferably, the transistor that comprises among the transistor that comprises among the transistor that comprises among the reference transistor T101L, the supply reference transistor T101RA and the supply reference transistor T101RB is set is distributed evenly on the chip.Utilize this structure, the variation that the transistorized transistor characteristic that comprises among reference transistor T101L and supply reference transistor T101RA and the T101RB is set is consistent.Like this, reduced the influence that transistorized transistor characteristic changes.
(embodiment 8)
＜general structure 〉
Except that the current driver of embodiment 8 comprises the bias voltage adjustment member 800 supply reference transistor T101RA that replaces Fig. 1, shown in Fig. 8, have the structure identical with the current driver 1 shown in Fig. 1 according to the current driver of the embodiment of the invention 8.Bias voltage adjustment member 800 produces drain current Idrs according to the grid voltage Vid that reference transistor T101L is set.
The inner structure of＜bias voltage adjustment member 800 〉
Bias voltage adjustment member 800 comprises: current-voltage converting unit 801, power supply 802, condition storage unit 803 and condition control circuit 804.
Current-voltage converting unit 801 comprise the current-voltage conversioning transistor T701-1 shown in Fig. 7 A to T701-P and (P-1) individual selection transistor S801-2 to S801-P.Select transistor S801-2 corresponding one by one with current-voltage conversioning transistor T701-2 to T701-P to S801-P.Select transistor S801-2 to be connected corresponding current-voltage conversioning transistor T701-2 between T701-P and the node N103A, come from the control signal CT-2 of condition control circuit 804 to CT-P to receive at grid to S801-P.
At control signal CT-2 when CT-P is in the L level, these signals are to be used for activating the voltage of selection transistor S801-2 to S801-P (PMOS transistor), and at control signal CT-2 when CT-P is in the H level, these signals are to be used to make select the voltage of transistor S801-2 to the S801-P inactivation.
Power supply 802 provides to condition control circuit 804 and condition storage unit 803 and reads voltage.Reading voltage is the voltage that is used for determining condition storage unit 803 connection status.
Condition storage unit 803 comprises that F fuse h8-1 is to h8-F (F is a natural number).Fuse h8-1 each in the h8-F all with when blowing with laser or big electric current, can become non electrically conductive material from conduction and make.Condition storage unit 803 is stored the binary data of F bit by represent fuse h8-1 with binary digit to the state (just, blow or do not blow) of h8-F.In this embodiment, assumed conditions storage unit 803 storage representation current-voltage conversioning transistor T701-2 in the T701-P with the number of transistors purpose binary data that is used.For example, fuse h8-1 be blown and other fuse h8-2 when h8-F is not blown, condition storage unit 803 storage representations are the data of " 1 " with the transistor size that is used.On the other hand, fuse h8-1 and h8-2 is blown and other fuse h8-3 when h8-F is not blown, condition storage unit 803 storage representations are the data of " 3 " with the transistor size that is used.
Condition control circuit 804 enters rigid condition pattern or simulation model according to the control signal CONT from the outside input of circuit.
In the rigid condition pattern, condition control circuit 804 is connected to condition control circuit 804 self to a terminal of the fuse h8-1 that comprises in the condition storage unit 803 each in the h8-F, reads the voltage level of being represented to h8-F by fuse h8-1.Read binary data by this way by state (just, blow or the do not blow) expression of fuse.Condition control circuit 804 is exported control signal CT-2 to CT-P by the binary data that has been read out is decoded.For example, when fuse h8-1 and h8-2 are blown in condition storage unit 803 (just, when expression is that the binary data of " 3 " is when being stored in the condition storage unit 803 with the transistor size that is used), by fuse h8-1 to the voltage level that h8-F represents be " L; L; H ..., H ".In the case, condition control circuit 804 is arranged on control signal CT-2 the L level and other control signal CT-5 is arranged on the H level to CT-P to CT-4.
Under simulation model, condition control circuit 804 is according to the data-signal DATA from the outside input of circuit, and fuse h8-1 and exports control signal CT-2 to CT-P to the state (just, blow or do not blow) of h8-F in the simulated conditions storage unit 803.Data-signal DATA be used for simulated conditions storage unit 803 fuses state (just, blow or do not blow) (being stored in the information in the condition storage unit 803) and show the signal of F voltage level according to the state (just, blow or do not blow) of fuse.For example, under the situation of the state (expression is that the information of " 1 " is stored in the state in the condition storage unit 803 with the transistor size that is used) that data-signal DATA simulation fuse h8-1 is blown, F the voltage level of representing by data-signal DATA be " L; H; H ..., H ".In the case, condition control circuit 804 is arranged on the L level to control signal CT-2, and other control signal CT-3 is arranged on the H level to CT-P.On the other hand, under the situation of the state that data-signal DATA simulation fuse h8-1 and h8-2 are blown, F the voltage level of representing by data-signal DATA be " L, L, H ..., H ".In the case, condition control circuit 804 is arranged on control signal CT-2 the L level and other control signal CT-5 is arranged on the H level to CT-P to CT-4.
＜operation 〉
Present operation with the bias voltage adjustment member 800 shown in the key diagram 8.
[rigid condition pattern]
Receiving when requiring to switch to the control signal CONT of rigid condition pattern, condition control circuit 804 enters the rigid condition pattern.
Then, condition control circuit 804 is connected to condition control circuit 804 self to a terminal of the fuse h8-1 that comprises in the condition storage unit 803 each in the h8-F, and reads the binary data of being represented to h8-F by fuse h8-1.
After this, 804 pairs of binary data that have been read out of condition control circuit are decoded, and control signal CT-2 is outputed to corresponding selection transistor S801-2 respectively to the grid of S801-P to CT-P.
When fuse h8-1 was blown, condition control circuit 804 was arranged on control signal CT-2 the L level and other control signal CT-3 is arranged on the H level to CT-P.Thereby selection transistor S801-2 is activated and current-voltage conversioning transistor T701-2 is connected on the node N103A, so that current-voltage conversioning transistor T701-1 is connected on the node N103A to T701-2.Therefore, the drain current (" 701-1 "+" I701-2 ") that is drain current I701-1 and drain current I701-2 sum flows to bias voltage generation transistor T 104A, drain current I701-1 is determined that by the current mirror ratios that is provided with between reference transistor T101L and the current-voltage conversioning transistor T701-1 drain current I701-2 is determined by the current mirror ratios that is provided with between reference transistor T101L and the current-voltage conversioning transistor T701-2.This makes the bias voltage VbiasA on the grid that is applied to bias voltage generation transistor T 104A be set to the magnitude of voltage definite according to the current value of drain current (" 701-1 "+" I701-2 ").
By this way the binary data that is stored in the condition storage unit 803 is decoded, thereby produce the output state of control signal CT-2 to CT-P.In addition, keep these output states.
[simulation model]
Receiving when requiring to switch to the control signal CONT of simulation model, condition control circuit 804 enters simulation model.
Then, condition control circuit 804 is exported control signal CT-2 to CT-P according to data-signal DATA.
In the case, tentation data signal DATA represents " fuse h8-1 neither one in the h8-F is blown ".So all control signal CT-2 from 804 outputs of condition control circuit are in H level (inactivation) to CT-P.Therefore, select transistor S801-2 neither one in the S801-P to be activated, and current-voltage conversioning transistor T701-2 neither one in the T701-P is connected on the node N103A, thereby has only current-voltage conversioning transistor T701-1 to be connected on the node N103A.Therefore, the drain current I701-1 that is determined by the current mirror ratios that is provided with between reference transistor T101L and the current-voltage conversioning transistor T701-1 flows to bias voltage and produces transistor T 104A.Like this, be applied to bias voltage VbiasA on the grid that bias voltage produces transistor T 104A and be set to the magnitude of voltage determined according to the current value of drain current I701-1.
In the above described manner, according to the fuse h8-1 in the data-signal DATA simulated conditions storage unit 803 (just to the state of h8-F, blow or do not blow), thus, performance between reference transistor T101L and the current-voltage converting unit 801 is set than being provided with arbitrarily.This makes to adjust and flows to the current value that bias voltage produces the drain current Id of transistor T 104A.
＜effect 〉
As mentioned above, condition control circuit 804 is adjusted the performance of current-voltage converting units 801, thus condition (optimal conditions) operation down that allows current driver to be optimised at the state of the output current Iout of driving transistors T105-1 in the T105-K.
In addition, if come the output state of storage control signal CT-2 to h8-F, then remain on the condition of obtaining when output current Iout is in optimum state to CT-P by blow the fuse h8-1 that comprises in the condition storage unit 803 based on simulation result.
In this embodiment, condition storage unit 803 comprises a plurality of fuses, be used for storing the transistor size of being selected to T701-P from current-voltage conversioning transistor T701-1 by condition control circuit 804 (just, control signal CT-2 is to the output state of CT-P).Alternately, yet current driver can have a kind of like this structure, represent that wherein control signal CT-2 is stored in such as also decoded in the medium of DRAM (dynamic RAM) or SRAM (static RAM) to the data of the output state of CT-P, to export control signal CT-2 to CT-P.
Alternately, condition control circuit 804 can use the rigid condition pattern to move as default mode.That is to say that condition control circuit 804 can be always under the rigid condition pattern except that simulation model.
Alternately, the number for the fuse that reduces to be blown can use such setting: the number of the fuse that is blown is increased based on the condition of obtaining when output current is in optimum state.For example, suppose in T701-P any two when being used at current-voltage conversioning transistor T701-1, output current Iout is in optimum state, by fuse h8-1 to the voltage level that h8-F represents be " H, H, H; ...; H " the time, the binary data of storage is decoded in 804 pairs of condition storage unit 803 of condition control circuit, thus control signal CT-2 is in the L level and other control signal CT-4 is in the H level to CT-P to CT-3.
(embodiment 9)
＜general structure 〉
Except that the current driver of embodiment 9 comprises the grid voltage adjustment member 900 supply reference transistor T101RA that replaces Fig. 1, shown in Fig. 9, have the structure identical with the current driver 1 shown in Fig. 1 according to the current driver of the embodiment of the invention 9.Grid voltage adjustment member 900 produces grid voltage, and this grid voltage has the magnitude of voltage of determining according to the current value of reference current Iref.
The inner structure of＜grid voltage adjustment member 900 〉
Grid voltage adjustment member 900 shown in Fig. 9 comprises: current-voltage converting unit 901, power supply 802, condition storage unit 803 and condition control circuit 904.
Current-voltage converting unit 901 comprises: Q select transistor T 702-1 to T702-Q, Q selection transistor Sa901-1 to Sa901-Q and Q selection transistor Sb901-1 to Sb901-Q.Select transistor Sa901-1 to be connected in series between power supply node and the node N905 to Sb901-Q to Sa901-Q and selection transistor Sb901-1.Select transistor Sa901-1 from condition control circuit 904, to receive control signal CTa-1 to CTa-Q at their grid respectively to Sa901-Q.Select transistor Sb901-1 to receive control signal CTb-1 to CTb-Q at their grid from condition control circuit 904 respectively to Sb901-Q.Select transistor T 702-1 to be provided between power supply node and the node N905, and have and be connected respectively to the grid of node N9-1 to the N9-Q to T702-Q.Node N905 is connected on the grid and reference current input node N101 (Fig. 1) of supply reference transistor T101RA and T101RB.
Control signal CTa-1 to CTa-Q and CTb-1 when CTb-Q is in the L level, these signals are to be used for activate selecting the voltage of transistor Sa901-1 to Sa901-Q and Sb901-1 to Sb901-Q (PMOS transistor), and control signal CTa-1 to CTa-Q and CTb-1 when CTb-Q is in the H level, these signals are to be used to make select the voltage of transistor Sa901-1 to Sa901-Q and Sb901-1 to the Sb901-Q inactivation.
Power supply 802 identical with shown in Fig. 8.
Condition storage unit 803 identical with shown in Fig. 8.In this embodiment, assumed conditions storage unit 803 storage representation current-voltage conversioning transistor T701-2 in the T701-P with the number of transistors purpose binary data that is used.For example, fuse h8-1 be blown and other fuse h8-2 when h8-F is not blown, condition storage unit 803 storage representations are the data of " 1 " with the transistor size that is used.On the other hand, fuse h8-1 and h8-2 is blown and other fuse h8-3 when h8-F is not blown, condition storage unit 803 storage representations are the data of " 3 " with the transistor size that is used.
As condition control circuit 804, condition control circuit 904 enters rigid condition pattern or simulation model according to the control signal CONT from the outside input of circuit.
In the rigid condition pattern, as condition control circuit 804, the binary data of storage is decoded in 904 pairs of condition storage unit 803 of condition control circuit, export thus control signal CTa-1 to CTa-Q and CTb-1 to CTb-Q.For example, when fuse h8-1 is blown in condition storage unit 803, condition control circuit 904 is arranged on the H level to control signal CTa-1, control signal CTa-2 is arranged on the L level to CTa-Q, control signal CTb-1 is arranged on the L level, and control signal CTb-2 is arranged on the H level to CTb-Q.
Under simulation model, as condition control circuit 804, condition control circuit 904 is according to the data-signal DATA from the outside input of circuit, fuse h8-1 in the simulated conditions storage unit 803 to the state of h8-F (just, blow or do not blow), thus output control signal CTa-1 to CTa-Q and CTb-1 to CTb-Q.For example, under the situation of the state that data-signal DATA simulation fuse h8-1 and h8-2 are blown, F the voltage level of representing by data-signal DATA be " L, L, H ..., H ".In the case, condition control circuit 904 is arranged on the H level to control signal CTa-1 to CTa-3, control signal CTa-4 is arranged on the L level to CTa-Q, control signal CTb-1 is arranged on the L level to CTb-3, and control signal CTb-4 is arranged on the H level to CTb-Q.
＜operation 〉
Present operation with the grid voltage adjustment member 900 shown in the key diagram 9.
[rigid condition pattern]
Receiving when requiring to switch to the control signal CONT of rigid condition pattern, condition control circuit 904 enters the rigid condition pattern.Then, condition control circuit 904 is connected to condition control circuit 904 self to a terminal of the fuse h8-1 that comprises in the condition storage unit 803 each in the h8-F, and read binary data by fuse state (just, blow or do not blow) expression.After this, 904 pairs of binary data that have been read out of condition control circuit are decoded, and control signal CTa-1 output to CTa-Q and CTb-1 to CTb-Q corresponding selection transistor Sa901-1 to Sa901-Q and Sb901-1 to the grid of Sb901-Q.
When fuse h8-1 was blown, condition control circuit 904 was arranged on L level (activation) to control signal CTb-1 and CTa-2 to CTa-Q, and other control signal CTa-1 and CTb-2 are arranged on H level (inactivation) to CTb-Q.Thereby, select transistor Sa901-1 not to be activated, and select transistor Sb901-1 to be activated, make the grid of current-voltage conversioning transistor T702-1 have identical current potential, and electric current flow through current-voltage conversioning transistor T702-1 with drain electrode.On the other hand, select transistor Sa901-2 to be activated to Sa901-Q, and select transistor Sb901-2 not to be activated to Sb901-Q, make current-voltage conversioning transistor T702-2 have identical current potential, and do not have electric current to flow through current-voltage conversioning transistor T702-2 to T702-Q with internal electric source node Vdd to the grid of T702-Q.That is to say that reference current Iref only flows in current-voltage conversioning transistor T702-1.By this way, the grid voltage Vid that the grid at current-voltage conversioning transistor T702-1 is produced is input on the grid of supply reference transistor T101RA and T101RB.
The output state of the control signal CTa-1 that has reproduced in the condition storage unit 803 storage by this way to CTa-Q and CTb-1 to CTb-Q.In addition, keep these output states.
[simulation model]
Receiving when requiring to switch to the control signal CONT of simulation model, condition control circuit 904 enters simulation model.Then, condition control circuit 904 is according to data-signal DATA, output control signal CTa-1 to CTa-Q and CTb-1 to CTb-Q.
In the case, when the data-signal DATA that is used to simulate the state that fuse h8-2 is blown is imported into condition control circuit 904, condition control circuit 904 is arranged on L level (activation) to control signal CTb-1, CTb-2 and CTa-3 to CTa-Q, and control signal CTa-1, CTa-2 and CTb-3 are arranged on H level (inactivation) to CTb-Q.Thereby selection transistor Sa901-1 is not activated and selects transistor Sb901-1 to be activated, and make grid and the drain electrode of current-voltage conversioning transistor T702-1 have same potential, and electric current flows through current-voltage conversioning transistor T702-1.Because selection transistor Sa901-2 is not activated and select transistor Sb901-2 to be activated, grid and the drain electrode of current-voltage conversioning transistor T702-2 have same potential, and electric current flows through current-voltage conversioning transistor T702-2.On the other hand, select transistor Sa901-3 to be activated and to select transistor Sb901-3 not to be activated to Sb901-Q to Sa901-Q, make current-voltage conversioning transistor T702-3 have the current potential identical, and do not have electric current to flow through current-voltage conversioning transistor T702-3 to T702-Q with power supply node Vdd to the grid of T702-Q.That is to say that reference current Iref only flows in current-voltage conversioning transistor T702-1 and T702-2.By this way, the grid voltage Vid that produces at the grid of current-voltage conversioning transistor T702-1 with at the grid voltage Vid that the grid of current-voltage conversioning transistor T702-2 produces, be input on the grid of supply reference transistor T101RA and T101RB.
Simulated fuse h8-1 in the condition storage unit 803 (just according to data-signal DATA by this way to the state of h8-F, blow or do not blow), thus the magnitude of voltage that is input to the grid voltage Vid that supplies reference transistor T101RA and T101RB adjusted.
＜effect 〉
As mentioned above, condition control circuit 904 is adjusted the performance of current-voltage converting units 901, thus condition (optimal conditions) operation down that allows current driver to be optimised at the state of the output current Iout of driving transistors T105-1 in the T105-K.
In addition, by blow based on simulation result the fuse h8-1 that comprises in the condition storage unit 803 come to h8-F storage control signal CTa-1 to CTa-Q and CTb-1 under the situation of the output state of CTb-Q, remain on the condition of obtaining when output current Iout is in optimum state.
(embodiment 10)
＜general structure 〉
Figure 10 illustrates the general structure according to the display device 10 of the embodiment of the invention 10.Display device 10 comprises: display panel 1001, control section 1002, data driver 1003 and gate drivers 1004.Display device 10 shows the video data (3 Bit datas (=8 grey levels)) on the outside display panel of importing 1001 here.
Display panel 1001 comprises M * N organic EL (M and N are natural numbers), the M of a Yan Shening data line and N gate line of extension in vertical direction in the horizontal direction.Each organic EL all is connected on the corresponding data line by on-off element.The grid of on-off element is connected on the corresponding gate line.That is to say that display panel 1001 is so-called " active matrix " panels.When a gate line is activated, be connected to M on-off element on this gate line coupling together corresponding to the organic EL (organic EL of Pai Lieing in the horizontal direction) of on-off element and corresponding to the data line of on-off element.
When video data D100 that receives outside input and control information CTRL, control section 1002 is exported to data driver 1003 to video data D100, commencing signal START and load signal LOAD, and meanwhile, scan control signal LINE is exported to gate drivers 1004.Video data D100 comprises that other video data of each pixel grayscale of expression D100-1 is to D100-M (data of a horizontal line in the display panel 1001) here.Control information CTRL represents various information, for example Displaying timer etc.Commencing signal START represents the time that data driver 1003 keeps video data D100.Load signal LOAD represents that data driver 1003 produces the time of drive current I100-1 to I100-M.
Data driver 1003 to M the data line that I100-M exports to display panel 1001, is used to drive the organic EL on the display panel 1001 to drive current I100-1 according to the video data 100 from control section 1002 outputs.Gate drivers 1002 is exported to sweep signal SL-1 N gate line of display panel 1001 according to the scan control line LINE from control section 1002 outputs to SL-N (N is a natural number).Should be noted that, data driver 1004 is sequentially exported to N gate line (so-called " row sequential scanning " pattern) to sweep signal SL-1 to SL-N from uppermost gate line here.
The inner structure of＜data driver 1003 〉
Data driver 1003 shown in Figure 10 comprises: the current driver 1 of data latching (latch) part 1011, reference current source 1012, Fig. 1 and M selection part 1013-1 are to 1013-M.
Data latching part 1011 is according to the commencing signal START from control section 1002 outputs, all corresponding to the video data D100-1 of the pixel form to D100-M, preserves the video data D100 that exports from control section 1002 with each.Data latching part 1011 is exported to selection part 1013-1 to the video data D100-1 that preserves to 1013-M to D100-M according to the load signal LOAD from control section 1002 outputs.
Reference current source 1012 offers current driver 1 to reference current Iref.
The reference current Iref that is provided by reference current source 1012 is provided current driver 1, a plurality of output current Iout are exported to select part 1013-1 here to 1013-M (, suppose current driver 1 comprises be used for 8 output current Iout are exported to each 8 * M the driving transistors of selection part 1013-1 to 1013-M).
Selection part 1013-1 all selects the output current Iout to the definite some of D100-M according to the video data D100-1 that exports from data latching part 1011 to 1013-M in 8 output current Iout of current driver 1 output.Select part 1013-1 corresponding one by one with M data line of display panel 1001 to 1013-M.Select part 1013-1 to 1013-M the summation of all output current Iout that select as drive current I100-1 to I100-M, export to the gate line to 1013-M corresponding to selection part 1013-1.
＜operation 〉
Next, export the step of the step of output current Iout, the operating process of the display device 10 shown in Figure 10 is described to the driving organic EL from current driver 1.
At first, current driver 1 is exported to 8 output current Iout and is selected part 1013-1 each in the 1013-M.
Selection part 1013-1 all selects the output current Iout to the definite some of D100-M according to the video data D100-1 that exports from data latching part 1011 to 1013-M in 8 output current Iout of current driver 1 output.For example, when representing " grey level=7 ", select part 1013-1 from 8 output current Iout, to select 7 at video data D100-1.In the case, if the current value of an output current Iout is " Ia ", the current value from the drive current I100-1 that selects part 1013-1 output is " 7 * Ia " so.Therefore, the drive current I100-1 with current value " 7 * Ia " is imported into corresponding in the data line of selecting part 1013-1.Select part 1013-2 to operate with the same manner to 1013-M, make selection part 1013-2 that M data line reception come from correspondence to the drive current I100-2 of 1013-M to I100-M.
Meanwhile, gate drivers 1004 according to from the scan control signal LINE output scanning signal SL-1 of control section 1002 outputs to SL-N.Here, when gate drivers 1004 outputs to sweep signal SL-1 on the gate line of display panel 1001 top lines, M the on-off element that is connected on the gate line of top line is activated, the M of the top line of display panel 1001 organic EL is connected on the corresponding data line thus, flows through the drive current I100-1 of respective data lines to I100-M with reception.
Then, M the organic EL at the top line place of display panel 1001 is luminous to the current value of I100-M according to drive current I100-1.Because I100-1 has respectively according to the grey level of being represented to D100-M by video data D100-1 and definite current value to I100-M, the brightness basis of each in M organic EL is determined by the video data D100-1 grey level that a video data of correspondence is represented in the D100-M.Therefore, the video data D100 that is used for a horizontal line is displayed on the horizontal line at top line place.
By this way all horizontal lines are carried out said process, on display panel 1001, show the video data of 3 bits (=8 grey levels) thus.
＜effect 〉
As mentioned above, current driver 1 is exported the output current Iout with same current value.Select part 1013-1 can produce drive current I100-1 accurately to I100-M, have the current value of determining according to the grey level of representing to D100-M by video data D100-1 to 1013-M.Like this, reduced the emission variation of photocell on the display panel 1001.
Although adopted the current driver 1 of embodiment 1 among this embodiment, can alternatively use any in the current driver (Fig. 2 to 5,7A, 7B, 8 and 9) of embodiment 2 to 5,7 and 8.Under the situation of the current driver 6 (Fig. 6) that uses embodiment 6, selecting part 1013-1 to be connected suitably to 606-K with the inverter circuit 606-1 of Fig. 6 to 1013-M, make to select part 1013-1 each in the 1013-M, according to video data D100-1 corresponding video data in the D100-M, the control signal of expression ON or OFF is exported to corresponding to this selection inverter circuit (or a plurality of inverter circuit) partly.
Although having a horizontal line of display panel 1001 among this embodiment has M pixel and the structure of an organic EL is provided for each pixel, a kind of alternative structure also is fine, wherein with three organic ELs (be used for the R-element organic EL, be used for the organic EL of G-element and be used for the organic EL of B-element) offer a pixel.In the case, video data D100 comprises that M * 3 a video data D100-1 is to D100-(M * 3).Data driver 1003 comprises that 3 current drivers and M * 3 a selection part 1013-1 are to 1013-(M * 3).These three current driver outputs have the output current Iout of the current value that is suitable for R-, G-and B-element.Selecting part 1013-1 in 1013-(M * 3), select part 1013-(3X-2) (X is the natural number that satisfies 1≤X≤M) to receive from output current Iout corresponding to the current driver of R-element, select part 1013-(3X-1) to receive, and select part 1013-(3X) to receive from output current Iout corresponding to the current driver of B-element from output current Iout corresponding to the current driver of G-element.Data latching part 1011 is exported to the video data D100-(3X-2) corresponding to the R-element and is selected part 1013-(3X-2), video data D100-(3X-1) corresponding to the G-element is exported to selection part 1013-(3X-1), and the video data D100-(3X) corresponding to the B-element is exported to selection part 1013-(3X).Utilize this structure, corresponding to the organic EL of R-element, corresponding to the organic EL of G-element with corresponding to the organic EL of B-element, have respectively according to corresponding to the definite brightness of the video data D100-(3X-2) of R-element, according to corresponding to the definite brightness of the video data D100-(3X-1) of G-element with according to the definite brightness of video data D100-(3X) corresponding to the B-element.By this way, adjust the current value of the output current Iout of the current driver output that offers R-, G-and B-element respectively, adjusted the brightness of the organic EL that offers R-, G-and B-element respectively thus respectively.Thereby, adjusted the brightness of each pixel accurately.
Current driver according to the present invention is useful as current drive-type display driver of organic EL panel etc.Current driver of the present invention can be applied to also comprise that a plurality of drive blocks provide accurately with the combination based on current value in the circuit block in the use of printer driver of output current etc.

Claims (24)

1, a kind of current driver comprises:
The first I/O part inputs or outputs first electric current by it;
First bias voltage produces transistor, is connected between this first I/O part and first reference mode;
The second I/O part inputs or outputs second electric current by it;
Second bias voltage produces transistor, is connected between this second I/O part and this first reference mode;
K driving transistors is connected by it and inputs or outputs between the output node and this first reference mode of output current, and wherein K is a natural number;
First grid polar curve, this first bias voltage produce the grid of transistorized grid, a described K driving transistors and this second bias voltage and produce transistorized grid and be connected on it in proper order with this;
First voltage supply node receives first voltage;
First differential amplifier circuit, the output tertiary voltage, this tertiary voltage has the magnitude of voltage that produces second voltage on transistorized first interconnecting nodes according to this first I/O part and first bias voltage, and the definite magnitude of voltage of difference between first magnitude of voltage of first voltage that is received by this first voltage supply node;
Second voltage supply node receives the 4th voltage; With
Second differential amplifier circuit, export the 6th voltage, the 6th voltage has the magnitude of voltage that produces the 5th voltage on transistorized second interconnecting nodes according to this second I/O part and second bias voltage, and the magnitude of voltage that the difference between the 4th magnitude of voltage of the 4th voltage that is received by this second voltage supply node is determined
Wherein this first bias voltage produces transistor and receives the tertiary voltage of being exported by this first differential amplifier circuit at its grid, and
This second bias voltage produces transistor and receives the 6th voltage of being exported by this second differential amplifier circuit at its grid.
2, current driver as claimed in claim 1, further comprise transistor is set, this is provided with transistor and is connected second reference mode and inputs or outputs between the I/O node of reference current by it, and transistorized grid is set for this and drain electrode is connected to each other, wherein:
This first I/O partly comprises first supply transistor, is connected between this second reference mode and this first interconnecting nodes, and the grid of this first supply transistor is connected to this and is provided with on the transistorized grid; And
This second I/O partly comprises second supply transistor, is connected between this second reference mode and this second interconnecting nodes, and the grid of this second supply transistor is connected to this and is provided with on the transistorized grid.
3, current driver as claimed in claim 2, wherein this is provided with transistor and this first and second supply transistor is connected by the cascode amplifier.
4, current driver as claimed in claim 1 further comprises:
The 3rd I/O part inputs or outputs the 3rd electric current by it;
The 3rd bias voltage produces transistor, is connected between the 3rd I/O part and first reference mode;
Tertiary voltage supply node receives the 7th voltage; With
The 3rd differential amplifier circuit, export the 9th voltage, the 9th voltage has the magnitude of voltage that produces the 8th voltage on transistorized the 3rd interconnecting nodes according to the 3rd I/O part and the 3rd bias voltage, and the magnitude of voltage that the difference between the 7th magnitude of voltage of the 7th voltage that is received by this tertiary voltage supply node is determined
Wherein this first bias voltage produces first grid to the H driving transistors, the 3rd bias voltage in transistorized grid, the described driving transistors and produces (H+1) in transistorized grid, the described driving transistors and produce transistorized grid to the grid of K driving transistors and this second bias voltage and be connected in proper order on this first grid polar curve with this, wherein H is the natural number that satisfies 1≤H≤K-1, and
The 3rd bias voltage produces transistor and receives the 9th voltage of being exported by the 3rd differential amplifier circuit at its grid.
5, current driver as claimed in claim 1 further comprises:
K output voltage limit transistor is connected between a described K driving transistors and this output node; With
The second grid line, the grid of described K output voltage limit transistor is connected on it,
Wherein this second grid line receives the deboost with scheduled voltage.
6, current driver as claimed in claim 5 further comprises:
The first voltage limit transistor is connected this first interconnecting nodes and first bias voltage and produces between the transistor; With
The second voltage limit transistor is connected this second interconnecting nodes and second bias voltage and produces between the transistor,
Wherein the grid of the transistorized grid of this first voltage limit, a described K output voltage limit transistor and the transistorized grid of this second voltage limit are connected on this second grid line in proper order with this.
7, current driver as claimed in claim 6 further comprises:
The 3rd I/O part inputs or outputs the 3rd electric current by it; With
The first and second cascode amplifier transistors are connected in series between the 3rd I/O part and this first reference mode,
Wherein this first cascode amplifier transistor is connected between the 3rd I/O part and the second cascode amplifier transistor, and the grid of this first cascode amplifier transistor and drain electrode are connected to each other,
This second cascode amplifier transistor is connected between this first cascode amplifier transistor and this first reference mode, and the grid of this second cascode amplifier transistor and drain electrode are connected to each other, and
This second grid line receives the primary grid voltage at the grid place that results from this first cascode amplifier transistor.
8, current driver as claimed in claim 7, wherein this first and second voltage supply node receives the primary grid voltage at the grid place that results from this first cascode amplifier transistor.
9, current driver as claimed in claim 5 further comprises voltage follower circuit,
Wherein this second grid line receives the output of this voltage follower circuit.
10, current driver as claimed in claim 9 further comprises:
The first voltage limit transistor is connected this first interconnecting nodes and this first bias voltage and produces between the transistor;
The 3rd I/O part inputs or outputs the 3rd electric current by it; With
The first and second cascode amplifier transistors are connected in series between the 3rd I/O part and this first reference mode,
Wherein this first cascode amplifier transistor is connected between the 3rd I/O part and the second cascode amplifier transistor, and the grid of this first cascode amplifier transistor and drain electrode are connected to each other,
This second cascode amplifier transistor is connected between this first cascode amplifier transistor and this first reference mode, and the grid of this second cascode amplifier transistor and drain electrode are connected to each other, and
The transistorized grid of this first voltage limit and this voltage follower circuit receive the primary grid voltage at the grid place that results from this first cascode amplifier transistor.
11, current driver as claimed in claim 10 further comprises:
The second voltage limit transistor is connected this second interconnecting nodes and this second bias voltage and produces between the transistor;
The 4th I/O part inputs or outputs the 4th electric current by it; With
The third and fourth cascode amplifier transistor is connected in series between the 4th I/O part and this first reference mode, and
Wherein the 3rd cascode amplifier transistor is connected between the 4th I/O part and the 4th cascode amplifier transistor, and the grid of the 3rd cascode amplifier transistor and drain electrode are connected to each other,
The 4th cascode amplifier transistor is connected between the 3rd cascode amplifier transistor and this first reference mode, and the grid of the 4th cascode amplifier transistor and drain electrode are connected to each other, and
This second voltage limit transistor receives the second grid voltage at the grid place that results from the 3rd cascode amplifier transistor at its grid.
12, current driver as claimed in claim 11, wherein:
This first voltage supply node receives the primary grid voltage at the grid place that results from this first cascode amplifier transistor; And
This second voltage supply node receives the second grid voltage at the grid place that results from the 3rd cascode amplifier transistor.
13, current driver as claimed in claim 1 further comprises:
K switching transistor is connected between a described K driving transistors and this output node;
K control section is one by one corresponding to a described K switching transistor; With
The second grid line receives the deboost with scheduled voltage,
In the wherein said K control section each all has first pattern and second pattern, and comprises the first terminal that is connected on this second grid line and second terminal that is connected on this first reference mode,
In this first pattern, the voltage on this first terminal is provided on the grid corresponding to the switching transistor of this control section; And
In this second pattern, the voltage on this second terminal is provided on the grid corresponding to the switching transistor of this control section.
14, current driver as claimed in claim 2, wherein:
This first supply transistor is formed by P current-voltage conversioning transistor, and wherein P is a natural number;
Described P current-voltage conversioning transistor is connected in parallel between this second reference mode and this first interconnecting nodes; And
In described P current-voltage conversioning transistor each all receives at its grid and results from the grid voltage that this is provided with transistorized grid place.
15, current driver as claimed in claim 14 further comprises:
Control section is selected N current-voltage conversioning transistor from described P current-voltage conversioning transistor, wherein N is the natural number that satisfies N≤P; With
The coupling part, each that is used for N current-voltage conversioning transistor will being selected by this control section all is connected to this first interconnecting nodes.
16, current driver as claimed in claim 2, wherein:
This is provided with transistor and is formed by P current-voltage conversioning transistor, and wherein P is a natural number;
Described P current-voltage conversioning transistor is connected in parallel between this second reference mode and this I/O node;
In described P current-voltage conversioning transistor each all has by grid connected to one another and drain electrode; And
In this first and second supply transistor each all receives the grid voltage that results from described P current-voltage conversioning transistor place at its grid.
17, current driver as claimed in claim 16 further comprises:
Control section is selected N current-voltage conversioning transistor from described P current-voltage conversioning transistor, wherein N is the natural number that satisfies N≤P; With
The coupling part is used for each at N the current-voltage conversioning transistor of being selected by this control section, grid and drain electrode is connected to each other,
Wherein each in this first and second supply transistor all receives the grid voltage at the grid place that results from described N current-voltage conversioning transistor at its grid, in described N current-voltage conversioning transistor, this grid is connected by this coupling part with drain electrode.
18, current driver as claimed in claim 15 further comprises storage area, is used for the number of transistors purpose information that storage representation will be selected from described P current-voltage conversioning transistor by this control section,
Wherein this control section is selected N current-voltage conversioning transistor according to the information that is stored in this storage area from described P current-voltage conversioning transistor.
19, current driver as claimed in claim 18, wherein:
This storage area comprises a plurality of fuses;
This control section has rigid condition pattern and simulation model;
When this control section moved in this rigid condition pattern, this control section was selected N current-voltage conversioning transistor according to the state of described a plurality of fuses from described P current-voltage conversioning transistor; And
When this control section moved under this simulation model, this control section was simulated the state of described a plurality of fuses, to select N current-voltage conversioning transistor from described P current-voltage conversioning transistor.
20, current driver as claimed in claim 17 further comprises storage area, is used for the number of transistors purpose information that storage representation will be selected from described P current-voltage conversioning transistor by this control section,
Wherein this control section is selected N current-voltage conversioning transistor according to the information that is stored in this storage area from described P current-voltage conversioning transistor.
21, current driver as claimed in claim 20, wherein:
This storage area comprises a plurality of fuses;
This control section has rigid condition pattern and simulation model;
When this control section moved in this rigid condition pattern, this control section was selected N current-voltage conversioning transistor according to the state of described a plurality of fuses from described P current-voltage conversioning transistor; And
When this control section moved under this simulation model, this control section was simulated the state of described a plurality of fuses, to select N current-voltage conversioning transistor from described P current-voltage conversioning transistor.
22, current driver as claimed in claim 2, wherein:
This be provided with in transistor, this first supply transistor and this second supply transistor each all form by a plurality of transistors; And
Forming these a plurality of transistors that transistorized a plurality of transistor are set, form a plurality of transistors of this first supply transistor and form this second supply transistor is distributed evenly on the chip.
23, a kind of data driver comprises:
The described current driver of claim 1;
Select part, be used for the video data according to the outside input, select X output current from K output current by this current driver output, wherein X is the natural number that satisfies X≤K; With
The drive current lead-out terminal is used as drive current from this drive current lead-out terminal output by the summation of X output current of this selection portion component selections,
Wherein this video data is represented grey level.
24, a kind of display device comprises:
The described data driver of claim 23; With
Display panel is by the drive current driving of this data driver output.
CNB2005101347890A 2004-12-21 2005-12-16 Current driver, data driver, and display device Expired - Fee Related CN100495504C (en)

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