CN1784758A - Circuit for trimming locking of integrated circuits - Google Patents
Circuit for trimming locking of integrated circuits Download PDFInfo
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- CN1784758A CN1784758A CN 200480012585 CN200480012585A CN1784758A CN 1784758 A CN1784758 A CN 1784758A CN 200480012585 CN200480012585 CN 200480012585 CN 200480012585 A CN200480012585 A CN 200480012585A CN 1784758 A CN1784758 A CN 1784758A
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- fuse
- locking circuit
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- trimming
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- 238000009966 trimming Methods 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims description 37
- 238000005538 encapsulation Methods 0.000 claims description 14
- 230000000903 blocking effect Effects 0.000 claims description 10
- 238000009413 insulation Methods 0.000 claims description 4
- 230000003068 static effect Effects 0.000 claims 2
- 230000008569 process Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 7
- 229920003023 plastic Polymers 0.000 description 6
- 239000004033 plastic Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
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- Semiconductor Integrated Circuits (AREA)
Abstract
A trimming locking circuit is provided for IC using a programmable fuse array for after-assembly trimming procedures. In one embodiment, a trimming locking circuit is provided for a single power supply input into the programmable fuse array. In another embodiment, a trimming locking circuit is provided to operate with two or more power supply inputs. The trimming locking circuit electrically isolates the programmable fuse array from over voltage conditions on the power supplies.
Description
Technical field
The present invention relates to trimming locking circuit and method after a kind of encapsulation of integrated circuit, particularly a kind of to trimming locking circuit and method after the encapsulation of power management integrated circuit.
Background technology
The IC calibration procedure finishes with a lock step usually after the conventional encapsulation, disconnection calibration block is connected with the package assembling pin, make these pins can be used for other functions, and in the parameter values status after preserving calibration, make the permanent failure of calibration block.Encapsulation back calibration procedure makes IC have a stable parameter, can not unexpectedly be revised again.Conventional IC calibration circuit as depicted in figs. 1 and 2.That shown in Figure 1 is an IC who has single supply voltage pin A (VCC) 5, and shown in Figure 2 be an IC who has two supply voltages, pin A (VCC) 5 and pin B (LVCC) 6.Changing the required electric energy of fuse state is provided by VCC_ calibration node 8, and this node can also can be connected with pin B6 with pin A5.Programmable fuse (perhaps Zener diode) array 2 comes addressing by input calibration data 9.The data of this input comprise the routine data to programmable fuse (perhaps Zener diode) addressing.Each independent fuse output can both obtain from the fuse state output 10 of programmable fuse array block 2.Each fuse cell 4 generally includes a fuse (perhaps Zener diode), a kind of device (being typically a switch) that can change fuse state, and the sensing block (not indicating among the figure) that fuse state output 10 is provided by 9 controls of input calibration data.
The conventional art of these trimming lockings is on the books in some patents.For example, the U.S. Patent number of people such as Russell invention is the patent application of No.5079516, the U.S. Patent number of people such as Shyr invention is the patent application of No.6472897, and the U.S. Patent number of Chen invention is that the French Patent (FRP) of people's inventions such as the patent application of No.6338032 and Laville number is the patent application of No.9908240.Generally speaking, these patents are to realize by suppressing the transmission of input calibration data from package pins to programmable fuse array block 2.
Switch in the fuse cell 4 can comprise a common MOS transistor or a SCR device.In case fuse is adjusted (fusing), this switch just can not the Be Controlled terminal be opened; Therefore in a single day fuse is adjusted, and fuse state just can not be changed.The major defect of this method is that the fuse (perhaps Zener diode) in the fuse cell 4 still keeps being connected with package pins after calibration procedure is finished with controllable switch.Like this, a concurrent abnormal volotage (overvoltage on pin A5 or pin B6, high dv/dt potential pulse, the electrostatic discharge (ESD) pulse) just might open autoeciously in the fuse cell 4 switch (for example, by overflowing, snap back and/or the capacitance of drain effect), and the corresponding fuse that unexpectedly fuses (perhaps making the Zener diode short circuit), the result of change original calibrated operation.This means that above-mentioned locking means is not an overall safety under possible ambient voltage situation.
Put down in writing another kind of trimming locking method in the U.S. Patent number of people such as Russell invention is the patent of No.5079516, in the method, two fuses of each calibration bits all have to be fused.Also need two SCR equipment to lock each calibration bits simultaneously.Therefore, this method will become complicated and will consume bigger chip area.In addition, this locking operation based on blow out fuse will only be only applicable to the cavate encapsulation, that is to say, the typical plastics encapsulation can not be used this locking means.
Summary of the invention
The object of the present invention is to provide a kind of trimming locking circuit and method that Plastic Package also can be used for the cavate encapsulated integrated circuit that both can be used for, calibration procedure after this trimming locking circuit and encapsulation of method application guarantees the safety of align mode under concurrent electrical event.Circuit of the present invention and method can change the physical path of transmission electric energy to programmable fuse.Therefore, no matter be the GN Normal Alignment operation, (ESD EOS) can not revise fuse to still any electrical event that can surpass normal running (operation) conditions, thereby has locked align mode.The present invention can be used in Plastic Package or the cavate packaged integrated circuits.The present invention can use encapsulation back calibration pin, and therefore execution of the present invention can be finished under the condition that does not need auxiliary pin.A spot of assembly can be only used in execution of the present invention.For example, in one exemplary embodiment as herein described, three or four attached integrated components that help can be only used in execution of the present invention: a metal fuse, one or two diode and a resistance.Thereby the present invention can use enforcement polysilicon fuse or Zener diode so that calibration data is encoded with encapsulation back calibration procedure equally.
In an one exemplary embodiment of the present invention, a trimming locking circuit that has single power supply has been described.In this embodiment, the trimming locking circuit that is used to have the integrated circuit of programmable fuse array comprises: be connected to an input pin after a metal fuse and one first blocking diode series connection; Be connected to a power supply after one second blocking diode and a source resistance parallel connection; Wherein said metal fuse, described source resistance and described blocking diode are used for the load of the overvoltage generation of the described input pin appearance of electric insulation.
In another one exemplary embodiment of the present invention, a trimming locking circuit that has two (perhaps a plurality of) power supplys has been described.In this embodiment, a trimming locking circuit that is used to have the integrated circuit of programmable fuse array comprises: a metal fuse and a source resistance parallel connection are connected between a second source and the programmable fuse array power line; Blocking diode reverse bias is connected between this metal fuse and this source resistance and one first power supply; Wherein this metal fuse, source resistance and blocking diode are used for the load of the overvoltage generation of this second source appearance of electric insulation.
What be worth those skilled in the art's attention is that though following detailed is based on most preferred embodiment and the using method thereof that provides, the present invention is not limited only to these embodiment and using method.On the contrary, the scope that the present invention relates to is extensive, and its scope is required to limit by respective right.
Other function and advantage of the present invention will embody by the description of subsequent embodiment, on basis with reference to the accompanying drawings, and with reference to the part of Digital ID among the figure, comprising:
Description of drawings
Figure 1 shows that the circuit diagram of a conventional IC calibration circuit;
Figure 2 shows that the circuit diagram of another kind of conventional IC calibration circuit;
Figure 3 shows that a circuit diagram based on exemplary calibration circuit of the present invention;
Figure 4 shows that another circuit diagram based on exemplary calibration circuit of the present invention;
Figure 5 shows that a circuit diagram based on exemplary programmable fuse array of the present invention.
Embodiment
Content of the present invention will be described below, and with reference to figure 3, Fig. 4 and Fig. 5, these figure have described the main modular of one exemplary embodiment of the present invention.The trimming locking Method and circuits is described respectively according to two kinds of IC types: single supply voltage IC (Fig. 4 and Fig. 5) and two or more supply voltage IC (Fig. 3 and Fig. 5).Say widely, the invention provides a kind of locking calibration circuit that inserts a metal fuse between power circuit and programmable fuse array (polysilicon fuse or Zener diode) that is included in.This metal fuse is selected to keep fusing polysilicon fuse or the required electric current of Zener diode.Use a circuit structure to make that metal fuse is fused, this also is a target of the present invention.In case metal fuse is fused, the electric energy that is transferred to programmable fuse (polysilicon fuse or Zener diode) array just is restricted, and the possibility of the parasitism fusing of such fuse has just fully been reduced.In other words, do not have concurrent stray voltage to transmit enough electric energy, so calibration result is just preserved safely to programmable fuse array.The present invention will be applicable to that calibration process of any use is provided with the integrated circuit of the numerical value of the one or more voltage/current signals that are associated with IC.
Fig. 4 has described an exemplary calibration circuit 100 that uses a metal fuse 33, two diode DLOCK1 32 and DLOCK2 31 and a source resistance 34.Calibration circuit 100 shown in Figure 4 be one based on the example that has the trimming locking circuit of single power supply of the present invention.No matter this circuit can lock calibration process and the figure place (in fuse cell 4) of having calibrated.Fig. 5 has described the concrete frame diagram of this exemplary fuse cell 4.
The power supply of programmable fuse array 2 is to be calibrated on 8 by supplying power to local area power line VCC_ with metal fuse 33 diode in series DLOCK2 31 by pin C14 (being typically the input pin that has nothing to do with calibration procedure among the IC) in back encapsulation calibration process process.The calibration process of a routine is to be carried out by the input calibration data signal 9 that offers switch 42 (shown in Figure 5) by a high impedance path (for example, the mos gate utmost point 46).Programmable fuse array is by high impedance path (for example, the mos gate utmost point) output signal 10.Pin A (VCC) 5 provides the IC standard power supply, and cooperates with pin C (input) 14 in the calibration process process.
In case calibration process is finished, pin A (VCC) 5 just is connected with ground GND7, and the voltage on the pin C14 is enhanced enough big so that fuse metal fuse 33 required electric currents can flow on the pin A (VCC) 5 by DLOCK231, metal fuse 33 and DLOCK1 32 from pin C14.After metal fuse 33 fusing, local VCC_ lubber-line 8 is powered by source resistance 34 by pin A (VCC) 5.The source current of programmable fuse array 2 only needs when detecting the calibration fuse state, so can for source resistance 34 a very big value be set according to coming such as the electric current demand of array of fuses.
During esd event took place the ESD of routine device 13,12, the overvoltage on pin C14 and the pin A5 node just was restricted.At last, after metal fuse 33 was by fusing, programmable fuse array 2 only linked to each other with the pin of package assembling by source resistance 34.Thereby the impedance of source resistance 34 is selected as enough making greatly the parasitic overvoltage (by 12 restrictions of ESD device) on the pin A (VCC) 5 transmit one or more required electric energy of calibration fuse in fuse cell 4 that may fuse can't for local area power line 8.Make encapsulation back trimming locking can prevent possible concurrent over-voltage events like this.When metal fuse 33 quilt fusing (as mentioned above), the input of pin C14 has just been insulated with programmable fuse array 2.Equally, pin C is owing to the hindrance function of diode DLOCK231 also has been insulated.Pin C14 can be used as second function (input) that it has.After metal fuse fusing, only limited electric energy can offer programmable fuse array 2, is not to be exactly the residual impedance that passes through the fuse metal fuse (high impedance, or even in Plastic Package) by source resistance (high impedance).
So this notion is equally applicable to plastic packaged IC.Even metal fuse 33 not exclusively fuses, its residual impedance also will be enough big, and therefore the electric energy that particularly transmits from this paths when overvoltage can't influence the programmable fuse the fuse cell 4.
Fig. 3 is discussed now, and it has described the exemplary calibration circuit 200 of metal fuse of another kind of use 21, a diode DLOCK 22 and a source resistance 23.Calibration circuit 200 shown in Figure 3 be one based on the example that comprises the trimming locking circuit of two power supplys of the present invention.This circuit is used to lock calibration process, and no matter the bit number of having calibrated (in fuse cell 4).Fig. 5 shows the concrete frame diagram of exemplary fuse cell 4.
The power supply of programmable fuse array 2 gives local power supply line VCC_ calibration 8 (normally second constant voltages lower than VCC) by pin B (LVCC) 6 by metal fuse 21 power supplies in the calibration process process after encapsulation.Use the calibration process (as mentioned above) of routine techniques to provide input calibration data signal 9 to switch 42 by a high impedance path (the mos gate utmost point 46) shown in Figure 5.In case calibration process finishes, pin A (VCC) 5 just is connected with ground GND7, and the voltage of pin B6 increases simultaneously, makes fuse metal fuse 21 required electric currents to be transferred on the pin A (VCC) 5 by metal fuse 21 and diode DLOCK22 like this.
After metal fuse 21 fusing, the VCC_ lubber-line 8 of local area is powered by source resistance 23 by pin B (LVCC) 6.The source current of programmable fuse array only needs when detecting the calibration fuse state, so can select a suitable big value for source resistance according to coming such as the electric current demand of array of fuses.
At last, after metal fuse 21 fusing, programmable fuse array 2 only links to each other with the pin of package assembling by source resistance 23, thereby the impedance of this source resistance 23 is selected as enough making greatly the parasitic overvoltage (by 11 restrictions of ESD device) on the pin B (LVCC) 6 can't the fuse in the programmable fuse array 2 be exerted an influence.
Therefore, the accidental electric energy (might one or more calibration fuses in blow out fuse unit 4) that is transferred to local area power line 8 has been prevented from equally.Pin B6 can be used as its specified major function (in this example, pin B is used as the constant voltage source voltage pin) then.This notion is equally applicable to plastic packaged IC.Even metal fuse 21 is not to fuse fully, its residual impedance also impedance than source resistance 23 is big, and the electric energy that transmits from this path when over-voltage events takes place can not influence the programmable fuse the fuse cell 4 yet.
One skilled in the art will recognize that other many improvement of the present invention schemes.For example, the present invention describes a trimming locking circuit of cooperating and using with a programmable fuse array 2.Yet the present invention can be adapted to any load, and therefore, this programmable fuse array can reduce a load at this.In addition, also spoken of a single power supply and duplicate supply topologies here, but the present invention can extend to any amount of power supply equally.
Equally, above-mentioned Fig. 3 and source resistance among Fig. 4 are provided with that relative big resistance is based on the current requirements of programmable fuse array 2 for example and are fixed.It is fixed that the definite resistance of source resistance 34 or source resistance 23 also can be come based on the tolerance of operating environment, selected application and assignment component.Therefore, the term " greatly " in the resistance of the source resistance of being referred to or " big relatively " should be interpreted as can locking according to the principle of setting in advance the selected value of programmable fuse array widely.All these improve all within the spirit and scope of the present invention that are defined by the claims.
Claims (10)
1. be used for a trimming locking circuit that has the integrated circuit of programmable fuse array, it is characterized in that, described trimming locking circuit comprises:
A metal fuse and a source resistance parallel connection are connected between a second source and the programmable fuse array power line;
Blocking diode reverse bias is connected between described metal fuse and described source resistance and one first power supply;
Wherein said metal fuse, described source resistance and described blocking diode are used for the load of the overvoltage generation of the described second source appearance of electric insulation.
2. trimming locking circuit as claimed in claim 1 is characterized in that, described trimming locking circuit also comprises:
An ESD device that is connected between described first power supply and the ground, and the 2nd an ESD device that is connected between described second source and the described ground; Described ESD device be used to suppress described first or the static of second source discharge.
3. trimming locking circuit as claimed in claim 1 is characterized in that: described source resistance has a resistance, selects this resistance to appear at overpressure situation on the described second source with minimizing.
4. trimming locking circuit as claimed in claim 1 is characterized in that: described metal fuse is selected at becomes open circuit under the selected function of current.
5. trimming locking circuit as claimed in claim 1 is characterized in that: calibration procedure after described metal fuse, described source resistance and the described programmable fuse array of described diode applications and encapsulation of described second source execution.
6. be used for a trimming locking circuit that has the integrated circuit of programmable fuse array, it is characterized in that, described trimming locking circuit comprises:
Be connected to an input pin after a metal fuse and one first blocking diode series connection;
Be connected to a power supply after one second blocking diode and a source resistance parallel connection;
Wherein said metal fuse, described source resistance and described blocking diode are used for the load of the overvoltage generation of the described input source appearance of electric insulation.
7. a trimming locking circuit as claimed in claim 6 is characterized in that, described trimming locking circuit also comprises:
An ESD device that is connected between described first power supply and the ground, the 2nd an ESD device that is connected between described input pin and the described ground; The static that described ESD device can suppress on described power supply or the described input pin discharges.
8. a trimming locking circuit as claimed in claim 6 is characterized in that: the resistance of described source resistance is selected to appear at overpressure situation on the described input pin with minimizing.
9. a trimming locking circuit as claimed in claim 6 is characterized in that: selected so that this metal fuse of described metal fuse is under a selected function of current and become open circuit.
10. a trimming locking circuit as claimed in claim 6 is characterized in that: calibration procedure after described metal fuse, described source resistance and the described programmable fuse array of described diode applications and encapsulation of described second input pin execution.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US47120503P | 2003-05-16 | 2003-05-16 | |
| US60/471,205 | 2003-05-16 | ||
| US10/624,295 | 2003-07-22 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1784758A true CN1784758A (en) | 2006-06-07 |
| CN100437870C CN100437870C (en) | 2008-11-26 |
Family
ID=36773867
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004800125853A Expired - Lifetime CN100437870C (en) | 2003-05-16 | 2004-05-13 | Circuit for trimming locking of integrated circuits |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100437870C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106033107A (en) * | 2015-03-19 | 2016-10-19 | 中芯国际集成电路制造(上海)有限公司 | Calibration method and circuit of fusing current of fuse |
| CN107148650A (en) * | 2014-11-12 | 2017-09-08 | 美光科技公司 | The device and method repaired after execute encapsulation |
| US10832791B2 (en) | 2019-01-24 | 2020-11-10 | Micron Technology, Inc. | Apparatuses and methods for soft post-package repair |
| US11984185B2 (en) | 2021-04-07 | 2024-05-14 | Micron Technology, Inc. | Apparatuses and methods for zone-based soft post-package repair |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4412241A (en) * | 1980-11-21 | 1983-10-25 | National Semiconductor Corporation | Multiple trim structure |
| US6338032B1 (en) * | 1998-12-16 | 2002-01-08 | Analog Devices, Inc. | System and method for trimming IC parameters |
| US6472897B1 (en) * | 2000-01-24 | 2002-10-29 | Micro International Limited | Circuit and method for trimming integrated circuits |
-
2004
- 2004-05-13 CN CNB2004800125853A patent/CN100437870C/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107148650A (en) * | 2014-11-12 | 2017-09-08 | 美光科技公司 | The device and method repaired after execute encapsulation |
| CN107148650B (en) * | 2014-11-12 | 2021-03-16 | 美光科技公司 | Apparatus and method for performing post-package trim |
| CN106033107A (en) * | 2015-03-19 | 2016-10-19 | 中芯国际集成电路制造(上海)有限公司 | Calibration method and circuit of fusing current of fuse |
| CN106033107B (en) * | 2015-03-19 | 2019-04-12 | 中芯国际集成电路制造(上海)有限公司 | The calibration method and circuit of the blowout current of fuse |
| US10832791B2 (en) | 2019-01-24 | 2020-11-10 | Micron Technology, Inc. | Apparatuses and methods for soft post-package repair |
| US11145387B2 (en) | 2019-01-24 | 2021-10-12 | Micron Technology, Inc. | Apparatuses and methods for soft post-package repair |
| US11984185B2 (en) | 2021-04-07 | 2024-05-14 | Micron Technology, Inc. | Apparatuses and methods for zone-based soft post-package repair |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100437870C (en) | 2008-11-26 |
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