CN1784743A - Phase error detection circuit and synchronization clock extraction circuit - Google Patents

Phase error detection circuit and synchronization clock extraction circuit Download PDF

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Publication number
CN1784743A
CN1784743A CN 200480012024 CN200480012024A CN1784743A CN 1784743 A CN1784743 A CN 1784743A CN 200480012024 CN200480012024 CN 200480012024 CN 200480012024 A CN200480012024 A CN 200480012024A CN 1784743 A CN1784743 A CN 1784743A
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China
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phase error
mentioned
reference value
data
value
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河边章
冈本好史
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

In a phase error detecting circuit used in a synchronous clock extracting circuit for extracting a clock which is synchronized with reproduced data, a cross reference value generator 72 inputs, as a rising cross reference value S 5 , rising phase error data S 3 calculated in a phase error calculator 71 to a rising cross detector 70 a and inputs, as a falling cross reference value S 6 , falling phase error data S 4 similarly calculated to a falling cross detector 70 b. Each of the cross detectors 70 a and 70 b calculates a difference value between the value of the reproduced data at a sampling point and the inputted cross reference value (cross offset value) S 5 or S 6 and outputs a rising or falling cross detection signal when one of two difference values at consecutive sampling points is negative and the other thereof is positive. Accordingly, a capture range is enlarged.

Description

Phase error detection circuit and synchronization clock extraction circuit
Technical field
The present invention relates to a kind of its recorded data of extracting out from recording mediums such as CD or disk, and in the read signal processing circuit of extracting synchronous synchronous clock out for extracting the phase error detection circuit of synchronous clock out.
Background technology
One example of the read signal processing circuit in the former optical disc apparatus is represented with Figure 12.
Among Figure 12, the 1st, the recording medium of CD etc., the 2nd, shaven head, the 3rd, analog tuner, the 12nd, digital signal treatment circuit.In the above-mentioned digital signal treatment circuit 12, the 4th, A/D converter, the 5th, digital filter, the 6th, demoder, the 13rd, synchronization clock extraction circuit.In the synchronization clock extraction circuit 13, the 7th, phase comparator, 8 and 11 is recursive filters, the 9th, voltage-controlled oscillator (VCO), the 10th, frequency comparator.Below narrate the concrete condition and the action summary of above-mentioned formation.
When regeneration is carved into the data of recording mediums 1 such as CD, at first,, read its reflected light, convert catoptrical power to electric signal and generate the simulation regenerated signal by shaven head 2 with laser radiation recording medium 1.The simulation regenerated signal that is read by this shaven head 2 is carried out the gain adjustment or the biasing of signal amplitude and adjusts by analog tuner 3, and to wait ripple be that the increase of high frequency composition and the noise of purpose removed processing.Simulation regenerated signal by analog tuner 3 ripples such as grade have been handled becomes A/D converter 4 digitized digital data.Below becoming digital signal handles.
In the digital signal treatment circuit 12, by A/D converter 4 digitizings playback of data, implement the waveform revisals by digital filter 5 and handle, become two-value data by code translator 6 decodings again.Also have, by above-mentioned A/D converter 4 digitizings playback of data, be imported into synchronization clock extraction circuit 13.
In the above-mentioned synchronization clock extraction circuit 13, frequency comparator 10 is calculated the frequency error that playback of data and VCO9 export clock, the frequency error of recursive filter 11 filtering said frequencies comparers 10 outputs.The frequency error value that XCO9, corresponding above-mentioned recursive filter 11 have flattened changes the frequency of the clock of this output.Equally, phase comparator 7 is calculated the phase error of playback of data and VCO9 output clock, the phase error of above-mentioned phase comparator 7 outputs of recursive filter 8 filtering, the phase error that VCO9, corresponding above-mentioned recursive filter 8 have flattened changes the frequency number of this output clock.By this feedback cycle, control is from the frequency error vanishing of the clock of VCO9 output.The action of synchronization clock extraction circuit 13 usually is according to revisal frequency error at first, and secondly the order of revisal phase error is carried out.The clock of VCO9 output also offers the digital signal treatment circuit 12 that comprises A/D converter 4, and frequency control and phase control become steady state (SS), and the clock of VCO9 output becomes the synchronous clock synchronous with playback of data.
The former formation of the phase comparator 7 in such synchronization clock extraction circuit is for example opened flat 8-17145 communique by the spy and is taken off and carry.Below, an example of the former formation of phase comparator 7 is represented with Figure 13.
In figure, phase comparator 7 is to calculate circuit 75 by zero crossing detection circuit 74 and phase error to constitute.Zero crossing detection circuit 74 detects zero cross point from playback of data, output zero cross detection signal.Phase error is calculated circuit 75, is input signal with the regenerated signal, is enabling signal with the zero cross detection signal, is timing output phase error data with the zero cross detection signal.
Next, an example of the former formation of zero crossing detection circuit 74 is represented by Figure 14.With the zero crossing detection circuit 74 of figure, be to constitute by averaging circuit 741, D bistable multivibrator 742, exclusive reason summing circuit 743.Averaging circuit 741 calculates the mean value of two continuous playback of data, exports its coded data.D bistable multivibrator 742 will be delayed a clock from the coded data of equalization circuit 741.The exclusive reason summing circuit 743 of coded data, receive the coded data of mean value of averaging circuit 741 outputs and two coded datas of the coded data of having delayed by D bistable multivibrator 742, the mark that detects coded data from just to negative and from negative to positive rollback point.The output of exclusive reason summing circuit 743 becomes the zero cross detection signal of zero crossing detection circuit 74.
Detection appearance one example of zero cross point is represented by Figure 15 in the zero crossing detection circuit 74.With figure, the appearance of zero cross point when expression detects the playback of data rising.The circle mark is represented the playback of data sample spot.Corresponding to the passing of time, expression a (n-1), a (n), a (n+1), this situation is a (n) as the zero cross point of phase error detection.The mark (*) that intersects is represented each former and later two mean value.Because the symbol of the mean value of coded data a (n-1) coded data a next with it (n) is for just, the symbol of the mean value of coded data a (n) coded data a next with it (n+1) is for negative, so, be positioned at its middle coded data a (n) and be judged to be zero cross point.Calculate phase error based on the value of this coded data a (n) and the direction of overlapping edges.
(inventing problem to be solved)
The problem of zero cross detection mode is in the past represented with Figure 16.With figure, expression is for the zero cross detection appearance of the reproduction waveform of 3T+3T (T is the raceway groove cycle).The usefulness zero cross detection mode that has been illustrated by Figure 15 with figure (a) expression is normally carried out the appearance of zero cross detection.As known in the figure, under the situation that playback of data and sample clock can be obtained synchronously, correctly detect zero cross point.To this, shown in figure (b), under the big situation of the frequency error of playback of data and sample clock, at certain phase reversal flase drop survey zero cross point takes place a bit.
Therefore, in the former phase error manner of comparison, have, capture the also little problem of wave band because the linear wave band of input is narrow and small.
Summary of the invention
The present invention, its purpose is to solve above-mentioned problem, even if can't obtain synchronously under the situation of playback of data and sample clock, also can correctly detect zero cross point.
For achieving the above object, among the present invention, under the situation that can't obtain playback of data and sample clock synchronously, do not use the zero cross detection mode, with the phase error data that detects in the engineering of front is reference value, detects intersecting the moment of the playback of data that intersects with this reference value.
Just, phase error detection circuit of the present invention, be based on from record regenerator regeneration and digitizing the phase error used when extracting out of playback of data with the synchronous synchronous clock of this playback of data self calculate circuit, to comprise: receive the defined reference value above-mentioned playback of data the time with input, the test section that intersects that intersects the moment that detects that above-mentioned playback of data and said reference value intersect; The intersection that receives above-mentioned playback of data and above-mentioned intersection test section is signal constantly, and the difference that is as the criterion constantly with above-mentioned playback of data and null value with above-mentioned intersection is that the phase error that phase error data is calculated is calculated portion; Receive above-mentioned phase error and calculate the phase error data of portion, the intersection reference value generating unit of upgrading the said reference value of above-mentioned intersection test section based on this phase error data is a feature.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned intersection reference value generating unit is whenever calculated phase error data one time by the above-mentioned phase error portion of calculating, and just this is calculated up-to-date phase error data and is updated to feature as the reference value of above-mentioned intersection test section.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned intersection test section have detect above-mentioned playback of data with respect to the said reference value rise the rising that intersects intersect rising constantly intersect test section and, detect above-mentioned playback of data and intersect decline constantly to intersect test section be feature with respect to the descend decline that intersects of said reference value.
The present invention, with in above-mentioned phase error detection circuit, the above-mentioned phase error portion of calculating receives above-mentioned rising and intersects the rising of test section and intersect signal constantly, intersecting the difference of above-mentioned playback of data constantly and said reference value with above-mentioned rising is that the rising phase error data are when being calculated, receive above-mentioned decline and intersect the decline of test section and intersect signal constantly, intersecting the difference of above-mentioned playback of data constantly and said reference value with above-mentioned decline be that the decline phase error data calculated is feature.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned intersection reference value generating unit, receive above-mentioned phase error and calculate the rising phase error data and the decline phase error data of portion, export to above-mentioned rising intersection test section with above-mentioned rising phase error data as the rising reference value, exporting to above-mentioned decline intersection test section with above-mentioned decline phase error data as the decline reference value is feature.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned intersection reference value generating unit, receive above-mentioned phase error and calculate the rising phase error data of portion, exporting to above-mentioned rising with above-mentioned rising phase error data as the rising reference value and intersect test section, is that the decline reference value is exported to above-mentioned decline to intersect test section be feature with the rising phase error data behind the symbol of the above-mentioned rising phase error data of reversing.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned intersection reference value generating unit, receive above-mentioned phase error and calculate the decline phase error data of portion, export to above-mentioned rising intersection test section with the decline phase error data behind the symbol of the above-mentioned decline phase error data that reverses as the rising reference value, exporting to above-mentioned decline intersection test section with above-mentioned decline phase error data as the decline reference value is feature.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned intersection reference value generating unit, receive above-mentioned phase error and calculate the rising phase error data and the decline phase error data of portion, calculate the rising phase error data of this input and decline phase error data and 1/2nd values, with this and 1/2nd values and sign-inverted value thereof export to above-mentioned rising as rising reference value and decline reference value and intersect test section and descending to intersect test section be feature.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned intersection reference value generating unit, has the formation that the reference value of above-mentioned intersection test section is fixed as null value, above-mentioned phase error detection circuit then comprises in the above-mentioned intersection reference value generating unit being that reference value renewal and the reference value of switching based on phase error data is the fixing of null value, and control signal generating unit from control signal to above-mentioned intersection reference value generating unit that export is a feature.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned control signal generating unit, receive above-mentioned phase error and calculate the phase error data of portion, corresponding to the phase error shown in this phase error data, upgrade and reference value is fixing of null value for switching in above-mentioned intersection reference value generating unit based on the reference value of phase error data, the generation control signal is a feature.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned control signal generating unit, when the phase error shown in the phase error data of above-mentioned reception generates control signal under for the situation that does not reach the defined value and approach steady state (SS), the generating mode of reference value is switched to the feature that is fixed as that reference value is a null value from upgrading based on the reference value of phase error data.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned control signal generating unit, for reaching the defined threshold value when the phase error shown in the phase error data of above-mentioned reception when above, upgrade reference value based on phase error data, and reach defined threshold value when electricity reference value is not fixed as null value, the generation control signal is a feature.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned control signal generating unit, reception is from the defined signal of above-mentioned phase error detection circuit outside, come from outside defined signal corresponding to this, upgrade and reference value is fixing of null value for switching in above-mentioned intersection reference value generating unit based on the reference value of phase error data, the generation control signal is a feature.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned control signal generating unit, reference value when the signal that will export when detecting the specific type of above-mentioned playback of data receives as the above-mentioned defined signal that comes from the outside generates, upgrade and reference value is fixing of null value for switching in above-mentioned intersection reference value generating unit based on the reference value of phase error data, the output control signal is a feature.
The present invention, with in above-mentioned phase error detection circuit, the signal of output when the specific type of above-mentioned playback of data is detected, the synchronous detection signal that generates during for the interval of the synchronizing symbol (sync mark) that detects CD is a feature.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned control signal generating unit, receive the anomaly detection signal that generates when generation is unusual in the above-mentioned playback of data, will upgrade the reference value that reset into the defined value based on the reference value of phase error data in above-mentioned intersection reference value generating unit is feature.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned control signal generating unit, when calculating the phase error data of portion with the above-mentioned phase error of input, the defined signal of circuit outside is calculated in reception from phase error, corresponding to phase error shown in the above-mentioned phase error data and above-mentioned defined signal from the outside, upgrade and reference value is fixing of null value for switching in above-mentioned intersection reference value generating unit based on the reference value of phase error data, the generation control signal is a feature.
Synchronization clock extraction circuit of the present invention, state phase error detection circuit to comprise, receive the phase error data by above-mentioned phase error detection circuit output, the voltage-controlled oscillator that changes the synchronous clock frequency corresponding to the phase error shown in this phase error data is a feature.
The present invention, with in above-mentioned phase error detection circuit, comprise the threshold value generating unit that is generated as the employed threshold value of reference value of upgrading above-mentioned intersection test section, above-mentioned intersection reference value generating unit, receive the threshold value of above-mentioned threshold value generating unit, calculate the phase error data of portion based on this threshold value and above-mentioned phase error, the reference value of upgrading above-mentioned intersection test section is a feature.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned threshold value generating unit, when the above-mentioned phase error of reception is calculated the phase error data of portion, reception is from the defined threshold data of outside, in the absolute value of the absolute value of above-mentioned phase error data and above-mentioned defined threshold data, be that threshold value is a feature with little absolute value.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned threshold value generating unit, generating the rising intersection is feature with the threshold value and the intersection moment that descends with threshold value constantly.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned intersection test section comprises: detect the rising intersection rising intersection test section constantly that above-mentioned playback of data rises and intersects with respect to the said reference value; Detecting above-mentioned playback of data is feature with respect to the decline intersection decline intersection test section constantly that the decline of said reference value intersects.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned phase error is calculated portion, receive the rising intersection moment signal of above-mentioned rising intersection test section, calculate above-mentioned rising and intersect the difference of above-mentioned playback of data constantly and said reference value as the rising phase error data, simultaneously, receive the decline intersection moment signal of above-mentioned decline intersection test section, calculating the above-mentioned playback of data in the above-mentioned decline intersection moment and the difference of said reference value is feature as the decline phase error data.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned intersection reference value generating unit, receiving above-mentioned phase error calculates the rising of the rising phase error data of portion and above-mentioned threshold value generating unit and intersects and use threshold value constantly, when intersecting constantly with medium and small that absolute value of the absolute value of threshold value as the rising reference value with the absolute value of above-mentioned rising phase error data and above-mentioned rising, receive above-mentioned phase error and calculate the decline of the decline phase error data of portion and above-mentioned threshold value generating unit and intersect and use threshold value constantly, intersecting the moment with the absolute value of above-mentioned decline phase error data and above-mentioned decline is feature with that medium and small absolute value of the absolute value of threshold value as the decline reference value.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned intersection reference value generating unit, receiving above-mentioned phase error calculates the rising of the rising phase error data of portion and above-mentioned threshold value generating unit and intersects and use threshold value constantly, when intersecting constantly with medium and small that absolute value of the absolute value of threshold value as the rising reference value, be feature as the decline reference value with the value of the symbol of the above-mentioned rising reference value of reversing with the absolute value of above-mentioned rising phase error data and above-mentioned rising.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned intersection reference value generating unit, receiving above-mentioned phase error calculates the decline of the decline phase error data of portion and above-mentioned threshold value generating unit and intersects and use threshold value constantly, when intersecting constantly with medium and small that absolute value of the absolute value of threshold value as the decline reference value, be feature as the rising reference value with the value of the symbol of the above-mentioned decline reference value of reversing with the absolute value of above-mentioned decline phase error data and above-mentioned decline.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned intersection reference value generating unit, have and calculate that above-mentioned phase error is calculated the absolute value of rising phase error data of portion and the rising of above-mentioned threshold value generating unit intersects constantly with that the little absolute value in the absolute value of threshold value, with calculate above-mentioned phase error and calculate the decline of the absolute value of decline phase error data of portion and above-mentioned threshold value generating unit and intersect constantly and to calculate circuit with the absolute value mean value of both sides' average absolute of that the little absolute value in the absolute value of threshold value, calculating above-mentioned two average absolute that circuit calculates with above-mentioned absolute value mean value is that rising reference value and decline reference value are feature.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned intersection reference value generating unit, as the reference value of above-mentioned intersection test section, beyond the reference value of the phase error data that the threshold value and the above-mentioned phase error of above-mentioned threshold value generating unit are calculated circuit, the reference value of null value, in addition, above-mentioned intersection reference value generating unit has the reference value of selecting above-mentioned null value, with above-mentioned be feature based on any one selection circuit in the reference value of threshold value and phase error data.
The present invention, with in above-mentioned phase error detection circuit, having that generation switches to the selection circuit of above-mentioned intersection reference value generating unit with the null value is that the control signal generating unit of control signal of reference value one side is characteristics.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned control signal generating unit, receive the phase error data that the above-mentioned phase error portion of calculating calculates, generate above-mentioned control signal in the time of in the value of this phase error data is converged in less than the scope of defined value, the selection circuit of again this control signal being exported to above-mentioned intersection reference value generating unit is a feature.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned control signal generating unit, read and during playback of data from CD at above-mentioned record regenerator, generate above-mentioned control signal when detecting the interval of the sync mark that is recorded in above-mentioned CD, the selection circuit of again this control signal being exported to above-mentioned intersection reference value generating unit is a feature.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned threshold value generating unit comprises: the circuit that successively decreases of the defined threshold value of successively decreasing; Any one selection circuit in the threshold value of selecting above-mentioned defined threshold value and having successively decreased by the above-mentioned circuit that successively decreases; And generation is a feature with the switching signal generating unit that above-mentioned selection circuit switches to the switching signal of above-mentioned circuit one side of successively decreasing.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned switching signal generating unit, when the zero crossing number of times of above-mentioned playback of data when defined does not reach the defined value in the time, generating above-mentioned switching signal, to export to above-mentioned selection circuit be feature.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned threshold value generating unit has the control signal of reception from the outside, and the selection circuit that is chosen as the threshold value of null value is a feature.
The present invention, with in above-mentioned phase error detection circuit, above-mentioned intersection reference value generating unit, having the gain adjustment circuit that the phase error data value that above-mentioned phase error is calculated portion is adjusted into the defined multiple is feature.
Synchronization clock extraction circuit of the present invention is to comprise above-mentioned phase error detection circuit; Input is from the phase error data of above-mentioned phase error detection circuit output, and the voltage-controlled oscillator that the phase error shown in should phase error data is changed the synchronous clock frequency is a feature.
By the above, among the present invention, the phase error data that is detected by the process of front feeds back as reference value, through upgrading, this reference value and regenerated signal are intersected the playback of data in the moment intersect detection signal as the next one, detect the phase error data of this intersection detection signal, so, even if do not obtain under the synchronous situation of playback of data and sample clock, correct detected phase error enlarges that to capture wave band be possible.
Particularly in the present invention, phase error diminishes and near after the common state, can move to the intersection of regenerated signal and null value constantly as intersecting the zero crossing mode of detection signal generation, so can effectively and carry out the detection of phase error unchangeably.
Have again, among the present invention, the phase error data that prior process is detected is during as reference value, when this reference value is bigger than preset threshold, this reference value is restricted to setting threshold, the reference value that is adopted is converged in the suitable scope, can strengthens the amplitude (jitter) of regenerated signal, more correctly the detected phase error.
Description of drawings
Fig. 1 is the figure of the phase error detection circuit of expression the 1st embodiment of the present invention.
Fig. 2 is that rising that expression same-phase error-detector circuit is had intersects the figure that the inside of test section constitutes.
Fig. 3 is that phase error that expression same-phase error-detector circuit is had is calculated the figure that the inside of portion constitutes.
Fig. 4 is the figure that the inside of the intersection reference value generating unit that had of expression same-phase error-detector circuit constitutes.
Fig. 5 is the appearance figure of expression with the phase error detection mode of the phase error detection circuit of embodiment.
Fig. 6 is the appearance figure of phase error detection mode of the phase error detection circuit of expression the 2nd embodiment of the present invention.
Fig. 7 is the appearance figure of phase error detection mode of the phase error detection circuit of expression the 3rd embodiment of the present invention.
Fig. 8 is the appearance figure of phase error detection mode of the phase error detection circuit of expression the 4th embodiment of the present invention.
Fig. 9 is the figure that the inside of the control signal generating unit that phase error detection circuit had of expression the 1st embodiment constitutes.
Figure 10 is the appearance figure of phase error detection mode of the phase error detection circuit of expression the 5th embodiment of the present invention.
Figure 11 is the appearance figure of phase error detection mode of the phase error detection circuit of expression the 6th embodiment of the present invention.
Figure 12 is the figure of the phase error detection circuit of expression the 9th embodiment of the present invention.
Figure 13 is the figure that the inside of the threshold value generating unit that had of expression same-phase error-detector circuit constitutes.
Figure 14 is the figure that the inside of the intersection reference value generating unit that had of expression same-phase error-detector circuit constitutes.
Figure 15 is the appearance figure of the intersection data detection mode of expression same-phase error-detector circuit.
Figure 16 is the figure that the inside of the intersection reference value generating unit that phase error detection circuit had of expression the present invention the 10th embodiment constitutes.
Figure 17 is the appearance figure of the intersection data detection mode of expression same-phase error-detector circuit.
Figure 18 is the figure that the inside of the intersection reference value generating unit that phase error detection circuit had of expression the present invention the 11st embodiment constitutes.
Figure 19 is the appearance figure of the intersection data detection mode of expression same-phase error-detector circuit.
Figure 20 is the appearance figure of intersection data detection mode that the situation of same-phase error-detector circuit has been out of shape in expression.
Figure 21 is the figure that the inside of the intersection reference value generating unit that phase error detection circuit had of expression the present invention the 12nd embodiment constitutes.
Figure 22 is the figure that the inside of the intersection reference value generating unit that phase error detection circuit had of expression the present invention the 13rd embodiment constitutes.
Figure 23 is the figure of the read signal processing circuit of the CD usually before the expression.
Figure 24 is that expression has the internal structure figure with the phase comparator of former read signal processing circuit.
Figure 25 is that expression has the figure that the inside with the zero crossing detection circuit of former phase comparator constitutes.
Figure 26 is the figure of expression with the appearance of the zero cross detection mode of former phase comparator.
Figure 27 (a) is with in the former phase comparator, can obtain the key diagram that normally carries out zero cross detection under the situation of playback of data and sample data simultaneously.
Figure 27 (b) is with in the former phase comparator, the key diagram of surveying at zero cross point generation flase drop under the big situation of the frequency error of playback of data and sample data.
Embodiment
Below, based on the description of drawings embodiments of the present invention.
(the 1st embodiment)
Fig. 1 is the figure of the phase error detection circuit of expression the 1st embodiment of the present invention.With the phase error detection circuit of figure, be in the read signal processing circuit of optical disc apparatus shown in Figure 12 (record regenerator), replace the circuit of the phase comparator 7 in the synchronization clock extraction circuit 13 that is included in digital signal treatment circuit 12.Therefore, have the formation of the synchronization clock extraction circuit or the read signal processing circuit of this phase error detection circuit, identical with Figure 12, omit its explanation.
Among Fig. 1,700, it is phase error detection circuit from regenerating by record regenerator and change the playback of data detected phase error output of (digitizing) at A/D converter 4AD shown in Figure 23, it is built-in to replace phase comparator 7 in synchronization clock extraction circuit shown in Figure 12 13, phase error data from phase error detection circuit 700 outputs, as has been described like that between recursive filter 8 input voltage control generators (VCO) 9, this voltage-controlled oscillator 9, corresponding to the phase error of the phase error data of above-mentioned input, change output synchronous clock frequency.
In the phase error detection circuit 700 of Fig. 1, the 70th, the playback of data that has carried out from digitizing intersects the intersection test section that detects, and built-in carry out rising that the intersection of playback of data when rising detect and intersects test section 70a and carry out playback of data equally and descend and intersect the decline intersection test section 70b that detects.The 71st, phase error is calculated portion, and the 72nd, intersection reference value generating unit, the 73rd, control signal generating unit.Also have, PBD is a playback of data, PED is a phase error data, S1 is the rising intersection detection signal from above-mentioned rising intersection test section 70a output, S2 is the decline intersection detection signal from above-mentioned decline intersection test section 70b output, S3 is rising phase error data of calculating portion's 71 outputs from above-mentioned phase error, S4 is the decline phase error data of calculating portion's 71 outputs from above-mentioned phase error equally, S5 is the rising intersection reference value from above-mentioned intersection reference value generating unit 72 outputs, S6 is the decline intersection reference value from above-mentioned intersection reference value generating unit 72 outputs equally, S7 is that S8 is from the external signal from above-mentioned phase error detection circuit 700 external circuits from the control signal of above-mentioned control signal generating unit 73 outputs.
Next, the inside configuration example of the rising intersection test section 70a that above-mentioned intersection test section 70 is comprised is illustrated among Fig. 2.Among the rising intersection test section 70a with figure, 70a-1 is the averaging circuit of calculating the mean value of continuous two playback of data, 70a-2 is the D bistable multivibrator, 70a-4 is a subtracter, 70a-5 is a logical circuit, PBD is a playback of data, and S1 is the intersection detection signal that rises, and S5 is the intersection reference value that rises.Above-mentioned decline intersects the inside of test section 70b and constitutes also that to intersect test section 70a with above-mentioned rising be the same formation.Below, with formation and its rising intersection detection action explanation together of the intersection test section 70a that rises.
At first, rise to intersect among the test section 70a, the input digit change playback of data PBD and rising intersect reference value S5.Averaging circuit 70a-1 calculates the mean value of continuous two playback of data PBD.Next, among the subtracter 70a-4, deduct the intersection reference value S5 that rises from the mean value of being tried to achieve by averaging circuit 70a-1, output is the coded data that benchmark obtains by the intersection reference value S5 that rises.Next, among the logical circuit 70a-5, the coded data of a clock and the coded data of subtracter 70a-4 output have been delayed by D bistable multivibrator 70a-2 reception, continuous two coded datas on the time of reception just, the symbol that detects these two coded datas intersect to rise reference value S5 be benchmark from negative value become on the occasion of point (intersecting constantly).The output of this logical circuit 70a-5 becomes the rising intersection detection signal S1 of the intersection test section 70a that rises.Same way, decline intersection test section 70b also is that detection is input to the coded data of logical circuit 70a-5 from the occasion of the point that becomes negative value, exports the intersection detection signal S2 that descends.
Next, the inside formation of phase error shown in Figure 1 being calculated circuit 71 is represented with Fig. 3.Calculate in the portion 71 with the phase error of figure, 71a constantly adjusts circuit, and 71b is a directional interpreting circuit, and 71c～71f is a selector switch (selector) separately, 71g～71i is the D bistable multivibrator, PBD is a playback of data, and PED is a phase error data, and S1 is the intersection detection signal that rises, S2 is the intersection detection signal that descends, S3 is the rising phase error data, and S4 is the decline phase error data, and RST is a release signal.
Below, illustrate that phase error shown in Figure 3 calculates the action of calculating of the detailed formation of portion 71 and this phase error.Phase error is calculated input playback of data PBD in the portion 71, the intersection that rises detection signal S1, the intersection that descends detection signal S2, release signal RST.Constantly adjust circuit 71a, adjust the moment of the playback of data PBD that has imported, output.Directional interpreting circuit 71b, the playback of data PBD that has adjusted for the above-mentioned moment, judgement is the direction that rises and intersect or descend and intersect, with this playback of data PBD value, just playback of data and null value is poor, when exporting as phase error data PED by D bistable multivibrator 71h, when directional interpreting circuit 71b differentiates under the situation of change direction for the intersection that rises, by two selector switch 71c, 71d and D bistable multivibrator 71g output rising phase error data S3, on the other hand, directional interpreting circuit 71b differentiates change direction under the situation of intersecting that descends, by two selector switch 71e, 71f and D bistable multivibrator 71i output decline phase error data S4.
Calculate in the portion 71 in above-mentioned phase error, rising phase error data S3 selector switch 71c, receive the intersection detection signal S1 that rises, when the value of this signal S1 is under the situation of " 1 ", selection is from the playback of data PBD of above-mentioned directional interpreting circuit 71b, and be under the situation of " 0 ", select the preservation data (playback of data PBD last time) of D bistable multivibrator 71g.Also have, rising phase error data S3 with beyond selector switch 71d, be under the common state of " 0 " in release signal RST value, select data from above-mentioned selector switch 71c, the selection null value is exported during for the recovery of " 1 ".The formation of selector switch 71e, 71f that decline phase error data S4 uses the also formation with above is the same.
Next, the formation with intersection reference value generating unit 72 shown in Figure 1 is illustrated among Fig. 4.In the intersection reference value generating unit 72 with figure, 72a, 71b is-symbol circuit for reversing, 72c are the many input selection circuits that are made of selector switch, and 72d is the null value as the defined fixed value, uses for reference value is fixed as null value.S3 is the rising phase error data, and S4 is the decline phase error data, and S5 is the intersection reference value that rises, and S6 is the intersection reference value that descends, and S7 is a control signal.
Next, the detailed formation and the generation action of reference value of intersecting of the intersection reference value generating unit 72 of above-mentioned Fig. 4 are described.
At first, intersect in the reference value generating unit 72, input is calculated up-to-date rising phase error data S3 and the decline phase error data S4 that portion 71 calculates by phase error, and control signal S7.Many input selection circuits 72c, with control signal S7 as selecting signal, switch output rising phase error data S3, data, decline phase error data S4 by sign inversion circuit 72a sign-inverted rising phase error data S3, by the data of sign inversion circuit 72a sign-inverted decline phase error data any one, just switch fixed value 72d is upgraded and reference value is fixed as in output based on the reference value of phase error data null value.The output of many input selection circuits 72c is used rise the intersection reference value S5 and the intersection reference value S6 that descends with regard to former state.
Below explanation is by a succession of action of detected phase error information in the phase error detection circuit 700 that above intersection test section 70, the phase error that has illustrated calculated portion 71, the reference value generating unit 72 of intersecting constitutes a part.
Intersect test section 70, the input playback of data, descend intersect reference value S5, descend and intersect reference value S6, intersect test section 70a, the test section 70b that intersects by descending when playback of data descends when playback of data rises rises/descends and intersect detection by rising.Phase error is calculated in the portion 71, receives playback of data and from the rise detection signal S1 and the decline detection signal S2 of above-mentioned intersection test section 70, output phase error data PED, rising phase error data S3, decline phase error data S4.Intersect in the reference value generating unit 72, receive the rising phase error data S3 and the decline phase error data S4 that calculate portion 71 from above-mentioned phase error, they are exported as up-to-date rising/decline intersection reference value S5, S6.This reference value S5, S6 are updated as the reference value that next one intersection detects.
With Fig. 5 above-mentioned phase error detection mode is described.In with figure, round mark is the sample spot of playback of data, and wherein particularly black mark is the phase error data point that detect, and Lr is the intersection reference value level that rises, and Lf is the intersection reference value level that descends.Also have, PE1, PE2, PE3, PE4 are each phase error data points.
At first, the level of detected phase error PE1 uses as next one rising reference value as rising reference value level Lr during rising, detects next rising phase error PE3.Also have, the level of detected phase error data PE2 uses as next one decline reference value as decline reference value level Lf during decline, detects next decline phase error PE4.
Just, form the feedback cycle of reference value of point of crossing of the rising/decline phase error of the next playback of data separately that detects the rising phase error data S3 that calculates before the program and decline phase error data S4.By using this to constitute, the wave band of capturing that enlarges phase error detection circuit just becomes possibility.
(the 2nd embodiment)
Next, phase error detection circuit in the 2nd embodiment is described.In the present embodiment, make and intersect the different of reference value that reference value generating unit 72 generates and the 1st embodiment.
Just, use the rising phase error data S3 of the intersection reference value generating unit 72 that is input to Fig. 1, to rising test section 70a output rising reference value S5, to the opposite rising intersection reference value S5 of decline test section 70b output absolute value equal symbol.With Fig. 6 this situation is described.The level Lr of phase error data point PE1 during with rising is a reference value, phase error data point PE3 when detecting next the rising, in the detection of phase error data point PE4, PE4 during decline, the value of the symbol of the level Lr of phase error data point PE1 when using the above-mentioned rising of counter-rotating.
Therefore, identical with the 1st embodiment, the wave band of capturing that enlarges phase error detection circuit just becomes possibility.
(the 3rd embodiment)
Next, phase error detection circuit in the 3rd embodiment is described.In the present embodiment, other embodiments that the expression reference value generates.
Just, use the decline phase error data S4 that imports intersection reference value generating unit 72, to the intersection test section 70b output decline intersection reference value S6 that descends, to the opposite decline intersection reference value S6 of intersection test section 70a output absolute value equal symbol that rises.The words that these illustrate with Fig. 7, the level Lf of phase error data point PE2 during with the decline that detects is a reference value, phase error data point PE4 when detecting next decline, and in the detection of the phase error data point PE3 when rising, the value of the symbol of the level Lf of the phase error data point PE 2 when reversing above-mentioned decline is a reference value.
Therefore, identical with the 1st embodiment, the wave band of capturing that enlarges phase error detection circuit just becomes possibility.
(the 4th embodiment)
Next, phase error detection circuit in the 4th embodiment is described.In the present embodiment, the other embodiment that the expression reference value generates.
Just, use the rising phase error data S3 and the decline phase error data S4 of the intersection reference value generating unit 72 that is input to Fig. 1, the mean value of calculating these two data.And, intersect reference value S5 as rising to the above-mentioned mean value of calculating of rising test section 70a output, intersect reference value S6 as descending to the opposite value of the absolute value equal symbol of the above-mentioned mean value of calculating of decline test section 70b output.
Below, with Fig. 8 above-mentioned action is described.When the level Lr of the phase error data point PE1 during from the rising that detects and the decline of detection the level Lf of phase error data PE2 calculate they and 1/2 mean value.The reference value of the phase error data point when detecting next the rising is used above-mentioned mean value (Lr+Lf)/2, the reference value of the phase error data point when detecting next decline, use reversed above-mentioned mean value symbol-(Lr+Lf)/2.
Therefore, identical with the 1st embodiment, the wave band of capturing that enlarges phase error detection circuit just becomes possibility.
(the 5th embodiment)
Next, phase error detection circuit in the 5th embodiment is described.In the present embodiment, the concrete formation of the control signal generating unit 73 of presentation graphs 1.
The inside configuration example of control signal generating unit 73 is illustrated among Fig. 9.In control signal generating unit 73 with figure, the 731st, comparator circuit, the 732nd, predefined defined threshold value, the 733rd, be switched and determined circuit, PED is a phase error data, and S7 is a control signal, and S8 is an external signal.
The detailed formation of the control signal generating unit 73 of key diagram 9 and the summary of an example of moving thereof.At first, the threshold value 732 of relatively input in the comparator circuit 731 and the value of having processed phase error data PED are to being switched and determined circuit 733 output comparative results.Be switched and determined circuit 733, receive the comparative result and the external signal S8 of above-mentioned comparator circuit 731, based on these signals, the control signal S7 of output control intersection reference value generating unit 72.
Below, the detailed engineering of a succession of action is described.Control signal generating unit 73, the contrast phase error is calculated the phase error data of portion 71, when phase error does not reach under the situation of defined threshold value 732 near steady state (SS), switches to the control signal S7 of zero cross detection mode to 72 outputs of intersection reference value generating unit.Such output control signal S7, received the intersection reference value generating unit 72 of this control signal S7, in Fig. 4, many input selection circuits 72c selects fixed value (null value just) 72d, as rising and descend intersection reference value S5, S6, export to intersection test section 70 with this fixed value.
Such control mode is illustrated with Figure 10.In figure, PE1～PE8 is the phase error data point, and the top/bottom latitude that dotted line enclosed among the figure is to judge that phase error does not reach the steady state (SS) determinating area of the steady state (SS) of threshold value.In figure, PE2 becomes steady state (SS) from phase error data point.After being judged to be steady state (SS), count the number of phase error data point in order, when the number of being counted surpassed threshold value 732, from being the detection feedback mode of benchmark with rise and descend intersection reference value S5, S6, switching to reference value was the zero cross detection mode of null value.
Just, phase error more than threshold value long-term between in, upgrade rising/decline intersection reference value S5, S6 one by one, reference data as the detection of next one intersection, but phase error diminishes near steady state (SS), from intersecting the null value of reference value generating unit 72 outputs as reference value, carry out former zero cross point detection mode, the phase error detection that implementation efficiency is good becomes possibility.
(the 6th embodiment)
Next, phase error detection circuit in the 6th embodiment is described.Present embodiment, expression switch to the variation of zero cross detection mode from feature detection feedback mode of the present invention.
In the present embodiment, control signal generating unit 73 shown in Figure 9, receiving phase error information PED, the phase error of this data representation is compared with predefined defined threshold value 732, surpass under the situation of threshold value 732, the intersection reference value of having selected to upgrade, on the other hand, under near the situation the zero crossing, do not export the control signal S7 that null value is selected as reference value when surpassing threshold value 732 to intersection test section 70.
Such control mode is illustrated with Figure 11.The circle mark is the sample number strong point, phase error data point during PE1～PE4, and it is that the zero cross detection mode adopts the zone that dotted line is placed down range section.The zero cross detection mode adopts zone and detection feedback mode to adopt the zone to be cut apart by threshold value 732.Phase error data point PE1, PE2 are because phase error is bigger than threshold value 732, so carry out phase error detection by the detection feedback mode, but phase error does not reach among phase error data point PE3, the PE4 that threshold value 732 diminishes, and switches to the zero cross detection mode.
Just, phase error surpasses under the situation of pre-set threshold 732, upgrade rising/decline intersection reference value, reference data as the detection of next one intersection, but phase error diminishes and does not reach under the situation of threshold value 732, from intersecting reference value generating unit 72 output null values, carry out former zero cross point detection mode, the phase error detection that implementation efficiency is good becomes possibility.
(the 7th embodiment)
Next, phase error detection circuit in the 7th embodiment is described.In the present embodiment, illustrate based on external signal and intersect the switch instances of detection mode.
In the CD of DVD etc., writing down sync mark (known symbol) (particular form) every certain interval.Just read the sync interval state, illustrated frequency error to diminish.In the time of the detection at the interval of reading this sync mark, the synchronous detection signal that generates when this is detected, receive by the switching determination circuit 733 of control signal generating unit 73 as external signal S8 shown in Figure 9, as regenerate the action just begun synchronizing signal be between low period, with detection feedback mode detected phase error, on the other hand, read the synchronizing signal synchronous detection signal and become under the situation of HI, exported control signal S7 for switching to the zero cross detection mode.
Just, synchronizing signal by detecting the certain intervals record with the synchronous detection signal that generates as external signal S8, the size of determination frequency error, when this synchronous detection signal is under the low level situation, upgrade rising/decline intersection reference value with the detection feedback mode, as the reference data that next one intersection detects, synchronous detection signal becomes under the little situation of HI frequency error, by using former zero cross point detection mode, the phase error detection that implementation efficiency is good becomes possibility.
(the 8th embodiment)
Next, phase error detection circuit in the 8th embodiment is described.Present embodiment illustrates based on external signal and intersects other variation of situation of switching of detection mode.
In the CDs such as DVD, because scuffing and dirt can make regenerated signal become peculiar state.The abnormal signal detection signal that generates when detecting this unusual regenerated signal, input to the switching determination circuit 733 of control signal generating unit 73 as the external signal S8 among Fig. 9, when the abnormal signal detection signal becomes HI, as the action release signal, to intersecting reference value generating unit 72 output control signal S7.
Just, by contrast abnormal signal detection signal, the intersection reference value that the reference value generating unit 72 of will intersecting when detecting this abnormal signal detection signal is exported reset into the defined value when abnormal signal that scuffing and dirt produce was arranged on detecting owing to recording medium.Therefore, can suppress the deviation owing to the phase error data of abnormal signal generation, the phase error detection that implementation efficiency is good becomes possibility.
And, the formation of control signal generating unit 73, much less, the formation of the formation of the formation of the embodiment of employing merging the above-mentioned the 6th and the 6th and the above-mentioned the 7th and the 8th embodiment also is fine.
(the 9th embodiment)
Next, the phase error detection circuit of the 9th embodiment of the present invention is described.
Figure 12 is the formation of the phase error detection circuit of expression present embodiment.In the above embodiment of having narrated, with the detected phase error data of the step of front is reference value, detection becomes the phase error data of next zero cross point, but, in the present embodiment, with the detected phase error data of preceding step is under the situation of reference value, and the value that should become the phase error data of this reference value is set at threshold value, the trembling of control signal.
Just, in the phase error detection circuit 710 shown in Figure 12,, set up threshold value generating unit 711 with respect to phase error detection circuit shown in Figure 1 700.Also have, being accompanied by being configured on the intersection reference value generating unit 712 of this threshold value generating unit 711 has increased change.
The formation of above-mentioned threshold value generating unit 711 is illustrated among Figure 13.With the represented threshold value generating unit 711 of figure, only represented to generate the formation that rises with the threshold value part.It is identical with the formation of the part of threshold value to generate sloping portion, so omit.In the threshold value generating unit 711 with figure, 723,727 and 728 is selector switchs, the 724th, and D bistable multivibrator, the 725th, the circuit that successively decreases, the 726th, threshold quantity switching signal generating unit (switching signal generating unit), the 729th, logical circuit.
From the setting threshold value S11 of outside input, select by above-mentioned selector switch 723, be saved in the D bistable multivibrator 724.Above-mentioned setting is changed with the value of threshold value S11 and is other values, and enabling signal S12 becomes " 1 " value from " 0 " value, and setting is after changing selected to be saved in the D bistable multivibrator 724 by selector switch 723 with threshold value S11.The above-mentioned circuit 725 that successively decreases remains on threshold value S11 in the D bistable multivibrator 724 to set arbitrarily to successively decrease.Threshold quantity switching signal generating unit 726 receives external signal S8.This external signal S8 is not when reaching the situation of defined value and produce output in the zero crossing number of times of playback of data is during defined.Threshold quantity switching signal generating unit 726 generates switching signal when having received this external signal S8, this switching signal is exported to selector switch (selection circuit) 727.Selector switch 727 receives above-mentioned switching signal, and the threshold value of selecting above-mentioned D bistable multivibrator 724 to preserve is selected the threshold value from the above-mentioned circuit 725 that successively decreases when not receiving above-mentioned switching signal.Other selector switch 728, receive by logical circuit 729 under the output signal or situation of above-mentioned threshold quantity switching signal generating unit 726 from the control signal S10 of outside, select the threshold value of null value, and selection is exported as rising the threshold value of this selection from the threshold value of the defined value of above-mentioned selector switch 727 under the situation that does not have to receive with threshold value S9a.
Next, the formation with above-mentioned intersection reference value generating unit 712 shown in Figure 12 is illustrated among Figure 14.In figure, the 713rd, the gain adjustment circuit that the intersection that rises data are used, the 714th, the intersection that descends data gain adjustment circuit, the 715, the 716th, subtracter, the 717,718,719, the 720th, selector switch.This intersection reference value generating unit 712, receive above-mentioned phase error and calculate the rising of portion 703/decline phase error data S3, S4, the threshold value S9 of above-mentioned threshold value generating unit 711, and the control signal S7 of above-mentioned control signal generating unit 713, output is risen with reference value S5 and is descended and uses reference value S6.
Above-mentioned subtracter 715 deducts from the rising of threshold value generating unit 711 threshold value S9a from the rising phase error data S3 that has been adjusted by 713 gains of above-mentioned gain adjustment circuit, and this subtraction result's coded data is exported to selector switch 717.Selector switch 717, when the coded data from above-mentioned subtracter 715 is just to select to rise under the situation of (1) use threshold value S9a, selection rising phase error data under for the situation of negative (0).Just, selector switch 717, relatively rising phase error data and the absolute value that rises with threshold value S9a are selected little value, and the reference value of intersecting as rising is exported.Other selector switch 719, receive the control signal S7 of above-mentioned control signal generating unit 713, when being (1), the value of this control signal selects the rising intersection reference value of null value, and selection is exported to the intersection reference value of selecting the rising intersection test section 701 of Figure 12 from the rising intersection reference value of selector switch 717 as the intersection reference value S5 that rises when the value of control signal is (0).
More than, the generation of intersection reference value S5 of rising in the intersection reference value generating unit 712 being described, because the generation of the intersection reference value S6 that descends is too, so omit its explanation.
Below, the action of the phase error detection circuit of present embodiment is described based on Figure 15.In figure, represented regenerated signal and sample spot that 3T+3T (T is the raceway groove cycle) repeats, PE1, PE2, PE3, PE4 are phase error datas, Lr1 is the intersection reference value that rises, Lf1, Lf2 descend to intersect reference value, and Lrth rises that use threshold value, Lfth be the decline threshold value.
Among Figure 15, at first, detected at the beginning rising phase error data PE1, to compare absolute value with threshold value Lrth little with rising, so the selector switch 717 of intersection reference value generating unit 712 is selected rising phase error data PE1, the amplitude of these rising phase error data PE1 becomes the intersection reference value Lr1 that rises.Among the next phase error data PE3, the mean value of the phase error data of this phase error data PE3 and its front (with mark among the figure * 1 expression) does not reach above-mentioned rising and intersects reference value Lr1 for negative, the mean value of this rising phase error data PE3 and phase error data thereafter (with mark among the figure * 2 expression) surpasses to rise and intersects reference value Lr1 for just, so this phase error data PE3 is detected as the rising phase error data.The amplitude of above-mentioned rising phase error data PE3, bigger than predefined rising with the absolute value of threshold value Lrth, so this rising becomes the next intersection reference value that rises with threshold value Lrth.
On the other hand, the detection of decline phase error data because detected at the beginning decline phase error data PE2 with descend that to compare absolute value with threshold value Lfth little, the amplitude of this decline phase error data PE2 becomes the intersection reference value Lf1 that descends.Next decline phase error data PE4 Shen, the absolute value of the mean value of this phase error data PE4 and the phase error data before it (with mark among the figure * 3 expressions) does not reach the absolute value of above-mentioned decline intersection reference value Lf1 for negative, the mean value of this phase error data PE4 and its later phase error data (with mark among the figure * 4 expressions) has surpassed the absolute value of above-mentioned decline intersection reference value Lf1 for just, so this phase error data PE4 is detected as the decline phase error data.This decline phase error data PE4, since littler than predefined decline with the absolute value of threshold value Lfth, so the amplitude of this decline phase error data PE4 becomes the next intersection reference value Lf2 that descends.
Like this, in the present embodiment, in the time of reference value that detected phase error data before the step is detected as next phase error data, because set threshold value, so in the diffusion that has suppressed because of vibration or the FEEDBACK CONTROL that causes of ectocine, the wave band of capturing that enlarges phase comparator becomes possibility.
(the 10th embodiment)
Next, the phase error detection circuit of the 10th embodiment of the present invention is described.
Present embodiment is the embodiment that has changed the part that the intersection reference value generating unit 712 of above-mentioned the 9th embodiment constitutes.
Just, among the intersection reference value generating unit 712a of Figure 16, appended absolute value mean value and calculated circuit 721 and sign inversion circuit 722.Above-mentioned absolute value mean value is calculated circuit 721, calculates the rising of being selected by selector switch 717 and intersects the absolute value of reference value and intersect the average absolute of reference value, output by the rising that selector switch 718 is selected.Calculate the average intersection reference value of circuit 721 from this absolute value mean value, when exporting to selector switch 719, by exporting to selector switch 720 after sign inversion circuit 722 sign-inverted with regard to former state.
Just, the intersection reference value generating unit 712a that Figure 16 is represented, as the intersection reference value of rising phase error data and decline phase error data, employing be the common reference value that absolute value equates.
The action of the phase error detection circuit of present embodiment is described based on Figure 17.In figure, regenerated signal and sample spot that 3T+3T (T is the raceway groove cycle) repeats have been represented.In figure, detected at the beginning rising phase error data PE1 with rise that to compare absolute value with threshold value Lrth little, so the amplitude of these rising phase error data PE1 becomes the intersection reference value Lr1 that rises.Also have, detected at the beginning decline phase error data PE2 also with rise that to compare absolute value with threshold value Lfth little, so amplitude that should decline phase error data PE2 becomes the intersection reference value Lf1 that descends.Thereafter, the average absolute ((Lr1+Lf1)/2) of this rising and descend two intersection reference value Lr1, Lf1, when becoming the detection reference value of next rising phase error data PE3, the sign-inverted value of its average absolute-((Lr1+Lf1)/2) become the detection reference value of next decline phase error data PE4.
Again, based on two absolute values and the rising of the two phase place error information PE3 of these risings and decline, PE4 amplitude and descend, generate continuously and rise and intersection reference value Lr2, the Lf2 of decline with the comparative result of the absolute value of two threshold value Lrth, Lfth.
Therefore, also the same with above-mentioned the 9th embodiment in the present embodiment, in the diffusion that has suppressed because of vibration or the FEEDBACK CONTROL that causes of ectocine, the wave band of capturing that enlarges phase comparator becomes possibility.
(the 11st embodiment)
Next, the phase error detection circuit of the 11st embodiment of the present invention is described.In the present embodiment, be the embodiment that has changed the part that the intersection reference value generating unit 712 of above-mentioned the 9th embodiment constitutes.
Just, among the intersection reference value generating unit 712b of Figure 18, the decline reference value of having omitted in the intersection reference value generating unit 712 shown in Figure 14 generates with gain adjustment circuit 714, subtracter 716 and selector switch 718, will generate rising with selector switch 717 from the rising reference value and intersect the value of reference value after by sign inversion circuit 722 sign-inverted and input to constituting of selector switch 720 as the intersection reference value that descends.Formation in addition is identical with formation of intersecting reference value generating unit 712 shown in Figure 12, omits its explanation.
Next, the action of the phase error detection circuit of present embodiment is described based on Figure 19.Among Figure 19, detected at the beginning rising phase error data PE1 with rise that to compare absolute value with threshold value Lrth little, so the amplitude of these rising phase error data PE1 becomes the intersection reference value Lr1 that rises.And, above-mentioned rising is intersected value after the sign-inverted of reference value Lr1 intersects reference value Lf1 as descending.Thereafter, next rising phase error data PE3, intersecting reference value Lr1 with above-mentioned rising is that benchmaring arrives, next decline intersected data PE4, intersect to descend reference value Lf1 (=Lr1) be that benchmaring arrives.
Next, based on two absolute values and the rising of the two phase place error information PE3 of these risings and decline, PE4 amplitude and descend, generate continuously and rise and intersection reference value Lr2, the Lf2 of decline with the comparative result of the absolute value of two threshold value Lrth, Lfth.
And, in the present embodiment, as intersecting reference value generating unit 712b, only being provided with the rising reference value generates with gain adjustment circuit 713, subtracter 715 and selector switch 717, on the contrary, in the intersection reference value generating unit 712 of Figure 12, the generation of rising reference value is set is fine certainly with gain adjustment circuit 714, subtracter 716 and selector switch 718.In this case, generate to descend intersect reference value, this is descended intersect value after the sign-inverted of reference value and intersect reference value as rising.The appearance that two intersection reference values of the rising of this situation and decline generate is represented with Figure 20.
(the 12nd embodiment)
Next, the phase error detection circuit of the 12nd embodiment of the present invention is described.
Present embodiment is specific, and the represented control signal generating unit 713 of Figure 12 generates the control signal embodiment in period.
Just, control signal generating unit 713 as shown in Figure 12, is imported the phase error data PED that calculates portion 703 from phase error, and with reference to this phase error data PED, this amount of phase error diminishes, and is such as shown in figure 21.If become the words that enter the steady state (SS) determinating area, crossing number strong point in the steady state (SS) determinating area becomes the moment of defined threshold value, and the control signal S5 that the intersection reference value that switches to rising and descend is fixed to the zero cross detection mode of zero level exports to intersection reference value generating unit 712 shown in Figure 12.
Therefore, in the present embodiment, such as shown in figure 21, the crossing number strong point later playback of data of PE2 enters in the steady state (SS) determinating area, thereafter, count to the moment that adds up to defined number (5) crossing number strong point PE2～PE6, control signal generating unit 713 generates control signal S7, in the intersection reference value generating unit 712, as shown in Figure 14, two selector switchs 719,720 are selected the intersection reference value of null value, so, switch to the zero cross detection mode from the detection feedback mode.
Like this, in the present embodiment, amount of phase error big during, upgrade the two intersection reference values that rise and descend, as the reference value of next one intersection Data Detection, still, amount of phase error diminishes near the words of steady state (SS), switch to zero crossing Data Detection mode, the phase error detection that implementation efficiency is good becomes possibility.
(the 13rd embodiment)
Next, the phase error detection circuit of the 13rd embodiment of the present invention is described.
The represented control signal generating unit 713 of Figure 12 that present embodiment is specific that generate control signals with embodiments above-mentioned different other periods.
Just, control signal generating unit 713 as shown in Figure 12, is imported the phase error data PED that calculates portion 703 from phase error, with reference to this phase error data PED, this amount of phase error and defined threshold value is compared.This threshold value, such as shown in figure 22, be the amount of phase error that has preestablished as the suitable application region of zero cross detection mode.Control signal generating unit 713, the result of Shu Ru phase error data PED and above-mentioned defined threshold value relatively, when not reaching above-mentioned defined threshold value as phase error data PED, and under near the situation the zero crossing, generate " 0 " value control signal, export to intersection reference value generating unit 712 shown in Figure 12.
Therefore, in the present embodiment, such as shown in figure 22, because crossing number strong point PE1, PE2, amount of phase error is big, intersects the detection of data by the detection feedback mode, still, the such amount of phase error of crossing number strong point PE3, PE4 is the situation that reaches the defined threshold value, switches to the zero cross detection mode.
Therefore, present embodiment, also the same with the 12nd embodiment, the phase error detection that implementation efficiency is good becomes possibility.
(the 14th embodiment)
Next, the phase error detection circuit of the 14th embodiment of the present invention is described.
In the present embodiment, the same with above-mentioned the 7th embodiment, as the external signal S8 of input control signal generating unit 713, adopt the synchronous detection signal that in detecting the CD of DVD etc., when sync mark is being write down at certain interval, is generating.
When above-mentioned control signal generating unit 713 had received above-mentioned synchronous detection signal, under the state that the frequency error of playback of data diminishes, the control signal S7 that generates " 1 " value exported to intersection reference value generating unit 712.In the above-mentioned intersection reference value generating unit 712, as shown in Figure 14, selector switch 719,720 is selected the intersection reference value of null value, so the detection mode of intersecting switches to the zero cross detection mode from feedback system.
Therefore, in the present embodiment, also the same with above-mentioned the 13rd embodiment, the phase error detection that implementation efficiency is good becomes possibility.
(the 15th embodiment)
Next, the phase error detection circuit of the 15th embodiment of the present invention is described.
In the present embodiment, the same with above-mentioned the 8th embodiment, as the external signal S8 of input control signal generating unit 713, adopt the detected regenerated signal that causes because of the scuffing or the dirt of CD to become the abnormal signal detection signal of the unusual regenerated signal of abnormality.
Above-mentioned control signal generating unit 713 when receiving above-mentioned abnormal signal detection signal, generates the control signal S7 of " 1 " value, and will to intersect the reference value recovery be null value by intersecting reference value generating unit 712.
Therefore, in the present embodiment, can suppress from the deviation of the detected intersection data of abnormal signal, the phase error detection that implementation efficiency is good becomes possibility.
And the formation of control signal generating unit 713 is taked and also is fine certainly with the formation of the embodiment of the formation of the above-mentioned the 12nd and the 13rd embodiment and the above-mentioned the 14th and the 15th.
On-the industry utilize possibility-
As described above, the present invention, even if can't obtain the synchronous of playback of data and sample clock, Correct detected phase error, wave band is captured in expansion becomes possibility, as phase error detection circuit and bag Clock extracting circuit of drawing together it etc. is useful.

Claims (36)

1. phase error detection circuit, be based on from record regenerator regeneration and digitizing the phase error used when extracting out of playback of data with the synchronous synchronous clock of this playback of data self calculate circuit, it is characterized by:
Comprise:
Intersect test section, receive the defined reference value in the time of with the above-mentioned playback of data of input, detect above-mentioned playback of data and intersecting the moment that the said reference value is intersected;
Phase error is calculated portion, receives the intersection moment signal of above-mentioned playback of data and above-mentioned intersection test section, is that phase error data is calculated with the above-mentioned playback of data in the above-mentioned intersection moment and the difference of null value; And
Intersection reference value generating unit receives the phase error data that above-mentioned phase error is calculated portion, upgrades the said reference value of above-mentioned intersection test section based on this phase error data.
2. phase error detection circuit according to claim 1 is characterized by:
Above-mentioned intersection reference value generating unit is whenever calculated phase error data one time by the above-mentioned phase error portion of calculating, and just the up-to-date phase error data that this is calculated is upgraded as the reference value of above-mentioned intersection test section.
3. phase error detection circuit according to claim 1 is characterized by:
Above-mentioned intersection test section has:
Rise to intersect test section, detect that above-mentioned playback of data rises with respect to the said reference value that the rising that intersects intersects constantly and
The intersection that descends test section detects above-mentioned playback of data and intersects constantly with respect to the decline that the decline of said reference value intersects.
4. phase error detection circuit according to claim 3 is characterized by:
Above-mentioned phase error is calculated portion, receive the rising intersection moment signal of above-mentioned rising intersection test section, intersecting the difference of above-mentioned playback of data constantly and said reference value with above-mentioned rising is that the rising phase error data are when being calculated, receiving the decline intersection moment signal of above-mentioned decline intersection test section, is that the decline phase error data is calculated with the above-mentioned playback of data in the above-mentioned decline intersection moment and the difference of said reference value.
5. phase error detection circuit according to claim 4 is characterized by:
Above-mentioned intersection reference value generating unit, receive above-mentioned phase error and calculate the rising phase error data and the decline phase error data of portion, export to above-mentioned rising intersection test section with above-mentioned rising phase error data as the rising reference value, export to above-mentioned decline intersection test section as the decline reference value with above-mentioned decline phase error data.
6. phase error detection circuit according to claim 4 is characterized by:
Above-mentioned intersection reference value generating unit, receive above-mentioned phase error and calculate the rising phase error data of portion, export to above-mentioned rising intersection test section with above-mentioned rising phase error data as the rising reference value, export to above-mentioned decline intersection test section as the decline reference value with the rising phase error data behind the symbol of the above-mentioned rising phase error data of reversing.
7. phase error detection circuit according to claim 4 is characterized by:
Above-mentioned intersection reference value generating unit, receive above-mentioned phase error and calculate the decline phase error data of portion, export to above-mentioned rising intersection test section with the decline phase error data behind the symbol of the above-mentioned decline phase error data that reverses as the rising reference value, export to above-mentioned decline intersection test section as the decline reference value with above-mentioned decline phase error data.
8. phase error detection circuit according to claim 4 is characterized by:
Above-mentioned intersection reference value generating unit, receive above-mentioned phase error and calculate the rising phase error data and the decline phase error data of portion, calculate the rising phase error data of this input and decline phase error data and 1/2nd values, with this and 1/2nd values and sign-inverted value thereof export to above-mentioned rising as rising reference value and decline reference value and intersect test section and descending and intersect test section.
9. according to any one described phase error detection circuit of claim 1 to 8, it is characterized by:
Above-mentioned intersection reference value generating unit has the formation that the reference value of above-mentioned intersection test section is fixed as null value,
Above-mentioned phase error detection circuit comprises, upgrades and reference value is the fixing control signal generating unit from control signal to above-mentioned intersection reference value generating unit that export of null value for switching based on the reference value of phase error data in the above-mentioned intersection standard value generating unit.
10. phase error detection circuit according to claim 9 is characterized by:
Above-mentioned control signal generating unit, receive above-mentioned phase error and calculate the phase error data of portion, corresponding to the phase error shown in this phase error data, reference value renewal and the reference value based on phase error data is the fixing of null value in the above-mentioned intersection reference value generating unit in order to switch, and generates control signal.
11. phase error detection circuit according to claim 10 is characterized by:
Above-mentioned control signal generating unit, phase error shown in the phase error data of above-mentioned reception is for exporting control signal under the situation that does not reach the defined value and approach steady state (SS), and to switch to reference value be the fixing of null value from upgrading based on the reference value of phase error data for the generating mode of reference value.
12. phase error detection circuit according to claim 10 is characterized by:
Above-mentioned control signal generating unit, to reach the defined threshold value when the phase error shown in the phase error data of above-mentioned reception when above, upgrade reference value based on phase error data, and reference value is fixed as when not reaching the defined threshold value mode of null value, generate control signal.
13. phase error detection circuit according to claim 9 is characterized by:
Above-mentioned control signal generating unit, reception is from the defined signal of above-mentioned phase error detection circuit outside, come from outside defined signal corresponding to this, be that reference value renewal and the reference value of switching based on phase error data is the fixing of null value in above-mentioned intersection reference value generating unit, generate control signal.
14. phase error detection circuit according to claim 13 is characterized by:
Above-mentioned control signal generating unit, the signal that to be exported when detecting the specific type of above-mentioned playback of data is as above-mentioned output control signal when coming from outside defined signal and receiving, and upgrades and reference value is fixing of null value for the generating mode of reference value switches in above-mentioned intersection reference value generating unit based on the reference value of phase error data.
15. phase error detection circuit according to claim 14 is characterized by:
The signal of output when the specific type of above-mentioned playback of data is detected, the synchronous detection signal that generates during for the interval of the sync mark that detects CD.
16. phase error detection circuit according to claim 9 is characterized by:
Above-mentioned control signal generating unit receives the anomaly detection signal that generates when generation is unusual in the above-mentioned playback of data, will upgrade the reference value that reset into the defined value based on the reference value of phase error data in above-mentioned intersection reference value generating unit.
17. phase error detection circuit according to claim 9 is characterized by:
Above-mentioned control signal generating unit, when calculating the phase error data of portion with the above-mentioned phase error of input, the defined signal of circuit outside is calculated in reception from phase error, corresponding to phase error shown in the above-mentioned phase error data and above-mentioned defined signal from the outside, upgrade and reference value is the fixing of null value, the generation control signal in above-mentioned intersection reference value generating unit, switching based on the reference value of phase error data.
18. a synchronization clock extraction circuit is characterized by:
Comprise:
The described phase error detection circuit of claim 1; With
Voltage-controlled oscillator receives the phase error data by above-mentioned phase error detection circuit output, changes the synchronous clock frequency corresponding to the phase error shown in this phase error data.
19. phase error detection circuit according to claim 1 is characterized by:
Comprise the threshold value generating unit, be generated as the employed threshold value of reference value of upgrading above-mentioned intersection test section,
Above-mentioned intersection reference value generating unit receives the threshold value of above-mentioned threshold value generating unit, calculates the phase error data of portion based on this threshold value and above-mentioned phase error, upgrades the reference value of above-mentioned intersection test section.
20. phase error detection circuit according to claim 19 is characterized by:
Above-mentioned threshold value generating unit, when the above-mentioned phase error of reception is calculated the phase error data of portion, reception in the absolute value of the absolute value of above-mentioned phase error data and above-mentioned defined threshold data, is a threshold value with little absolute value from the defined threshold data of outside.
21. phase error detection circuit according to claim 20 is characterized by:
Above-mentioned threshold value generating unit generates the rising intersection and uses threshold value with the threshold value and the intersection moment that descends constantly.
22. phase error detection circuit according to claim 21 is characterized by:
Above-mentioned intersection test section comprises:
Rising intersection test section detects the rising intersection moment that above-mentioned playback of data rises and intersects with respect to the said reference value; With
The intersection that descends test section detects above-mentioned playback of data and intersects constantly with respect to the decline that the decline of said reference value intersects.
23. phase error detection circuit according to claim 22 is characterized by:
Above-mentioned phase error is calculated portion, receive the rising intersection moment signal of above-mentioned rising intersection test section, calculate above-mentioned rising and intersect the difference of above-mentioned playback of data constantly and said reference value as the rising phase error data, simultaneously, receive above-mentioned decline and intersect the decline of test section and intersect signal constantly, calculate above-mentioned decline and intersect the difference of above-mentioned playback of data constantly and said reference value as the decline phase error data.
24. phase error detection circuit according to claim 23 is characterized by:
Above-mentioned intersection reference value generating unit, receiving above-mentioned phase error calculates the rising of the rising phase error data of portion and above-mentioned threshold value generating unit and intersects and use threshold value constantly, when intersecting constantly with medium and small that absolute value of the absolute value of threshold value as the rising reference value with the absolute value of above-mentioned rising phase error data and above-mentioned rising, receive above-mentioned phase error and calculate the decline of the decline phase error data of portion and above-mentioned threshold value generating unit and intersect and use threshold value constantly, intersect medium and small that absolute value of the absolute value of using threshold value constantly as the decline reference value with the absolute value of above-mentioned decline phase error data and above-mentioned decline.
25. phase error detection circuit according to claim 23 is characterized by:
Above-mentioned intersection reference value generating unit, receiving above-mentioned phase error calculates the rising of the rising phase error data of portion and above-mentioned threshold value generating unit and intersects and use threshold value constantly, when intersecting constantly with medium and small that absolute value of the absolute value of threshold value as the rising reference value with the absolute value of above-mentioned rising phase error data and above-mentioned rising, with the value of the symbol of the above-mentioned rising reference value of reversing as the decline reference value.
26. phase error detection circuit according to claim 23 is characterized by:
Above-mentioned intersection reference value generating unit, receiving above-mentioned phase error calculates the decline of the decline phase error data of circuit and above-mentioned threshold value generating unit and intersects and use threshold value constantly, when intersecting constantly with medium and small that absolute value of the absolute value of threshold value as the decline reference value with the absolute value of above-mentioned decline phase error data and above-mentioned decline, with the value of the above-mentioned decline reference value symbol that reverses as the rising reference value.
27. phase error detection circuit according to claim 23 is characterized by:
Above-mentioned intersection reference value generating unit, have absolute value mean value and calculate circuit, it is calculated, and above-mentioned phase error is calculated the absolute value of rising phase error data of portion and the rising of above-mentioned threshold value generating unit intersects constantly with that the little absolute value in the absolute value of threshold value, the decline of calculating the absolute value of decline phase error data of portion and above-mentioned threshold value generating unit with above-mentioned phase error intersects constantly with both sides' average absolute of that the little absolute value in the absolute value of threshold value
Above-mentioned intersection reference value generating unit is rising reference value and decline reference value to be calculated above-mentioned two average absolute that circuit calculates by above-mentioned absolute value mean value.
28. phase error detection circuit according to claim 19 is characterized by:
Above-mentioned intersection reference value generating unit, as the reference value of above-mentioned intersection test section, beyond the reference value of the phase error data of calculating circuit based on the threshold value and the above-mentioned phase error of above-mentioned threshold value generating unit, the reference value of null value,
Above-mentioned intersection reference value generating unit has the reference value of selecting above-mentioned null value, above-mentioned based on any one selection circuit in the reference value of threshold value and phase error data.
29. phase error detection circuit according to claim 28 is characterized by:
Have the control signal generating unit, generating that selection circuit with above-mentioned intersection reference value generating unit switches to the null value is the control signal of reference value one side.
30. phase error detection circuit according to claim 29 is characterized by:
Above-mentioned control signal generating unit, the phase error data that the above-mentioned phase error portion of calculating calculates, generate above-mentioned control signal in the time of in the value of this phase error data is converged in less than the scope of defined value, again this control signal is exported to the selection circuit of above-mentioned intersection reference value generating unit.
31. phase error detection circuit according to claim 29 is characterized by:
Above-mentioned control signal generating unit, read and during playback of data from CD at above-mentioned record regenerator, when detecting the interval of the sync mark that is recorded in above-mentioned CD, generate above-mentioned control signal, again this control signal is exported to the selection circuit of above-mentioned intersection reference value generating unit.
32. phase error detection circuit according to claim 19 is characterized by:
Above-mentioned threshold value generating unit comprises:
The circuit that successively decreases, the defined threshold value of successively decreasing;
Select circuit, select above-mentioned defined threshold value and the threshold value of having successively decreased by the above-mentioned circuit that successively decreases in any one; And
The switching signal generating unit generates the switching signal that above-mentioned selection circuit is switched to above-mentioned circuit one side of successively decreasing.
33. phase error detection circuit according to claim 32 is characterized by:
Above-mentioned switching signal generating unit, when the zero crossing number of times of above-mentioned playback of data when defined does not reach the defined value in the time, generate above-mentioned switching signal and export to above-mentioned selection circuit.
34. phase error detection circuit according to claim 32 is characterized by:
Above-mentioned threshold value generating unit has the control signal of reception from the outside, is chosen as the selection circuit of the threshold value of null value.
35. phase error detection circuit according to claim 19 is characterized by:
Above-mentioned intersection reference value generating unit has the gain adjustment circuit that the phase error data value that above-mentioned phase error is calculated portion is adjusted into the defined multiple.
36. a synchronization clock extraction circuit is characterized by:
Comprise:
The described phase error detection circuit of claim 19; With
Voltage-controlled oscillator, input be from the phase error data of above-mentioned phase error detection circuit output, and the phase error shown in should phase error data is changed the synchronous clock frequency.
CN 200480012024 2003-09-09 2004-06-11 Phase error detection circuit and synchronization clock extraction circuit Pending CN1784743A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2003316774 2003-09-09
JP316774/2003 2003-09-09
JP407206/2003 2003-12-05

Publications (1)

Publication Number Publication Date
CN1784743A true CN1784743A (en) 2006-06-07

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN 200480012024 Pending CN1784743A (en) 2003-09-09 2004-06-11 Phase error detection circuit and synchronization clock extraction circuit

Country Status (1)

Country Link
CN (1) CN1784743A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101636991A (en) * 2007-02-27 2010-01-27 佳能株式会社 Data communications equipment, data communication system and data communications method
CN101548326B (en) * 2007-09-03 2012-04-11 松下电器产业株式会社 Phase comparator, clock generator circuit using same, video display, and reproduction signal processing device
CN106845133A (en) * 2017-02-16 2017-06-13 成都天衡电科科技有限公司 A kind of computational methods and computing system of phase bit flipping number

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101636991A (en) * 2007-02-27 2010-01-27 佳能株式会社 Data communications equipment, data communication system and data communications method
CN101548326B (en) * 2007-09-03 2012-04-11 松下电器产业株式会社 Phase comparator, clock generator circuit using same, video display, and reproduction signal processing device
US8188795B2 (en) 2007-09-03 2012-05-29 Panasonic Corporation Phase comparator and reproduction signal processor using the same
CN106845133A (en) * 2017-02-16 2017-06-13 成都天衡电科科技有限公司 A kind of computational methods and computing system of phase bit flipping number
CN106845133B (en) * 2017-02-16 2019-04-05 成都天衡电科科技有限公司 A kind of calculation method and computing system of phase bit flipping number

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