CN1782830A - Liquid crystal display and its producing method - Google Patents
Liquid crystal display and its producing method Download PDFInfo
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- CN1782830A CN1782830A CN 200410098205 CN200410098205A CN1782830A CN 1782830 A CN1782830 A CN 1782830A CN 200410098205 CN200410098205 CN 200410098205 CN 200410098205 A CN200410098205 A CN 200410098205A CN 1782830 A CN1782830 A CN 1782830A
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Abstract
The available LCD making process with reduced steps has the demerits of less margin and lower production quality, and the present invention provides superior LCD making process. The present invention introduces the halftone exposure technology, and the LCD making process of the present invention has reasonable semiconductor layer islanding step, reasonable etching cut-off layer forming step, reasonable electrode terminal protection layer forming anode oxidizing step, reasonable simultaneous pixel electrode and scanning line forming step, etc., which forms the four-mask production process and the three-mask production process separately for TN-type LCD and IPS-type LCD.
Description
Invention field
The present invention is about having the liquid crystal indicator of coloured image Presentation Function, the liquid crystal indicator of especially relevant active type.
Prior art
In recent years, along with development of technology such as Micrometer-Nanometer Processing Technology, liquid crystal material technology and high-density installation technology, 5～50cm is supplied in commercial kitchen area in a large number to the television image or the various image display of the liquid crystal indicator of uniform angle.Simultaneously, a side of the two sheet glass substrates that constitute liquid crystal panel, also realize colored the demonstration than being easier to by prior formation RGB dyed layer.Particularly be provided with in each pixel on the so-called active type liquid crystal panel of on-off element, can guarantee to obtain to crosstalk (crosstalk) is less and have an image that reaction velocity is very fast and contrast is high.
These liquid crystal indicators (liquid crystal panel), though be with 200～1200 sweep traces, matrix with about 300～1600 signal wires is organized as modal formation, but recently, is carrying out just simultaneously becoming more meticulous corresponding to big pictureization and height that the capacity of display increases.
Figure 17 represents the installment state of liquid crystal panel, constitute a side's of liquid crystal panel 1 transparent insulated substrate, for example, by using the electric conductivity sticker to connect COG (the Chip On Glass) mode that the electrode tip subgroup 5 that is formed on the sweep trace on the glass substrate 2 is provided the semiconductor integrated circuit chip 3 of drive signal, or for example with the polyimide resin film as basic unit, the TCP film 4 of Copper Foil terminal (not shown) with gold-plated or plated solder, be fixed on the seating meanses such as TCP (Tape Carrier Package) mode of the electrode tip subgroup 6 of signal wire with the suitable sticker crimping that comprises the electric conductivity medium, electric signal is provided to image displaying part.Though illustrate two kinds of mounting meanss simultaneously at this, be actually and suitably select any one mode.
7, the 8th, connect the pixel that is positioned at liquid crystal panel 1 substantial middle image displaying part partly, and the wiring between the electrode terminal 5,6 of sweep trace and signal wire, electrode tip subgroup 5,6 not necessarily constitutes with same conductive.The 9th, on opposite face, have the relative glass substrate or the colored filter of another sheet transparency insulated substrate of the comparative electrode of common transparent conductivity in all liquid crystal cells.
Figure 18 is expression is used as on-off element with the active type liquid crystal indicator at each pixel arrangement insulated gate electrode transistor npn npn 10 a equivalent circuit diagram, 11 (being 7 on Figure 17) are sweep trace, 12 (being 8 on Figure 17) are signal wire, 13 is liquid crystal cells, and liquid crystal cells 13 is taken as capacity cell on circuit.The element that solid line is described is formed on a slice glass substrate 2 that constitutes liquid crystal panel, all liquid crystal cells 13 of being described with dotted line common comparative electrode 14 be formed on the relative interarea of another sheet glass substrate 9.
In the lower occasion of the resistance of the OFF of insulated gate electrode transistor npn npn 10 resistance or liquid crystal cells 13 or pay attention to the occasion of display image GTG, can manage to increase the circuit setting, in order to increase as the time constant of the liquid crystal cells 13 of load and the complementary capacitance of setting up 15 be connected in parallel on liquid crystal flat 13 circuit such as grade.
Figure 19 is the main position sectional view of the image displaying part of expression liquid crystal indicator, constitute two sheet glass substrates 2,9 of liquid crystal panel 1, be by the resinousness fiber, particle or be formed on column spacer material (not shown) uniformly-spaced on the colored filter 9, specific range about space-number μ m and forming, and its gap (at interval), it is peripheral part at glass substrate 9, the encapsulant and the joint filling material (all not having diagram) that are constituted by organic property resin form the confined space that seals, at this confined space filling liquid crystal 17.
When realizing colored the demonstration, cover the organic film about any one or boths' thickness 1～2 μ m of the dyestuff that is called dyed layer 18 or pigment at the confined space of glass substrate 9, and provide the color Presentation Function, glass substrate 9 colored filter (being called for short CF) that is otherwise known as at this moment.And, according to the different in kind of liquid crystal material 17, on glass substrate 9 or glass substrate 2 below any one side or on the two sides, all attach Polarizer, make liquid crystal panel 1 bring into play function as photovalve.Now, at most of liquid crystal panel of being sold on the market, use TN (twisted nematic) liquid crystal, Polarizer 19 needs two usually.Though not shown, the permeation type liquid crystal panel is to dispose back side light source to be used as light source, from below irradiation white light.
Contacting with liquid crystal 17 and be formed on polyimide film 20 about for example thickness 0.1 μ m on the two sheet glass substrates 2,9, is to make the alignment film of liquid crystal alignment at specific direction.The 21st, the drain electrode (wiring) of the drain electrode of connection insulated gate electrode transistor npn npn 10 and the pixel electrode 22 of transparent conductivity, most and signal wire (source electrode line) 12 forms simultaneously.Between signal wire 12 and drain electrode 21 is semiconductor layer 23, will describe in detail in the back.On colored filter 9, the Cr thin layer 24 that is formed on about the thickness 0.1 μ m on adjacent dyed layer 18 borders is to be used to prevent that exterior light is incident upon the light curtain-shaped cover member of semiconductor layer 23 and sweep trace 11 and signal wire 12, and Here it is belongs to the so-called black matrix (abbreviating BM as) of known technology.
At this, illustrate about structure and manufacture method as the insulated gate electrode transistor npn npn of on-off element.What the insulated gate electrode transistor npn npn was commonly used at present has two kinds, is introduced as conventional example (being called the etching cut-off type) with wherein a kind of.Figure 20 represents to constitute the planimetric map of unit picture element of the active base plate (semiconductor device that is used for display device) of traditional liquid crystal panel, and Figure 21 represents the sectional view on Figure 20 (e) A-A ', B-B ' and the C-C ' line, its manufacturing process of following simple declaration.
At first, glass substrate 2 about thickness 0.5～1.1 μ m that shown in Figure 20 (a) and Figure 21 (a), selects for use as thermotolerance and resistance to chemical reagents and the high insulativity substrate of the transparency, for example on the interarea of the name of an article 1737 of (healthy and free from worry CORNING) company's manufacturing, use SPT (sputter) equal vacuum film forming apparatus optionally to form for example Cr, Ta, Mo etc. or cover thickness 0.1～0.3 μ m of these alloys or metallic silicon compounds about the first metal layer, and by Micrometer-Nanometer Processing Technology, selectivity forms also sweep trace 11 and the capacitor storage beam 16 of double as gate electrode 11A.The material of sweep trace is preferably taken all factors into consideration thermotolerance and resistance to chemical reagents and anti-fluoric acid and electric conductivity and is selected.
Reduce the resistance value of sweep trace for the big pictureization that adapts to liquid crystal panel or high becoming more meticulous, though to use aluminium comparatively reasonable as the material of sweep trace, but aluminium is at free state, because thermotolerance is lower, so the metal silicide of stacked above-mentioned heating resisting metal such as Cr, Ta, Mo or these metals, or from the teeth outwards with anodic oxidation additional oxide layer (Al
2O
3) etc. way all belong to present prior art.That is to say that sweep trace 11 is made of the metal level more than one deck.
Secondly, on whole of glass substrate 2, use the PCVD device to cover a SiN in regular turn with the thickness about 0.3 μ m-0.5 μ m-μ m respectively as gate insulator
xFirst amorphous silicon (a-Si) layer 31 of (silicon nitride) layer 30 and passage as the insulated gate electrode transistor npn npn free from foreign meter, and as the 2nd SiN of the insulation course of protection passage
xLayer three kinds of thin layer such as 32 grades with shown in Figure 21 (b), make two SiN of gate electrode 11A by Micrometer-Nanometer Processing Technology as Figure 20 (b)
x Layer 32 optionally residual than gate electrode 11A width thinner as 32A, and expose first amorphous silicon layer 31.
Secondly, that uses that identical PCVD device covers 0.05 μ m left and right sides thickness on whole comprises impurity for example after second amorphous silicon layer 33 of phosphorus, shown in Figure 20 (c) and Figure 21 (c), use SPT equal vacuum film forming apparatus covers the Ti about 0.1 μ m in regular turn, Cr, heating resisting metal thin layers 34 such as Mo are used as heat resistant metal layer, aluminum film layer 35 about thickness 0.3 μ m is as the low resistance wiring layer, ti thin film layer 36 about thickness 0.1 μ m is as intermediate conductive layer, pass through Micrometer-Nanometer Processing Technology, selectivity forms: by as source electrode, three kinds of film 34A of this of drain electrode wiring material, 35A, the drain electrode 21 of 36 the insulated gate electrode transistor npn npn that lamination constituted and the signal wire 12 of double as source electrode.The generation type of this selectivity pattern, be will be used to form the photoresist pattern of source electrode, drain electrode wiring as mask, in regular turn etching Ti thin layer 36, aluminum film layer 35, and Ti thin layer 34 after, remove source electrode, drain electrode 12,21 second amorphous silicon layer 33, and expose the 2nd SiN
xLayer 32A simultaneously, also remove first amorphous silicon layer 31 on other zones, expose gate insulator 30 and form.So, because there is the 2nd SiN of path protection layer
xLayer 32A, so the etching meeting of second amorphous silicon layer 33 finishes automatically, so this manufacture method is called as etching by manufacture method.
For making the insulated gate electrode transistor npn npn not become bias voltage (offset) structure, source electrode, drain electrode 12,21 are that partly (number μ m) planarity is overlapping and form with gate electrode 11A.Because this overlapping electricity effect with stray capacitance, so it is the smaller the better, but because the institutes such as glass substrate temperature during normally with the expansion coefficient of the precision of the alignment precision of exposure machine and mask plate and glass substrate and exposure are determined, so the numerical value of practicality is 2 μ m to the maximum.
Then, on whole of glass substrate 2, use the PCVD device equally with gate insulator, covering about as the thickness 0.3 μ m of transparent insulation course the SiNx layer and as passivation (passivation) insulation course 37, shown in Figure 20 (d) and Figure 21 (d), by Micrometer-Nanometer Processing Technology selective removal passivation insulation 37, and at drain electrode 21, form opening portion 62, with form opening portion 63 on the position of the electrode terminal 5 that forms sweep trace 11 in image displaying part zone exceptionally, with formation opening portion 64 on the position of the electrode terminal 6 that forms sweep trace 12, and expose the some of drain electrode 21 and sweep trace 11 and signal wire 12.On capacitor storage beam 16 (with the electrode pattern of parallel gathering), form opening portion 65 and expose the part of capacitor storage beam 16.
At last, the for example ITO (indium tin oxide) or the IZO (indium-zinc oxide) that use SPT equal vacuum film forming apparatus to cover about thickness 0.1～0.2 μ m are used as transparency conducting layer, shown in Figure 20 (e) and Figure 21 (e), comprise opening portion 62 and on passivation insulation 37 by Micrometer-Nanometer Processing Technology, selectivity forms pixel electrode 22, finishes active base plate 2.With the some of the sweep trace 11 that exposes in the opening portion 63 as electrode terminal 5, some with the signal wire 12 that exposes in the opening portion 64 also is fine as electrode terminal 6, as shown in the figure, comprise opening portion 63,64 and on passivation insulation 37, selectivity forms and also is fine by the formed electrode terminal 5A of ITO, 6A, but also forms the transparent conductivity short-circuit line 40 that is connected between electrode terminal 5A, the 6A simultaneously usually.Though its reason is not shown but forms elongated striated between electrode terminal 5A, 6A and the short-circuit line 40 and high resistanceization can be used as the high resistance that antistatic countermeasure is used by making.Similarly, comprise opening portion 65 and the electrode terminal of formation capacitor storage beam 16.
When the cloth line resistance of signal wire 12 can not throw into question, the low resistance wiring layer 35 that not necessarily need be formed by aluminium then in this case, if when selecting heating resisting metal material such as Cr, Ta, Mo, can be simplified source electrode, drain electrode wiring 12,21 single-layered.In addition, the thermotolerance of relevant insulated gate electrode transistor npn npn, write up is opened flat 7-74368 communique in the spy of existing example.Simultaneously, in Figure 20 (c), capacitor storage beam 16 is with drain electrode 21 sandwich gate insulators 30 and overlapping areas 50 (upper left oblique line toward the bottom right) though form storage capacitors 15, is omitted its detailed description at this.
The above five road mask plate technologies of narrating, though omit its detailed description, but to be the island chemical industry preface that belongs to semiconductor layer form the result that operation is cut down a procedure with contacting for this, so needed the operation about 7～8 roads originally, also by introducing dry etch technique, reduce to five roads now and help the significantly reduction of technology cost.In order to reduce the production cost of liquid crystal indicator, reduce the technology cost at the production process of active base plate, and be to belong to effective means with module installation procedure reduction component costs at the panel assembling procedure, this is well-known development goal.In order to reduce the technology cost, when also having the operation that adopt to shorten technology to cut down, with the process exploitation of cheapness or replace technology, but enumerate the example that the four road mask plate technologies that make active base plate with four road mask plates cut down as operation and be illustrated at this.Four road mask plate technologies are to introduce shadow tone (halftone) exposure technique, and reduction photo etching operation, therefore Figure 22 is the unit picture element planimetric map corresponding to the active base plate of four road mask plate technologies, and Figure 23 is A-A ', the B-B ' of expression Figure 22 (e) and the sectional view of C-C ' line.Narrate as previous, what the insulated gate electrode transistor npn npn often used now has two kinds, adopts channel etch type insulated gate electrode transistor npn npn at this.
At first, identical with five road mask plate technologies, at the first metal layer that uses on the interarea of glass substrate 2 about SPT equal vacuum film forming apparatus covering thickness 0.1～0.3 μ m, with shown in Figure 23 (a), form the sweep trace 11 and capacitor storage beam 16 of double as gate electrode 11A as Figure 22 (a) by the Micrometer-Nanometer Processing Technology selectivity.
That secondly, uses on whole of glass substrate 2 that the PCVD device covers thickness 0.3 μ m-0.2 μ m-0.5 μ m respectively in regular turn will be as the SiN of gate insulator
xLayer 30, first amorphous silicon layer 31 of the impure hardly passage as the insulated gate electrode transistor npn npn, and comprise the source electrode as the insulated gate electrode transistor npn npn of impurity, three kinds of thin layers such as second amorphous silicon layer 33 of drain electrode.Then, use SPT equal vacuum film forming apparatus for example to cover the Ti thin layer 34 about thickness 0.1 μ m in regular turn as heat resistant metal layer 35, for example aluminum film layer 35 about thickness 0.3 μ m is as the low resistance wiring layer, for example Ti thin layer 36 about thickness 0.1 μ m is as intermediate conductive layer, just cover source electrode in regular turn, the drain electrode wiring material, form the drain electrode 21 of double as insulated gate electrode transistor npn npn and the signal wire 12 of source electrode by the Micrometer-Nanometer Processing Technology selectivity, its maximum characteristics are when forming this selection pattern, by shadow tone (halftone) exposure technique, shown in Figure 22 (b) and Figure 23 (b), source electrode, passage between drain electrode wiring forms the thickness of regional 80C (lower-left oblique line part up), for example be 1.5 μ m, form and compare source electrode, drain electrode wiring forms regional 80A, the thinner photoresist pattern 80A～80C of thickness 3 μ m of 80B.
The photoresist pattern 80A～80C that forms like this, when the making of the substrate that is used for liquid crystal indicator, use normal Photosensitive resin usually, therefore source electrode, drain electrode wiring form regional 80A, and 80B is a black, that is to say, form the Cr film, passage area 80C is a grey, for example forms the Cr pattern at the lines null interval (Line And Space) about width 0.5～1 μ m, and other zones are white, that is to say, use the mask plate of removing the Cr film to get final product.Gray area is because the lack of resolution of exposure machine, therefore can imaging not go out lines and null (Line And Space), and from light source to the irradiates light of mask plate can see through only about half of about, therefore can obtain to have the photoresist pattern 80A～80C of the section shape shown in Figure 23 (b) according to the residual membrane property of normal Photosensitive resin.
With above-mentioned photoresist pattern 80A～80C as mask, shown in Figure 22 (b) and Figure 23 (b), etching Ti thin layer 36, Al thin layer 35, Ti thin layer 34, second amorphous silicon layer 33 and first amorphous silicon layer 31 in regular turn, and expose after the gate insulator 30, shown in Figure 22 (c) and Figure 23 (c), make the thickness of photoresist pattern 80A～80C by ashing means such as oxygen plasma, for example reduce more than the 1.5 μ m from 3 μ m, 81A, 81B, 80C disappear and expose passage area.At this, to cut down the photoresist pattern 80A～80C of film as mask, the Ti thin layer 36A of (passage forms the zone), Al thin layer 35A, Ti thin layer 34A, the second amorphous silicon layer 33A and the first amorphous silicon layer 31A between etching source electrode, drain electrode wiring in regular turn once more, the first amorphous silicon layer 31A is etched to about residual 0.05～0.1 μ m.Being called as the etched reason of passage and being etching like this, to become the semiconductor of passage formed.And, on handling, above-mentioned oxygen plasma preferably strengthens anisotropy for the anisotropy that suppresses pattern dimension.Its reason will be introduced in the back.
And, to remove after above-mentioned photoresist pattern 81A, the 81B, five road mask plate technologies are same shown in Figure 22 (d) and Figure 23 (d), at the SiN that covers on whole of glass substrate 2 about thickness 0.3 μ m
xLayer is as transparent insulation course, and the zone that forms at the electrode terminal 5,6 that forms drain electrode 21 and sweep trace 11 and signal wire 12 forms opening portion 62,63,64 respectively, and removes passivation insulation 37 and gate insulator 30 in the opening portion.
At last, the for example ITO or the IZO that use SPT equal vacuum film forming apparatus to cover about thickness 0.1～0.2 μ m are used as transparency conducting layer, shown in 22 (e) and Figure 23 (e), make on passivation insulation 37 by Micrometer-Nanometer Processing Technology, comprise opening portion 62 selectivity and form the pixel electrode 22 of transparent conductivity and finish active base plate 2.About electrode terminal, this comprise opening portion 63,64 and on passivation insulation 37 selectivity form by the formed electrode terminal 5A of ITO, 6A.
So, in five road mask plate technologies and four road mask plate technologies, carry out simultaneously with the contact hole formation operation of sweep trace 11 owing to lead to drain electrode 21, therefore different with kind corresponding to the thickness of insulating layer in this opening portion 62,63.Passivation insulation 37 is lower and membranous poor than the system film temperature of gate insulator 30, when by fluoric acid being the etching solution etching of oxygen, etching speed be respectively thousands of dusts (A)/minute with hundreds of dusts (A)/minute, differ an order of magnitude, the section shape of the opening portion 62 on the drain electrode 21, because top produces over etching and uncontrollable aperture, therefore taking to utilize fluorine is the dry etching (dry etching) of gas.
Even the employing dry etching, the opening portion 62 on the drain electrode 21 owing to be passivation insulation 37 only, is therefore compared with the opening portion 63 of sweep trace, can't avoid over etching, and along with the material difference, intermediate conductive layer 36A is sometimes because of the etching gas attenuate.In addition, when etching finishes back removal photoresist pattern, at first in order to remove the polymkeric substance on the surface of being fluoridized, with the oxygen plasma ashing surface of photoresist pattern is cut down about 0.1～0.3 μ m,, generally use organic stripper, such as the soup of the stripper 106 made of Tokyo Ying Hua company etc. is handled thereafter, but when middle conductive layer 36A was exposed the state of substrate aluminium lamination 35A by skiving, the surface with the oxygen plasma ashing treatment at aluminium lamination 35A formed insulator Al
2O
3, and pixel electrode 22 between can't obtain Ohmic contact.So even also do not hinder when intermediate conductive layer 36A thickness is cut down, its thickness is for example set the thicker thickness of 0.2 μ m for and is avoided this problem.Perhaps, form opening portion 62～65 o'clock, the method of evading the question of removing aluminium lamination 35A and form pixel electrode 22 again after the thin layer 34A that exposes the substrate heat resistant metal layer also is fine, and in this case, the benefit that does not need intermediate conductive layer 36A is from the beginning arranged.
But in the measure in front, when the inner evenness of the thickness of this film was bad, this cooperation may not necessarily play useful effect, when the inner evenness of etching speed is bad in addition, also is identical.In the measure of back, though need not intermediate conductive layer 36A, but increase the operation of removing aluminium lamination 35A, and control when insufficient when the section of opening portion 62, may cause the broken string of pixel electrode 22.
In addition, in the insulated gate electrode transistor npn npn of channel etch type, first amorphous silicon layer 31 that passage area is free from foreign meter, if when not covering thicker (more than channel etch type is generally 0.2 μ m) in advance, to have a significant impact and make characteristics of transistor, particularly cut-off current uneven tendency can occur the inner evenness of glass substrate.This produces situation to the running rate of PCVD and dust will produce quite big influence, also be very important item from the viewpoint of production cost.
In addition, the passage that is suitable in four road mask plate technologies forms operation, because source electrode, drain electrode wiring material and semiconductor layer that selective removal source electrode, drain electrode wiring are 12,21, therefore be the operation of the passage length (is 4～6 μ m at present volume production product) of conducting (ON) characteristic that determines significantly to influence the insulated gate electrode transistor npn npn.The change of this passage length, owing to significantly change the conducting current value of insulated gate electrode transistor npn npn, therefore strict manufacturing management usually, but passage length, the pattern dimension that also promptly is decided by shadow tone (halftone) exposure area, the amount of being exposed (the pattern precision of the intensity of light source and mask plate, especially lines and null size), the coating thickness of photoresist, the video picture of photoresist is handled, and in the influence of all multiparameters such as film reduction of the photoresist of this etching work procedure, and, the inner evenness of described all volumes also is relative to each other, differ and improve productive rate and steady production surely, compare with traditional manufacturing management, need stricter manufacturing management, still can not be called at present and reached high level.Especially passage length be 6 μ m when following its tendency more obvious.
The present invention is owing to finishing in view of present situation, problem when not only avoiding common contact hole in five traditional road mask plate technologies or four road mask plate technologies to form, and adopt bigger shadow tone (halftone) exposure technique of foozle tolerance limit and realize the minimizing of manufacturing process.Simultaneously, realize the low price of liquid crystal panel, needing the more meticulous necessity of pursuing the reduction of manufacturing process in order to be adapted to increase in demand gradually is to understand easily, and the technology by simplification or other main manufacturing processes of cost degradation improves value of the present invention more.
Summary of the invention
In the present invention, at first be that shadow tone (halftone) exposure technique is applicable to that the formation operation of the etching stopping layer that the pattern accuracy control is more or less freely and contact hole form operation and realize the reduction of manufacturing process.Secondly, for only with source electrode, the effective passivation of drain electrode wiring, merged the anodizing technology that forms insulation course on the surface of the formed source electrode of aluminium, drain electrode wiring that the spy who is disclosed in prior art opens flat 2-216129 communique, and realization technology is rationalized and low temperatureization.To be willing to that the formation operation of the pixel electrode of flat 5-268726 communique is applicable to the present invention through the spy who is disclosed in prior art who rationalizes again.In order to cut down operation more, when the anodic oxide coating of source electrode, drain electrode wiring forms, also adopt shadow tone (halftone) exposure technique and the protective seam that rationalizes electrode terminal forms operation.
At the described insulated gate electrode transistor npn npn of claim 1; it is characterized in that on passage, having the protection insulation course; to comprise and on the source electrode that forms, drain electrode wiring by the some in the electrical connection zone of the formed source wiring of conductive material that is different from source electrode, drain electrode wiring material; be formed with the bottom gate type insulated gate electrode transistor npn npn of photonasty organic insulator; therefore its photonasty organic insulator performance passivation protection function need not provide SiN
xDeng the protection insulation course, the correlationship of liquid crystal indicator offers some clarification on the claim 5 and second embodiment.
At the described insulated gate electrode transistor npn npn of claim 2; it is characterized in that on passage, having the protection insulation course; except that the electrical connection zone of source wiring; only on source wiring; form the bottom gate type insulated gate electrode transistor npn npn of photonasty organic insulator; its photonasty organic insulator is because therefore the performance deactivation function need not provide SiN
xDeng the protection insulation course, and with the correlationship of liquid crystal indicator in claim 6, offer some clarification on 8,10 and the 3rd, five, seven embodiment.
At the described insulated gate electrode transistor npn npn of claim 3; it is characterized in that on passage, having the protection insulation course; constituting source electrode, drain electrode wiring by anodised metal level; simultaneously; except that the electrical connection zone of source wiring, on source electrode, drain electrode wiring, form the bottom gate type insulated gate electrode transistor npn npn of anodic oxide coating; its anodic oxide coating is because therefore the performance deactivation function need not provide SiN
xDeng the protection insulation course, and on claim 4,7,9,11 and first, fourth, six, eight embodiment, offer some clarification on about liquid crystal indicator.
At the described insulated gate electrode transistor npn npn of claim 4, be on an interarea, to have at least: the sweep trace of insulated gate electrode transistor npn npn and the transistorized gate electrode of double as aforementioned dielectric grid type, become the first transparent insulated substrate of two-dimensional-matrix-like by assortment with the signal wire and the unit picture element of pixel electrode that is connected drain electrode wiring etc. of double as source wiring, and between the second transparent insulated substrate or colored filter relative with the aforementioned first transparent insulated substrate, the liquid crystal indicator that filling liquid crystal forms; It is characterized in that at least on an interarea of the first transparent insulated substrate, form by the sweep trace that metal level constituted more than one deck; First semiconductor layer free from foreign meter is formed island clipping the gate insulator more than one deck on the gate electrode; On first semiconductor layer on the gate electrode, form the protection insulation course thinner than aforementioned grid width; On the some of aforementioned protective seam and on first semiconductor layer, form by second semiconductor layer that comprises impurity and the source electrode that lamination constituted, drain electrode wiring that can anodised metal level; On the some of aforementioned drain electrode wiring with gate insulator on, in the pixel electrode of transparent conductivity and the zone outside the pixel display part, on signal wire, form the electrode terminal of transparent conductivity; Except that with the electrode terminal zone of the pixel electrode overlapping areas of aforementioned drain electrode wiring and signal wire, on the surface of source electrode, drain electrode wiring, form anodic oxide coating.
By this structure, on the passage between source electrode, drain electrode, form the protection insulation course, and in the protection passage, also form the tantalum pentoxide (Ta of the anodic oxide coating of insulativity on the surface of signal wire and drain electrode wiring
2O
5), or aluminium oxide (Al
2O
3) and deactivation function is provided.Therefore, need not cover passivation insulation on the whole surface of glass substrate, so the thermotolerance of insulated gate electrode transistor npn npn is a problem no longer.And can obtain to have the TN type liquid crystal indicator of transparent conductivity electrode terminal.
The described liquid crystal indicator of claim 5, it is characterized in that equally on an interarea of at least the first transparent insulated substrate, form by the sweep trace that lamination constituted and the pixel electrode of transparent conductivity and the identical signal line electrode terminal of transparency conducting layer with the first metal layer; On gate electrode, clip plasma protective seam and gate insulator island ground and form first semiconductor layer that does not comprise impurity; On first semiconductor layer on the gate electrode, form the protection insulation course thinner than aforementioned gate electrode width; Plasma protective seam on aforementioned pixel electrode and gate insulator form opening portion; On the some of aforementioned protection insulation course and first semiconductor layer and on the some of the electrode terminal of signal wire, formation is by second semiconductor layer that comprises impurity, the source electrode that lamination constituted (signal wire) wiring with second metal level more than one deck, with on the some of aforementioned protective seam and first semiconductor layer and on the pixel electrode some in the aforementioned opening portion, form drain electrode wiring equally; On aforementioned source electrode, drain electrode wiring, form the photonasty organic insulator.
By this structure, on the passage between source electrode, drain electrode, form the protection insulation course and in the protection passage, on the surface of signal wire and drain electrode wiring, formation photonasty organic insulator and deactivation function is provided.Therefore, on whole of glass substrate, need not cover passivation insulation, so the thermotolerance of insulated gate electrode transistor npn npn no longer becomes problem.And can obtain to have the TN type liquid crystal indicator of transparent conductivity electrode terminal.
The described liquid crystal indicator of claim 6 is characterized in that at least on an interarea of the first transparent insulated substrate, forms the pixel electrode that clips by formed sweep trace of the lamination of transparency conducting layer and the first metal layer and transparent conductivity; On gate electrode, clip plasma protective seam and gate insulator and formed first semiconductor layer free from foreign meter by island; On first semiconductor layer on the gate electrode, form ratio at the thinner protection insulation course of aforementioned gate electrode width; Plasma protective seam on aforementioned pixel electrode and gate insulator form opening portion; On the some and first semiconductor layer of aforementioned protection insulation course, formation is by the source electrode that lamination constituted (signal wire) wiring of second semiconductor layer that comprises impurity and second metal level more than one deck, with on the some of aforementioned protective seam with first semiconductor layer on and on the some of pixel electrode in the aforementioned opening portion, form drain electrode wiring equally; Except that the electrode terminal of signal wire with on signal wire, form the photonasty organic insulator.
By this structure, on the passage between source electrode, drain electrode, form the protection insulation course and in the protection passage, on the surface of signal wire, form the photonasty organic insulator and deactivation function is provided.Therefore, on whole of glass substrate, need not cover passivation insulation, so the thermotolerance of insulated gate electrode transistor npn npn no longer becomes problem.Thereby can obtain to have TN type liquid crystal indicator with signal wire same metal electrode terminal.
The described liquid crystal indicator of claim 7 is characterized in that at least on an interarea of the first transparent insulated substrate, forms by the sweep trace that lamination constituted of transparency conducting layer and metal level and the pixel electrode of transparent conductivity; On gate electrode, clip plasma protective seam and gate insulator island ground and form first semiconductor layer free from foreign meter; On first semiconductor layer on the gate electrode, form the protection insulation course thinner than aforementioned gate electrode width; Plasma protective seam on aforementioned pixel electrode and gate insulator form opening portion; On the some of aforementioned protection insulation course and on first semiconductor layer, formation comprises second semiconductor layer of impurity, with the source electrode that lamination constituted (signal wire) wiring that can anodised metal level, with on the some of aforementioned protective seam and first semiconductor layer and on the first transparent insulated substrate and on the some of the pixel electrode in the aforementioned opening portion, form drain electrode wiring equally; Except that the electrode terminal of signal wire, at source electrode. the drain electrode wiring surface forms anodic oxide coating.
By this structure, on the passage between source electrode, drain electrode, formation is protected insulation course and in the protection passage, also on the surface of signal wire and drain electrode wiring, is formed the tantalum pentoxide (Ta of insulativity anodic oxide coating
2O
5), or aluminium oxide (Al
2O
3) and deactivation function is provided.Therefore, on whole of glass substrate, need not cover passivation insulation, so the thermotolerance of insulated gate electrode transistor npn npn no longer becomes problem.Thereby can obtain to have TN type liquid crystal indicator with the electrode terminal of signal wire same metal.
The described liquid crystal indicator of claim 8, it is on an interarea, to have at least: the insulated gate electrode transistor npn npn, sweep trace with the transistorized gate electrode of double as aforementioned dielectric grid type, signal wire with the double as source wiring, with the pixel electrode that is connected aforementioned source grid type transistor drain, become the first transparent insulated substrate of two-dimensional-matrix-like by assortment with the unit picture element of comparative electrode that forms with aforementioned pixel electrode gap specific range etc., and between the second transparent insulated substrate or colored filter relative with the aforementioned first transparent insulated substrate, the liquid crystal indicator that filling liquid crystal forms; It is characterized by: on an interarea of the first transparent insulated substrate, form at least by formed sweep trace of the metal level more than one deck and comparative electrode; Form first semiconductor layer free from foreign meter on the gate insulator island ground that clips on the gate electrode more than one deck; On first semiconductor layer on the gate electrode, form the protection insulation course thinner than aforementioned gate electrode width; On the some of aforementioned protective seam and on first semiconductor layer, form the source electrode that lamination constituted (signal wire) wiring by second semiconductor layer that comprises impurity and second metal level more than one deck, and drain electrode wiring (pixel electrode); Except that the electrode terminal of signal wire, on signal wire, form the photonasty organic insulator; The electrode terminal of sweep trace, in image displaying part zone exceptionally, second metal level that forms by comprising the opening portion that is formed on the gate insulator on the sweep trace.
By this structure, on the passage between source electrode, drain electrode, formation is protected insulation course and in the protection passage, also on the surface of signal wire and drain electrode wiring, is formed the tantalum pentoxide (Ta of the anodic oxide coating of insulativity
2O
5), or aluminium oxide (Al
2O
3) and deactivation function is provided.Therefore, on whole of glass substrate, need not cover passivation insulation, so the thermotolerance of insulated gate electrode transistor npn npn no longer becomes problem.Thereby can obtain to have IPS type liquid crystal indicator with the electrode terminal of signal wire same metal.
The described liquid crystal indicator of claim 9 is characterized in that at least on an interarea of the first transparent insulated substrate, forms by sweep trace that metal level constituted and comparative electrode more than one deck; Form first semiconductor layer free from foreign meter on the gate insulator island ground that clips on the gate electrode more than one deck; On first semiconductor layer on the gate electrode, form the protection insulation course thinner than aforementioned gate electrode width; On the some and first semiconductor layer of aforementioned protective seam, form by second semiconductor layer that comprises impurity and the source electrode that lamination constituted (signal wire) wiring that can anodised metal level, and drain electrode wiring (pixel electrode); Except that the electrode terminal of signal wire, form anodic oxide coating on source electrode, drain electrode wiring surface; The electrode terminal of sweep trace is in image displaying part zone exceptionally, by comprising the opening portion that is formed on the gate insulator on the sweep trace and can being constituted by anodised metal level of forming.
By this structure, on the passage between source electrode, drain electrode, formation is protected insulation course and in the protection passage, also on the surface of signal wire and drain electrode wiring, is formed the tantalum pentoxide (Ta of insulativity anodic oxide coating
2O
5), or aluminium oxide (Al
2O
3) and deactivation function is provided.Therefore, on whole of glass substrate, need not cover passivation insulation, so the thermotolerance of insulated gate electrode transistor npn npn no longer becomes problem.Thereby can obtain to have IPS type liquid crystal indicator with the electrode terminal of signal wire same metal.
At the described liquid crystal indicator of claim 10, it is characterized in that at least on an interarea of the first transparent insulated substrate, form by sweep trace that metal level constituted and comparative electrode more than one deck; Form first semiconductor layer free from foreign meter on the gate insulator island ground that clips on the gate electrode more than one deck; On first semiconductor layer on the gate electrode, form the protection insulation course thinner than aforementioned grid width; On the some of aforementioned protective seam and on first semiconductor layer, form the source electrode that lamination constituted (signal wire) wiring and drain electrode wiring (pixel electrode) by second semiconductor layer that comprises impurity and second metal level more than one deck; Except that the electrode terminal of signal wire, on signal wire, form the photonasty organic insulator; The electrode terminal of sweep trace is in image displaying part zone exceptionally, and second metal level that constitutes is formed with the lamination of second metal level by comprising the opening portion that is formed on the gate insulator on the sweep trace.
By this structure, be to be roughly same configuration with the described liquid crystal indicator of claim 8, can obtain the less I PS of manufacturing process type liquid crystal indicator simultaneously.
The described liquid crystal indicator of claim 11 is characterized in that at least on an interarea of the first transparent insulated substrate, forms by sweep trace that metal level constituted and comparative electrode more than one deck; Form first semiconductor layer free from foreign meter on the gate insulator island ground that clips on the gate electrode more than one deck; On first semiconductor layer on the gate electrode, form the protection insulation course thinner than aforementioned gate electrode width; On the some of aforementioned protective seam and on first semiconductor layer, form by second semiconductor layer that comprises impurity and the source electrode that lamination constituted (signal wire) wiring and drain electrode wiring (pixel electrode) that can anodised metal level; Except that the electrode terminal of signal wire, at source electrode. the drain electrode wiring surface forms anodic oxide coating; The electrode terminal of sweep trace is the zone outside the pixel display part, form by comprising the opening portion that is formed on the gate insulator on the sweep trace second semiconductor layer and can anodised metal level lamination constituted.
By this structure, be to be roughly identical construction with the described liquid crystal indicator of claim 9, also can obtain the liquid crystal indicator of the less I PS of manufacturing process type simultaneously.
By this structure, use one mask plate can handle the formation operation of etching cut-off layer and the island chemical industry preface of semiconductor layer, and realize cutting down photography etching work procedure number.And, when forming pixel electrode, but anodic oxidation source electrode, drain electrode wiring and the result that need not form the reduction manufacturing process of passivation insulation is to use four road mask plates can make TN type liquid crystal indicator.
By this structure, can use one mask plate and cut down the photography etching work procedure number of processed pixels electrode and sweep trace, handle the formation operation of etching cut-off layer and the island chemical industry preface of semiconductor layer with using mask plate, and then realize cutting down photography etching work procedure number.In addition, cut down employed photonasty organic insulator and keep the residual reduction that makes the manufacturing process that no longer needs to form passivation insulation when forming source electrode, drain electrode wiring, the result can use three road mask plates to make TN type liquid crystal indicators.
By this structure, can use one mask plate and reduce the photography etching work procedure number of processed pixels electrode and sweep trace, use one mask plate and handle the formation operation of etching cut-off layer and the island chemical industry preface of semiconductor layer, and then realize the reduction etching work procedure number of photographing.In addition, when forming source electrode, drain electrode wiring, use shadow tone (halftone) exposure technique and only on signal wire, the residual photonasty organic insulator of selectivity and need not form the result that the manufacturing process of passivation insulation cuts down and to use three road mask plates to make TN type liquid crystal indicator.
By this structure, can use one mask plate and cut down the photography etching work procedure number of processed pixels electrode and sweep trace, handle the formation operation of etching cut-off layer and the island chemical industry preface of semiconductor layer with using mask plate, and then realize cutting down photography etching work procedure number.In addition, when forming source electrode, drain electrode wiring, use shadow tone (halftone) exposure technique and only on source electrode, drain electrode wiring, selectivity forms anodic oxide coating and the reduction result that need not form the manufacturing process of passivation insulation can use three road mask plates to make TN type liquid crystal indicator.
Claim 16 is manufacture methods of the described liquid crystal indicator of claim 8.It is characterized in that at least on an interarea of the first transparent insulated substrate, form by the sweep trace that the first metal layer constituted more than one deck and the operation of comparative electrode; Cover above gate insulator of one deck and first amorphous silicon layer and the operation of protecting insulation course free from foreign meter in regular turn; On gate electrode, the residual operation of exposing first amorphous silicon layer than the thinner protection insulation course of gate electrode width; Cover comprehensively and comprise after second amorphous silicon layer of impurity, electrode terminal at sweep trace forms on the zone, form opening portion and remove second amorphous silicon layer and first amorphous silicon layer and gate insulator in the aforementioned opening portion, and expose the operation of sweep trace some; Cover after the second above metal level of one deck, correspond respectively to source wiring (signal wire), the drain electrode wiring (pixel electrode) partly overlapping with aforementioned protection insulation course, and comprise the electrode terminal of the sweep trace of aforementioned opening portion, with electrode terminal, and form the operation of the thicker photonasty organic insulation layer pattern in other zones of Film Thickness Ratio on the signal wire respectively by the signal wire that some constituted of signal wire; With aforementioned photonasty organic insulation layer pattern as mask, and selective removal second metal level and second amorphous silicon layer and first amorphous silicon layer, and form the operation of the electrode terminal of sweep trace and signal wire and source electrode, drain electrode wiring; Reduce the thickness of aforementioned photonasty organic insulation layer pattern, and expose the operation of the electrode terminal and the drain electrode wiring of sweep trace and signal wire.
By this structure, when forming source electrode, drain electrode wiring, use shadow tone (halftone) exposure technique and only on signal wire, the residual photonasty organic insulator of selectivity and need not form the reduction of the manufacturing process of passivation insulation can use four road mask plates to make IPS type liquid crystal indicators.
Claim 17 is manufacture methods of the described liquid crystal indicator of claim 9.It is characterized in that at least on an interarea of the first transparent insulated substrate, form by the sweep trace that the first metal layer constituted more than one deck and the operation of comparative electrode; Cover above gate insulator of one deck and first amorphous silicon layer and the operation of protecting insulation course free from foreign meter in regular turn; The residual operation of exposing first amorphous silicon layer than the thinner protection insulation course of gate electrode width on gate electrode; Cover comprehensively and comprise after second amorphous silicon layer of impurity, form at the electrode terminal of sweep trace and to form opening portion on the zone and remove second amorphous silicon layer and first amorphous silicon layer and gate insulator in the aforementioned opening portion, and expose the operation of the some of sweep trace; Cover one deck above can anodised metal level after, correspond respectively to source wiring (signal wire), the drain electrode wiring (pixel electrode) partly overlapping with aforementioned protection insulation course, electrode terminal with the sweep trace that contains aforementioned opening portion, with the electrode terminal of a part of formed signal wire of signal wire, and form the operation of the thicker photoresist pattern in other zones of Film Thickness Ratio on the electrode terminal of sweep trace and signal wire respectively; As mask, and selective removal can anodised metal level and second amorphous silicon layer and first amorphous silicon layer with aforementioned photoresist pattern, and form the operation of the electrode terminal of sweep trace and signal wire and source electrode, drain electrode wiring; Reduce the thickness of aforementioned photoresist pattern, and expose the operation of source electrode, drain electrode wiring; The operation of the source electrode of anodic oxidation simultaneously, drain electrode wiring on the protection former electrodes terminal.
By this structure, when forming source electrode, drain electrode wiring, use shadow tone (halftone) exposure technique and on source electrode, drain electrode wiring, selectivity forms anodic oxide coating and need not form the reduction of the manufacturing process of passivation insulation, can use four road mask plates to make IPS type liquid crystal indicators.
Claim 18 is manufacture methods of the described liquid crystal indicator of claim 10.It is characterized in that at least on an interarea of the first transparent insulated substrate, form by the sweep trace that the first metal layer constituted more than one deck and the operation of comparative electrode; Cover above gate insulator of one deck and first amorphous silicon layer and the operation of protecting insulation course free from foreign meter in regular turn; Electrode terminal at sweep trace forms on the zone, form to have opening portion, and the protection insulation course on the gate electrode forms the operation of the thicker photoresist pattern in other zones of Film Thickness Ratio in zone; Remove protection insulation course and first amorphous silicon layer and gate insulator in the aforementioned opening portion, and expose the operation of sweep trace some; Reduce the thickness of aforementioned photoresist pattern, and expose the operation of protecting insulation course; The residual operation of exposing first amorphous silicon layer than the thinner protection insulation course of gate electrode width on gate electrode; Remove after the aforementioned photoresist pattern, cover the operation of second amorphous silicon layer that comprises impurity comprehensively; Cover after the second above metal level of one deck, correspond respectively to source wiring (signal wire), the drain electrode wiring (pixel electrode) partly overlapping with aforementioned protection insulation course, and comprise the electrode terminal of the sweep trace of second amorphous silicon layer in the opening portion, and, form the operation of the thicker photonasty organic insulation layer pattern in other zones of Film Thickness Ratio on the signal wire respectively by the electrode terminal of the signal wire that some constituted of signal wire; With aforementioned photonasty organic insulation layer pattern as photomask, and selective removal second metal level and second amorphous silicon layer and first amorphous silicon layer, and form the operation of the electrode terminal of sweep trace and signal wire and source electrode, drain electrode wiring; Reduce the thickness of aforementioned photonasty organic insulation layer pattern, and expose the operation of the electrode terminal and the drain electrode wiring of sweep trace and signal wire.
By this structure, can use with mask plate and handle the formation operation of etching cut-off layer and the opening portion formation operation of gate insulator, and then realize cutting down photography etching work procedure number.In addition, when forming source electrode, drain electrode wiring, use shadow tone (halftone) exposure technique and only on signal wire, the residual photonasty organic insulator of selectivity and need not form the reduction of the manufacturing process of passivation insulation can use three road mask plates to make IPS type liquid crystal indicators.
Claim 19 is manufacture methods of the described liquid crystal indicator of claim 11.It is characterized in that at least on an interarea of the first transparent insulated substrate, form by the sweep trace that the first metal layer constituted more than one deck and the operation of comparative electrode; Cover above gate insulator of one deck and first amorphous silicon layer and the operation of protecting insulation course free from foreign meter in regular turn; Electrode terminal at sweep trace forms on the zone, forms to have opening portion and protection insulation course on the gate electrode forms the operation of the thicker photoresist pattern in other zones of Film Thickness Ratio in zone; Remove protection insulation course and first amorphous silicon layer and gate insulator in the aforementioned opening portion, and expose the operation of sweep trace some; Reduce the thickness of aforementioned photoresist pattern, and expose the operation of protecting insulation course; The residual operation of exposing first amorphous silicon layer than the thinner protection insulation course of gate electrode width on gate electrode; Remove after the aforementioned photoresist pattern, cover the operation of second amorphous silicon layer that comprises impurity comprehensively; Cover one deck above can anodised metal level after, correspond respectively to source wiring (signal wire), the drain electrode wiring (pixel electrode) partly overlapping with aforementioned protection insulation course, and comprise the electrode terminal of the sweep trace of second amorphous silicon layer in the opening portion, and by the electrode terminal of the signal wire that some constituted of signal wire, and form the operation of the thicker photoresist pattern in other zones of Film Thickness Ratio on the electrode terminal of sweep trace and signal wire respectively; Can anodised metal level and second amorphous silicon layer and first amorphous silicon layer with aforementioned photoresist pattern as the mask selective removal, and form the operation of the electrode terminal of sweep trace and signal wire and source electrode, drain electrode wiring; Reduce the thickness of aforementioned photoresist pattern, and expose the operation of source electrode, drain electrode wiring; The operation of the source electrode of anodic oxidation simultaneously, drain electrode wiring on the protection former electrodes terminal.
By this structure, can use the formation operation of handling etching cut-off layer with mask plate and the opening portion of gate insulator to form operation, and then realize the reduction etching work procedure number of photographing.In addition, when forming source electrode, drain electrode wiring, use shadow tone (halftone) exposure technique and only on source electrode, drain electrode wiring, selectivity forms anodic oxide coating and need not form the reduction of the manufacturing process of passivation insulation, can use three road mask plates to make IPS type liquid crystal indicators.
Brief description of drawingsfig
Fig. 1 is the planimetric map of the semiconductor device that is used for display device of expression first embodiment of the invention;
Fig. 2 is manufacturing process's sectional view of the semiconductor device that is used for display device of expression first embodiment of the invention;
Fig. 3 is the planimetric map of the semiconductor device that is used for display device of expression second embodiment of the invention;
Fig. 4 is manufacturing process's sectional view of the semiconductor device that is used for display device of expression second embodiment of the invention;
Fig. 5 is the planimetric map of the semiconductor device that is used for display device of expression third embodiment of the invention;
Fig. 6 is manufacturing process's sectional view of the semiconductor device that is used for display device of expression third embodiment of the invention;
Fig. 7 is the planimetric map of the semiconductor device that is used for display device of expression fourth embodiment of the invention;
Fig. 8 is manufacturing process's sectional view of the semiconductor device that is used for display device of expression fourth embodiment of the invention;
Fig. 9 is the planimetric map of the semiconductor device that is used for display device of expression fifth embodiment of the invention;
Figure 10 is manufacturing process's sectional view of the semiconductor device that is used for display device of expression fifth embodiment of the invention;
Figure 11 is the planimetric map of the semiconductor device that is used for display device of expression sixth embodiment of the invention;
Figure 12 is manufacturing process's sectional view of the semiconductor device that is used for display device of expression sixth embodiment of the invention;
Figure 13 is the planimetric map of the semiconductor device that is used for display device of expression seventh embodiment of the invention;
Figure 14 is manufacturing process's sectional view of the semiconductor device that is used for display device of expression seventh embodiment of the invention;
Figure 15 is the planimetric map of the semiconductor device that is used for display device of expression eighth embodiment of the invention;
Figure 16 is manufacturing process's sectional view of the semiconductor device that is used for display device of expression eighth embodiment of the invention;
Figure 17 is the installment state oblique view of expression liquid crystal panel;
Figure 18 is the equivalent circuit diagram of expression liquid crystal panel;
Figure 19 is the sectional view of the conventional liquid crystal panel of expression;
Figure 20 is the active base plate planimetric map of the conventional example of expression;
Figure 21 is manufacturing process's sectional view of the active base plate of the conventional example of expression;
Figure 22 is the sectional view of the active base plate of expression rationalization;
Figure 23 is manufacturing process's sectional view of the active base plate of expression rationalization.
Embodiment
Based on Fig. 1 to Figure 16 embodiments of the invention are described.Fig. 1 is the planimetric map of the semiconductor device that is used for display device (active base plate) of expression first embodiment of the invention, and Fig. 2 is on the A-A ' line of presentation graphs 1 and on the B-B ' line and the sectional view of the manufacturing process on the C-C ' line.In the same manner, second embodiment, the 3rd embodiment, the 4th embodiment, the 5th embodiment, the 6th embodiment, the 7th embodiment, the 8th embodiment with Fig. 3 and Fig. 4, Fig. 5 and Fig. 6, Fig. 7 and Fig. 8, Fig. 9 and Figure 10, Figure 11 and Figure 12, Figure 13 and Figure 14, Figure 15 and Figure 16, represent the planimetric map of active base plate and the sectional view of manufacturing process with each.In addition, the position identical with existing example distributed identical symbol and omitted its detailed description.
First embodiment
The relevant first embodiment of the present invention is described.The existing example of first embodiment is identical, at first, shown in Fig. 1 (a) and Fig. 2 (a), on an interarea of glass substrate 2, use SPT (sputter) equal vacuum film forming apparatus, with for example Cr, Ta, Mo etc. or cover the alloy of these metals or metal silicide forms the first metal layer about thickness 0.1～0.3 μ m, the sweep trace 11 that forms double as gate electrode 11A by the Micrometer-Nanometer Processing Technology selectivity appearance line 16 of switch on together.More detailed description will illustrate afterwards that in the present invention, the sweep trace material will be almost without limits.
Secondly, on whole of glass substrate 2, use the PCVD device and for example cover in regular turn about thickness 0.3 μ m will be as a SiN of gate insulator
xImpure hardly about (nitrogenize rule) layer 30 and thickness 0.5 μ m and as first amorphous silicon (a-Si) layer 31 of the passage of insulated gate electrode transistor npn npn, and the 2nd SiN of the insulation course of the protection of the conduct about thickness 0.1 μ m passage
xThree kinds of thin layers of layer 31; and; shown in Fig. 1 (b) and Fig. 2 (b); in image displaying part zone exceptionally; form on the zone and to form by the halftone exposure technology and to have opening portion 63A (form at the electrode terminal of common electric capacity line 16 and be opening portion 65A on the zone) at the electrode terminal of sweep trace 11; simultaneously; the protection insulation course forms the zone; that is to say; the thickness of regional 82A on the gate electrode 11A; for example be the 2 μ m photoresist pattern 82As also thicker than the thickness 1 μ m of other regional 82B; 82B; with photoresist pattern 82A; 82B is as mask, and the 2nd SiN of the path protection layer in the selective removal opening portion 63A (with opening portion 65A)
xThe one SiN of layer 32 and first amorphous silicon layer 31 and gate insulator
xLayer 30 and expose the some 72 of sweep trace 11 (energising hold line 16) together.The spacing of the electrode terminal of sweep trace 11 is maximum only to about half of the electrode gap that is used to drive LSI, owing to have the above size of 20 μ m usually, therefore form the making of the mask plate of opening portion 63A (white portion), and it is very easy to finish the accuracy control of size.
Secondly, by ashing means such as oxidation plasmas above-mentioned photoresist pattern 82A, 82B are cut down thickness 1 μ m when above, photoresist pattern 82B disappears, as Fig. 1 (c) with shown in Fig. 2 (c), at the 2nd SiN
xWhen layer 32 exposes, can only form selectivity formation photoresist pattern 82C on the zone at the protection insulation course.And, handle in above-mentioned oxygen plasma, preferably strengthen anisotropy in order to control the pattern change in size, but when the pattern precision is low, do not have its necessity.Photoresist pattern 82C, that is to say, the pattern width of etching cut-off layer, it is the size between source electrode, drain electrode wiring, add the mask plate quality of fit, so be 4～6 μ m between source electrode, drain electrode wiring, and quality of fit is when being ± 3 μ m, dimensional accuracy is 10～12 μ m, and dimension precision requirement is not strict.But when photoresistance pattern 82A converted 82C to, the photoresistance pattern evenly waited when 1 μ m is cut down on ground, size is not only dwindled 2 μ m, and the mask plate quality of fit when forming source electrode, drain electrode wiring, is reduced into 1 μ m and becomes ± 2 μ m, compare with the former, the latter's influence is stricter to the requirement of technology.Therefore, in above-mentioned oxygen plasma is handled,, preferably strengthen anisotropy in order to control the variation of pattern dimension.Particularly, preferably by RIE (reactive ion etching, Reactive Ion Etching) mode, or oxygen plasma processing with ICP (the Inductive Coupled Plasama) mode or TCP (TransferCoupled Plasama) mode in high-density plasma source.And, shown in Fig. 1 (d) and Fig. 2 (d), with photoresist pattern 82C as mask, and with the 2nd SiN
xLayer 32 is etched to thinner than gate electrode 11A width, becomes the 2nd SiN
xLayer 32A simultaneously, exposes first amorphous silicon layer 31.The protection insulation course forms the zone; that is to say; the size of photoresist pattern 82C (black region); even minimum dimension also has 10 μ m sizes; not only the mask plate making is more or less freely as shadow tone (halftone) exposure area with the zone beyond black region and the white portion; and compare with the insulated gate transistor of channel etch type; the starting current of decision insulated gate electrode transistor npn npn be the size of path protection insulation course 32A; rather than the size of 12,21 of source electrodes, drain electrode wiring, therefore be easier to process management.Particularly, for example be of a size of 5 ± 1 μ m between the source electrode of channel etch type, drain electrode wiring, be of a size of 10 ± 1 μ m at the protection insulation course of etching stop type, under identical development conditions, the variable quantity of conducting electric current approximately reduces by half.At this moment; the sweep trace 11 a part of 72 of exposure is owing to be etching gas or the medicine that is exposed to protection insulation course 32A; therefore along with the material difference of sweep trace 11; the thickness that should be noted that the some 72 that produces sweep trace 11 is cut down; even but the situation that has aluminium alloy for example to expose; if select Ti to be used as source electrode, drain electrode wiring material at orlop, can avoid the influence of oxidation easily.Other as illustrated at existing example, also can adopt the lamination of for example in advance sweep trace 11 being made aluminium/titanium/aluminium, even the titanium on upper strata disappears, also can adopt the method for making of removing aluminium and the titanium of lower floor being exposed.
After removing aforementioned photoresist pattern 82C, use the PCVD device on whole of glass machine plate 2, for example to cover after for example phosphorous second amorphous silicon layer 33 as impurity with the thickness about 0.05 μ m, use SPT equal vacuum film forming apparatus, cover the heating resisting metal thin layers 34 such as Ti, Ta that for example conduct about thickness 0.1 μ m can anodised heat resistant metal layer in regular turn; And the identical conduct about thickness 0.3 μ m can anodised low resistance wiring layer aluminum film layer 35; And the identical conduct about thickness 0.1 μ m can anodised intermediate conductive layer heating resisting metal thin layers 36 such as Ta.Then, pass through Micrometer-Nanometer Processing Technology, usability photosensitiveness resin pattern and etching in regular turn are by source electrode, drain electrode wiring material that this three-layer thin-film constituted, with second amorphous silicon layer 33 and first amorphous silicon layer 31, and expose gate insulator 30, with shown in Fig. 2 (e), selectivity forms the drain electrode 21 of the insulated gate electrode transistor npn npn that is made of lamination 34A, 35A, 36A and the signal wire 12 of double as source electrode as Fig. 1 (e).And, usually, forming source electrode, drain electrode wiring 12,21 o'clock, some 72 ground that also comprise sweep trace form scan-line electrode terminal 5 simultaneously, but, also there is the possibility that does not form electrode terminal as shown in the figure herein along with the material difference of source electrode, drain electrode wiring.If the comparatively loose words of restriction of resistance value, can simplify the structure of source electrode, drain electrode wiring 12,21 and make the Ta individual layer, it goes up the aluminium alloy of this external interpolation Nd that chemical potential descends and reacts with the chemical corrosion of ITO in alkaline solution and be suppressed, therefore in the case, need not intermediate conductive layer 36, can make the stromatolithic structure of source electrode, drain electrode wiring 12,21 make double-layer structural, how many structures of source electrode, drain electrode wiring 12,21 is simplified.
Form after source electrode, the drain electrode wiring 12,21, using SPT equal vacuum film forming apparatus to cover for example transparency conducting layer about ITO formation 0.1～0.2 μ m on whole of glass substrate 2, shown in Fig. 1 (f) and Fig. 2 (f), by Micrometer-Nanometer Processing Technology make the intermediate conductive layer 36A comprise drain electrode 21 some and on gate insulator 30 selectivity form pixel electrode 22.At this moment, on the some 72 (or electrode terminal 5) and image displaying part signal wire 12 exceptionally of sweep trace, also form nesa coating and become electrode terminal 5A, the 6A of transparent conductivity.And at this, the short-circuit line 40 that transparent conductivity is set with existing example is identical, forms elongated strip between electrode terminal 5A, 6A and the short-circuit line 40 and makes its high resistanceization be easy to the high resistance of using as the electrostatic prevention countermeasure by making.
Secondly, shown in Fig. 1 (g) and Fig. 2 (g), the photoresist pattern 83 that will be used for optionally forming pixel electrode 22 patterns is as photomask, irradiates light anodic oxidation simultaneously source electrode, drain electrode wiring 12,21 and in its surface formation oxide layer.At source electrode, expose Ta above the drain electrode wiring 12,21, and expose Ta, Al, Ti in the side, the lamination of the second amorphous silicon layer 33A and the first amorphous silicon layer 31A makes by anodic oxidation that the second amorphous silicon layer 33A is rotten and is impure silicon oxide layer (SiO
2) 66, make the rotten silicon oxide layer (SiO free from foreign meter of being of the first amorphous silicon layer 31A
2) 67, make Ti rotten for belonging to semi-conductive titanium dioxide (TiO
2) 68, it is the aluminium oxide (AL of insulation course that AL is gone bad
2O
3) 69, and make that Ta is rotten to be the tantalum pentoxide (Ta at insulation course
2O
5) 70.Though titanium oxide layer 68 is not an insulation course, its thickness as thin as a wafer and to expose area also little, therefore can not throw into question to passivation in principle, and heating resisting metal thin layer 34A preferably selects Ta in advance.Yet because Ta is different from Ti, it is short of the surface area oxide layer at the bottom of absorption base and the characteristic that is easy to the Ohmic contact function must be noted.
On drain electrode wiring 21, in order to form good membranous anodic oxide coating, in irradiates light, implement anodic oxidation, this is the emphasis of anodic oxidation operation, and is open in existing example kind.Particularly, shine about 10,000 luxs (lux) abundant strong light and the leakage current of insulated gate electrode transistor npn npn if surpass μ A, calculate from the area of drain electrode 21 and can get 10m/cm
2About anodic oxidation be to obtain good membranous current density.But, even the anodic oxide coating on the drain electrode wiring 21 is membranous insufficient, generally speaking also can obtain abundant trustworthiness, its reason is the drive signal that is applied to liquid crystal cells, be essentially interchange, so that the mode that the DC voltage composition between comparative electrode 14 and the pixel electrode 22 (drain electrode 21) reduces, when image is checked, adjust the voltage (reducing flicker adjustment) of comparative electrode 14, on the ultimate principle with only on signal wire 12 mode of no flip-flop electric current form insulation course in advance and get final product.
Just very abundant with the passivation that each oxide layer of the formed tantalum pentoxide 70 of anodic oxidation, aluminium oxide 69, titanium dioxide 68, silicon oxide layer 66,67 thickness about with 0.1～0.2 μ m is used as connecting up, make reactant liquor such as spent glycol and the voltage that applies can be realized with the identical 100V of surpassing.Answer points for attention during the anodic oxidation of source electrode, drain electrode wiring 12,21, though not shown but all signal wires 12 must be formed the in parallel or series connection of electricity, if after certain of manufacturing process when not removing this series/parallel, not only the electric checking of active base plate 2 has problem, and obstacle is also arranged when continuous cropping is the liquid crystal indicator real work.Can cause evapotranspiring by laser light illumination as the releasing means, or be comparatively easy method, detailed here by the mechanicalness excision that scriber carries out being produced.
Covering pixel electrodes 22 in advance with photoresist pattern 83 not only need not anodic oxidation pixel electrode 22, and the kinetic current that flows into drain electrode 21 via the insulated gate electrode transistor npn npn need not guarantee can solve more than the necessary size.
At last, remove aforementioned photoresist pattern 83, with shown in Fig. 2 (h), finish active base plate 2 (semiconductor device that is used for display device) as Fig. 1 (h).The active base plate 2 of gained like this and colored filter are fitted and make liquid crystal panelization, finish the first embodiment of the present invention.Structure about storage capacitors 15, shown in Fig. 1 (h), illustrate and clip the example that gate insulator 30 planarityes overlapping (upper left oblique line part toward the bottom right) are constituted in storage capacitors 16 and the pixel electrode 22, but the structure of storage capacitors 15 is not limited to this, between pixel electrode 22 and leading portion sweep trace 11, also can clip the structure of the insulation course that comprises gate insulator 30.In addition, other structures also can, but omit its explanation.Similarly, form operation, therefore use transparency conducting layer conductive material or semiconductor layer in addition also to be easy to carry out antistatic countermeasure owing to have the contact hole of sweep trace.
Among first embodiment; form at the contact hole of sweep trace operation and path protection layer (etching cut-off layer or protection insulation course) this low pattern precision of formation operation layer suitable shadow tone (halftone) exposure technique and the etching work procedure of photographing is cut down; make active base plate with four road mask plates; but because with the formation of one mask plate processed pixels electrode and sweep trace; can cut down operation again and can make active base plate, therefore be described in detail as second to the 4th embodiment with three road mask plates.
Second embodiment
In a second embodiment, at first, on an interarea of glass substrate 2, transparency conducting layer 91 about use SPT equal vacuum film forming apparatus covering thickness 0.1～0.2 μ m is ITO for example, with the first metal layer 92 that covers about thickness 0.1～0.3 μ m, shown in Fig. 3 (a) and Fig. 4 (a), the lamination that forms by transparency conducting layer 91A and the first metal layer 92A by the Micrometer-Nanometer Processing Technology selectivity is constituted, the also sweep trace 11 of double as gate electrode 11A, with by the analog pixel electrode 93 that lamination constituted of transparency conducting layer 91B and the first metal layer 92B with by the simulation electrode terminal 94 of the signal wire that lamination constituted of transparency electrode 91C and the first metal layer 92C.For example select the refractory metals such as Cr, Ta, Mo or the alloy of these metals or metal silicide to be used as the first metal layer.Sandwich gate insulator and improve dielectric voltage withstand with signal wire, in order to improve yield rate, this electrode, preferably carry out the inclined-plane control of section shape by thousand method etchings (dry etch), but the dry etch technique of ITO uses the technology of HI (hydrogen iodide) or hydrogen bromide (HBr) to be developed at etching gas, but the accumulating amount at the resultant of reaction of exhaust system is too big, does not reach the degree of practicability, and therefore the splash that is to use Ar (argon gas), the etching of adopting at present gets final product.
Secondly, on whole of glass substrate 2, cover as the transparent insulating layer of plasma protective seam TaO for example with the thickness about 0.1 μ m
xOr SiO2 and form 71.This plasma protective seam 71 is in order to prevent at the SiN that is formed gate insulator by PCVD device described later
xThe time, the transparency conducting layer 91A, the 91B that expose in the limit of sweep trace 11 and analog pixel electrode 93 part are reduced, and make SiN
xMembranous change necessary, detailed content is opened clear 59-9962 communique with reference to the spy of existing example.
Cover after the plasma protective seam 71, identical with first embodiment, use PCVD device forms the SiN as gate insulator with 0.2 μ m-0.05 μ m-0.1 μ m left and right sides thickness in regular turn
xFirst amorphous silicon layer 31 of layer 30 and the impure hardly passage as the insulated gate electrode transistor npn npn, and as the 2nd SiN of the insulation course of protection passage
xThree kinds of thin layers such as layer 32 grade; on analog pixel electrode 93; in opening portion 74 and image displaying part zone exceptionally; form at the electrode terminal of sweep trace 11 and to have opening portion 63A on the zone; with on simulation electrode terminal 94; has opening portion 64A; simultaneously; the protection insulation course forms the zone; just; the thickness of regional 84A on the gate electrode 11A, for example 2 μ m photoresist pattern 84A, the 84B also thicker than the thickness 1 μ m of other regional 84B forms by shadow tone (halftone) exposure technique.At this, gate insulator is because become a plasma protective seam and a SiN
xThe lamination of layer, a SiN
xCan form than also thin in the past.With photoresist pattern 84A, 84B as mask, shown in Fig. 3 (b) and Fig. 4 (b), the 2nd SiN in the above-mentioned opening portion of etching in regular turn
xLayer 32; first amorphous silicon layer 31; gate insulator 30; plasma protective seam 71, and the first metal layer 92 expose the transparency conducting layer of sweep trace 11 somes; and make the electrode terminal 5A of sweep trace; similarly, expose the transparency conducting layer of simulation electrode terminal 94 and make the electrode terminal 6A of signal wire, expose the transparency conducting layer 91B of analog pixel electrode 93 and make pixel electrode 22.
Secondly,, when making above-mentioned photoresist pattern 84A, 84B reduction thickness 1 μ m above, remove photoresist pattern 84B, with shown in Fig. 4 (b), can expose the 2nd SiN as Fig. 3 (b) by ashing means such as oxygen plasma
xIn the time of layer 32B, only form selectivity formation photoresist pattern 84C on the zone at the protection insulation course.On above-mentioned oxygen plasma is handled,, therefore preferably strengthen anisotropy (anisotropy), and suppress the variation of pattern dimension in order not reduce the mask quality of fit of source electrode described later, drain electrode wiring formation operation.And shown in Fig. 3 (d) and Fig. 4 (d), with photoresist pattern 84C as mask, and selective etch the 2nd SiN
xLayer 32B forms two SiN thinner than the pattern width of gate electrode 11A
xLayer 32A also exposes the first amorphous silicon layer 31B simultaneously.At this moment, expose the electrode terminal 5A of sweep trace of the transparent conductivity in above-mentioned opening portion 63A and the electrode terminal 6A and the pixel electrode 22 of signal wire, though be exposed to the 2nd SiN
xThe etching gas of layer 32B is that etching gas can't produce the thickness that reduces these transparency conducting layers but be to use fluorine, or changes resistance value, or changes flaw problem such as transparency, and is therefore very suitable.
Then, remove after the aforementioned photoresist pattern 84C, use the PCVD device on whole of glass substrate 2, cover for example for example phosphorous second amorphous silicon layer 33 of 0.05 μ m left and right sides thickness in regular turn as impurity, use SPT equal vacuum film forming apparatus, the thin layer such as heating resisting metal such as for example Ti, Ta etc. 34 that covers about thickness 0.1 μ m is used as heat resistant metal layer, and the aluminum film layer 35 about covering thickness 0.3 μ m is as the low resistance wiring layer.Then, with the formed source electrode of this two-layer thickness, drain electrode wiring material, with second amorphous silicon layer 33 and the first amorphous silicon layer 31B etc., pass through Micrometer-Nanometer Processing Technology, usability photosensitiveness resin pattern 85 etchings in regular turn and expose gate insulator 30A, shown in Fig. 3 (e) and Fig. 4 (e), optionally form the some comprise pixel electrode 22 and by the drain electrode 21 of the formed insulated gate electrode transistor npn npn of the lamination of 34A and 35A, with the some of the electrode terminal 6A that comprises signal wire, the also signal wire 12 of double as source electrode.The electrode terminal 5A of sweep trace and the electrode terminal 6A of signal wire when finishing the etching of source electrode, drain electrode wiring 12,21, expose on glass substrate 2.And when if the restriction of resistance value is not strict, the structure of source electrode, drain electrode wiring 12,21 can be reduced to the individual layer of Ta, Cr, Mo etc.
So carry out, resulting active base plate 2 and colored filter are fitted and make liquid crystal panelization, finish the second embodiment of the present invention.In a second embodiment, photoresist pattern 85 is because the contact liquid crystal, therefore photoresist pattern 85 be not employing be the common photosensitive resin of principal ingredient with the clear resin of phenolic acid, and be to use purity height, principal ingredient to use the higher photonasty organic insulator of thermotolerance that contains polyacrylic resin or polyimide resin is very important, some can make liquidation by heating with the material difference, and the mode that covers the side of source electrode, drain electrode wiring 12,21 constitutes, in this case, improve the trustworthiness of liquid crystal panel more.Formation about storage capacitors 15; shown in Fig. 3 (e); with source electrode; drain electrode wiring 12; 21; with a part of formed storage electrode 73 that comprises pixel electrode 22; grade with the jut that is arranged on leading portion sweep trace 11; sandwich plasma protective seam 71A; with gate insulator 30A; and the overlapping existing example of formation of planarity illustrates (upper left oblique line part 52 toward the bottom right); but the structure of storage capacitors 15 is not limited to this; as first embodiment, also can adopt between the common electric capacity line 16 and pixel electrode 22 of sweep trace and formation simultaneously, sandwich comprises the formation of the insulation course of gate insulator 30A.In addition, other structures also are fine, but omit its detailed description.
In a second embodiment, it must be restriction on the device of transparency conducting layer constitutes that the electrode terminal of sweep trace and the electrode terminal of signal wire all have, but, remove device, the technology of its restriction and also can implement, this is illustrated as the 3rd, the 4th embodiment.
The 3rd embodiment
In the 3rd embodiment, shown in Fig. 5 (d) and Fig. 6 (d),, be to carry out with roughly identical technology with second embodiment to the formation operation of contact formation operation and path protection layer (etching cut-off layer).But, because reason described later not necessarily needs to use simulation electrode terminal 94.Thereafter, remove photoresist pattern 84C, use the PCVD device and on whole of glass substrate 2, for example cover and comprise impurity for example after second amorphous silicon layer 33 of phosphorus with the thickness about 0.05 μ m, on the formation operation of source electrode, drain electrode wiring, use SPT equal vacuum film forming apparatus, the thin layer such as heating resisting metal such as for example Ti, Ta etc. 34 that covers in regular turn about thickness 0.1 μ m is used as heat resistant metal layer, and the aluminum film layer 35 about thickness 0.3 μ m is as the low resistance wiring layer.Then, the source electrode that this double-layer films constituted, the drain electrode wiring material, with second amorphous silicon layer 33 and the first amorphous silicon layer 31B, pass through Micrometer-Nanometer Processing Technology, 86 etchings in regular turn of usability photosensitiveness resin pattern, and expose gate insulator 30A, shown in Fig. 5 (e) and Fig. 6 (e), selectivity forms the some contain pixel electrode 22 and by the drain electrode 21 of the insulated gate electrode transistor npn npn that lamination constituted of 34A and 35A, the also signal wire 12 of double as source wiring, forming source electrode, drain electrode wiring 12,21 o'clock, also comprise the scan-line electrode terminal that exposes simultaneously and form regional 5A and form the electrode terminal 5 of sweep trace and the electrode terminal that some constituted 6 by signal wire.That is to say,, not necessarily need to use simulation electrode terminal 94 as second embodiment.At this moment, the thickness of 86A on the signal wire 12, for example be 3 μ m, than on the drain electrode 21 with electrode terminal 5,6 on, the thickness 1.5 μ m that reach the 86B on the storage electrode 73 also want thick photoresist pattern 86A, 86B to form in advance by shadow tone (halftone) exposure technique, and this is the key character of the 3rd example.Minimum dimension corresponding to the 86B of electrode terminal 5,6 is tens of μ m, and is bigger; Though mask plate is made and the manufactured size management is also very easy, but owing to the minimum dimension corresponding to signal wire 12 regional 86A is 4～8 μ m, dimension precision requirement is higher, therefore is necessary to adopt the pattern than areolar to be used as shadow tone (halftone) zone.But, illustrated as existing example, source electrode, the drain electrode wiring 12,21 of formation are compared with the second etch processing with handling with single exposure, source electrode of the present invention, drain electrode wiring 12,21, as long as handle with an etch processes and can form with single exposure, therefore the factor that influences the pattern width change is less, and the size of source electrode, drain electrode wiring 12,21 management, and 12,21 of source electrodes, drain electrode wiring, the size of passage length management just also than the easier management of carrying out the pattern precision of shadow tone (halftone) exposure technique in the past.In addition; compare with the insulated gate transistor of channel etch type; the conducting electric current of decision insulated gate electrode transistor npn npn be the size of path protection insulation course 32A, therefore the rather than size of 12,21 of source electrodes, drain electrode wiring is appreciated that it is easier to carry out process management.
Form source electrode, drain electrode wiring 12, after 21, by ashing means such as oxygen plasma with above-mentioned photoresist pattern 86A, when 86B reduction thickness 1.5 μ m are above, photoresist pattern 86B disappears, shown in Fig. 5 (f) and Fig. 6 (f), can be at drain electrode 21 and electrode terminal 5,6 when exposing, only on signal wire 12, selectivity forms photoresist pattern 86C, when handling the pattern width that makes photoresist pattern 86C and attenuate with above-mentioned oxygen plasma, exposes the upper surface of signal wire 12 and reduces trustworthiness, therefore preferably need to strengthen anisotropy (anisotropy), suppress the variation of pattern dimension.In addition, if when the restriction of resistance value is not strict, the structure of source electrode, drain electrode wiring 12,21 can be reduced to individual layers such as Ta, Cr, Mo.
To so carry out the applying of resulting active base plate 2 and colored filter and make liquid crystal panelization, finish the third embodiment of the present invention.Even in the 3rd embodiment, photoresist pattern 86C is owing to touch liquid crystal, therefore not adopt with the clear resin of phenolic acid be the common photosensitive resin of principal ingredient to photoresist pattern 86C, and adopt purity height, principal ingredient to use the higher photonasty organic insulator of thermotolerance that contains polyacrylic resin or polyimide resin is very important, some can make liquidation by heating along with the material difference, and the mode that covers the side of source electrode, drain electrode wiring 12,21 constitutes, and improves the trustworthiness of liquid crystal panel in this case more.The pass is in the formation of storage capacitors 15; shown in Fig. 5 (f); source electrode, drain electrode wiring 12,21; with a part of formed storage electrode 73 that comprises pixel electrode 22; grade with the jut that is arranged on leading portion sweep trace 11; sandwich plasma protective seam 71A and gate insulator 30A, and the overlapping existing example of formation of planarity illustrates (upper left oblique line part 52 toward the bottom right).In addition, be connected to form at electrode terminal and form transparent conductivity pattern 6A (simulation electrode terminal 91C) under regional 5A and the signal wire 12, electrically conducting transparent layer pattern with short-circuit line 40, by its shape is made elongated wire, can be used as the high resistance wiring of antistatic countermeasure, but can certainly adopt the antistatic countermeasure that has used other electroconductive components.
In the third embodiment of the present invention, be that only drain electrode 21 exposes under the state of maintenance electric conductivity forming organic insulator on the signal wire 12, even so also can obtain the reason of abundant trustworthiness, be to be essentially AC signal because be applied to the drive signal of liquid crystal cells, mode with the minimizing of the DC voltage composition between comparative electrode 14 and the pixel electrode 22 (drain electrode 21), when checking, image adjusts the voltage (reducing the adjustment of flicker) of comparative electrode 14, therefore, so that only on signal wire 12, have the mode of flip-flop to form insulation course in advance to get final product.
In the of the present invention second and the 3rd embodiment, only forming organic insulator on source electrode, the drain electrode wiring and on the signal wire respectively, and promote deleting of manufacturing process, but the thickness of organic insulator is generally more than the 1 μ m, therefore when the orientation of the alignment film that uses abrasive cloth is handled, its height may cause non-orientation state or the guaranteeing of gap precision of liquid crystal cells may occur hindering.So, make it possess passivation (passivation) technology of changing into organic insulator to append minimal process number at the 4th embodiment.
The 4th embodiment
In the 4th embodiment, shown in Fig. 7 (d) and Fig. 8 (d), form to contact till the formation operation of operation and path protection layer (etching cut-off layer), be to carry out with roughly identical technology with the 3rd embodiment.Remove after the photoresist pattern 84C, use the PCVD device on whole of glass substrate 2, cover for example second amorphous silicon layer 33 of the impure for example phosphorus of 0.05 μ m left and right sides thickness, form operation at source electrode, drain electrode wiring, use SPT equal vacuum film forming apparatus, covering in regular turn that thin layer such as heating resisting metal such as for example Ti, Ta etc. 34 about thickness 0.1 μ m is used as can anodised heat resistant metal layer, and the aluminum film layer 35 about thickness 0.3 μ m be used as identical can anodised low resistance wiring layer.Then, by Micrometer-Nanometer Processing Technology usability photosensitiveness resin pattern 87 source electrode, the drain electrode wiring material that are constituted of this double-layer films of etching in regular turn, with second amorphous silicon layer 33 and the first amorphous silicon layer 31B, and expose gate insulator 30A, shown in Fig. 7 (e) and Fig. 8 (e), selectivity forms the some contain pixel electrode 22 and by the drain electrode 21 of the insulated gate electrode transistor npn npn that lamination constituted of 34A and 35A and the also signal wire 12 of double as source wiring; Be included in the scan-line electrode terminal that exposes when forming source electrode, drain electrode wiring 12,21 simultaneously and form regional 5A, also form the electrode terminal 5 of sweep trace and the electrode terminal that some constituted 6 by signal wire.At this moment, the thickness (black region) of 87A on the electrode terminal 5,6 for example is 3 μ m, ratio is corresponding to source electrode, drain electrode wiring 12,21 and the thickness 1.5 μ m of the regional 87B (gray-scale areas) of storage electrode 73 also want thick photoresist pattern 87A, 87B forms in advance by shadow tone (halftone) exposure technique, and this is the key character of the 4th embodiment.
Form after source electrode, the drain electrode wiring 12,21, by ashing means such as oxygen plasma above-mentioned photoresist pattern 87A, 87B are cut down thickness 1.5 μ m when above, photoresist pattern 87B disappears, expose source electrode, drain electrode wiring 12,21 and storage electrode 73, the while is selectivity formation photoresist pattern 87C on electrode terminal 5,6 only.Even handle the pattern width of photoresist pattern 87C attenuates in above-mentioned oxygen plasma, only around electrode terminal 5,6, form anodic oxide coating with big pattern dimension, to electrical specification and almost not influence such as yield rate and quality, this is the what is worth mentioning feature.With photoresist pattern 87C as mask and irradiates light, simultaneously shown in Fig. 7 (f) and Fig. 8 (f), anodic oxidation source electrode, drain electrode wiring 12,21 and form oxide layer 68,69, the second amorphous silicon layer 33A at the downside of source electrode, drain electrode wiring 12,21 is exposed in anodic oxidation simultaneously, with the first amorphous silicon layer 31A, and the silicon oxide layer (SiO of formation insulation course
2) 66,67.
After finishing anodic oxidation, remove photoresist pattern 87C, shown in Fig. 7 (g) and Fig. 8 (g), expose the electrode terminal 5,6 that is constituted by the low resistance thin film layer that is formed anodic oxide coating in its side.The side of the electrode terminal 6 of sweep trace by being used for the high resistance shorts line 91C of electrostatic prevention, and flows into oxidation current, therefore compares with the electrode terminal 5 of signal wire, can understand the thickness of insulating layer attenuation that it is formed on the side.And, if when the restriction of resistance value is not strict, the structure of source electrode, drain electrode wiring 12,21, can be simplified to can anodised Ta individual layer.The active base plate that obtains 2 like this and colored filter are fitted and make liquid crystal panelization, finish the 4th example of the present invention.Structure about storage capacitors 15; shown in Fig. 7 (g); with source electrode, drain electrode wiring 12,21 with comprise a part of formed storage electrode 73 of pixel electrode 22; grade with the jut that is arranged on leading portion sweep trace 11; the overlapping existing example of formation of sandwich plasma protective seam 71A and gate insulator 30A and planarity illustrates (upper left oblique line part 52 toward the bottom right).
In the 4th embodiment, so, during the anodic oxidation of source electrode, drain electrode wiring 12,21 and the second amorphous silicon layer 33A and the first amorphous silicon layer 31A, because the pixel electrode 22 that is electrically connected with drain electrode 21 also exposes, so pixel electrode 22 is greatly different with first embodiment also simultaneously by the anodic oxidation this point.Therefore, also because along with the membranous difference according to the transparency conducting layer that constitutes pixel electrode 22 makes anodic oxidation increase resistance value, in this case, the suitable film forming condition of change transparency conducting layer and need make oxygen membranously in advance, but anodic oxidation can't reduce the transparency of transparency conducting layer.In addition, for the electric current of anodic oxidation drain electrode 21 with pixel electrode 22, also the passage by the insulated gate electrode transistor npn npn provides, but,, no matter shine how strong outer light so need bigger kinetic current or reaction for a long time because pixel electrode 22 areas are bigger, the resistance of channel part all can become obstacle, on drain electrode 21 and storage electrode 73, form with signal wire 12 on equal plasma membrane and the anodic oxide coating of thickness, only depend on the prolongation in reaction time to be difficult to realize.But,, can obtain in practicality, not having the trustworthiness of obstacle mostly even how much complete inadequately the anodic oxide coating that is formed on the drain electrode wiring 21 is.Reason is as discussed previously, the drive signal that is applied to liquid crystal cells is essentially interchange, between comparative electrode 14 and pixel electrode 22 (drain electrode 21), so that the mode that the DC voltage composition tails off is adjusted the voltage (reducing the adjustment of flicker) of relative voltage 14 when image is checked, that is to say, get final product so that the mode that flip-flop only flows through on signal wire 12 forms insulation course in advance.
Above Shuo Ming liquid crystal indicator, be to use TN type liquid crystal cells, but later pixel electrode specific range and the liquid crystal indicator of IPS (In-Plain-Switching) mode that a pair of comparative electrode that is formed and pixel electrode are controlled the horizontal direction electric field at interval, the operation that also is suitable for the present invention's suggestion is cut down, and illustrates with the embodiment that introduces later.
The 5th embodiment
In the 5th embodiment, at first, on an interarea of glass substrate 2, use the first metal layer about SPT equal vacuum film forming apparatus covering thickness 0.1～0.3 μ m, with shown in Figure 10 (a), form the sweep trace 11 and comparative electrode 16 of double as gate electrode 11A as Fig. 9 (a) by the Micrometer-Nanometer Processing Technology selectivity.
Secondly, on whole of glass substrate 2, use the PCVD device to cover a SiN in regular turn as gate insulator with for example thickness about 0.3 μ m-0.05 μ m-0.1 μ m
x(silicon nitride) layer 30 and impure hardly and as first amorphous silicon (a-Si) of insulated gate electrode transistor npn npn passage layer 31 with as the 2nd SiN of the insulation course of protection passage
xThree kinds of thin layers such as layer 32 grade are shown in Fig. 9 (b), by the 2nd SiN on the optionally residual gate electrode 11A of Micrometer-Nanometer Processing Technology
xLayer makes its width thinner and expose first amorphous silicon layer 31 and be used as 32A than gate electrode 11A.Then as Figure 10 (b) shown in, use the PCVD device and on whole of glass substrate, comprise for example second amorphous silicon layer 33 of phosphorus of impurity with for example covering of the thickness about 0.05 μ m.
Secondly, pass through Micrometer-Nanometer Processing Technology, shown in Fig. 9 (c) and Figure 10 (c), zone outside the pixel display part, electrode terminal at sweep trace 11 forms the zone, form opening portion 63A (form form opening portion 65A on the zone at the also electrode terminal of the comparative electrode 16 of double as capacitor storage beam), second amorphous silicon layer 33 and first amorphous silicon layer 31 and gate insulator 30 in the selective removal opening portion 63A, and expose the some 72 of sweep trace 11.
Secondly, on whole of glass substrate 2, use SPT equal vacuum film forming apparatus, cover in regular turn and for example be used as heat resistant metal layer with heating resisting metal thin layers 34 such as Ti, Ta about thickness 0.1 μ m, then the aluminum film layer 35 about thickness 0.3 μ m is used as the low resistance wiring layer.Then, by Micrometer-Nanometer Processing Technology usability photosensitiveness resin pattern 86A, 86B etching in regular turn is by source electrode that this double-layer films constituted, the drain electrode wiring material, with second amorphous silicon layer 33 and first amorphous silicon layer 31, and expose gate insulator 30, shown in Fig. 9 (d) and Figure 10 (d), on gate insulator 30, selectivity forms the drain electrode 21 by the gate insulator transistor npn npn that becomes pixel electrode that lamination constituted of 34A and 35A, the also signal wire 12 of double as source wiring, form source electrode, drain electrode wiring 12,21 o'clock, comprise the some 72 of the sweep trace 11 that exposes in the opening portion 63 and also form simultaneously by the electrode terminal 5 of sweep trace the electrode terminal that some constituted 6 with signal wire 12.At this moment, identical with the 3rd embodiment, the thickness of 86A on the signal wire 12 for example is 3 μ m, forms than also thick photoresist pattern 86A, the 86B of thickness 1.5 μ m that reaches the 86B on the electrode terminal 5,6 on the drain electrode 21 by shadow tone (halftone) exposure technique.
Form after source electrode, the drain electrode wiring 12,21, by ashing means such as oxygen plasma, when making above-mentioned photoresist pattern 84A, 84B reduction thickness 1.5 μ m above, photoresist pattern 86B disappears, shown in Fig. 9 (e) and Figure 10 (e), when exposing drain electrode wiring 21 and electrode terminal 5,6, only selectivity forms photoresist pattern 86C on signal wire 12.Handle by above-mentioned oxygen plasma, preferably the mode that attenuates with the pattern width that does not make photoresist pattern 86C is strengthened anisotropy (anisotropy) and the variation of inhibition size, and this is also describing in detail before.And when if the restriction of resistance value is not strict, the structure of source electrode, drain electrode wiring 12,21 also can be simplified to the individual layer of Ta, Cr, Mo etc.
Thus, resulting active base plate 2 and colored filter are fitted and make liquid crystal panelization, finish the fifth embodiment of the present invention.Photoresist pattern 86C, be not employing with the common photosensitive resin of the clear resin of phenolic acid as principal ingredient, but must adopt purity height, principal ingredient to use the higher photonasty organic insulator of thermotolerance that contains polyacrylic resin or polyimide resin, described certainty is in narration before.Structure about storage capacitors 15, shown in Fig. 9 (e), comparative electrode (capacitor storage beam) 16 and pixel electrode (drain electrode) 21 therebetween person's gate insulators 30 have been illustrated and the example of planarity overlapping areas 50 (upper left oblique line part) formation storage capacitors 15 toward the bottom right, it also is possible constituting storage capacitors 15 as for drain electrode 21 and leading portion sweep trace 11 sandwich gate insulators 30, but omits its detailed description at this.And, in Fig. 9 (e), connect with the high resistance parts between the electrode terminal 5 of sweep trace and the electrode terminal 6 of signal wire, in the occasion of IPS type liquid crystal indicator because do not need transparency conducting layer, therefore use the sweep trace material, any one of signal line material or semiconductor layer, and the antistatic countermeasure or the designing technique that connect with the insulated gate electrode transistor npn npn or the elongated electric conductivity circuit of OFF state, though not special diagram, be set up opening portion 63A but provide, and expose the operation of the some 72 of sweep trace 11, so the situation that the electrostatic prevention countermeasure is reached easily remarks additionally at this.
In the fifth embodiment of the present invention, only selectivity forms organic insulator on signal wire, and promoting the reduction of manufacturing process, but the thickness of organic insulator has more than the 1 μ m, therefore may have obstacle in the gap precision of guaranteeing liquid crystal cells.So, in the 6th embodiment, will provide the passivating technique that replaces organic insulator to append minimal process number.
The 6th embodiment
In the 6th embodiment, with shown in Figure 12 (c), form the zone as Figure 11 (c) up to electrode terminal at sweep trace 11, form opening portion 63A and expose till the some 72 of sweep trace 11, almost carry out with the 5th embodiment with identical technology.Then, form operation at source electrode, drain electrode wiring, use SPT equal vacuum film forming apparatus and cover in regular turn that rete such as heating resisting metal such as for example Ti, Ta etc. 34 about thickness 0.1 μ m is used as can anodised heat resistant metal layer, the aluminum film layer 35 about thickness 0.3 μ m be used as identical can anodised low resistance wiring layer.Then, pass through Micrometer-Nanometer Processing Technology, usability photosensitiveness resin pattern 87 is by source electrode, drain electrode wiring material that this double-layer films constituted, with second amorphous silicon layer 33 and first amorphous silicon layer 31, and expose gate insulator 30, shown in Figure 11 (d) and Figure 12 (d), the lamination that selectivity forms 34A and 35A on gate insulator 30 constitutes, and becomes the drain electrode 21 of insulated gate electrode transistor npn npn of pixel electrode and the signal wire 12 of double as source wiring.Forming source electrode, drain electrode wiring 12,21 o'clock, also forming the electrode terminal 5 and the electrode terminal that some constituted 6 of the sweep trace of the some 72 that comprises the sweep trace 11 that exposes in opening portion 63A simultaneously by signal wire.At this moment, the thickness (black region) of 87A on the electrode terminal 5,6 for example is 3 μ m, ratio is also wanted thick photoresist pattern 87A, 87B corresponding to the thickness 1.5 μ m of the regional 87B (middle tone zone) of source electrode, drain electrode wiring 12,21, form in advance by shadow tone (halftone) exposure technique, this is the key character of the 6th embodiment.
Forming source electrode, drain electrode wiring 12, after 21, by ashing means such as oxygen plasma above-mentioned photoresist pattern 87A, 87B are cut down thickness 1.5 μ m when above, photoresist pattern 87B disappears, expose source electrode, drain electrode wiring 12,21, the while is selectivity formation photoresist pattern 87A, 87B on electrode terminal 5,6 only.So, with photoresist pattern 83 simultaneously as Figure 11 (e) and anodic oxidation source electrode shown in Figure 12 (e), drain electrode wiring 12,21 and formation oxide layer 68,69 as the mask irradiates light, simultaneously, the second amorphous silicon layer 33A and the first amorphous silicon layer 31A at source electrode, drain electrode wiring 12,21 downsides exposed in anodic oxidation, and forms the silicon oxide layer (SiO of insulation course
2) 66,67.
After anodic oxidation finishes, when removing photoresist pattern 87C, with shown in Figure 12 (f), expose the electrode terminal 5,6 that is constituted by the low resistance thin film layer as Figure 11 (f).And if the undemanding words of the restriction of resistance value, the structure of source electrode, drain electrode wiring 12,21 also can be simplified to can anodised Ta individual layer.Thus, resulting active base plate 2 and colored filter are fitted and make liquid crystal panelization, finish the sixth embodiment of the present invention.Structure about storage capacitors 15, shown in Figure 11 (f), for example understand comparative electrode (capacitor storage beam) 16 and pixel electrode (drain electrode) 21 sandwich gate insulators 30 and the example of overlapping areas 50 (upper left oblique line part) formation storage capacitors 15 toward the lower right.In addition, at Figure 11 (f) and Figure 12 (f), the antistatic countermeasure that is connected with the high resistance parts between the electrode terminal 5 of sweep trace and the electrode terminal 6 of signal wire, not special diagram, so electrode terminal 6 of signal wire 12, with source electrode, drain electrode wiring 12,21 differences, only form the anodic oxide coating of insulation course in the side, side at the electrode terminal 5 of sweep trace 11, though do not form anodic oxide coating, but it is as discussed previously, the operation that is set up opening portion 63A and exposes the some 72 of sweep trace 11 is provided, so antistatic countermeasure easy to implement, when implementing antistatic countermeasure, in the side of the electrode terminal 5 of sweep trace 11, the concrete condition that also forms thin anodic oxide coating repeats no more.
In the 5th and the 6th embodiment, when forming drain electrode wiring, when carrying out novel passivation formation by being suitable for shadow tone (halftone) exposure technique, also carrying out operation cuts down, realize the making of liquid crystal indicator with four road mask plates, identical with first to fourth embodiment, by forming suitable shadow tone (halftone) exposure technique of operation in the formation operation of etching cut-off layer and the opening portion of gate insulator, and make liquid crystal indicator with three road mask plates, owing to can predict the further reduction of manufacturing process, so this is illustrated in the 7th and the 8th embodiment.
The 7th embodiment
In the 7th embodiment, at first on an interarea of glass substrate 2, use the first metal layer about SPT equal vacuum film forming apparatus covering thickness 0.1～0.3 μ m, with shown in Figure 14 (a), form the sweep trace 11 and comparative electrode 16 of double as gate electrode 11A as Figure 13 (a) by the Micrometer-Nanometer Processing Technology selectivity.
Secondly, on whole of glass substrate 2, use PCVD (PCVD) to install a SiN who covers in regular turn about 0.3 μ m-0.05 μ m--0.1 μ m as gate insulator
x(silicon nitride) layer 30 and impure hardly and as first amorphous silicon (a-Si) layer 31 of the passage of insulated gate electrode transistor npn npn, and as the 2nd SiN of the insulation course of protection passage
xThree kinds of thin layers such as layer 32 grade; in image displaying part zone exceptionally; form at the electrode terminal of sweep trace 11 and to have opening portion 63A on the zone; form the zone at the protection insulation course simultaneously; just the thickness of the regional 82A on the gate electrode 11A is 2 μ m; form photoresist pattern 82A, the 82B also thicker by shadow tone (halftone) exposure technique than the thickness 1 μ m of other regional 82B; with photoresist pattern 82A, 82B as mask; shown in Figure 13 (b) and Figure 14 (b), the 2nd SiN in the selective removal opening portion 63A
xLayer 32 and first amorphous silicon layer 31, and gate insulator 30, and expose the some 72 of sweep trace 11.
Secondly, by ashing means such as oxygen plasma, when making above-mentioned photoresist pattern 82A, 82B reduction thickness 1 μ m above, photoresist pattern 82B disappears, and with shown in Figure 14 (c), exposes the 2nd SiN as Figure 13 (c)
x Layer 32B can only form selectivity formation photoresist pattern 82C on the zone at the protection insulation course simultaneously.In above-mentioned oxygen plasma is handled, suppress the variation of pattern dimension, preferably strengthen anisotropy (anisotropy), this formerly narrates.Then, shown in Figure 13 (c) and Figure 14 (c), with photoresist pattern 82C as mask, and selective etch the 2nd SiN
xLayer 32 becomes two SiN thinner than gate electrode 11A width
xLayer 32A also exposes first amorphous silicon layer 31 simultaneously.At this moment, the some 72 of the sweep trace 11 that exposes is owing to be exposed to the 2nd SiN
xTherefore layer 32 etching gas or etching medicine must note the material difference along with sweep trace 11, contain the situation that the thickness of the some 72 of sweep trace 11 is cut down, but its countermeasure are as discussed previously.
Secondly, remove aforementioned photoresist pattern 82C, use the PCVD device at second amorphous silicon layer 33 that for example covers impure for example phosphorus on whole of glass substrate 2 with the thickness about 0.05 μ m, be used as heat resistant metal layer at the heating resisting metal thin layer 34 that uses SPT equal vacuum film forming apparatus to cover for example Ti, Cr about thickness 0.1 μ m, Mo etc. in regular turn on whole of glass substrate 2, and the aluminum film layer 35 about thickness 0.3 μ m is used as the low resistance wiring layer.Then, by Micrometer-Nanometer Processing Technology usability photosensitiveness resin pattern 86A, 86B etching in regular turn is by the formed source electrode of this double-layer films, the drain electrode wiring material and second amorphous silicon layer 33 and first amorphous silicon layer 31, and expose gate insulator 30, on gate insulator 30, selectivity forms the drain electrode 21 by the exhausted transistor npn npn of the grid that becomes pixel electrode that lamination constituted of 34A and 35A, signal wire 12 with the double as source wiring, forming source electrode, drain electrode wiring 12,21 o'clock, also comprise simultaneously and expose near the second amorphous silicon layer 33C the opening portion 63A and form by the electrode terminal 5 of sweep trace and the electrode terminal that some constituted 6 of signal wire 12.At this moment, be same as the 3rd embodiment, the thickness of 86A on the signal wire 12 for example is 3 μ m, by shadow tone (halftone) exposure technique form than and drain electrode 21 on electrode terminal 5,6 on also thick photoresist pattern 86A, the 86B of thickness 1.5 μ m of 86B.
Form after source electrode, the drain electrode wiring 12,21, by ashing means such as oxygen plasma, when making above-mentioned photoresist pattern 86A, 86B reduction thickness 1.5 μ m above, photoresist pattern 86B disappears, shown in Figure 13 (f) and Fig. 4 (f), when exposing drain electrode 21 and electrode terminal 5,6, can be only on signal wire 12 selectivity form photoresist pattern 86C.In above-mentioned oxygen plasma is handled, for the pattern width that does not make photoresist pattern 86C attenuates, preferably strengthen anisotropy (anisotropy), the situation that suppresses the pattern dimension variation is in narration before.If when the restriction of resistance value is not strict on the formation of source electrode, drain electrode wiring 12,21, also can be simplified to the Ta individual layer.
The active base plate 2 that so obtains and colored filter are fitted and make liquid crystal panelization, finish the seventh embodiment of the present invention.Photoresist pattern 86C, be not employing be the common photosensitive resin of principal ingredient with the clear resin of phenolic acid, but must adopt purity height, principal ingredient to contain the higher photonasty organic insulator of thermotolerance of polyacrylic resin or polyimide resin, this necessity is in narration before.Structure about storage capacitors 15, shown in Figure 13 (f), illustrate comparative electrode (capacitor storage beam) 16 and pixel electrode (drain electrode) 21 sandwich gate insulators 30 and the example of planarity overlapping areas 50 (upper left oblique line part) formation storage capacitors 15 toward the bottom right, drain electrode wiring 21 and leading portion sweep trace 11 sandwich gate insulators 30 and to constitute storage capacitors 15 also be feasible omit its detailed description at this.In addition, in Figure 13 (f), between the electrode terminal 6 of the electrode terminal 5 of sweep trace and signal wire with the high resistance parts, for example by insulated gate electrode transistor npn npn of (OFF) state or the antistatic countermeasure that elongated electric conductivity circuit connects, though not special diagram is provided with opening portion 63A because provide, and exposes the operation of the some 72 of sweep trace 11, therefore antistatic countermeasure is carried out easily, and this situation does not become.
In the seventh embodiment of the present invention, promote the reduction of manufacturing process by on signal wire, forming organic insulator, but the thickness of organic insulator is more than the 1 μ m, therefore for the gap precision of guaranteeing liquid crystal cells, obstacle to some extent.So, in the 8th embodiment, will provide the passivating technique that replaces organic insulator to append minimal process number.
The 8th embodiment
In the 8th embodiment,, form the zone up to electrode terminal and form opening portion 63A, and expose the some 72 of sweep trace 11 with shown in Figure 16 (d) as Figure 15 (d) at sweep trace 11, forming simultaneously till the etching cut-off layer 32A, all is to carry out with almost identical with the 7th embodiment technology.Secondly, removing aforementioned photoresist pattern 82C uses the PCVD device to cover for example second amorphous silicon layer 33 of phosphorus that contains of 0.05 μ m left and right sides thickness for example in regular turn on whole of glass substrate, using SPT equal vacuum film forming apparatus to cover that thin layer such as heating resisting metal such as for example Ti, Ta etc. 34 about thickness 0.1 μ m is used as can anodised heat resistant metal layer, and covering then that aluminum film layer 35 about thickness 0.3 μ m is used as equally can anodised low resistance wiring layer.Then, pass through Micrometer-Nanometer Processing Technology, usability photosensitiveness resin pattern 87A, 87B etching in regular turn is by source electrode that this double-layer films constituted, the drain electrode wiring material, with second amorphous silicon layer 33 and first amorphous silicon layer 31, expose gate insulator 30, shown in Figure 15 (e) and Figure 16 (e), on gate insulator 30, selectivity forms the drain electrode 21 by the insulated gate electrode transistor npn npn that becomes pixel electrode that lamination constituted of 34A and 35A, the also signal wire 12 of double as source wiring, be formed at source electrode, drain electrode wiring 12,21 o'clock, comprise near the second amorphous silicon layer 33C the opening portion 63A simultaneously and form the electrode terminal 5 of sweep trace and the electrode terminal that some constituted 6 by signal wire.At this moment, the thickness (black region) of 87A on the electrode terminal 5,6 for example is 3 μ m, form in advance than the thickness 1.5 μ m corresponding to the regional 87B (gray-scale areas) of source electrode, drain electrode wiring 12,21 by shadow tone (halftone) exposure technique and also to want thick photoresist pattern 87A, 87B, this is the key character of the 8th embodiment.
Form after source electrode, the drain electrode wiring 12,21, by ashing means such as oxygen plasma above-mentioned photoresist pattern 87A, 87B are cut down thickness 1.5 μ m when above, photoresist pattern 87B disappears, expose source electrode, drain electrode wiring 12,21, the while is selectivity formation photoresist pattern 87C on electrode terminal 5,6 only.At this, with photoresist pattern 87C as mask and irradiates light, simultaneously, shown in Figure 15 (f) and Figure 16 (f), anodic oxidation source electrode, drain electrode wiring 12,21 and form oxide layer 68,69; The second amorphous silicon layer 33A and the first amorphous silicon layer 31A at the downside of source electrode, drain electrode wiring 12,21 exposed in anodic oxidation simultaneously, and forms the silicon oxide layer (SiO of insulation course
2) 66,67.
Finish after the anodic oxidation, remove photoresist pattern 87C, shown in Figure 15 (g) and Figure 16 (g), expose the electrode terminal 5,6 that constitutes by low resistance thin film.When the restriction of resistance value was not strict, the structure of source electrode, drain electrode wiring 12,21 can be simplified to can anodised Ta individual layer.In addition, at Figure 15 (g) and Figure 16 (g), 6 of the electrode terminals of the electrode terminal 5 of sweep trace and signal wire, the antistatic countermeasure that connects with the high resistance parts does not illustrate especially, the electrode terminal 6 of signal wire 12, only in the side different with source electrode, drain electrode wiring 12,21, change the anodic oxide coating that forms insulation course, but need not illustrate between the electrode terminal that is used for antistatic countermeasure with suitable electroconductive component to connect, and be formed some anodic oxide coatings yet in the side of the electrode terminal 6 of sweep trace.So, resulting active base plate 2 and colored filter are fitted and make liquid crystal panelization, finish the eighth embodiment of the present invention.About the structure of storage capacitors 15, shown in Figure 15 (g), show comparative electrode (capacitor storage beam) 16 and pixel electrode (drain electrode) 21 sandwich gate insulators 30 and the example of overlapping areas (lower right oblique line part) formation storage capacitors 15.
The invention effect
As mentioned above; in liquid crystal indicator of the present invention; the insulated gate electrode transistor npn npn has the protection insulation course on passage; therefore only on the source electrode in image displaying part, the drain electrode wiring; or only on signal wire; selectivity forms the photonasty organic insulator, perhaps anodic oxidation by can anodised source electrode, source electrode that the drain electrode wiring material constituted, drain electrode wiring and form insulation course, deactivation function is provided.Therefore, be not accompanied by special heating process, and do not need excessive thermotolerance as the insulated gate electrode transistor npn npn of semiconductor layer with amorphous silicon layer.In other words, also have passivation and form the effect that can't produce the electric property deterioration.In addition, when anodic oxidation at source electrode, drain electrode wiring, can the selective protection sweep trace or the electrode terminal of signal wire by introducing shadow tone (halftone) exposure technique, can obtain the effect that stops the photo etching process number to increase.
In addition, by introducing shadow tone (halftone) exposure technique, can handle the formation operation of etching cut-off layer with one mask plate, form the operation reduction that operation is brought with the opening portion of gate insulator, by introducing the analog pixel electrode, with the rationalization of one mask plate processed pixels electrode and sweep trace etc., can make the photo etching process number by five times and then cut down in the past, can use four roads or three road mask plates to make liquid crystal indicators.This is the result who reduces the worker ordinal number of active base plate, and from the viewpoint of whole cost cutting, this is the worth maximum feature of mentioning especially.And the pattern accuracy requirement of these operations is not very high, and is therefore little to yield rate or quality influence, is easy to production management yet.
And, in the IPS type liquid crystal indicator of the 5th and the 7th embodiment made, the electric field that is produced between comparative electrode and pixel electrode, be applied only in gate insulator, in addition, IPS type liquid crystal indicator by the 6th and the 8th embodiment made, owing to be applied in the anodic oxide coating of gate insulator and pixel electrode, therefore can the traditional more second-rate passivation insulation of defective of sandwich, and have the advantage of burning ghost phenomena that is difficult for producing display image and can not ignore.Because drain electrode wiring (pixel electrode) the bright insulation course of anodic oxide coating therefore not equal to the function of its performance resistive formation does not produce Charge Storage.
In addition, main points of the present invention, can know from above-mentioned explanation and to learn, in the insulated gate electrode transistor npn npn of etching cut-off type, use can anodised source electrode, drain electrode wiring, and the anodic oxidation source electrode, drain electrode wiring surface and insulation stratification, about formation in addition, clearly, connect different pixel electrodes, the semiconductor device that is used for display device of the material of gate insulator etc. or thickness etc., the perhaps difference of its manufacture method, also belong in the field of the invention, even to reflection-type liquid-crystal display device, practicality of the present invention is also constant, in addition also clearly, the semiconductor layer of insulated gate electrode transistor npn npn is not limited to amorphous silicon.
Symbol description
1 liquid crystal panel
2 active base plates (glass substrate)
3 semiconductor integrated circuit chips
4 TCP films
5,6 electrode terminals
9 colored filters (relative glass substrate)
10 insulated gate electrode transistor npn npns
11 scan lines (gate electrode)
12 holding wires (source wiring, source electrode)
16 common electric capacity lines (in IPS type electrode, being comparative electrode)
17 liquid crystal
19 Polarizers
20 alignment films
21 drain electrodes (in IPS type electrode, being pixel electrode)
22 (transparent conductivity) pixel electrode
A 30 gate insulators (SiNxLayer)
31 (free from foreign meter), second amorphous silicon layer
32 the 2nd SiNxLayer
33 (impure), second amorphous silicon layer
34 (can be anodised) heat resistant metal layer
35 (can be anodised) low resistance metal layers (aluminium)
36 (can be anodised) intermediate conductive layer
37 passivation insulation
50,51,52 storage capacitors form the zone
62 (on the drain electrode) opening portion
63,63A (on the sweep trace) opening portion
64 (on the signal wire) opening portion
65,65A (on the comparative electrode) opening portion
66 impure silicon oxide layers
67 silicon oxide layers free from foreign meter
68 anodic oxide coatings (titanium dioxide, TiO
2)
69 anodic oxide coatings (aluminium oxide, Al
2O
3)
70 anodic oxide coatings (tantalum pentoxide, Ta
2O
5)
71 plasma protective seams
73 storage electrodes
The part of 72 sweep traces
83 (routine of confession formation pixel electrode) photoresist pattern
82,84,87 (forming) photoresist pattern with halftone exposure
85,86 (forming) photonasty organic insulator with halftone exposure
91 transparency conducting layers
92 the first metal layers
Claims (19)
1, a kind of bottom gate type insulated gate electrode transistor npn npn; it is characterized in that on passage, having the protection insulation course; to comprise on the source electrode that forms by the some in the electrical connection zone of the formed source wiring of conductive material that is different from source electrode, drain electrode wiring material, the drain electrode wiring, form the photonasty organic insulator.
2, a kind of bottom gate type insulated gate electrode transistor npn npn is characterized in that having the protection insulation course on passage, except the electrical connection zone of source wiring, only on source wiring, forms the photonasty organic insulator.
3, a kind of bottom gate type insulated gate electrode transistor npn npn is characterized in that having the protection insulation course on passage, with constituting source electrode, drain electrode wiring by anodised metal level; simultaneously; except that the electrical connection zone of source wiring, on source electrode, drain electrode wiring, form anodic oxide coating.
4, a kind of liquid crystal indicator, be on an interarea, to have at least: the sweep trace of insulated gate electrode transistor npn npn and the also transistorized gate electrode of double as aforementioned dielectric grid type, become the first transparent insulated substrate of two-dimensional-matrix-like by assortment with the signal wire of also double as source wiring and the unit picture element that is connected the pixel electrode etc. of drain electrode wiring, and between the second transparent insulated substrate or colored filter relative with the aforementioned first transparent insulated substrate, filling liquid crystal and the liquid crystal indicator that forms;
It is characterized in that: on an interarea of the first transparent insulated substrate, form at least by the sweep trace that metal level constituted more than one deck; First semiconductor layer free from foreign meter is formed island clipping the gate insulator more than one deck on the gate electrode; On first semiconductor layer on the gate electrode, form the protection insulation course thinner than aforementioned grid width; On the some and first semiconductor layer of aforementioned protective seam, form by the second impure semiconductor layer and the source electrode that lamination constituted, drain electrode wiring that can anodised metal level; On the some and gate insulator of aforementioned drain electrode wiring,, on signal wire, form the electrode terminal of transparent conductivity in the pixel electrode of transparent conductivity and the zone outside the pixel display part; Except that with the electrode terminal zone of the pixel electrode overlapping areas of aforementioned drain electrode wiring and signal wire, on the surface of source electrode, drain electrode wiring, form anodic oxide coating.
5, a kind of liquid crystal indicator, be on an interarea, to have at least: the sweep trace of insulated gate electrode transistor npn npn and the also transistorized gate electrode of double as aforementioned dielectric grid type, become the first transparent insulated substrate of two-dimensional-matrix-like by assortment with the signal wire and the unit picture element of pixel electrode that is connected drain electrode wiring etc. of also double as source wiring, and between the second transparent insulated substrate or colored filter relative with the aforementioned first transparent insulated substrate, filling liquid crystal and the liquid crystal indicator that forms;
It is characterized by, on an interarea of the first transparent insulated substrate, form at least by the sweep trace that lamination constituted and the pixel electrode of transparent conductivity and the identical signal line electrode terminal of transparency conducting layer with the first metal layer; On gate electrode, clip plasma protective seam and gate insulator island ground and form first semiconductor layer free from foreign meter; On first semiconductor layer on the gate electrode, form the protection insulation course thinner than aforementioned gate electrode width; Plasma protective seam on aforementioned pixel electrode and gate insulator form opening portion; On the some of aforementioned protection insulation course and on first semiconductor layer and on the some of the electrode terminal of signal wire, form the second impure semiconductor layer, the source electrode that lamination constituted (signal wire) wiring with second metal level more than one deck, with on the some of aforementioned protective seam with first semiconductor layer on and on the some of pixel electrode in the aforementioned opening portion, form drain electrode wiring equally; On aforementioned source electrode, drain electrode wiring, form the photonasty organic insulator.
6, a kind of liquid crystal indicator, be on an interarea, to have at least: the sweep trace of insulated gate electrode transistor npn npn and the also transistorized gate electrode of double as aforementioned dielectric grid type, become the first transparent insulated substrate of two-dimensional-matrix-like by assortment with the signal wire and the unit picture element of pixel electrode that is connected drain electrode wiring etc. of also double as source wiring, and between the second transparent insulated substrate or colored filter relative with the aforementioned first transparent insulated substrate, filling liquid crystal and the liquid crystal indicator that forms;
It is characterized by: on an interarea of the first transparent insulated substrate, form the pixel electrode that clips by formed sweep trace of the lamination of transparency conducting layer and the first metal layer and transparent conductivity at least; On gate electrode, clip plasma protective seam and gate insulator island ground and form first semiconductor layer free from foreign meter; On first semiconductor layer on the gate electrode, form the protection insulation course thinner than aforementioned gate electrode width; Plasma protective seam and gate insulator on aforementioned pixel electrode form opening portion; On the some of aforementioned protection insulation course and on first semiconductor layer, formation is by the source electrode that lamination constituted (signal wire) wiring of second impure semiconductor layer and second metal level more than one deck, with on the some of aforementioned protective seam with first semiconductor layer on and on the some of pixel electrode in the aforementioned opening portion, form drain electrode wiring equally; Except that the electrode terminal of signal wire with on signal wire, form the photonasty organic insulator.
7, a kind of liquid crystal indicator, be on an interarea, to have at least: the sweep trace of insulated gate electrode transistor npn npn and the also transistorized gate electrode of double as aforementioned dielectric grid type, become the first transparent insulated substrate of two-dimensional-matrix-like by assortment with the signal wire and the unit picture element of pixel electrode that is connected drain electrode wiring etc. of also double as source wiring, and between the second transparent insulated substrate or colored filter relative with the aforementioned first transparent insulated substrate, filling liquid crystal and the liquid crystal indicator that forms;
It is characterized by: on an interarea of the first transparent insulated substrate, form at least by the sweep trace that lamination constituted of transparency conducting layer and metal level and the pixel electrode of transparent conductivity; On gate electrode, clip plasma protective seam and gate insulator island and form first semiconductor layer free from foreign meter; On first semiconductor layer on the gate electrode, form the protection insulation course thinner than aforementioned grid width; Plasma protective seam on aforementioned pixel electrode and gate insulator form opening portion; On the some and first semiconductor layer of aforementioned protection insulation course, formation is by the second impure semiconductor layer, with the source electrode that lamination constituted (signal wire) wiring that can anodised metal level, with on the some of aforementioned protective seam and on first semiconductor layer and on the first transparent insulated substrate and on the some of the pixel electrode in the aforementioned opening portion, form drain electrode wiring equally; Except that the electrode terminal of signal wire,, form anodic oxide coating on source electrode, drain electrode wiring surface.
8, a kind of liquid crystal indicator, it is on an interarea, to have at least: the insulated gate electrode transistor npn npn, the also sweep trace of the transistorized gate electrode of double as aforementioned dielectric grid type, with the also signal wire of double as source wiring, with the pixel electrode that is connected aforementioned source grid type transistor drain, become the first transparent insulated substrate of two-dimensional-matrix-like by assortment with the unit picture element of comparative electrode that forms with aforementioned pixel electrode gap specific range etc., and between the second transparent insulated substrate or colored filter relative with the aforementioned first transparent insulated substrate, filling liquid crystal and the liquid crystal indicator that forms;
It is characterized by: on an interarea of the first transparent insulated substrate, form at least by formed sweep trace of the metal level more than one deck and comparative electrode; Form first semiconductor layer free from foreign meter on the gate insulator island ground that clips on the gate electrode more than one deck; On first semiconductor layer on the gate electrode, form the protection insulation course thinner than aforementioned gate electrode width; On the some of aforementioned protective seam and on first semiconductor layer, form the source electrode that lamination constituted (signal wire) wiring by second semiconductor layer that comprises impurity and second metal level more than one deck, and drain electrode wiring (pixel electrode); Except that the electrode terminal of signal wire, on signal wire, form the photonasty organic insulator; The electrode terminal of sweep trace, in image displaying part zone exceptionally, second metal level that forms by comprising the opening portion that is formed on the gate insulator on the sweep trace.
9, a kind of liquid crystal indicator, it is on an interarea, to have at least: the insulated gate electrode transistor npn npn, the also sweep trace of the transistorized gate electrode of double as aforementioned dielectric grid type, with the also signal wire of double as source wiring, with the pixel electrode that is connected aforementioned source grid type transistor drain, become the first transparent insulated substrate of two-dimensional-matrix-like by assortment with the unit picture element of comparative electrode that forms with aforementioned pixel electrode gap specific range etc., and between the second transparent insulated substrate or colored filter relative with the aforementioned first transparent insulated substrate, the liquid crystal indicator that filling liquid crystal forms; It is characterized by: at least
On an interarea of the first transparent insulated substrate, form by sweep trace that metal level constituted and comparative electrode more than one deck; Form first semiconductor layer free from foreign meter on the gate insulator island ground that clips on the gate electrode more than one deck; On first semiconductor layer on the gate electrode, form the protection insulation course thinner than aforementioned gate electrode width; On the some of aforementioned protective seam and on first semiconductor layer, form by second semiconductor layer that comprises impurity and the source electrode that lamination constituted (signal wire) wiring that can anodised metal level, and drain electrode wiring (pixel electrode); Except that the electrode terminal of signal wire, form anodic oxide coating on source electrode, drain electrode wiring surface; The electrode terminal of sweep trace in image displaying part zone exceptionally, is by comprising the opening portion that is formed on the gate insulator on the sweep trace and can being constituted by anodised metal level of forming.
10, a kind of liquid crystal indicator, it is on an interarea, to have at least: the insulated gate electrode transistor npn npn, the also sweep trace of the transistorized gate electrode of double as aforementioned dielectric grid type, with the also signal wire of double as source wiring, with the pixel electrode that is connected aforementioned source grid type transistor drain, become the first transparent insulated substrate of two-dimensional-matrix-like by assortment with unit picture element with formed comparative electrode of aforementioned pixel electrode gap specific range etc., and between the second transparent insulated substrate or colored filter relative with the aforementioned first transparent insulated substrate, the liquid crystal indicator that filling liquid crystal forms;
It is characterized by: on an interarea of the first transparent insulated substrate, form at least by sweep trace that metal level constituted and comparative electrode more than one deck; Form first semiconductor layer that does not comprise impurity on the gate insulator island ground that clips on the gate electrode more than one deck; On first semiconductor layer on the gate electrode, form the protection insulation course thinner than aforementioned gate electrode width; On the some of aforementioned protective seam and on first semiconductor layer, form the source electrode that lamination constituted (signal wire) wiring and drain electrode wiring (pixel electrode) by second semiconductor layer that comprises impurity and second metal level more than one deck; Except that the electrode terminal of signal wire, on signal wire, form the photonasty organic insulator; The electrode terminal of sweep trace is in image displaying part zone exceptionally, and second metal level that forms by comprising the opening portion that is formed on the gate insulator on the sweep trace constitutes with the lamination of second metal level.
11, a kind of liquid crystal indicator, it is on an interarea, to have at least: the insulated gate electrode transistor npn npn, the also sweep trace of the transistorized gate electrode of double as aforementioned dielectric grid type, with the also signal wire of double as source wiring, with the pixel electrode that is connected aforementioned source grid type transistor drain, become the first transparent insulated substrate of two-dimensional-matrix-like by assortment with unit picture element with formed comparative electrode of aforementioned pixel electrode gap specific range etc., and between the second transparent insulated substrate or colored filter relative with the aforementioned first transparent insulated substrate, filling liquid crystal and the liquid crystal indicator that forms;
It is characterized by: on an interarea of the first transparent insulated substrate, form at least by sweep trace that metal level constituted and comparative electrode more than one deck; Form first semiconductor layer free from foreign meter on the gate insulator island ground that clips on the gate electrode more than one deck; On first semiconductor layer on the gate electrode, form the protection insulation course thinner than aforementioned gate electrode width; On the some of aforementioned protective seam and on first semiconductor layer, form by second semiconductor layer that comprises impurity and the source electrode that lamination constituted (signal wire) wiring and drain electrode wiring (pixel electrode) that can anodised metal level; Except that the electrode terminal of signal wire,, form anodic oxide coating on source electrode, drain electrode wiring surface; The electrode terminal of sweep trace is the zone outside the pixel display part, and the opening portion that is formed on the gate insulator on the sweep trace forms second semiconductor layer and lamination that can anodised metal level constitutes by comprising.
12, a kind of manufacture method of liquid crystal indicator, be on an interarea, to have at least: the sweep trace of insulated gate electrode transistor npn npn and the also transistorized gate electrode of double as aforementioned dielectric grid type, become the first transparent insulated substrate of two-dimensional-matrix-like by assortment with the unit picture element of the signal wire of also double as source wiring and the pixel electrode that is connected aforementioned drain electrode wiring, and between the second transparent insulated substrate or colored filter relative with the aforementioned first transparent insulated substrate, the liquid crystal indicator that filling liquid crystal forms;
It is characterized by: on an interarea of the first transparent insulated substrate, form operation at least by the sweep trace that metal level constituted more than one deck; Cover the above gate insulator of one deck in regular turn and do not comprise the operation of first amorphous silicon layer and the protection insulation course of impurity; Electrode terminal at sweep trace forms on the zone, forms to have opening portion and protection insulation course on the gate electrode forms the operation that thick photoresist pattern is also wanted in other zones of Film Thickness Ratio in zone; Remove protection insulation course and first amorphous silicon layer and gate insulator in the aforementioned opening portion, and the electrode terminal that exposes sweep trace forms the operation in zone; Reduce the thickness of aforementioned photoresist pattern, and expose the operation of protecting insulation course; Residual width exposes the operation of first amorphous silicon layer than the also thin protection insulation course of gate electrode on gate electrode; Remove after the aforementioned photoresist pattern, cover the operation of the second impure amorphous silicon layer comprehensively; In the mode partly overlapping with aforementioned protective seam, form by second amorphous silicon layer and more than one deck can anodised metal level the source electrode that lamination constituted (signal wire), the operation of drain electrode wiring; On the some of gate insulator and aforementioned drain electrode wiring,, on signal wire, form the operation of the electrode terminal of transparent conductivity in the pixel electrode and the image displaying part zone exceptionally of transparent conductivity; The photoresist pattern that will be used for the selectivity pattern formation of aforementioned pixel electrode and electrode terminal, as mask, protection pixel electrode and electrode terminal, simultaneously, the operation of anodic oxidation source electrode, drain electrode wiring.
13, a kind of manufacture method of liquid crystal indicator, be on an interarea, to have at least: the sweep trace of insulated gate electrode transistor npn npn and the also transistorized gate electrode of double as aforementioned dielectric grid type, become the first transparent insulated substrate of two-dimensional-matrix-like by assortment with the signal wire and the unit picture element of pixel electrode that is connected aforementioned drain electrode wiring etc. of also double as source wiring, and between the second transparent insulated substrate or colored filter relative with the aforementioned first transparent insulated substrate, filling liquid crystal and the manufacture method of the liquid crystal indicator that forms; It is characterized by:
At least on an interarea of the first transparent insulated substrate, form the sweep trace that lamination constituted and the simulation electrode terminal of signal wire and the operation of analog pixel electrode by transparency conducting layer and the first metal layer; Order covers plasma protective seam and gate insulator and does not comprise the operation of first amorphous silicon layer with the protection insulation course of impurity; Electrode terminal at sweep trace and signal wire forms on the zone, on the analog pixel electrode, forms and to have opening portion and protection insulation course on the gate electrode forms the thickness in zone, than other zones, forms the operation of the photoresist pattern of also wanting thick; Remove protection insulation course and first amorphous silicon layer and gate insulator and plasma protective seam and the first metal layer in the aforementioned opening portion, and form the operation of the regional identical pixel electrode that exposes with the electrode terminal of the sweep trace of transparent conductivity and signal wire; Reduce the thickness of aforementioned photoresist pattern, and expose the operation of protecting insulation course; On gate electrode, the residual operation of exposing first amorphous silicon layer than the thinner protection insulation course of gate electrode width; Remove after the aforementioned photoresist pattern, cover the operation of the second impure amorphous silicon layer comprehensively; Cover after the second above metal level of one deck; the electrode terminal that formation comprises signal wire by the lamination formation of second amorphous silicon layer and second metal level more than one deck and aforementioned protection insulation course with overlapping forms the zone and has the identical pixel electrode of source wiring (signal wire) of photonasty organic insulator on its surface, and forms the operation of drain electrode wiring.
14, a kind of manufacture method of liquid crystal indicator, be on an interarea, to have at least: the sweep trace of insulated gate electrode transistor npn npn and the also transistorized gate electrode of double as aforementioned dielectric grid type, become the first transparent insulated substrate of two-dimensional-matrix-like by assortment with the signal wire and the unit picture element of pixel electrode that is connected aforementioned drain electrode wiring etc. of also double as source wiring, and between the second transparent insulated substrate or colored filter relative with the aforementioned first transparent insulated substrate, the manufacture method of the liquid crystal indicator that filling liquid crystal forms;
It is characterized by: on an interarea of the first transparent insulated substrate, form operation at least by the sweep trace that lamination constituted and the analog pixel electrode of transparency conducting layer and the first metal layer; The operation of first amorphous silicon layer that covers plasma protective seam and gate insulator in regular turn and do not comprise impurity and protection insulation course; Electrode terminal at sweep trace forms on the zone, on the analog pixel electrode, forms and to have opening portion and protection insulation course on the electrode forms the operation that thick photoresist pattern is also wanted in other zones of Film Thickness Ratio in zone;
Remove protection insulation course and first amorphous silicon layer and gate insulator and plasma protective seam and the first metal layer in the aforementioned opening portion, and form the regional identical operation of exposing pixel electrode with the electrode terminal of the sweep trace of transparent conductivity; Reduce the thickness of aforementioned photoresist pattern, and expose the operation of protecting insulation course; On gate electrode, the residual operation of exposing first amorphous silicon layer than the thinner protection insulation course of the width of gate electrode; Remove after the aforementioned photoresist pattern, cover the operation of the second impure amorphous silicon layer comprehensively; Cover after the second above metal level of one deck, correspond respectively to the source wiring (signal wire) partly overlapping with aforementioned protection insulation course, reach drain electrode wiring with the partly overlapping pixel electrode of aforementioned protection insulation course, and the electrode terminal that comprises the sweep trace of transparent conductivity forms the electrode terminal of the sweep trace in zone, and by the electrode terminal of the signal wire that some constituted of signal wire, and form the operation of the thicker photonasty organic insulation layer pattern in other zones of Film Thickness Ratio of four kinds of signal wires; With aforementioned photonasty organic insulation layer pattern as mask, and selective removal second metal level and second amorphous silicon layer and first amorphous silicon layer, and form the operation of the electrode terminal of sweep trace and signal wire and source electrode, drain electrode wiring; Reduce the thickness of aforementioned photonasty organic insulation layer pattern, and expose the operation of the electrode terminal and the drain electrode wiring of sweep trace and signal wire.
15, a kind of manufacture method of liquid crystal indicator, be on an interarea, to have at least: the insulated gate electrode transistor npn npn and also the transistorized gate electrode of double as aforementioned dielectric grid type sweep trace, with the also signal wire of double as source wiring, become the first transparent insulated substrate of two-dimensional-matrix-like by assortment with the unit picture element of pixel electrode that is connected aforementioned drain electrode wiring etc., and between the second transparent insulated substrate or colored filter relative with the aforementioned first transparent insulated substrate, filling liquid crystal and the liquid crystal indicator that forms;
It is characterized by: on an interarea of the first transparent insulated substrate, form operation at least by the sweep trace that lamination constituted and the analog pixel electrode of transparency conducting layer and metal level; Order covers plasma protective seam and gate insulator and first amorphous silicon layer and the operation of protecting insulation course free from foreign meter; The electrode terminal of sweep trace form on the zone with the analog pixel electrode on, form and have opening portion and protect insulation course to form the operation of the thicker photoresist pattern in other zones of Film Thickness Ratio in zone; Remove protection insulation course and first amorphous silicon layer and gate insulator and plasma protective seam and metal level in the aforementioned opening portion, and expose the operation that forms regional identical pixel electrode with the electrode terminal of the sweep trace of transparent conductivity; Reduce the thickness of aforementioned photoresist pattern, and expose the operation of protecting insulation course; On gate electrode, the residual operation of exposing first amorphous silicon layer than the thinner protection insulation course of gate electrode width; Remove after the aforementioned photoresist pattern, cover the operation of second amorphous silicon layer that comprises impurity; Cover one deck above can anodised metal level after, correspond respectively to the source wiring (signal wire) partly overlapping with aforementioned protection insulation course, and the identical drain electrode wiring that contains pixel electrode, and the electrode terminal that comprises the sweep trace of transparent conductivity forms the electrode terminal of the sweep trace in zone, and by the electrode terminal of the signal wire that some constituted of signal wire, and form the operation of the thicker photoresist pattern in other zones of Film Thickness Ratio of electrode terminal of sweep trace and signal wire respectively; As mask, and selective removal can anodised metal level and second amorphous silicon layer and first amorphous silicon layer with aforementioned photoresist pattern, and form the operation of the electrode terminal of sweep trace and signal wire and source electrode, drain electrode wiring; Reduce the thickness of aforementioned photoresist pattern, and expose the operation and the protection former electrodes terminal of source electrode, drain electrode wiring, and the operation of anodic oxidation source electrode, drain electrode wiring.
16, a kind of manufacture method of liquid crystal indicator, it is on an interarea, to have at least: the insulated gate electrode transistor npn npn, the also sweep trace of the transistorized gate electrode of double as aforementioned dielectric grid type, with the also signal wire of double as source wiring, with the pixel electrode that is connected aforementioned dielectric grid type transistor drain, become the first transparent insulated substrate of two-dimensional-matrix-like by assortment with the unit picture element of comparative electrode that is constituted with aforementioned pixel electrode gap specific range etc., and between the second transparent insulated substrate or colored filter relative with the aforementioned first transparent insulated substrate, filling liquid crystal and the manufacture method of the liquid crystal indicator that forms;
It is characterized by: on an interarea of the first transparent insulated substrate, form at least by the sweep trace that the first metal layer constituted more than one deck and the operation of comparative electrode; Order covers above gate insulator of one deck and first amorphous silicon layer and the operation of protecting insulation course free from foreign meter; On gate electrode, the residual operation of exposing first amorphous silicon layer than the thinner protection insulation course of gate electrode width; Cover comprehensively and comprise after second amorphous silicon layer of impurity, electrode terminal at sweep trace forms on the zone, form opening portion and remove second amorphous silicon layer and first amorphous silicon layer and gate insulator in the aforementioned opening portion, and expose the operation of the some of sweep trace; Cover after the second above metal level of one deck, correspond respectively to source wiring (signal wire), the drain electrode wiring (pixel electrode) partly overlapping with aforementioned protection insulation course, and comprise the electrode terminal of the sweep trace of aforementioned opening portion, and by the electrode terminal of the signal wire that some constituted of signal wire, and form the operation of the thicker photonasty organic insulation layer pattern in other zones of Film Thickness Ratio on the signal wire respectively; With aforementioned photonasty organic insulation layer pattern as mask, and selective removal second metal level and second amorphous silicon layer and first amorphous silicon layer, and form the operation of the electrode terminal of sweep trace and signal wire and source electrode, drain electrode wiring; Reduce the thickness of aforementioned photonasty organic insulation layer pattern, and expose the operation of the electrode terminal and the drain electrode wiring of sweep trace and signal wire.
17, a kind of manufacture method of liquid crystal indicator, it is on an interarea, to have at least: the insulated gate electrode transistor npn npn, the also sweep trace of the transistorized gate electrode of double as aforementioned dielectric grid type, with the also signal wire of double as source wiring, with the pixel electrode that is connected aforementioned dielectric grid type transistor drain, become the first transparent insulated substrate of two-dimensional-matrix-like by assortment with the unit picture element of comparative electrode that is constituted with aforementioned pixel electrode gap specific range etc., and between the second transparent insulated substrate or colored filter relative with the aforementioned first transparent insulated substrate, filling liquid crystal and the manufacture method of the liquid crystal indicator that forms;
It is characterized by: on an interarea of the first transparent insulated substrate, form at least by the sweep trace that the first metal layer constituted more than one deck and the operation of comparative electrode; Cover above gate insulator of one deck and first amorphous silicon layer and the operation of protecting insulation course free from foreign meter in regular turn; On gate electrode, the residual operation of exposing first amorphous silicon layer than the thinner protection insulation course of gate electrode width; Cover comprehensively and comprise after second amorphous silicon layer of impurity, form at the electrode terminal of sweep trace and to form opening portion on the zone and remove second amorphous silicon layer and first amorphous silicon layer and gate insulator in the aforementioned opening portion, and expose the operation of sweep trace some; Cover more than one deck can anodised metal level after, correspond respectively to source wiring (signal wire), the drain electrode wiring (pixel electrode) a part of overlapping with aforementioned protection insulation course, electrode terminal with the sweep trace that contains aforementioned opening portion, electrode terminal with a part of formed signal wire of signal wire, and form thickness on the electrode terminal of sweep trace and signal wire respectively, the operation of the photoresist pattern thicker than other zones; As mask, and selective removal can anodised metal level and second amorphous silicon layer and first amorphous silicon layer with aforementioned photoresist pattern, and form the operation of the electrode terminal of sweep trace and signal wire and source electrode, drain electrode wiring; Reduce the thickness of aforementioned photoresist pattern, and expose the operation of source electrode, drain electrode wiring; The operation of the source electrode of anodic oxidation simultaneously, drain electrode wiring on the protection former electrodes terminal.
18, a kind of manufacture method of liquid crystal indicator, it is on an interarea, to have at least: the insulated gate electrode transistor npn npn, the also sweep trace of the transistorized gate electrode of double as aforementioned dielectric grid type, with the also signal wire of double as source wiring, with the pixel electrode that is connected aforementioned dielectric grid type transistor drain, become the first transparent insulated substrate of two-dimensional-matrix-like by assortment with the unit picture element of comparative electrode that is constituted with aforementioned pixel electrode gap specific range etc., and between the second transparent insulated substrate or colored filter relative with the aforementioned first transparent insulated substrate, the manufacture method of the liquid crystal indicator that filling liquid crystal forms;
It is characterized by: on an interarea of the first transparent insulated substrate, form at least by the sweep trace that the first metal layer constituted more than one deck and the operation of comparative electrode; Cover above gate insulator of one deck and first amorphous silicon layer and the operation of protecting insulation course free from foreign meter in regular turn; Electrode terminal at sweep trace forms on the zone, form to have opening portion, and the protection insulation course on the gate electrode forms the thickness in zone the operation of the photoresist pattern thicker than other zones; Remove protection insulation course and first amorphous silicon layer and gate insulator in the aforementioned opening portion, and expose the operation of sweep trace some; Reduce the thickness of aforementioned photoresist pattern, and expose the operation of protecting insulation course; On gate electrode, the residual operation of exposing first amorphous silicon layer than the thinner protection insulation course of gate electrode width; Remove after the aforementioned photoresist pattern, cover the operation of second amorphous silicon layer that comprises impurity comprehensively; Cover after the second above metal level of one deck, correspond respectively to source wiring (signal wire), the drain electrode wiring (pixel electrode) partly overlapping with aforementioned protection insulation course, and comprise the electrode terminal of the sweep trace of second amorphous silicon layer in the opening portion, and, form the operation of the thicker photonasty organic insulation layer pattern in other zones of Film Thickness Ratio on the signal wire respectively by the electrode terminal of the signal wire that some constituted of signal wire; With aforementioned photonasty organic insulation layer pattern as mask, and selective removal second metal level and second amorphous silicon layer and first amorphous silicon layer, and form the operation of the electrode terminal of sweep trace and signal wire and source electrode, drain electrode wiring; Reduce the thickness of aforementioned photonasty organic insulation layer pattern, and expose the operation of the electrode terminal and the drain electrode wiring of sweep trace and signal wire.
19, a kind of manufacture method of liquid crystal indicator, it is on an interarea, to have at least: the insulated gate electrode transistor npn npn, the also sweep trace of the transistorized gate electrode of double as aforementioned dielectric grid type, with the also signal wire of double as source wiring, with the pixel electrode that is connected aforementioned dielectric grid type transistor drain, become the first transparent insulated substrate of two-dimensional-matrix-like by assortment with the unit picture element of comparative electrode that is constituted with aforementioned pixel electrode gap specific range etc., and between the second transparent insulated substrate or colored filter relative with the aforementioned first transparent insulated substrate, the manufacture method of the liquid crystal indicator that filling liquid crystal forms;
It is characterized by: on an interarea of the first transparent insulated substrate, form at least by the sweep trace that the first metal layer constituted more than one deck and the operation of comparative electrode; Cover above gate insulator of one deck and first amorphous silicon layer and the operation of protecting insulation course free from foreign meter in regular turn; Electrode terminal at sweep trace forms on the zone, forms to have opening portion, and the protection insulation course on the gate electrode forms the operation of the thicker photoresist pattern in regional other zones of Film Thickness Ratio; Remove protection insulation course and first amorphous silicon layer and gate insulator in the aforementioned opening portion, and expose the operation of sweep trace some; Reduce the thickness of aforementioned photoresist pattern, and expose the operation of protecting insulation course; On gate electrode, the residual operation of exposing first amorphous silicon layer than the thinner protection insulation course of the width of gate electrode; Remove after the aforementioned photoresist pattern, cover the operation of the second impure amorphous silicon layer comprehensively; Cover one deck above can anodised metal level after, correspond respectively to source wiring (signal wire), the drain electrode wiring (pixel electrode) partly overlapping with aforementioned protection insulation course, and comprise the electrode terminal of the sweep trace of second amorphous silicon layer in the opening portion, and by the electrode terminal of the signal wire that some constituted of signal wire, and form the operation of the thicker photoresist pattern in other zones of Film Thickness Ratio on the electrode terminal of sweep trace and signal wire respectively; Can anodised metal level and second amorphous silicon layer and first amorphous silicon layer with aforementioned photoresist pattern as the mask selective removal, and form the operation of the electrode terminal of sweep trace and signal wire and source electrode, drain electrode wiring; Reduce the thickness of aforementioned photoresist pattern, and expose the operation of source electrode, drain electrode wiring; The operation of protection former electrodes terminal anodic oxidation simultaneously source electrode, drain electrode wiring.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105717738A (en) * | 2014-12-17 | 2016-06-29 | Hoya株式会社 | Method of producing photomask and method of producing display apparatus |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105717738A (en) * | 2014-12-17 | 2016-06-29 | Hoya株式会社 | Method of producing photomask and method of producing display apparatus |
| CN105717738B (en) * | 2014-12-17 | 2019-08-06 | Hoya株式会社 | The manufacturing method of photomask and the manufacturing method of display device |
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