CN1779716A - Realization of rapid coding-decoding circuit with run-length - Google Patents
Realization of rapid coding-decoding circuit with run-length Download PDFInfo
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- CN1779716A CN1779716A CN 200510026218 CN200510026218A CN1779716A CN 1779716 A CN1779716 A CN 1779716A CN 200510026218 CN200510026218 CN 200510026218 CN 200510026218 A CN200510026218 A CN 200510026218A CN 1779716 A CN1779716 A CN 1779716A
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Abstract
A method for realizing quick run length coding/decoding circuit includes marking nonzero coefficient while quantizing when run length is coded and finalizing real time RLC coding when Hoffman coding is carried on in system, obtaining RLC coding while finalizing counter-scanning when run length is decoded and finalizing recovery of quantization coefficient when counter-quantizing is carried on.
Description
Affiliated technical field
The present invention adopts a kind of hardware structure of novelty, utilizes less hardware resource, has realized quick run length encoding and decoding (Run length code/Run length decode) hardware circuit design.This invention can directly apply to the design of digital figure compression of images decompression hardware accelerator (as JPEG hardware-compressed decompress(ion), dynamic video image Compress softwares) chip, it has reduced the realization scale of run length encoding and decoding (RLC/RLD) circuit effectively, improve the hardware process speed of run length encoding and decoding simultaneously, improved the performance of system on the whole.
Background technology
At present, more common run length coding, RLC (RLC) hardware and circuit realizing is:
(1) quantization parameter that at first will handle quantizer (Quantizer) output of (Block processing) based on piece stores in the quantization parameter working storage (quantized coefficients memory), the size of each piece is 8 * 8 (as the JPEG codings) normally, also can be 4 * 4 or 16 * 16;
(2) after current block quantizes to finish, according to scanning sequency (level, vertical or zigzag scanning), scanning quantization parameter working storage, and calculate the run length of 0 value, obtain the Run-Length Coding (Run length code) of current block, and be stored in the corresponding RLC working storage.
(3) run length coding, RLC in the RLC working storage (RLC coding) is delivered to the next stage processing unit, i.e. hardware or software Huffman (Huffman) coding.
The implementation method of general run length decoding (RLD) is:
(1) distance of swimming sign indicating number that Hofmann decoding is obtained writes in the RLC working storage.
(2) counter-scanning must recover each quantization parameter, and it is written to the relevant position of quantization parameter working storage.
(3) quantization parameter that runs decoding (RLD) is obtained is delivered to the next stage processing unit, i.e. inverse DCT (Dequantizer).
Without any problem, but that circuit is realized scale to general run length codec hardware circuit is relatively large on circuit function, the scanning of each coefficient all takies a clock period separately, on overall performance, has increased the flowing water that a piece handles and has postponed.
Summary of the invention
The present invention adopts a kind of hardware structure of novelty, utilize less hardware resource (to need not run length coding, RLC and export working storage: the RLC working storage), the clock period that block scan takies when having removed the realization of general run length encoding and decoding (RLC/RLD) hardware, when realizing, particular hardware accomplished to realize quickly and efficiently the run length encoding and decoding.
The technical solution adopted for the present invention to solve the technical problems is as follows:
Overall design philosophy is: in when coding run length coding, RLC (RLC) is split and quantize and two stages of huffman coding finish: finish the mark of nonzero coefficient when quantizing to export, finish scanning (Scanning) and run length coding, RLC (RLC) in real time when huffman coding.In when decoding, run length decoding (RLD) is split Hofmann decoding and two stages of inverse quantization finish, promptly when Hofmann decoding, finish counter-scanning (Inverse Scanning), when inverse quantization, finish the recovery of quantization parameter in real time.
Concrete scheme of the present invention is:
(1) realization of run length coding, RLC (RLC)
Adopt implementation method of the present invention, need establish a marker bit register for each quantization parameter, the default value of marker bit is 0, for one 8 * 8 piece, needs 64 marker bit registers.When quantizing output, if current coefficient is non-0 value, then the respective markers position is made as 1, otherwise still remains 0.After quantification is finished, what next need to finish is real-time RLC coding, its specific implementation principle is, the non-zero marker bit is rearranged by scanning sequency, promptly finished current nonzero coefficient scanning, this process is the outer clock period of occupying volume not, rearranging of marker bit, also only need combinational circuit (if design support level seldom, vertically, three kinds of scan modes of zigzag, then the row again of each coefficient at most only need one three and select one selection, if the zigzag scan mode is only supported in design, then need not any hardware resource, just change that puts in order).Nonzero coefficient with correspondence takes out in advance simultaneously, calculates current coefficient 0 run length (according to the number of lasting 0 between two adjacent non-zero quantized coefficients of scanning sequency) before, finishes the RLC coding, stores in the RLC output register.Read RLC when coding when current block being carried out huffman coding; a RLC coding to finishing is in advance immediately sent; and the RLC that finishes next nonzero coefficient simultaneously encodes; be updated to the RLC output register; can guarantee that like this huffman coding is when reading the RLC coding; without any latent period, removed when last RLC coding of current block, the run length coding, RLC of current block also finishes.
(2) realization of run length decoding (RLD)
The principle of run length decoding (RLD) is: in the Hofmann decoding stage, when decoding circuit receives the RLC coding, in the same clock period that receives each RLC coding, obtain the position (corresponding address in quantized coefficients memory) of current quantization parameter in current processing block according to the run length information in the current RLC coding, and the nonzero coefficient that will obtain from current RLC coding is written in the corresponding address, simultaneously the coefficient marker bit register of correspondence put 1.When last RLC coding of current processing block was received, the counter-scanning of current block also finished simultaneously.Next start the inverse quantization operation of current block, during for 8 * 8 piece inverse quantization, need read from 0 to 63 quantization parameter successively, non-zero marker bit state according to correspondence, if the current quantization parameter that reads is zero, then directly the current coefficient of delivering to inverse DCT is changed to 0 by force, if the current quantization parameter that reads is a nonzero value, then from the quantization parameter working storage, read the corresponding quantization coefficient, and deliver to inverse DCT.When last quantization parameter is sent, the decoding of the run length of current block is also promptly finished.
The invention has the beneficial effects as follows: (1) realizes the run length encoding and decoding with less hardware resource; (2) need not the extra special clock cycle finishes run length encoding and decoding (RLC/RLD), has reduced the pipelining delay of system; (3) when realizing run length encoding and decoding (RLC/RLD), an access non-zero quantized coefficients has reduced and has visited the power consumption that quantizes the number working storage.
Description of drawings
Fig. 1: the set process flow diagram of 64 non-zero marker bit register vectors during 8 * 8 processing (Block Processing).QC[i] refer to current quantization parameter, NZF[i] be its corresponding non-zero flag register.
Fig. 2: the real-time RLC coding of run length coding, RLC process flow diagram during 8 * 8 processing (Block Processing).Rrlc is a RLC coding output register, Aprenz is meant the scanning coordinate value of previous nonzero coefficient, Acurnz refers to the scanning coordinate value of current nonzero coefficient, NZF[63:0] refer to the original non-zero flag register vector of current block, NZFs[63:0] refer to the non-zero label vector behind the scanning sequency transposition, R refers to 0 value run length of the current nonzero coefficient that calculates in real time, RLC[Acurnz] refer to the RLC coding of current nonzero coefficient.
Counter-scanning process flow diagram during Fig. 3: RLD decoding.Aprenz is meant the counter-scanning coordinate figure of previous nonzero coefficient, Acurnz refers to the counter-scanning coordinate figure of current nonzero coefficient, NZF[63:0] refer to the original non-zero flag register vector of current block, QCrlc is meant the current zero coefficient values that current RLD decoding obtains, QCmem[Acurnz] refer to current nonzero coefficient correspondence the quantization parameter working storage storage unit
Quantization parameter real-time recovery process flow diagram during Fig. 4: RLD decoding.NZF[i] refer to the original non-zero flag register vector of current block, QC[i] refer to deliver to the quantization parameter of inverse DCT, QCmem[i] refer to i storage unit in the quantization parameter working storage.
Embodiment
The set process flow diagram of 64 non-zero marker bit register vectors when Fig. 1 is 8 * 8 processing (Block Processing).Before current block quantizes beginning, NZF[63:0] initial value is 0.After quantizing beginning, in case hardware circuit detects current quantization parameter QC[i] non-vanishing, then with corresponding non-zero flag register position 1, as last quantization parameter NZF[63 of quantizer output current block] simultaneously, the non-zero flag of current block is finished.
The real-time RLC coding of run length coding, RLC process flow diagram when Fig. 2 is 8 * 8 processing (Block Processing).Side circuit work time-division two clock period are finished the RLC coding of a nonzero coefficient.First cycle is the code period of looking ahead, second period is a RLC coding readout interval, but also be the code period of looking ahead of next nonzero coefficient simultaneously, thereby the stream line operation that coding and the RLC coding of having realized looking ahead is read, the minimum RLC encoded clock periodicity of one 8 * 8 piece adds the RLC of the current block number of encoding for first prefetch cycle.Look ahead the coding principle of work as follows:
At first, with the vectorial NZF[63:0 of the non-zero flag register of current block] the non-zero zero flag vector NZFs[63:0 of transposition for arranging by scanning sequency].If scanning put in order into b0, b1, b2 ... b62, b63}, then
The transposition process has been finished the scanning to current nonzero coefficient.
Then, NZFs is carried out the right of priority coding, obtain the scanning coordinate value Acurnz of current nonzero coefficient.NZFs[0] right of priority is the highest, NZFs[63] right of priority is minimum.NZFs[0] be 1 o'clock, Acurnz=0 is when having only NZFs[63] and when being 1, Acurnz=63.Acurnz is sent to the Aprenz register at next clock.The scanning coordinate Aprenz that the scanning coordinate value Acurnz of current nonzero coefficient deducts a nonzero coefficient has promptly obtained the run length R of current nonzero coefficient, the RLC coding RLC[Acurnz that the value of it and current coefficient is encoded and obtains current coefficient] and be latching to RLC output register Rrlc, be sent at the RLC readout interval.When current nonzero coefficient after prefetch cycle is finished coding, its corresponding non-zero flag register by clear 0, discharges priority encoding power at readout interval, has begun the coding of looking ahead of next nonzero coefficient.When the RLC of last nonzero coefficient coding is read out the RLC end-of-encode of current block.
Counter-scanning process flow diagram when Fig. 3 is the RLD decoding.When the RLD decoding circuit receives the RLC coding that Hofmann decoding obtains, run length information from the RLC sign indicating number solves the counter-scanning coordinate figure of current nonzero coefficient immediately, corresponding non-zero flag register is put 1, and the coefficient that will solve from the RLC sign indicating number is written in the quantization parameter working storage simultaneously.When last RLC sign indicating number of current block is received, the RLD decoding counter-scanning of current block also promptly finishes.
Quantization parameter real-time recovery process flow diagram when Fig. 4 is the RLD decoding.When the RLD decoding circuit realizes that the real-time quantization coefficient recovers, judge at first whether the read signal that inverse DCT sends is effective, when effective, if the non-zero of current coefficient is labeled as 1, then from the quantization parameter working storage, read this nonzero coefficient and deliver to inverse DCT, if the non-zero of current coefficient is labeled as 0, then do not read the quantization parameter working storage, and the quantization parameter that directly will deliver to inverse DCT is forced to 0.Simultaneously, add 1 in the address of the quantization parameter working storage counting, wait for that inverse DCT reads next quantization parameter value, when last quantization parameter is read out, the inverse quantization of current block also finishes.
Claims (4)
1. the implementation method of rapid coding-decoding circuit with run-length in the digital figure compression of images decompression hardware accelerator.Have circuit and realize small scale, the characteristics that distance of swimming encoding and decoding speed is fast and low in energy consumption.
2. according to claim 1, when utilizing the method to realize the run length encoding and decoding, only be required to be each coefficient and set up the non-zero flag register position of a 1bit, need not the RLC working storage (the RLC working storage is used for storing whole RLC coding, the RLC coding of each quantization parameter takies the storage unit of bit bit wide more than, each RLC coding bit wide is 19bit during as the MPEG4 Compress softwares), circuit is realized small scale.
3. according to claim 1, when utilizing the method to realize the run length encoding and decoding, when run length coding, RLC (RLC), when quantizing, finish the mark of nonzero coefficient, real time scan is finished the RLC coding when doing huffman coding in system.When run length decoding (RLD), it has finished counter-scanning when obtaining the RLC coding, finish the recovery of quantization parameter when inverse quantization in real time.The run length encoding and decoding of each piece are the outer processing clock cycle of occupying volume not, thereby has reached purpose fast.The gordian technique of wherein encoding have following some: (1) when quantizing output with the mark position 1 of nonzero coefficient; Prefetch mechanisms when (2) RLC encodes; (3) the direct scanning of the marker bit register being finished current nonzero coefficient by the scanning sequency transposition, utilize the right of priority coding of current block non-zero flag register, calculate the run length of current nonzero value in real time, directly from the quantization parameter working storage, read this coefficient, obtain the RLC coding.The gordian technique of wherein decoding has following 2 points: (1) is when obtaining the RLC coding, immediately according to flow process length information in the RLC sign indicating number, solve the position of current coefficient in scanning sequence, it is made counter-scanning, can obtain the address of current nonzero coefficient in the quantization parameter working storage immediately, with corresponding non-zero mark position 1, the quantization parameter that obtains of will decoding from the RLC sign indicating number simultaneously writes this address; (2) when inverse quantization is done in decoding, real-time recovery goes out to quantize matrix of coefficients: according to the non-zero flag of current block coefficient, only read zero coefficient values from the quantization parameter storer, for 0 value quantization parameter, need not read the quantization parameter working storage, and directly 0 value be delivered to inverse DCT.
4. according to claim 1,2,3 described, when utilizing the method to realize the run length encoding and decoding, circuit scale is little, need only read/write zero coefficient values when scanning/counter-scanning, has reduced the storage number of times of quantization parameter working storage.These advantages have all reduced the power consumption when side circuit is realized.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100442853C (en) * | 2006-06-01 | 2008-12-10 | 上海交通大学 | Runs decoding, anti-scanning, anti-quantization and anti-inverting method and apparatus |
| CN101478311B (en) * | 2009-01-22 | 2010-10-20 | 浙江大学 | Hardware accelerated implementation process for bzip2 compression algorithm |
| CN102065288A (en) * | 2010-06-30 | 2011-05-18 | 美商威睿电通公司 | Video processing system and method realized by combining software with hardware and device thereof |
| CN102891927A (en) * | 2011-07-17 | 2013-01-23 | 白壮 | Mobile phone near field communication method based on audio air transmission |
| RU2609096C2 (en) * | 2011-04-27 | 2017-01-30 | Шарп Кабусики Кайся | Images decoding device, images encoding device and data structure of encoded data |
| CN107844829A (en) * | 2017-10-31 | 2018-03-27 | 中国科学院计算技术研究所 | Method and system and neural network processor for accelerans network processing unit |
| CN110313178A (en) * | 2018-04-04 | 2019-10-08 | 深圳市大疆创新科技有限公司 | Code device and system |
| CN112449201A (en) * | 2019-08-30 | 2021-03-05 | 腾讯科技（深圳）有限公司 | Decoding method, encoding method, corresponding devices, electronic equipment and storage medium |
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2005
- 2005-05-26 CN CN 200510026218 patent/CN1779716A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100442853C (en) * | 2006-06-01 | 2008-12-10 | 上海交通大学 | Runs decoding, anti-scanning, anti-quantization and anti-inverting method and apparatus |
| CN101478311B (en) * | 2009-01-22 | 2010-10-20 | 浙江大学 | Hardware accelerated implementation process for bzip2 compression algorithm |
| CN102065288A (en) * | 2010-06-30 | 2011-05-18 | 美商威睿电通公司 | Video processing system and method realized by combining software with hardware and device thereof |
| CN102065288B (en) * | 2010-06-30 | 2013-07-24 | 美商威睿电通公司 | Video processing system and method realized by combining software with hardware and device thereof |
| RU2609096C2 (en) * | 2011-04-27 | 2017-01-30 | Шарп Кабусики Кайся | Images decoding device, images encoding device and data structure of encoded data |
| RU2653319C1 (en) * | 2011-04-27 | 2018-05-07 | Шарп Кабусики Кайся | Images decoding device, images encoding device and data structure of encoded data |
| CN102891927A (en) * | 2011-07-17 | 2013-01-23 | 白壮 | Mobile phone near field communication method based on audio air transmission |
| CN107844829A (en) * | 2017-10-31 | 2018-03-27 | 中国科学院计算技术研究所 | Method and system and neural network processor for accelerans network processing unit |
| CN110313178A (en) * | 2018-04-04 | 2019-10-08 | 深圳市大疆创新科技有限公司 | Code device and system |
| CN112449201A (en) * | 2019-08-30 | 2021-03-05 | 腾讯科技（深圳）有限公司 | Decoding method, encoding method, corresponding devices, electronic equipment and storage medium |
| CN112449201B (en) * | 2019-08-30 | 2021-12-17 | 腾讯科技（深圳）有限公司 | Decoding method, encoding method, corresponding devices, electronic equipment and storage medium |
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