CN1777008A - Power converter controller - Google Patents

Abstract

Detecting and controlling the switching current of the power converter, the controller controls output current. The controller includes a first circuit, a second circuit, a third circuit and a switching circuit. Based on switching current of the power converter, the first power converter generates a first signal. The second circuit detects discharge time of transformer. Based on integral carried out by discharge time on the first signal, the third circuit generates a third signal. Time constant of the third circuit is changeable, and related to the switching period of the switching signal. Thus, the third signal is proportioned to the output current. Receiving the third signal and based on a reference voltage, the switching circuit controls the pulse wave width of the switching signal so as to adjust output current of the power converter.

Description

The controller of power converter

Technical field:

The invention relates to a kind of power converter, be meant the controller of resonant power converter especially, it is the output current of the resonant power converter of control.

Background technology:

Press, multiple now power converter extensively applies to provide adjustment voltage and electric current.Power converter now can be provided with a current-sensing circuit and a control circuit at output in order accurately to control output current.Yet the current-sensing circuit of output can cause power consumption, and is especially more obvious in the output current power consumption that heals when high.In addition, the control circuit of output can take printed circuit board (PCB) (Print Circuit Board, space PCB) and the manufacturing cost that increases power converter.

Therefore, based on above-mentioned problem, the invention provides a control circuit, this control circuit is the commutation circuit in conjunction with power converter, to be used to control output current.Because the switch current of power converter is generally less than output current, so utilize switch current control output current can reduce power consumption.In addition, control circuit more can be integrated into an integrated circuit with commutation circuit, with space and the cost that reduces power converter effectively.

Summary of the invention:

Main purpose of the present invention is to provide a kind of controller of power converter, and it is the output current that utilizes the switch current power controlling transducer of power converter, reduces power consumption and reduces the purpose that takes up room to reach.

The invention provides a kind of controller of power converter, it is applied to resonant power converter, and controller of the present invention is by the switch current of power controlling transducer, with the output current of power controlling transducer.Controller includes one first circuit, and the switch current of a transformer that is used to detect power converter is to produce one first signal; One second circuit is coupled to transformer and produces one second signal with a discharge time of detecting transformer; One tertiary circuit carries out integration to produce one the 3rd signal according to second signal to first signal; One switches circuit, receives the 3rd signal and a reference voltage and switches signal to produce one, in order to the output current of switching transformer with the adjustment power converter.Wherein, for reaching the purpose of accurate control output current, the time constant of tertiary circuit is to be designed to be associated with the switching frequency that switches signal.

Description of drawings:

Fig. 1 is the circuit diagram of the resonant power converter of the embodiment of the invention;

Fig. 2 is the oscillogram of the resonant power converter of the embodiment of the invention;

Fig. 3 is the circuit diagram of the controller of the embodiment of the invention;

Fig. 4 is the curve chart of the output voltage of the embodiment of the invention with respect to the variation of output current;

Fig. 5 is the circuit diagram of the voltage control loop of the embodiment of the invention;

Fig. 6 is the circuit diagram of first circuit of the embodiment of the invention;

Fig. 7 is the circuit diagram of the second circuit of the embodiment of the invention;

Fig. 8 is the circuit diagram of the tertiary circuit of the embodiment of the invention;

Fig. 9 is the circuit diagram of the 4th circuit of the embodiment of the invention;

Figure 10 is the circuit diagram of cut-off circuit of the 4th circuit of the embodiment of the invention;

Figure 11 is the circuit diagram of turning circuit of the 4th circuit of the embodiment of the invention;

Figure 12 is the circuit diagram that the pulse wave of the turning circuit of the embodiment of the invention produces circuit;

Figure 13 is the oscillogram of the turning circuit of embodiments of the invention;

Figure 14 is the circuit diagram of timing circuit of the 4th circuit of the embodiment of the invention.

The figure number explanation:

10 transformers, 20 power electric crystals, 30 current sensing resistors

32 building-out capacitors, 40 rectifiers, 45 filter capacitors

50 resistance, 51 resistance, 53 Zener diodes

55 optical couplers, 60 rectifiers, 65 power capacitors

70 controllers, 71 first operational amplifiers, 75 first comparators

80 commutation circuits, 90 output circuit 91 first and locks

92 second and lock 93 first inverters 95 first flip-flops

100 first circuit, 101 second operational amplifiers, 103 second sample circuits

105 the 4th comparators, 106 offset voltages 109 the 4th switch

112 the 8th electric capacity 115 the 5th inverter, 116 hex inverters

117 second flip-flops 118 the 3rd flip-flop 119 the 5th and lock

120 second fixed current sources 121 the 6th electric capacity 122 the 3rd electric crystal

123 the 3rd fixed current sources 124 the 7th electric capacity 125 the 4th electric crystal

126 very first time delay circuits 127 first are clicked signal generating circuit

150 second inverters 151 the 3rd inverter 152 the 4th inverter

155 the 3rd and lock 156 the 4th and lock 200 second circuits

The 5th fixed current source, 210 cut-off circuits 211 the 4th fixed current source 212

215 the 5th comparators 217 the 6th electric crystal 218 the 7th electric crystal

223 the 11 electric capacity 224 the 12 electric capacity 241 the 7th inverter

242 the 8th inverters, 245 first and not b gate 246 the 6th and locks

250 turning circuits 251 the 8th electric crystal 252 the 13 electric capacity

253 the 6th fixed current sources 261 the 9th inverter 262 the tenth inverter

263 second and not b gates 265 the 7th and lock 270 first pulse waves produce circuit

280 second pulse waves produce circuit 290 timing circuits 291 counters

293 temporary buffer 295 oscillators 297 the 14 inverters

300 tertiary circuits, 305 peak sensing circuit, 307 first sample circuits

310 the 3rd comparators, 312 second switches 315 the 4th electric capacity

320 first fixed current sources 325 the 3rd switch 330 first switches

335 the 5th electric capacity, 350 second time delay circuit 351 the 11 inverters

352 the 7th fixed current sources 353 the 9th electric crystal 354 the 14 electric capacity

355 the 8th and lock 360 second click signal generating circuit

361 the 12 inverters 362 the 8th fixed current source 363 the tenth electric crystal

364 the 15 electric capacity 365 the 9th and lock 366 the 13 inverters

400 the 4th circuit, 405 voltages are to current converter circuit

410 the 3rd operational amplifiers 420 the 5th electric crystal

421 electric crystals, 422 electric crystals, 423 electric crystals

424 electric crystals, 425 electric crystals, 430 switches

431 switches, 432 switches, 433 switches

434 switches, 435 switches, 450 resistance

451 resistance, 452 resistance, 453 resistance

454 resistance, 455 resistance 460 the 5th switch

461 octavos are closed 462 the 6th switches 465 the 3rd sample circuit

472 output capacitances, 482 switches, 483 switches

484 switches, 485 switches, 486 minions are closed

489 the 9th electric capacity 490 the tenth electric capacity, 600 voltage control loops

610 second electric crystals, 611 resistance, 612 resistance

613 resistance, 620 add circuits, 630 second comparators

CLR removes signal FB and feedbacks end GND earth terminal

I ₁₂₀Second electric current I ₁₂₃The 3rd electric current I ₄₂₀First electric current

I ₃₅₂Electric current I ₃₆₂Electric current I _OOutput current

I _PPrimary side switch current I _PAPrimary side switch current peak value

I _SSecondary side switch current I _SASecondary side switch current peak value

N _AAuxiliary winding N _PFirst side winding N _SSecondary side winding

OUT output PLS setting signal RAMP slope signal

The RST first replacement signal SMP bolt-lock signal STB voltage sampling signal

S _DSThe second signal S _ICurrent circuit signal S _VThe voltage circuit signal

T switching cycle T _D1First time of delay T _D2Second time of delay

T _DSDDischarge time T _ONON time T _P1First pulse bandwidth

T _P2The second pulse bandwidth VALY trough detection signal V _AUXReflected voltage

VCC power source supply end DET detecting voltage end VS current sense end

V _AThe first signal V _DETDetecting voltage V _FBThe back coupling signal

V _INInput voltage V _OOutput voltage V _PWMSwitch signal

V _REF1Reference voltage V _REF2Reference voltage V _SPrimary side switch current signal

V _SPPeak value signal V _XThe 3rd signal

Execution mode:

Now further understand and understanding for your auditor is had architectural feature of the present invention and the effect reached, sincerely help with preferred embodiment figure and cooperate detailed explanation, be described as follows:

Seeing also Fig. 1, is the circuit diagram of the resonant power converter of the embodiment of the invention.Resonant power converter of the present invention includes a transformer 10, and it is provided with an auxiliary winding N _A, a first side winding N _PAn and secondary side winding N _SOne controller 70, it produces one and switches signal V _PWMAnd see through a power electric crystal 20, in order to switch this transformer 10, to adjust the output voltage V of power converter _OWith output current I _OSeeing also Fig. 2, is the oscillogram of the resonant power converter of the embodiment of the invention.When switching signal V _PWMCan order about power electric crystal 20 conductings during for high levle, thereby produce a primary side switch current I at the primary side of transformer 10 _PThis primary side switch current I _PPeak I _PACan be expressed as:

$I_{\mathrm{PA}}=\frac{V_{\mathrm{IN}}}{L_P}\×T_{\mathrm{ON}}---\left(1\right)$

Wherein, V _INBe an input voltage, be applied to transformer 10; L _PBe the first side winding N of transformer 10 _PInductance value; T _ONBe to switch signal V _PWMAn ON time.

In case switch signal V _PWMWhen reducing to low level, transformer 10 stored energy will be sent to the secondary side of transformer 10, and be sent to the output of this power converter through a rectifier 40, and rectifier 40 is coupled with a filter capacitor 45.The secondary side of transformer 10 has a secondary side switch current I _s, this secondary side switch current I _SPeak I _SACan be expressed as:

$I_{\mathrm{SA}}=\frac{(V_O+V_F)}{L_S}\×T_{\mathrm{DSD}}---\left(2\right)$

Wherein, V _OIt is the output voltage of power converter; V _FIt is the forward bias voltage drop of rectifier 40; L _SBe the secondary side winding N of transformer 10 _SInductance value; T _DSDBe secondary side switch current I _SA discharge time.

At this moment, the auxiliary winding N of transformer 10 _ABe to produce a reflected voltage V _AUX, it can be expressed as:

$V_{\mathrm{AUX}}=\frac{T_{\mathrm{NA}}}{T_{\mathrm{NS}}}\×(V_O+V_F)---\left(3\right)$

$I_{\mathrm{SA}}=\frac{T_{\mathrm{NP}}}{T_{\mathrm{NS}}}\×I_{\mathrm{PA}}---\left(4\right)$

Wherein, T _NAWith T _NSBe respectively the auxiliary winding N of transformer 10 _AWith secondary side winding N _SUmber of turn.As secondary side switch current I _SWhen reducing to zero, reflected voltage V _AUXThen begin to reduce, this also the energy of indication transformer 10 will move moment at this and discharge fully, this is the feature of resonant power converter just, promptly transformer 10 can fully release energy before next switching cycle begins.So T discharge time of equation (2) as shown in Figure 2, _DSDCan switch signal V by measuring _PWMThe drop edge to reflected voltage V _AUXDrop point time and learn.

Multiple with reference to figure 1, controller 70 includes a power source supply end VCC, a detecting voltage end DET, an earth terminal GND, a current sense end VS, back coupling end FB, an output OUT and a current compensation end COMI.Signal V is switched in output OUT output _PWM, detecting voltage end DET sees through a resistance 50 and is coupled to auxiliary winding N _A, with detecting reflected voltage V _AUXReflected voltage V _AUXSee through 65 chargings of 60 pairs one power capacitors of a rectifier, with power supply to controller 70.Current sense end VS is coupled to a current sensing device, a current sensing resistor 30 for example, and the one end couples the one source pole of power electric crystal 20, and the other end then is coupled to earth terminal, with conversion primary side switch current I _PBe a primary side switch current signal V _S

Multiple with reference to figure 1, power converter is provided with an optical coupler 55 by the secondary side at transformer 10, and the output voltage that the input of optical coupler 55 is subjected to see through a resistance 51 transmission and checking of a Zener diode 53 are received driven, make output produce a back coupling signal V _FB, and transfer to the back coupling end FB of controller 70, to form feedback control circuit.Current compensation end COMI is coupled with a building-out capacitor 32.

Seeing also Fig. 3, is the circuit diagram of the controller of the embodiment of the invention.Controller 70 of the present invention includes one first circuit 100, and it is coupled to current sense end VS, that is is coupled to current sensing resistor 30, and primary side switch current signal V is used to take a sample _S, to produce one first signal V _AOne second circuit 200 sees through the discharge time of detecing side transformer 10, goes out secondary side switch current I to detect side _ST discharge time _DSDOne the 4th circuit 400 is used to produce a setting signal PLS, switches signal V with decision _PWMSwitching frequency; One tertiary circuit 300 is at T discharge time _DSDTo the first signal V _ACarry out integration, to produce one the 3rd signal V _XWherein, because a time constant of tertiary circuit 300 and switching signal V _PWMSwitching cycle T relevant, so the 3rd signal V _XOutput current I with power converter _OProportional.

Controller 70 more includes one and switches circuit 80, and it includes one first operational amplifier 71 and a reference voltage V _REF1With as an error amplifier, be used to control output current; One first comparator 75 see through one first and lock 91 couple with one first flip-flop 95, with the output control switching signal V of foundation error amplifier _PWMPulse bandwidth.Error amplifier amplifies the 3rd signal V _XAnd a loop gain is provided, to be used to control output current.Current control loop comprises detecting primary side switch current I _PCircuit, in order to adjust to switch signal V _PWMPulse bandwidth.Current control loop is according to reference voltage V _REF1And control primary side switch current I _PSize.Shown in equation (4), secondary side switch current I _SWith primary side switch current I _PProportional.Multiple with reference to waveform shown in Figure 2, the output current I of power converter _OBe secondary side switch current I _SMean value, the output current I of power converter _OCan be expressed as:

$I_O=I_{\mathrm{SA}}\×\frac{T_{\mathrm{DS}}}{2T}---\left(5\right)$

Wherein, T _DSBe the discharge time of transformer 10, it equals secondary side switch current I _ST discharge time _DSDSo, the output current I of power converter _OBe can be controlled.

Multiple with reference to figure 1, the present invention utilizes current sensing resistor 30 conversion primary side switch current I _PBe primary side switch current signal V _SFirst circuit, 100 detecting primary side switch current signal V _S, to produce the first signal V _A300 couples first signal V of tertiary circuit _AIntegration and produce the 3rd signal V _X, the 3rd signal V _XCan be expressed as:

$V_X=\frac{V_A}{2}\×\frac{T_{\mathrm{DS}}}{T_1}---\left(6\right)$

Wherein, V _ACan be expressed as:

$V_A=\frac{T_{\mathrm{NS}}}{T_{\mathrm{NP}}}\×R_S\×I_{\mathrm{SA}}---\left(7\right)$

Wherein, T ₁Be the time constant of tertiary circuit 300, R _SIt is the resistance value of current sensing resistor 30.

With reference to equation (4) to equation (7), the 3rd signal V _XCan be expressed as:

$V_X=\frac{\mathrm{<figure-callout\; id="1"\; label="T\; T"\; filenames="A20051012569000281.png"\; state="\{\{state\}\}">T</figure-callout>}}{T_{}}\&times;\frac{T_{\mathrm{NS}}}{T_{\mathrm{NP}}}{\&times;R}_S\&times;I_O---\left(8\right)$

Wherein, it should be noted that the 3rd signal V _XBe output current I with power converter _OProportional, so the 3rd signal V _XDuring enhancing, output current I _OAlso increase thereupon, however the 3rd signal V _XMaximum see through the adjustment of current control loop, and be subjected to reference voltage V _REF1Value limit.In other words, current control loop is according to reference voltage V _REF1Value control switch signal V _PWMPulse bandwidth, with control output current I _OUnder the back coupling control of current control loop, maximum output current I _{O (MAX)}Can be expressed as:

$I_{O\left(\mathrm{MAX}\right)}=\frac{T_{\mathrm{NP}}}{T_{\mathrm{NS}}}\&times;\frac{G_A\&times;G_{\mathrm{SW}}\&times;{\mathrm{<figure-callout\; id="1"\; label="V\; R"\; filenames="A20051012569000281.png"\; state="\{\{state\}\}">V</figure-callout>}}_R}{1+(G_A\&times;G_{\mathrm{SW}}\&times;\frac{R_S}{K})}---\left(9\right)$

Wherein, K is that constant equals T ₁/ T; V _R1Be reference voltage V _REF1Magnitude of voltage; G _AIt is the gain of error amplifier; G _SWIt is the gain of commutation circuit 80.

If the very high (G of loop gain of current control loop _A* G _SW＞＞1), maximum output current I then _{O (MAX)}Can be expressed as:

$I_{O\left(\mathrm{MAX}\right)}=K\&times;\frac{T_{\mathrm{NP}}}{T_{\mathrm{NS}}}\&times;\frac{V_{R1}}{R_S}---\left(10\right)$

Therefore, according to reference voltage V _REF1Can be with the maximum output current I of power converter _{O (MAX)}Be adjusted into fixed current.Output voltage V of the present invention _OWith respect to output current I _OVariation curve chart promptly as shown in Figure 4.

Commutation circuit 80 of the present invention more includes an output circuit 90, and it includes 95 outputs of first flip-flop and switches signal V _PWM, with switchover power converter.One clock pulse end CK of first flip-flop 95 is the outputs that couple one first inverter 93, and the setting signal PLS that is produced by the 4th circuit 400 can set first flip-flop 95 through first inverter 93.One input D of first flip-flop 95 is used for receiving a supply voltage V _CC, an output Q of first flip-flop 95 be couple one second and a first input end of lock 92, second and one second input of lock 92 are the outputs that couple first inverter 93, and second and the output of lock 92 are the output OUT that couple controller 70.One of first flip-flop 95 reset end R be couple first and an output of lock 91, first and a first input end of lock 91 receive a voltage circuit signal S _V, voltage circuit signal S _VProduced by voltage control loop 600, voltage control loop 600 is in order to adjust the output voltage V of power converter _O

First and one second input of lock 91 are the outputs that are coupled to first comparator 75, be used to receive the current circuit signal S that first comparator 75 is exported _I, to reach the purpose of control output current.First and one the 3rd input of lock 91 then receive the one first replacement signal RST that the 4th circuit 400 is produced.Wherein, current circuit signal S _IWith voltage circuit signal S _VBe respectively the second replacement signal and the 3rd replacement signal.The just first replacement signal RST, current circuit signal S _IWith voltage circuit signal S _V, be first flip-flop 95 of can resetting, shorten to switch signal V _PWMPulse bandwidth, so can adjust output voltage V _OWith output current I _OOne anode of first comparator 75 is coupled to an output of first operational amplifier 71, and a negative terminal of first comparator 75 is coupled to the 4th circuit 400, is used to receive the slope signal RAMP that the 4th circuit 400 is produced.

Seeing also Fig. 5, is the circuit diagram of the voltage control loop of the embodiment of the invention.Voltage control loop 600 of the present invention includes one second electric crystal 610, three resistance 611,612,613, an add circuit 620 and one second comparator 630.Wherein, the gate of second electric crystal 610 is to couple with the back coupling end FB of controller 70 and an end of resistance 611.The drain of second electric crystal 610 is that the other end with resistance 611 couples and receive supply voltage V _CCThe source electrode of second electric crystal 610 then couples with an end of resistance 612, couples and the other end of resistance 612 is ends with resistance 613, and the other end of resistance 613 then is coupled to ground connection.One anode of second comparator 630 is coupled to feedback through second electric crystal 610, resistance 612,613 holds FB, in order to accurate Bit Shift and decay, a negative terminal of second comparator 630 is coupled to the output of add circuit 620 to receive slope signal RAMP and primary side switch current signal V _S, it is to utilize add circuit 620 addition primary side switch current signal V _SWith slope signal RAMP to obtain slope-compensation, the output of second comparator 630 like this is output voltage loop signal S _V

Seeing also Fig. 6, is the circuit diagram of first circuit of the embodiment of the invention.First circuit 100 of the present invention includes a peak sensing circuit 305, and its anode that includes one the 3rd comparator, 310, the three comparators 310 again couples the current sense end VS of this controller 70.Primary side switch current signal V _SValue be and primary side switch current I _PValue proportional, it is in order to nip primary side switch current signal V that a negative terminal of the 3rd comparator 310 is coupled to one the 4th electric capacity, 315, the four electric capacity 315 _SPeak value.

The 4th electric capacity 315 is by 320 chargings of one first fixed current source, the first fixed current source 315 and supply voltage V _CCCouple.Be coupled with one first switch 330 between the 4th electric capacity 315 and the first fixed current source 320, the two ends of first switch 330 are respectively coupled to the first fixed current source 320 and the 4th electric capacity 315, the conducting of first switch 330 is the output that is controlled by the 3rd comparator 310 with ending, and the current potential at the 4th electric capacity like this 315 two ends is a peak value signal V _SPPeak value signal V _SPShown in 2 figure, be and primary side switch current I _PPeak I _PAProportional.The 4th electric capacity 315 is to be parallel with the discharge that a second switch 312 is used to control the 4th electric capacity 315, and second switch 312 is controlled by the removing signal CLR that the 4th circuit 400 is produced.First circuit 100 still includes one first sample circuit 307, it includes one the 3rd switch 325 and one the 5th electric capacity 332, it is coupled between the 4th electric capacity 315 and the 5th electric capacity 335 and is controlled by the bolt-lock signal SMP that the 4th circuit 400 is produced, be used for periodically conducting and end, with the peak value signal V that take a sample from the 4th electric capacity 315 _SPTo the 5th electric capacity 335, so both can obtain the first signal V by the 5th electric capacity 335 _A

Seeing also Fig. 7, is the circuit diagram of the second circuit of the embodiment of the invention.Second circuit 200 of the present invention includes a very first time delay circuit 126 and one first and clicks (one-shot) signal generating circuit 127, and very first time delay circuit 126 includes one second inverter 150, one the 3rd electric crystal 122, one second fixed current source 120, one the 6th electric capacity 121 and one the 3rd and lock 155.The second fixed current source 120 is coupled to supply voltage V _CCAnd between the drain of the 3rd electric crystal 122.The 6th electric capacity 121 and the 3rd and an input of lock 155 also be coupled to the drain of the 3rd electric crystal 122, the gate of the 3rd electric crystal 122 receives and switches signal V _PWM, source electrode then is coupled to ground connection.The 3rd and another input of lock 155 be coupled to the output of second inverter 150, the input of second inverter 150 is brought in to receive and is switched signal V _PWMOne input of very first time delay circuit 126 receives and switches signal V _PWM, in order to switching signal V _PWMThe drop edge one transmission delay (propagation delay) is provided.One second electric current I in the second fixed current source 120 ₁₂₀With the time of the capacitance of the 6th electric capacity 121 decision transmission delay.

First clicks signal generating circuit 127 includes one the 3rd inverter 151, one the 4th inverter 152, one the 4th electric crystal 125, one the 3rd fixed current source 123, one the 7th electric capacity 124 and one the 4th and lock 156, is used to produce a voltage sampling signal STB.First input of clicking signal generating circuit 127 is coupled to the output of very first time delay circuit 126, promptly the input of the 3rd inverter 151 is coupled to the 3rd and the output of lock 155, and the output of the 3rd inverter 151 then is coupled to the gate of the 4th electric crystal 125.The 3rd fixed current source 123 is coupled to supply voltage V _CCAnd between the drain of the 4th electric crystal 125, the drain of the 4th electric crystal 125 more couples with the input of the 7th electric capacity 124 and the 4th inverter 152, and source electrode then is coupled to ground connection.The output of the 4th inverter 152 be coupled to the 4th and an input of lock 156, the 4th and another input of lock 156 then be coupled to the 3rd and the output of lock 155.The pulse bandwidth of one the 3rd electric current I 123 in the 3rd fixed current source 123 and the capacitance of the 7th electric capacity 124 decision voltage sampling signal STB.

Second circuit 200 still includes one second operational amplifier 101, and it is as a buffer amplifier.One output and a negative terminal of second operational amplifier 101 couple mutually, and the anode of the second operational amplifier 101 just input of buffer amplifier and the detecting voltage end DET of this controller 70 couples.Detecting voltage end DET sees through the auxiliary winding N that is coupled to transformer 10 by resistance 50 _A, be used to detect reflected voltage V _AUXOne second sample circuit 103, it includes one the 4th switch 109 and one the 8th electric capacity 112.The two ends of the 4th switch 109 are coupled to the output and the 8th electric capacity 112 of second operational amplifier 101 respectively.The conducting of the 4th switch 109 with by being controlled by voltage sampling signal STB, reflected voltage V is used to take a sample _AUXBe a sample signal, it is a detecting voltage V _DETTo learn discharge time detecting voltage V _DETWill be by nip at the 8th electric capacity 112.

One the 4th comparator 105 of second circuit 200 is in order to detecting reflected voltage V _AUXReduction.One anode of the 4th comparator 105 is coupled to the 8th electric capacity 112, one negative terminal of the 4th comparator 105 then is coupled to an offset voltage 106, offset voltage 106 is coupled between the output of the negative terminal of the 4th comparator 105 and second operational amplifier 101, is used to provide a critical voltage to detect lateral reflection voltage V _AUXReduction.So as reflected voltage V _AUXReduction when exceeding the magnitude of voltage of offset voltage 106, the output of the 4th comparator 105 is the end signal of a high levle.

One input of one the 5th inverter 115 of second circuit 200 receives and switches signal V _PWMOne input of one hex inverter 116 receives voltage sampling signal STB; One the 5th and a first input end of lock 119 be coupled to an output of the 4th comparator 105; One second flip-flop 117 and one the 3rd flip-flop 118 are provided with the replacement end that a setting is held and high levle triggers that upper limb triggers separately, and the setting end S of the 3rd flip-flop 118 and replacement end R couple an output of hex inverter 116 respectively and receive switching signal V _PWMOne output Q of the 3rd flip-flop 118 then couples the 5th and second input of lock 119.One output Q of second flip-flop 117 exports the second signal S _DS, the setting end S of second flip-flop 117 is coupled to the output of the 5th inverter 115, so the second signal S _DSBe that activation is in switching signal V _PWMCut-off state, the replacement end R of second flip-flop 117 then is coupled to the 5th and an output of lock 119, that is the 5th and lock 119 receive stop signals and the second signal S when transferring to second flip-flop 117 _DSCan forbidden energy.The second above-mentioned signal S _DSPulse bandwidth and T discharge time of transformer 10 _DSRelevant.

Seeing also Fig. 8, is the circuit diagram of the tertiary circuit of the embodiment of the invention.Tertiary circuit 300 of the present invention includes a voltage to current converter circuit 405, and it includes one the 3rd operational amplifier 410, plural resistance 450-455 and one the 5th electric crystal 420 again.The anode of the 3rd operational amplifier 410 receives the first signal V _A, the negative terminal of the 3rd operational amplifier 410 then couples the source electrode of resistance 450-455 and the 5th electric crystal 420.The output of the 3rd operational amplifier 410 then is coupled to the gate of the 5th electric crystal 420, and the drain of the 5th electric crystal 420 couples mutually with the drain of electric crystal 421.The 3rd operational amplifier 410 is according to the first signal V _AMagnitude of voltage produce one first electric current I of programmed ₄₂₀The power plural current mirror includes plural electric crystal 421-425, is used to shine upon first electric current I ₄₂₀Produce power plural current I ₄₂₂-I ₄₂₅, the source electrode of electric crystal 421-425 is to be coupled in together and to be coupled to supply voltage V _CC, the gate of electric crystal 421-425 also is coupled in together and is coupled to the drain of electric crystal 421.Wherein resistance 450-455 and one the 9th electric capacity 489 and 1 the tenth electric capacity 490 determine the time constant of tertiary circuits 300.

One the 5th switch 460 is coupled to electric current I ₄₂₂-I ₄₂₅And between two electric capacity 489,490, the 5th switch 460 is only at T discharge time _DSJust conducting of cycle, the conducting of promptly representing the 5th switch 460 is to be controlled by the second signal S _DSOne the 6th switch 462 is to be parallel to two electric capacity 489,490, and to control the discharge of two electric capacity 489,490, the 6th switch 462 is controlled by the removing signal CLR that the 4th circuit 400 is produced.The two ends of one minion pass 486 are respectively coupled between the 9th electric capacity 489 and the 5th switch 460.

One the 3rd sample circuit 465, it includes 461 and one output capacitance, 472, the octavos pass, octavo pass 461 and is coupled between two electric capacity 489,490 and the output capacitance 472.Octavo close 461 be controlled by that the 4th circuit 400 produced fasten lock signal SMP, be used for periodically conducting with by with from two electric capacity, 489,490 sampling voltages to output capacitance 472, so can obtain the 3rd signal V by output capacitance 472 _XThe 3rd signal V _XCan be expressed as:

$V_X=\frac{1}{R_X{C}_X}{\&times;V}_A\&times;T_{\mathrm{DS}}---\left(11\right)$

Wherein, R _XResistance value for resistance 450-455; C _XCapacitance for electric capacity 489,490.

In order to allow the time constant (R of tertiary circuit 300 _X, C _X) and switch signal V _PWMSwitching frequency relevant, the capacitance and the electric current I of the resistance value of resistance 450-455, electric capacity 489,490 ₄₂₂-I ₄₂₅Be programmed control, it is by the plural switch 430-435 that is coupled to resistance 450-455, the plural switch 482-485 that is coupled to two switches 462,486 of two electric capacity 489,490 and is coupled to electric crystal 422-425.Switch 430-435 and switch 482-486 are controlled by the 4th signal N that the 4th circuit 400 is produced _n... N ₀Control.

Seeing also Fig. 9, is the circuit diagram of the 4th circuit of the embodiment of the invention.The 4th circuit 400 includes a cut-off circuit 210, a turning circuit 250 and a timing circuit 290.Cut-off circuit 210 receives and switches signal V _PWM, switching signal V _PWMON time produce slope signal RAMP, and produce the first replacement signal RST according to slope signal RAMP, switch signal V with decision _PWMMaximum ON time.Turning circuit 250 is according to the second signal S _DSEnd and produce setting signal PLS, wherein turning circuit 250 more according to setting signal PLS produce to remove signal CLR and to fasten lock signal SMP.Timing circuit 290 is to receive to remove signal CLR and fasten lock signal SMP to produce the 4th signal N _n... N ₀

Seeing also Figure 10, is the circuit diagram of cut-off circuit of the 4th circuit of the embodiment of the invention.Cut-off circuit 210 includes one the 7th inverter 241, and its receiving terminal receives and switches signal V _PWMOutput then couples the gate of one the 6th electric crystal 217.One the 4th fixed current source 211 is coupled in and is connected in the drain of the 6th electric crystal 217 with 1 the 11 electric capacity 223, and the source electrode of the 6th electric crystal 217 then is coupled to ground connection, and the 4th fixed current source 211 and the 11 electric capacity 223 are according to switching signal V _PWMConducting state produce slope signal RAMP.One the 5th comparator 215, the one anode receives reference voltage V _REF2And a negative terminal is coupled to the 11 electric capacity 223, produces the first replacement signal RST according to slope signal RAMP, switches signal V with decision _PWMMaximum turn-on cycle.

The output of the 5th comparator 215 is coupled to a first input end of one first and not b gate 245, and one second input and one the 3rd input of first and not b gate 245 receive voltage circuit signal S respectively _VWith current circuit signal S _I, the output of first and not b gate 245 then couples the gate of one the 7th electric crystal 218, and the source electrode of the 7th electric crystal 218 then is coupled to ground connection.One the 5th fixed current source 212 is coupled in and is connected in the drain of the 7th electric crystal 218 with 1 the 12 electric capacity 224, and is connected to one the 6th and a first input end of lock 246.The 4th above-mentioned fixed current source 211 and the 5th fixed current source 212 all with supply voltage V _CCCouple.The output of first and not b gate 245 more is coupled to the input of one the 8th inverter 242, the output of the 8th inverter 242 with the 6th and one second input of lock 246 couple mutually, the 6th and the output of lock 246 produce the first replacement signal RST.The 5th fixed current source 212 and the 12 electric capacity 224 are minimum pulse bandwidths of guaranteeing the first replacement signal RST.

Seeing also Figure 11, is the circuit diagram of turning circuit of the 4th circuit of the embodiment of the invention.Turning circuit 250 includes one the 8th electric crystal 251, and its gate receives the second signal S _DSAnd drain is coupled in the input of one the 6th fixed current source the 253, the 13 electric capacity 252 and one the 9th inverter 261, the output of the 9th inverter 261 is coupled to one the 7th and a first input end of lock 265, and the 6th fixed current source 253 also with supply voltage V _CCCouple.The input of 1 the tenth inverter 262 receives the second signal S _DSAnd output is coupled to the 7th and one second input of lock 265 and a first input end of one second and not b gate 263, one second input of second and not b gate 263 receives a trough detection signal VALY, the output of second and not b gate 263 then be coupled to the 7th and one the 3rd input of lock 265, the 7th and the output of lock 265 produce setting signal PLS.

The 7th and lock 265 be according to the second signal SDS by producing setting signal PLS with the activation of selectable trough detection signal VALY.Trough detection signal VALY is used for opening switching signal V _PWM, with the resonance frequency of power converter synchronously and reach flexible and switch.The 6th above-mentioned fixed current source 253 and the 13 electric capacity 252 are pulse bandwidths of decision setting signal PLS.One first pulse wave generation circuit 270 and one second pulse wave generation circuit 280 produce respectively according to setting signal PLS and fasten lock signal SMP and remove signal CLR.The circuit diagram of first pulse wave generation circuit 270 and second pulse wave generation circuit 280 as shown in figure 12.Setting signal PLS, the sequential of fastening lock signal SMP and removing signal CLR and waveform are as shown in figure 13.

Seeing also Figure 12, is the circuit diagram that produces circuit for the pulse wave of embodiments of the invention.The present invention produces circuit by two pulse waves to fasten lock signal SMP and remove signal CLR with generation, and pulse wave generation circuit of the present invention includes one second time delay circuit 350 and one second and clicks signal generating circuit 360.Second time delay circuit 350 includes 1 the 11 inverter 351, one the 7th fixed current source 352, one the 9th electric crystal 353,1 the 14 electric capacity 354 and one the 8th and lock 355 again.The input of the 11 inverter 351 receives setting signal PLS, and the output of the 11 inverter 351 then is coupled to the gate of the 9th electric crystal 353.The drain of the 9th electric crystal 353 be with the 7th fixed current source the 352, the 14 electric capacity 354 and the 8th and an input of lock 355 couple, the source electrode of the 9th electric crystal 353 then is coupled to ground connection.The 7th fixed current source 352 also with supply voltage V _CCCouple.In addition the 8th and another input of lock 355 then receive setting signal PLS.

Second clicks signal generating circuit 360 includes 1 the 12 inverter 361, one the 8th fixed current source 362,1 the tenth electric crystal 363,1 the 15 electric capacity 364, one the 9th and lock 365 and 1 the 13 inverter 366.The input of the 12 inverter 361 and the 8th and the output of lock 355 couple, the output of the 12 inverter 361 then couples with the gate of the tenth electric crystal 363.The input of the drain of the tenth electric crystal 363 and the 8th fixed current source the 362, the 15 electric capacity 364 and the 12 inverter 366 couples, and the source electrode of the tenth electric crystal 363 then is coupled to ground connection, in addition the 8th fixed current source 362 and supply voltage V _CCCouple.The 9th and a first input end of lock 365 and output that one second input then couples the 13 inverter 366 respectively and the 8th and the output of lock 355.Second output of clicking the 9th and the lock 365 of signal generating circuit 360 is the output that pulse wave produces circuit.

The output signal that pulse wave produces circuit is second to click the signal of clicking that signal generating circuit 360 exported, and be and fasten lock signal SMP or remove signal CLR, and input signal is the setting signal PLS that is sent to an input of second time delay circuit 350.One electric current I in the 7th fixed current source 352 ₃₅₂Determine time of delay of second time delay circuit 350 with the capacitance of the 14 electric capacity 354, one output of second time delay circuit 350 is coupled to second input of clicking signal generating circuit 360, promptly the 8th and the output of lock 355 couple mutually with the input of the 12 inverter 361.One electric current I in the 8th fixed current source 362 ₃₆₂Click the pulse bandwidth of signal with the decision of the capacitance of the 15 electric capacity 364.

See also Figure 13, be the oscillogram of the turning circuit of embodiments of the invention.Fasten lock signal SMP and remove signal CLR as shown in figure 13.The present invention be trigger by the positive edge of setting signal PLS first pulse wave produce circuit 270 through one first time of delay T _D1After promptly produce and fasten lock signal SMP, it is for having one first pulse bandwidth T _P1One click signal, the positive edge of same time set signal PLS be trigger second pulse wave produce circuit 280 through one second time of delay T _D2After promptly produce and have one second pulse bandwidth T _P2Removing signal CLR.Second time of delay T _D2Be longer than first time of delay T _D1

Seeing also Figure 14, is the circuit diagram of timing circuit of the 4th circuit of the embodiment of the invention.Timing circuit 290 includes a counter 291, one temporary buffer 293, one the 5th circuit 295 and 1 the 14 inverter 297.The input of the 14 inverter 297 receives removes signal CLR, and output then is coupled to counter 291.The 5th circuit 295 is used to produce a clock pulse signal CLK.Counter 291 receives time pulse signal CLK and removes signal CLR to produce a binary code.Temporary buffer 293 produces the 4th signal N according to fastening lock signal SMP sampling binary code _n... N ₀One time constant (R of the 5th circuit 295 _YC _Y) be the time constant (R that is associated with tertiary circuit 300 _XC _X), and signal V is switched in the representative of the binary code of counter 291 _PWMA switching cycle, so switch signal V _PWMSwitching cycle T can determine be:

T＝R _Y×C _Y×N _Count (12)

Wherein, N _COUTBe the 4th signal N _n... N ₀Value.

Therefore, the 3rd signal V _XBe and secondary side switch current I _SAnd the output current I of power converter ₀Relevant, so equation (8) can be expressed as with equation (11)

As follows:

$V_X=m\&times;\frac{T_{\mathrm{NS}}}{T_{\mathrm{NP}}}\&times;R_S\&times;I_O---\left(13\right)$

Wherein, m is a constant, and it can be expressed as:

$m=\frac{R_Y{\&times;C}_Y}{R_X{\&times;C}_X}\&times;N_{\mathrm{Cout}}---\left(14\right)$

Because time constant R _XC _XBe according to the 4th signal N _n... N ₀So Be Controlled and stylizing is (R _YC _Y* N _COUT) value equal R _XC _XValue, so the 3rd signal V _XBe output current I with power converter _OProportional.

The above, it only is preferred embodiment of the present invention, be not to be used for limiting scope of the invention process, all according to the described shape of the present patent application claim, structure, feature and principle etc. change and modify, all should be contained in the claim of the present invention.

Claims (11)

1, a kind of controller of power converter is applied to a resonant power converter, and it includes:

One first circuit is coupled to a current sensing device of this resonant power converter, and the switching electric current with according to a transformer of this resonant power converter produces one first signal;

One second circuit is coupled to this transformer, according to a discharge time of this transformer, produces one second signal;

One tertiary circuit according to this this first signal of second signal integration, produces one the 3rd signal;

One switches circuit, receives the 3rd signal and a reference voltage, produces one and switches signal, and this switching signal is used to switch this transformer to adjust an output current of this resonant power converter.

As the 1st described controller of claim, it is characterized in that 2, a time constant of this tertiary circuit is the switching frequency that is associated with this switching signal.

3, as the 1st described controller of claim, it is characterized in that, more include one the 4th circuit, it is that switching frequency according to this switching signal produces one the 4th signal, the 4th signal be used to the to stylize time constant of this tertiary circuit is to carry out integration.

4, as the 3rd described controller of claim, it is characterized in that, the 4th circuit produces a setting signal when this second signal finishes, and produce a slope signal in the ON time of this switching signal, and produce one first replacement signal according to this slope signal, in order to determine a maximum ON time of this switching signal.

5, as the 4th described controller of claim, it is characterized in that the 4th circuit includes:

One turning circuit receives this second signal, and this turning circuit produces this setting signal when this second signal finishes, and removes signal and according to this setting signal generation one and fasten the lock signal;

One cut-off circuit receives this switching signal, and this cut-off circuit produces this slope signal in the ON time of this switching signal, and produces this first replacement signal according to this slope signal, in order to determine this maximum ON time of this switching signal;

One timing circuit receives this removing signal and this fastens the lock signal, produces the 4th signal.

6, as the 5th described controller of claim, it is characterized in that this timing circuit more includes:

One the 5th circuit produces a clock pulse signal;

One counter receives this time pulse signal and this removing signal, produces a binary code;

One temporary buffer is fastened lock signal this binary code of taking a sample according to this, produces the 4th signal;

Wherein, the time constant of the 5th circuit is the time constant that is associated with this tertiary circuit, and this binary code of this counter switches a switching cycle of signal for this.

7, as the 1st described controller of claim, it is characterized in that this commutation circuit includes:

One operational amplifier receives the 3rd signal and this reference voltage, produces an error signal;

One comparator receives this error signal and a slope signal, produces one second replacement signal;

One output circuit receives a setting signal and orders about this switching signal conducting, receives one first replacement signal or this second replacement signal and orders about this switching signal and end.

8, as the 1st described controller of claim, it is characterized in that this first circuit includes:

One peak sensing circuit is coupled to this current sensing device, with the peak value according to this switch current, produces a peak value signal;

One first sample circuit couples this peak sensing circuit, and this peak value signal of taking a sample produces this first signal.

9, as the 1st described controller of claim, it is characterized in that this second circuit includes:

One second sample circuit couples this transformer, and a reflected voltage of this transformer of taking a sample produces a sample signal and is used to learn this discharge time;

One comparator, one input end couples this transformer through an offset voltage, detects this reflected voltage of this transformer, and another input of this comparator receives this sample signal, and the output output one of this comparator finishes signal;

One flip-flop receives this switching signal and this end signal, produces this second signal, and this second signal is the activation according to the cut-off state of this switching signal, and this second signal is during according to this end signal and forbidden energy.

10, as the 1st described controller of claim, it is characterized in that this tertiary circuit includes:

One electric capacity is used to produce the 3rd signal;

One change-over circuit receives this first signal to produce one first electric current, is used for this electric capacity charging;

One switch is coupled between this first electric current and this electric capacity, and this second signal is controlled this switch to control this first electric current to this electric capacity charging;

One the 3rd sample circuit couples this electric capacity, and the voltage of this electric capacity of taking a sample produces the 3rd signal;

Wherein, a resistance of this change-over circuit, this electric capacity and this first electric current are the time constants of this tertiary circuit of decision.

11, the 10th described controller of claim is characterized in that, the current value of the resistance value of this resistance, the capacitance of this electric capacity and this first electric current is to be decided by one the 4th signal.

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