CN1773864A - Extended Reed-Solomon code decoding method which error-correcting capcity is 2 - Google Patents

Abstract

A decoding method of expanded Reed-Soloman code with error correction ability of 2 includes calculating out syndrome of data with error to be corrected, storing data in FIFO buffer, calculating auxiliary parameter according to syndrome calculation result, confirming number and scope of error code according said result and said parameter, calculating out error value error position as per different error situation, adding data in buffer with error value for correcting error, deleting calibration byte to finalize error correction decoding.

Description

A kind of error correcting capability is the interpretation method of extended Reed-Solomon code of 2

Technical field

The present invention relates to the Reed Solomon code that a kind of many mass storage adopts data are handled as error-control method, particularly relate to a kind of error correcting capability and be the interpretation method of extended Reed-Solomon code of 2.

Background technology

In transmission of Information and storage, because the interference of channel or ambient noise tends to cause transmission and canned data to make a mistake.1948, Shannon proposed information theory.Wherein, " thanks for your hospitality the channel coding theorem of discrete channel " and point out the technology of carrying out error control by the redundancy that increases information, be that information data is encoded before transmission and storage, when receiving and extract data, decipher, be corrected in the mistake that takes place in transmission and the storing process by redundant information.People have worked out multiple code word and coding and decoding method.Nineteen sixty, REED and SOLOMON have proposed Reed Solomon code, are called for short the RS sign indicating number.The RS sign indicating number has the ability of outstanding burst-error-correction, is widely used in radio communication and storage system.

Because RS sign indicating number self, the more complicated of the interpretation method of RS sign indicating number own, the Project Realization of interpretation method be difficulty relatively, and engineering cost is higher, and is difficult to the decoding speed that reaches desirable.A kind of decoder of RS sign indicating number can Project Realization and the cost of Project Realization and effect how, often become the whether practical decisive factor of this RS sign indicating number.And the Project Realization of RS decoder also becomes the focus of engineers and technicians' research and practice.

Mass storage is widely used in the storage in fields such as space flight, industry, consumer electronics.Rugged environment will cause the storage data that unpredictalbe mistake takes place; At magnetic, the optical storage media of consumer electronics field, also can be owing to the physics breakage causes loss of data and damage.Therefore, the correct reliable and zero access technology of data is one of key technologies of mass storage.At present, many mass storages have all adopted the RS sign indicating number that data are handled measure as error control.But, because mass storage self, as require to guarantee quite high memory capacity, high speed data access, control complex logic or the like all requires to adopt a kind of advantages of simplicity and high efficiency RS code word and effective interpretation method, fast operation, and be easy to Project Realization.

Summary of the invention

The objective of the invention is in order to overcome because the interpretation method complexity of RS sign indicating number, the slow shortcoming of decoder that is unfavorable for Project Realization or realization, thereby provide a kind of can in the mass storage through RS (256,252) coded data is carried out the high speed error-correcting decoding, correct two bytes with interior mistake, the error-correcting decoding method of the Reed Solomon code that whole error decoding circuit is all realized in programmable logic device (can be FPGA) chip, this method are applicable to that error correcting capability is 2 expansion RS sign indicating number.

Parameters related in the error-correcting decoding method of the present invention is:

S (S ₀, S ₁, S ₂, S ₃): syndrome (Syndrome);

H: check matrix;

R: data block to be decoded;

FIFO: first-in first-out buffer memory;

N: the number of code word in each data block to be decoded;

K: the number of information word in each data block to be decoded;

B ₀, B ₁, B ₂, E, CO ₀, CO ₁: auxiliary parameter, wherein B ₁, B ₂Be used for the judgement of error situation; B ₀, B ₁, B ₂It still is the coefficient of finding the solution the linear equation in two unknowns of wrong occurrence positions under the 5th kind of situation; E is an improper value under the 4th kind of error situation, CO ₀, CO ₁It is the coefficient of the 5th kind of improper value accounting equation under the error situation;

α: the primitive element of finite field;

(n-1, k): the former RS sign indicating number before the expansion, true form only can be corrected the mistake of 1 code word to RS.

(n, k): the RS sign indicating number after the expansion expands by increasing an additional check code word RS.Should additional check code word be the algebraical sum of a front n-1 code word.Expansion back code block has n code word, and n-k=4, can correct the mistake of two code words.

The error-correcting decoding method of a kind of Reed Solomon code provided by the present invention comprises the steps:

(1) at first the syndrome counting circuit is calculated in the input of data to decode piece, calculate syndrome S (S ₀, S ₁, S ₂, S ₃); Simultaneously, the RS coded data R (x) with input deposits FIFO (first-in first-out buffer memory) in;

Wherein store the polynomial expression formula of data:

R (x)=r _N-1x ^N-1+ ...+r ₁x ¹+ r ₀, r wherein ₀Be additional check code word;

By channel coding theorem, syndrome S:

S＝R·H ^T＝(S ₀，S ₁，S ₂，S ₃)＝(r ₀，r ₁，...，r _n-1)·H ^T；

(2) calculate next step (3) and the needed auxiliary parameter B of step (4) ₀, B ₁, B ₂, E, CO ₀And CO ₁Computing formula is as follows:

${\mathrm{<figure-callout\; id="0"\; label="B"\; filenames="A20041009080500181.png,A20041009080500201.png"\; state="\{\{state\}\}">B</figure-callout>}}_0={\mathrm{<figure-callout\; id="1"\; label="S"\; filenames="A20041009080500181.png"\; state="\{\{state\}\}">S</figure-callout>}}_1^2+S_0{\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="A20041009080500181.png,A20041009080500201.png"\; state="\{\{state\}\}">S</figure-callout>}}_2$

${\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="A20041009080500181.png"\; state="\{\{state\}\}">B</figure-callout>}}_1={\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="A20041009080500181.png,A20041009080500201.png"\; state="\{\{state\}\}">S</figure-callout>}}_2^2+S_1{S}_3$

B ₂＝S ₁S ₂+S ₀S ₃

E＝S ₁S ₂/S ₃

CO ₀＝B0S ₁/B ₂

CO ₁＝B ₁S ₀/B ₂

(3) according to the resulting syndrome S of step (1) (S ₀, S ₁, S ₂, S ₃), and the resulting auxiliary parameter of step (2), come the number of misjudgment code word and position or the scope that wrong code word occurs, select the improper value computation schema different again with errors present;

(4), obtain wrong position and corresponding error value again according to the estimate of situation of step (3);

(5) with the improper value addition of data in buffer and correspondence position, carry out error correction; All check code words of data are finished decoding after the amputation error correction.

In the step (3) of technique scheme, described basis for estimation:

First kind of situation illustrates that this blocks of data is correct, and mistake did not take place, and do not need to carry out error correction;

Second kind of situation illustrates that a mistake has taken place this blocks of data, appears at additional check code word, and just mistake has taken place last code word;

The third situation illustrates that a mistake has taken place this blocks of data, appears at additional check code word some code words in addition, and a mistake has taken place just preceding n-1 code word;

The 4th kind of situation illustrates that two mistakes have taken place this blocks of data, appears at additional check code word and certain non-add check code word, and mistake has taken place some code words in the just preceding n-1 code word, and mistake has also taken place last code word simultaneously;

The 5th kind of situation illustrates that two mistakes have taken place this blocks of data, appears at additional check code word two code words in addition, that is to say that mistake has taken place certain two code word in the preceding n-1 code word;

Other situations.For other wrong more than two any situations take place, (decoder can not be discerned for n, k) Ma error correction and error detecing capability, still is considered as the 5th kind of situation, sees Table 1 to exceed RS;

In the step (4) of technique scheme, according to the result of calculation of the judged result of step (3) and step (1), (2), the branch situation is carried out correction process:

For first kind of situation, directly the output buffers data do not process;

For second kind of situation, mistake appears in additional check byte, and its improper value is S ₀

For the third situation, a mistake has appearred in the non-add check byte, and its improper value is S ₀Bit-error locations equation S ₂+ S ₁α ⁱ=0 separate is the position alpha that makes a mistake ⁱ

For the 4th kind of situation, the improper value of additional check byte is E+S ₀, the improper value of non-add check byte is E, bit-error locations equation S ₂+ S ₁α ⁱ=0 separate is the position alpha that makes a mistake in the non-add check byte ⁱ

For the 5th kind of situation, bit-error locations equation B ₀(α ⁱ) 2+B ₂α ⁱ+ B ₁Separate α for two of=0 ⁱAnd α ^jBe the position of making a mistake, corresponding improper value is respectively: CO ₁α ^-i+ CO ₀And CO ₁α ^-j+ CO ₀

The advantage of the inventive method is:

It is RS (256, the 252) sign indicating number of two bytes that error-correcting decoding method provided by the present invention adopts error correcting capability.Because RS (256,252) sign indicating number is RS (255,252) sign indicating number is by increasing the extended code that an additional check byte obtains, make the error correcting capability of mass storage bring up to 2 bytes from 1 byte, this error correcting capability enough can satisfy the needs of the memory device error control of space exploration, Industry Control and magnetic, light medium, and deciphers fairly simple.Another selects RS (256,252) Ma major reason is, in 256 bytes store data, the information data that 252 bytes are arranged, it is extra check byte that increase that 4 byte datas are only arranged, in whole storage data, account for very little ratio, so adopt this error control coding and decoding very little to the memory capacity influence.Simultaneously, the storage cell of digital storage equipment generally is 2 integral number power, and the operating unit of access instruction is also often with 2 integral number power.And RS (256,252) sign indicating number is by expansion, and the length of every block codewords is increased to 256 bytes from 255, and promptly 28 powers are very easy to use.This method error correcting capability is strong, and decoding is simple, and decoding speed is fast, particularly is easy to Project Realization.

Description of drawings

Fig. 1 is the flow chart of the method for a kind of error-correcting decoding provided by the invention;

Fig. 2 is a kind of RS (256,252) code error-correcting decoding block diagram of system of implementing the inventive method.

Fig. 3 is RS (256,252) the code error-correcting decoding chip circuit block diagram of implementing in the system of the inventive method.

Fig. 4 is the syndrome counting circuit block diagram of implementing in the system of the inventive method.

Fig. 5 is the finite field multiplication and division computing circuit block diagram of implementing in the system of the inventive method.

Fig. 6 A, Fig. 6 B, Fig. 6 C are respectively the finite field gfs of implementing in the system of the inventive method (2 ⁸) element multiply by α, α ²And α ³Circuit block diagram.

Fig. 7 is a kind of work schedule signal waveforms of implementing system's chips of the inventive method.

The drawing explanation:

1 input interface circuit, 2 error decoding circuits, 3 error decoding circuits

4 output interface circuits, 5 syndrome counting circuits, 6 auxiliary parameter counting circuits

7 error situation decision circuitry, 8 fifo circuits, 9 improper values are by wrong position

Output circuit 10 error decoding circuits 11 error byte counting circuits

Circuit is selected in 91 error correction

A0, a1, a2, a3, a4, a5, a6, a7 1 bit register

B0, b1, b2, b3, b4, b5, b6, b7 1 bit register

C0, c1, c2, c3, c4, c5, c6, c7 1 bit register

Embodiment

Below in conjunction with the drawings and specific embodiments the present invention is done and to describe in further detail.

With RS (256,252) sign indicating number be example, uses method of the present invention to carry out the error-correcting decoding of RS (256,252) sign indicating number, and RS (256,252) is that to expand the error correcting capability that obtains from RS (255,252) be extended Reed-Solomon code of 2.

An existing correct RS (256,252) sign indicating number code word data, totally 256 byte datas according to input sequence are:

(1)8’h01；

(2)8′h02；

(3)8′h02；

(4)8′h04；

(5)8′h0F；

(6)8′hF0；

(7)-(251)8′h00；

(252)8′h81；

(253)8′h86；

(254)8′h66；

(255)8′h06；

(256)8′h9D；

Above-mentioned data all represent with 16 systems, the width of the each input of " 8 " expression data, i.e. and figure place, " h " represents hexadecimal, wherein the data value of the 7th byte to the 251 bytes all is 8 ' h00.

Embodiment 1

Use interpretation method of the present invention that RS (256,252) sign indicating number is carried out error-correcting decoding, supposing does not in the present embodiment have mistake in RS (256, the 252) code word.The error-correcting decoding process is as follows.

1) at first with data to decode piece input syndrome counting circuit, calculates syndrome S (S ₀, S ₁, S ₂, S ₃); Simultaneously, the RS coded data R (x) with input deposits FIFO (first-in first-out buffer memory) in; To deposit 256 byte datas in the first-in first-out buffer memory exactly in the present embodiment, and calculate syndrome, obtain the result of syndrome: S about these data ₀=S ₁=S ₂=S ₃=0.

2) according to the syndrome result of calculation S (S of step 1) ₀, S ₁, S ₂, S ₃), calculation procedure 3) and the auxiliary parameter B that needs of step 4) ₀, B ₁, B ₂, E, CO ₀And CO ₁, computing formula is ${\mathrm{<figure-callout\; id="0"\; label="B"\; filenames="A20041009080500181.png,A20041009080500201.png"\; state="\{\{state\}\}">B</figure-callout>}}_0={\mathrm{<figure-callout\; id="1"\; label="S"\; filenames="A20041009080500181.png"\; state="\{\{state\}\}">S</figure-callout>}}_1^2+S_0{\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="A20041009080500181.png,A20041009080500201.png"\; state="\{\{state\}\}">S</figure-callout>}}_2,$

${\mathrm{<figure-callout\; id="0"\; label="B"\; filenames="A20041009080500181.png,A20041009080500201.png"\; state="\{\{state\}\}">B</figure-callout>}}_0={\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="A20041009080500181.png,A20041009080500201.png"\; state="\{\{state\}\}">S</figure-callout>}}_2^2+S_1{S}_3,$ B ₂＝S ₁S ₂+S ₀S ₃，E＝S ₁S ₂/S ₃，CO ₀＝B ₀S ₁/B ₂，CO ₁＝B ₁S ₀/B ₂；

Readily appreciate that from the result of above-mentioned syndrome the value of above auxiliary parameter is 0 or does not exist.

3) from step 1) and 2) result of calculation S (S ₀, S ₁, S ₂, S ₃) and B ₁, B ₂, judge table 1 according to error situation, determine the number of wrong code word and position or the scope that wrong code word occurs,

The inventive method has following five kinds of estimate of situations:

If first kind of situation is S ₀=S ₁=S ₂=S ₃=0, illustrate that this blocks of data is correct, mistake did not take place, do not need to carry out error correction;

If second kind of situation is S ₀≠ 0, S ₁=S ₂=S ₃=0, illustrate that a mistake has taken place this blocks of data, appears at additional check code word;

If the third situation is S ₁≠ 0, S ₂≠ 0, S ₃≠ 0, B ₁=B ₂=0, illustrate that a mistake has taken place this blocks of data, appear at additional check code word some code words in addition;

If the 4th kind of situation is S ₁≠ 0, S ₂≠ 0, S ₃≠ 0, B ₁=0, B ₂≠ 0, illustrate that two mistakes have taken place this blocks of data, appear at additional check code word and certain non-add check code word;

If the 5th kind of situation is S ₁≠ 0, S ₂≠ 0, S ₃≠ 0, B ₁≠ 0, illustrate that two mistakes have taken place this blocks of data, appear at additional check code word two code words in addition;

Other situations, for other wrong more than two any situations take place, (decoder can not be discerned for n, k) Ma error correction and error detecing capability, still is considered as the 5th kind of situation to exceed RS;

In the present embodiment, judge it is first kind of situation by the result of calculation of syndrome in the step 1), promptly this blocks of data is correct, and mistake did not take place, and does not need to carry out error correction.

4) according to 3) judged result, the improper value that mistake in computation position and correspondence position occur;

The inventive method has five kinds of different dispositions:

For first kind of situation, directly the output buffers data do not process;

For second kind of situation, mistake appears in additional check byte, and its improper value is S ₀

For the third situation, a mistake has appearred in the non-add check byte, and its improper value is S ₀, bit-error locations equation S ₂+ S ₁α ⁱ=0 separate is the position alpha that makes a mistake ⁱ

For the 4th kind of situation, the improper value of additional check byte is E+S ₀, the improper value of non-add check byte is E, bit-error locations equation S ₂+ S ₁α ⁱ=0 separate is the position alpha that makes a mistake in the non-add check byte ⁱ

For the 5th kind of situation, bit-error locations equation B ₀(α ⁱ) ²+ B ₂α ⁱ+ B ₁Separate α for two of=0 ⁱAnd α ^jBe the position of making a mistake, corresponding improper value is respectively: CO ₁α ^-i+ CO ₀And CO ₁α ^-j+ CO ₀

Specific to present embodiment, judge present embodiment by step 3) and belong to first kind of situation, so direct output buffers data.

5) with data in the buffer memory and improper value addition, carry out error correction; Last amputation check code word is finished error-correcting decoding.

In the present embodiment, data do not make a mistake, so this step can be skipped.

Final decode results:

(1)8’h01；

(2)8′h02；

(3)8′h02；

(4)8′h04；

(5)8′h0F；

(6)8′hF0；

(7)-(251)8′h00；

(252)8′h81。

Embodiment 2

In the present embodiment,, become 8 ' h0D from 8 ' h9D if mistake has taken place the data of the 256th byte of above-mentioned correct RS (256,252) sign indicating number code word.Use interpretation method of the present invention that it is carried out error-correcting decoding.

1) at first with data to decode piece input syndrome counting circuit, calculates syndrome S (S ₀, S ₁, S ₂, S ₃), simultaneously, deposit the RS coded data R (x) that imports in FIFO (first-in first-out buffer memory).In the present embodiment, syndrome result of calculation is S ₀=8 ' h90 ≠ 0, S ₁=S ₂=S ₃=0.

2) according to the syndrome result of calculation S (S of step 1) ₀, S ₁, S ₂, S ₃), calculation procedure 3) and the auxiliary parameter B that needs of step 4) ₀, B ₁, B ₂, E, CO ₀And CO ₁, computing formula is ${\mathrm{<figure-callout\; id="0"\; label="B"\; filenames="A20041009080500181.png,A20041009080500201.png"\; state="\{\{state\}\}">B</figure-callout>}}_0={\mathrm{<figure-callout\; id="1"\; label="S"\; filenames="A20041009080500181.png"\; state="\{\{state\}\}">S</figure-callout>}}_1^2+S_0{\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="A20041009080500181.png,A20041009080500201.png"\; state="\{\{state\}\}">S</figure-callout>}}_2,$ ${\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="A20041009080500181.png"\; state="\{\{state\}\}">B</figure-callout>}}_1={\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="A20041009080500181.png,A20041009080500201.png"\; state="\{\{state\}\}">S</figure-callout>}}_2^2+S_1{S}_3,$ B ₂＝S ₁S ₂+S ₀S ₃，E＝S ₁S ₂/S ₃，CO ₀＝B ₀S ₁/B ₂，CO ₁＝B ₁S ₀/B ₂。

In the present embodiment, each auxiliary parameter is 0 or does not exist.

3) from step 1) and 2) result of calculation S (S ₀, S ₁, S ₂, S ₃) and B ₁, B ₂, judge table 1 according to error situation, determine the number of wrong code word and the position that wrong code word occurs, various possible estimate of situations are described in detail in embodiment 1.In the present embodiment, by S ₀=8 ' h90 ≠ 0, S ₁=S ₂=S ₃=0, judge this blocks of data a mistake has taken place, appear at additional check code word.

4) according to 3) judged result, the improper value that mistake in computation position and correspondence position occur; In the present embodiment, mistake occurs in additional check code word, and improper value is S ₀, i.e. 8 ' h90.

5) with data in the buffer memory and improper value addition, carry out error correction; Last amputation check code word is finished error-correcting decoding.In the present embodiment, be about to last 1 byte 8 ' h0D improper value 8 ' h90 that " adds (XOR) ", obtain right value 8 ' h9D, finish error correction, last amputation check code word, dateout.Obtain:

(1)8’h01；

(2)8′h02；

(3)8′h02；

(4)8′h04；

(5)8′h0F；

(6)8′hF0；

(7)-(251)8′h00；

(252)8′h81；

Embodiment 3

In the present embodiment,, become 8 ' h0A from 8 ' h01 if mistake has taken place the data of the 1st byte of above-mentioned correct RS (256,252) sign indicating number code word.Use interpretation method of the present invention that it is carried out error-correcting decoding.

1) at first with data to decode piece input syndrome counting circuit, calculates syndrome S (S ₀, S ₁, S ₂, S ₃); Simultaneously, the RS coded data R (x) with input deposits FIFO (first-in first-out buffer memory) in; Will deposit 256 byte datas in the first-in first-out buffer memory exactly in the present embodiment, and calculate the syndrome about these data, the result is: S ₀=8 ' h0B ≠ 0, S ₁=8 ' h8B ≠ 0, S ₂=8 ' hCB ≠ 0, S ₃=8 ' hEB ≠ 0.

2) according to the syndrome result of calculation S (S of step 1) ₀, S ₁, S ₂, S ₃), calculation procedure 3) and the auxiliary parameter B that needs of step 4) ₀, B ₁, B ₂, E, CO ₀And CO ₁, computing formula is ${\mathrm{<figure-callout\; id="0"\; label="B"\; filenames="A20041009080500181.png,A20041009080500201.png"\; state="\{\{state\}\}">B</figure-callout>}}_0={\mathrm{<figure-callout\; id="1"\; label="S"\; filenames="A20041009080500181.png"\; state="\{\{state\}\}">S</figure-callout>}}_1^2+S_0{\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="A20041009080500181.png,A20041009080500201.png"\; state="\{\{state\}\}">S</figure-callout>}}_2,$ ${\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="A20041009080500181.png"\; state="\{\{state\}\}">B</figure-callout>}}_1={\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="A20041009080500181.png,A20041009080500201.png"\; state="\{\{state\}\}">S</figure-callout>}}_2^2+S_1{S}_3,$ B ₂＝S ₁S ₂+S ₀S ₃，E＝S ₁S ₂/S ₃，CO ₀＝B ₀S ₁/B ₂，CO ₁＝B ₁S ₀/B ₂。

In the present embodiment, the result of calculation of auxiliary parameter is: B ₁=B ₂=0.

3) from step 1) and 2) result of calculation S (S ₀, S ₁, S ₂, S ₃) and B ₁, B ₂, judge table 1 according to error situation, determine the number of wrong code word and the position that wrong code word occurs, various possible estimate of situations are described in detail in embodiment 1.In the present embodiment, by above-mentioned syndrome result and auxiliary parameter, as can be known: a mistake has taken place in this blocks of data, appears at additional check code word some code words in addition.

4) according to 3) judged result, the improper value that mistake in computation position and correspondence position occur; In the present embodiment, improper value is S ₀, i.e. 8 ' h0B is by bit-error locations equation S ₂+ S ₁α ⁱ=0 asks the position alpha that makes a mistake ⁱ, the position that wrong code word occurs in the present embodiment is the 1st byte in code word as can be known.

5) with data in the buffer memory and improper value addition, carry out error correction; Last amputation check code word is finished error-correcting decoding.In the present embodiment, the 1st byte 8 ' h0A " adds (XOR) " improper value 8 ' h0B obtains right value 8 ' h01, and last amputation check byte obtains:

(1)8’h01；

(2)8′h02；

(3)8′h02；

(4)8′h04；

(5)8′h0F；

(6)8′hF0；

(7)-(251)8′h00；

(252)8′h81。

Embodiment 4

In the present embodiment, if mistake has all taken place for the 3rd byte of above-mentioned correct RS (256,252) sign indicating number code word and the data of the 256th byte, the former has become 8 ' h8A from 8 ' h02, and the latter has become 8 ' h62 from 8 ' h9D.Use interpretation method of the present invention that it is carried out error-correcting decoding.

1) at first with data to decode piece input syndrome counting circuit, calculates syndrome S (S ₀, S ₁, S ₂, S ₃); Simultaneously, the RS coded data R (x) with input deposits FIFO (first-in first-out buffer memory) in; Will deposit 256 byte datas in the first-in first-out buffer memory exactly in the present embodiment, and calculate the syndrome about these data, the result is: S ₀=8 ' h77, S ₁=8 ' h11 ≠ 0, S ₂=8 ' hAF ≠ 0, S ₃=8 ' h71 ≠ 0.

2) according to the syndrome result of calculation S (S of step 1) ₀, S ₁, S ₂, S ₃), calculation procedure 3) and the auxiliary parameter B that needs of step 4) ₀, B ₁, B ₂, E, CO ₀And CO ₁, computing formula is ${\mathrm{<figure-callout\; id="0"\; label="B"\; filenames="A20041009080500181.png,A20041009080500201.png"\; state="\{\{state\}\}">B</figure-callout>}}_0={\mathrm{<figure-callout\; id="1"\; label="S"\; filenames="A20041009080500181.png"\; state="\{\{state\}\}">S</figure-callout>}}_1^2+S_0{\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="A20041009080500181.png,A20041009080500201.png"\; state="\{\{state\}\}">S</figure-callout>}}_2,$ ${\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="A20041009080500181.png"\; state="\{\{state\}\}">B</figure-callout>}}_1={\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="A20041009080500181.png,A20041009080500201.png"\; state="\{\{state\}\}">S</figure-callout>}}_2^2+S_1{S}_3,$ B ₂＝S ₁S ₂+S ₀S ₃，E＝S ₁S ₂/S ₃，CO ₀＝B ₀S ₁/B ₂，CO ₁＝B ₁S ₀/B ₂。

In the present embodiment, B ₁=0, B ₂=8 ' h13 ≠ 0, E=8 ' h88.

3) from step 1) and 2) result of calculation S (S ₀, S ₁, S ₂, S ₃) and B ₁, B ₂, judge table 1 according to error situation, determine the number of wrong code word and the position that wrong code word occurs, various possible estimate of situations are described in detail in embodiment 1.In the present embodiment, by S ₁≠ 0, S ₂≠ 0, S ₃≠ 0, B ₁=0, B ₂≠ 0, illustrate that two mistakes have taken place this blocks of data, appear at additional check code word and certain non-add check code word.

4) according to 3) judged result, the improper value that mistake in computation position and correspondence position occur; In the present embodiment, the improper value of additional check byte is E+S ₀=8 ' h88+8 ' h77=8 ' hFF, the improper value of non-add check byte are E=8 ' h88, bit-error locations equation S ₂+ S ₁α ⁱ=0 separate is exactly the position alpha that makes a mistake in the non-add check byte ⁱ, result of calculation is that the 3rd byte makes a mistake.

5) with data in the buffer memory and improper value addition, carry out error correction; Last amputation check code word is finished error-correcting decoding.In the present embodiment, the 3rd byte 8 ' h8A " adds (XOR) " improper value 8 ' h88 obtains right value 8 ' h02, and last 1 byte 8 ' h62 adds 8 ' hFF, obtains right value 8 ' h9D.With data amputation check byte, obtain:

(1)8’h01；

(2)8′h02；

(3)8′h02；

(4)8′h04；

(5)8′h0F；

(6)8′hF0；

(7)-(251)8′h00；

(252)8′h81。

Embodiment 5

In the present embodiment, if mistake has all taken place for the 1st byte of above-mentioned correct RS (256,252) sign indicating number code word and the data of the 4th byte, the former has become 8 ' h9E from 8 ' h01, and the latter has become 8 ' hFB from 8 ' h04.Use interpretation method of the present invention that it is carried out error-correcting decoding.

1) at first with data to decode piece input syndrome counting circuit, calculates syndrome S (S ₀, S ₁, S ₂, S ₃); Simultaneously, the RS coded data R (x) with input deposits FIFO (first-in first-out buffer memory) in; In the present embodiment, the result of calculation of syndrome is S ₁=8 ' h72 ≠ 0, S ₂=8 ' h90 ≠ 0, S ₃=8 ' h14 ≠ 0.

2) according to the syndrome result of calculation S (S of step 1) ₀, S ₁, S ₂, S ₃), calculation procedure 3) and the auxiliary parameter B that needs of step 4) ₀, B ₁, B ₂, E, CO ₀And CO ₁, computing formula is ${\mathrm{<figure-callout\; id="0"\; label="B"\; filenames="A20041009080500181.png,A20041009080500201.png"\; state="\{\{state\}\}">B</figure-callout>}}_0={\mathrm{<figure-callout\; id="1"\; label="S"\; filenames="A20041009080500181.png"\; state="\{\{state\}\}">S</figure-callout>}}_1^2+S_0{\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="A20041009080500181.png,A20041009080500201.png"\; state="\{\{state\}\}">S</figure-callout>}}_2,$ ${\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="A20041009080500181.png"\; state="\{\{state\}\}">B</figure-callout>}}_1={\mathrm{<figure-callout\; id="2"\; label="S"\; filenames="A20041009080500181.png,A20041009080500201.png"\; state="\{\{state\}\}">S</figure-callout>}}_2^2+S_1{S}_3,$ B ₂＝S ₁S ₂+S ₀S ₃，E＝S ₁S ₂/S ₃，CO ₀＝B ₀S ₁/B ₂，CO ₁＝B ₁S ₀/B ₂。

In the present embodiment, B ₁=8 ' hA8 ≠ 0, CO ₀=8 ' h41, CO ₁=8 ' h6F.

3) from step 1) and 2) result of calculation S (S ₀, S ₁, S ₂, S ₃) and B ₁, B ₂, judge table 1 according to error situation, determine the number of wrong code word and the position that wrong code word occurs, various possible estimate of situations are described in detail in embodiment 1.In the present embodiment, S ₁≠ 0, S ₂≠ 0, S ₃≠ 0, B ₁≠ 0, illustrate that two mistakes have taken place this blocks of data, appear at additional check code word two code words in addition.

4) according to 3) judged result, the improper value that mistake in computation position and correspondence position occur; In the present embodiment, by bit-error locations equation B ₀(α ⁱ) ²+ B ₂α ⁱ+ B ₁Separate α for two of=0 ⁱAnd α ^jObtain the position of making a mistake, corresponding improper value is respectively: CO ₁α ^-i+ CO ₀And CO ₁α ^-j+ CO ₀With the correlation substitution, the code word that makes a mistake as can be known is respectively the 1st byte and the 4th byte, and improper value is respectively 8 ' h9F and 8 ' hFF.

5) with data in the buffer memory and improper value addition, carry out error correction; Last amputation check code word is finished error-correcting decoding.In the present embodiment, the 1st byte 8 ' h9E " adds (XOR) " improper value 8 ' h9F obtains right value 8 ' h01, and the 4th byte 8 ' hFB adds 8 ' hFF, obtains right value 8 ' h04.Last amputation check byte obtains:

(1)8’h01；

(2)8′h02；

(3)8′h02；

(4)8′h04；

(5)8′h0F；

(6)8′hF0；

(7)-(251)8′h00；

(252)8′h81。

Error correction method of the present invention is to carry out on referring to the system that Fig. 2 did, and the RS that present embodiment provides (256,252) code error-correcting decoding system comprises input interface circuit 1, error decoding circuit 2 and 3, and output interface circuit 4.Input interface circuit 1 is connected with concrete system environments on the one hand, from system, obtain clock, reset, read and write control, control signal and data/address signal such as sheet choosing, link to each other with 3 with error decoding circuit 2 on the other hand, supply with error decoding circuit correct data input and error-correcting decoding enable signal.Output interface circuit 4 is connected with 3 with error decoding circuit 2, obtains the error-correcting decoding result, and to subordinate equipment output serial data and serial data clock.

Error decoding circuit is the core of the chip that provides of present embodiment.Referring to Fig. 3.256 byte datas enter syndrome counting circuit 5 and calculate syndrome, and data enter fifo circuit 8 simultaneously.Auxiliary parameter counting circuit 6 is connected with circuit 5, calculates auxiliary parameter according to the output of syndrome counting circuit 5.Error situation decision circuitry 7 is connected with auxiliary parameter counting circuit 6 with syndrome counting circuit 5 respectively, calculates 6 result of calculation according to syndrome counting circuit 5 and auxiliary parameter, and circuit 7 is judged the error situation of 256 byte datas.Errors present is connected with circuit 7 by wrong position output circuit 9, according to the output result of error situation decision circuitry 7, improper value selects circuit 91 to select different submodules 92,93 by the error correction in the wrong position output circuit 9,94 or 95, according to errors present output error value.The output of last each submodule is selected 96 outputs by multichannel.The output of the output of fifo circuit 8 and circuit 9 all is connected to error decoding circuit 10, realizes error-correcting decoding.Error byte counting circuit 11 links to each other with error situation decision circuitry 7, obtains the error byte number, and back output adds up.

In error decoding circuit, syndrome counting circuit 5 is referring to Fig. 4.In each clock cycle, S ₀Add up with the parallel data of input; S ₁, S ₂And S ₃The result of last computation multiply by α, α respectively in the register ²And α ³, and with 8 parallel-by-bit data additions, the result still preserves back former register.After 256 clock cycle, what preserve in each register is exactly syndrome result of calculation.

Finite field gf (2 in the syndrome counting circuit 5 ⁸) element multiply by α, α ²And α ³Circuit referring to Fig. 6 A, Fig. 6 B, Fig. 6 C.

The realization of multiplication and division arithmetic in the auxiliary parameter counting circuit 6 utilizes finite field gf (2 ⁸) element and itself be with respect to the corresponding relation between the power of primitive element time, field element is mapped to the index of oneself by tabling look-up, multiplication and divide operations are converted to the addition and the subtraction of mould 255, again the result of mould plus and minus calculation is shone upon back finite field at last.Each computing is all tabled look-up by twice and one-off pattern adds and finishes.Direct transform that this circuit is realized and inverse transformation need two mapping tables, and each table is realized with the RAM of 256 bytes.Because finite field element 0 can't shine upon, so, when having one to be 0 in the element that carries out computing, do not need to shine upon the computing of adding and subtracting with mould 255, directly export result of calculation 0.If though divisor is 0 result of calculation also is 0, there is not physical significance, the parameter (E, the CO that calculate by division circuit ₀And CO ₁) service condition, guaranteed that divisor is not 0 when carrying out these division calculation, result of calculation is correct.

Such implementation has not only been saved logical resource valuable in the programmable logic device chip, and has made full use of the block RAM resource of chip.Multiplication of realizing and division circuit at most only need 4 clock cycle, but this implementation requires chip to have certain block RAM capacity.The specific implementation circuit is referring to Fig. 5.

Improper value is by wrong position output circuit 9, and the circuit of mistake in computation value in the circuit of mistake in computation position and the submodule 95 all is by Fig. 6 A in the submodule 93,94 and 95 wherein, the finite field gf (2 among Fig. 6 B and Fig. 6 C ⁸) element multiply by α, α ²And α ³Circuit is realized.

Fig. 7 is the clock signal oscillogram of error decoding circuit.CLK is a clock signal among the figure, and RST is a reset signal, and ENIN treats that for input error-correcting decoding data, ECASE are error situation for input enable signal, RS, and M is data behind the error-correcting decoding, and ENOUT is an output enable.Through 14 clock cycle, export first byte behind the every 256 byte data input error decoding circuit through error-correcting decoding; Through 13 clock cycle, this circuit can begin to receive new a collection of 256 byte datas; Each treats that error correction entered behind the error decoding circuit through 270 clock cycle, exported corresponding error-correcting decoding result.

Table 1 error situation is judged table

Wherein, "/" is illustrated in and do not consider this value when judging

Claims (8)

1. an error correcting capability is the interpretation method of 2 expansion RS sign indicating number, comprises the steps:

1) at first the syndrome counting circuit is calculated in the input of data to decode piece, calculate syndrome S (S ₀, S ₁, S ₂, S ₃); Simultaneously, the RS coded data R (x) with input deposits first-in first-out buffer memory FIFO in;

Wherein store the polynomial expression formula of data:

R (x)=r _N-1x ^N-1+ ... + r ₁x ¹+ r ₀, r wherein ₀Be additional check code word;

By channel coding theorem, syndrome S:

S＝R·H ^T＝(S ₀，S ₁，S ₂，S ₃)＝(r ₀，r ₁，…，r _n-1)·H ^T；

2) according to the syndrome result of calculation S (S of step 1) ₀, S ₁, S ₂, S ₃), calculation procedure 3) and the auxiliary parameter B that needs of step 4) ₀, B ₁, B ₂, E, CO ₀And CO ₁

Wherein computing formula is $B_0=S_1^2+S_0{S}_2;$

$B_1=S_2^2+S_1{S}_3;$

B ₂＝S ₁S ₂+S ₀S ₃；

E＝S ₁S ₂/S ₃；

CO ₀＝B ₀S ₁/B ₂；

CO ₁＝B ₁S ₀/B ₂；

3) from the result of calculation S (S of step 1) ₀, S ₁, S ₂, S ₃) and step 2) resulting auxiliary parameter B ₁, B ₂, judge table according to error situation, come the number of misjudgment code word and position or the scope that wrong code word occurs, select the improper value computation schema different again with errors present;

4) according to the judged result of step 3), the improper value that occurs of mistake in computation position and correspondence position again;

5) with data in the buffer memory and the resulting improper value addition of step 4), carry out error correction; Last amputation check code word is finished error-correcting decoding.

2. a kind of error correcting capability according to claim 1 is the interpretation method of 2 expansion RS sign indicating number, it is characterized in that: in the step (3), and described basis for estimation:

First kind of situation illustrates that this blocks of data is correct, and mistake did not take place, and do not need to carry out error correction;

Second kind of situation illustrates that a mistake has taken place this blocks of data, appears at additional check code word, and just mistake has taken place last code word;

The third situation illustrates that a mistake has taken place this blocks of data, appears at additional check code word some code words in addition, and a mistake has taken place just preceding n-1 code word;

The 4th kind of situation illustrates that two mistakes have taken place this blocks of data, appears at additional check code word and certain non-add check code word, and mistake has taken place some code words in the just preceding n-1 code word, and mistake has also taken place last code word simultaneously;

The 5th kind of situation illustrates that two mistakes have taken place this blocks of data, appears at additional check code word two code words in addition, that is to say that mistake has taken place certain two code word in the preceding n-1 code word;

Other situations.For other wrong more than two any situations take place, (decoder can not be discerned for n, k) Ma error correction and error detecing capability, still is considered as the 5th kind of situation to exceed RS.

3. a kind of error correcting capability according to claim 2 is the interpretation method of 2 expansion RS sign indicating number, it is characterized in that: for first kind of situation, directly the output buffers data do not process.

4. a kind of error correcting capability according to claim 2 is the interpretation method of 2 expansion RS sign indicating number, and it is characterized in that: for second kind of situation, mistake appears in additional check byte, and its improper value is S ₀

5. a kind of error correcting capability according to claim 2 is the interpretation method of 2 expansion RS sign indicating number, and it is characterized in that: for the third situation, a mistake has appearred in the non-add check byte, and its improper value is S ₀, bit-error locations equation S ₂+ S ₁α ⁱ=0 separate is the position alpha that makes a mistake ⁱ

6. a kind of error correcting capability according to claim 2 is the interpretation method of 2 expansion RS sign indicating number, it is characterized in that: for the 4th kind of situation, the improper value of additional check byte is E+S ₀, the improper value of non-add check byte is E, bit-error locations equation S ₂+ S ₁α ⁱ=0 separate is the position alpha that makes a mistake in the non-add check byte ⁱ

7. a kind of error correcting capability according to claim 2 is the interpretation method of 2 expansion RS sign indicating number, it is characterized in that: for the 5th kind of situation, bit-error locations equation B ₀(α ⁱ) ²+ B ₂α ⁱ+ B ₁Separate α for two of=0 ⁱAnd α ^jBe the position of making a mistake, corresponding improper value is respectively: CO ₁α ^-i+ CO ₀And CO ₁α ^-j+ CO ₀

8, a kind of error correcting capability according to claim 1 is the interpretation method of 2 expansion RS sign indicating number, it is characterized in that: according to code word number that makes a mistake and the wrong scope that occurs, select different improper values and errors present account form to carry out error-correcting decoding.

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