CN1770457A - Non-volatile memory and its manufacturing method and operating method - Google Patents
Non-volatile memory and its manufacturing method and operating method Download PDFInfo
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- CN1770457A CN1770457A CN 200410089724 CN200410089724A CN1770457A CN 1770457 A CN1770457 A CN 1770457A CN 200410089724 CN200410089724 CN 200410089724 CN 200410089724 A CN200410089724 A CN 200410089724A CN 1770457 A CN1770457 A CN 1770457A
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Abstract
This invention relates to non-volatile memory with baseboard, selective transistor and grove transistor, wherein, The selective transistor is located on baseboard comprising first grating electrode on baseboard and first source electrode and leakage electrode area on baseboard and second ones; The groove transistor is set on baseboard comprising second grating electrode in groove and charge concaved layer between second grating electrode and groove and third source electrode or leakage electrode area in baseboard on both sides of second grating electrode, wherein, the groove transistor and selected transistor share second source electrode or leakage electrode area.
Description
Technical field
The present invention relates to a kind of semiconductor memery device and manufacture method thereof and method of operation, particularly relate to a kind of non-volatility memorizer and manufacture method thereof and method of operation.
Background technology
When semiconductor entered the manufacturing process of deep-sub-micrometer (Deep Sub-Micron), size of component was dwindled gradually, and for memory component, just the representative memory cell size is more and more little.On the other hand, along with the information electronic product (as computer, mobile phone, digital camera or personal digital assistant (Personal Digital Assistant, PDA)) data that need to handle, store increase day by day, and memory span required in these information electronic products is also just more and more big.For this size decreases and memory span needs the situation that increases, how manufacturing dimension dwindle, high integration, the memory component that can take into account its quality again is the consistent target of industry.
According to the difference of read/write function, memory can simply be divided into two classes: read-only memory (ReadOnly Memory; ROM) with random access memory (Random Access Memory, RAM).(Random Access Memory is a kind of volatile (volatile) memory RAM), and is widely used in the information electronic product random access memory.Generally speaking, random access memory comprise static RAM (Static Random Access Memory, SRAM) with dynamic random access memory (Dynamic Random Access Memory, DRAM).
Mode according to design, DRAM memory cell normally capacitor of a transistor AND gate constitutes, and DRAM is that electrically charged (Charging) state with electric capacity in the memory cell stores digital signal, that is DRAM utilizes the binary data that is expressed as " 0 " or " 1 " at the electrically charged and neutral of suprabasil capacitor.But because the leakage current of element itself, so be stored in data in the memory cell of DRAM, then must upgrade (Refresh) termly again, and cause power consumption, and after power supply removed, data also can disappear thereupon.
Summary of the invention
In view of this, purpose of the present invention is providing a kind of non-volatility memorizer and manufacture method thereof and method of operation exactly, and by in the memory cell of DRAM charge immersing layer being set, it is non-volatile that it is had, and its manufacturing process is simple, and can reduce cost.
Another object of the present invention provides a kind of non-volatility memorizer and manufacture method and method of operation, utilizes the foundation of the change of capacitance size as the interpretation digital code information, and has the function of DRAM fast access.
The present invention proposes a kind of non-volatility memorizer, has first memory cell, and this first memory cell comprises substrate, the first transistor and transistor seconds.The first transistor is arranged in the substrate, and this first transistor comprises and is arranged at suprabasil first grid and is arranged at first source/drain regions and second source/drain regions in the first grid substrate on two sides respectively.Transistor seconds is arranged in the substrate, this transistor seconds comprises and is arranged at suprabasil second grid, is arranged at the charge immersing layer between second grid and the substrate and is arranged at the 3rd source/drain regions and second source/drain regions in the second grid substrate on two sides respectively that wherein transistor seconds and the first transistor are shared second source/drain regions.
In above-mentioned non-volatility memorizer, the first grid of the first transistor is connected to word line.First source/drain regions of the first transistor is connected to bit line.The 3rd source/drain regions of transistor seconds is for floating, and the second grid of transistor seconds is connected to program line.Stop dielectric layer and tunneling dielectric layer being respectively arranged with between charge immersing layer and the second grid and between charge immersing layer and the substrate.
And in above-mentioned non-volatility memorizer, transistor seconds also can be a plough groove type transistor, and second grid is arranged in the groove of substrate, and charge immersing layer is arranged between second grid and the groove.Stop that dielectric layer is arranged between charge immersing layer and the second grid, tunneling dielectric layer is arranged between charge immersing layer and the groove.
In addition, in above-mentioned non-volatility memorizer, also comprise second memory cell, this second memory cell has the structure identical with first memory cell, and selection transistors share first source/drain regions of selection transistor AND gate first memory cell of second memory cell.
Non-volatility memorizer of the present invention selects transistor to be used for reading store information and the sequencing of traffic bit line end or the information of erasing that electric charge causes that writes.The plough groove type transistor is used for storing and writes or the information of erasing has the function of non-volatile memory.The memory cell structure of the similar DRAM of non-volatility memorizer of the present invention, and, and make memory cell of the present invention have non-volatile characteristic by storage node with the existing DRAM of SONOS (silicon/oxidative silicon/nitrogenize silicon/oxidative silicon/silicon) element (plough groove type transistor) replacement.And the manufacturing process of this kind non-volatility memorizer is simple, can with existing DRAM manufacturing process compatibility, and can reduce cost.
The present invention proposes a kind of method of operation of non-volatility memorizer, this non-volatility memorizer comprises at least: be arranged at suprabasil selection transistor AND gate plough groove type transistor, this selects transistorized first source area to be connected with plough groove type transistor second drain region, transistorized second source area of plough groove type is floated, the transistorized second grid of plough groove type fills up the groove in the substrate, and between groove and second grid, be provided with a charge immersing layer, the method is included in carries out programming operations, with when this memory writes " 1 ", prior to selecting transistorized first drain region to apply first positive voltage, apply second positive voltage in the transistorized second grid of plough groove type, make the transistorized channel region counter-rotating of plough groove type.Then, in selecting transistorized first grid to apply the 3rd positive voltage, make to select transistorized passage to open.Then, make the bias voltage that puts on the transistorized second grid of plough groove type be promoted to the 4th positive voltage, make and select transistorized passage to boost, produce, make electronics can not enter charge immersing layer to avoid the F-N tunneling effect by second positive voltage.Carrying out programming operations,,, applying second positive voltage, making the transistorized channel region counter-rotating of plough groove type in the transistorized second grid of plough groove type prior to the bias voltage of selecting transistorized first drain region to apply 0 volt with when this memory writes " 0 ".Then, in selecting transistorized first grid to apply the 3rd positive voltage, make to select transistorized passage to open.Afterwards, make the bias voltage that puts on the transistorized second grid of plough groove type be promoted to the 4th positive voltage,, make electronics enter charge immersing layer so that the F-N tunneling effect produces by second positive voltage.
In the method for operation of above-mentioned non-volatility memorizer, when carrying out read operation, apply the 5th positive voltage prior to selecting transistorized first drain region, apply the 6th positive voltage in the transistorized second grid of plough groove type.Then, in selecting transistorized first grid to apply the 7th positive voltage, make to select transistorized passage to open.Charge immersing layer has electronics, and when the transistorized second grid of plough groove type applied the 6th positive voltage, the transistorized passage of plough groove type can conducting, and the electric capacity that is brought out is less.Charge immersing layer does not have electronics, when the transistorized second grid of plough groove type applies the 6th positive voltage, and the passage of slot type capacitor meeting conducting, the electric capacity that is brought out is bigger.
In the method for operation of above-mentioned non-volatility memorizer, when carrying out erase operation for use, apply first negative voltage in the transistorized second grid of plough groove type, the electronics in the charge immersing layer is drained in the substrate via the F-N tunneling effect.
In the operator scheme of non-volatility memorizer of the present invention, it utilizes whether there is electronics in the charge immersing layer, and the capacitance size that is caused is judged digital code information.Therefore the interpretation of non-volatility memorizer of the present invention mechanism is also inequality with existing DRAM or flash memory.And, depositing the electronics of charge immersing layer in and be not easy and omit, the end, do not need to upgrade again the action of (Refresh) mutually for non-volatility memorizer of the present invention and existing DRAM.Therefore, current drain is little, can effectively reduce the power loss of whole memory.
The present invention provides a kind of manufacture method of non-volatility memorizer again, and substrate at first is provided, and has formed grid structure in this substrate, and grid structure comprise first grid and be arranged at first grid and substrate between gate dielectric layer.Then, after in the grid structure substrate on two sides, forming first doped region and second doped region, in substrate, form first interlayer insulating film, and remove part first interlayer insulating film, part substrate, to form groove, this groove is separated into the 3rd doped region and the 4th doped region with second doped region.Then, in groove, form tunneling dielectric layer, charge immersing layer and stop dielectric layer, and in substrate, form the second grid that fills up groove.
In the manufacture method of above-mentioned non-volatility memorizer, also be included in the substrate and form second interlayer insulating film and on second interlayer insulating film, to form the bit line that is electrically connected with first doped region.And, in substrate, form in the step of the second grid that fills up groove, also comprise forming the program line that is electrically connected second grid.
The manufacture method of non-volatility memorizer of the present invention, can with existing DRAM manufacturing process compatibility, and manufacturing process is simple, and can reduce cost.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. elaborates.
Description of drawings
Figure 1A and Figure 1B are for illustrating the section of structure of non-volatility memorizer of the present invention respectively.
Fig. 2 A to Fig. 2 E illustrate is the manufacturing process profile of non-volatility memorizer of the present invention.
Fig. 3 A to Fig. 3 C is for being illustrated in the programming operations schematic diagram that non-volatility memorizer of the present invention writes " 1 ".
Fig. 4 A to Fig. 4 C is for being illustrated in the programming operations schematic diagram that non-volatility memorizer of the present invention writes " 0 ".
Fig. 5 A to Fig. 5 C is for being illustrated in non-volatility memorizer read operation schematic diagram of the present invention.
Fig. 6 is for being illustrated in non-volatility memorizer erase operation for use schematic diagram of the present invention.
The simple symbol explanation
A, B: memory cell
100,200: substrate
102,202, PW:P type wellblock
104: select transistor
106: the plough groove type transistor
106a: transistor
108,116,206a: grid
110,204a: gate dielectric layer
112,114,120: source/drain regions
118,218: composite dielectric layer
118a, 218a: tunneling dielectric layer
118b, 218b: charge immersing layer
118c, 218c: stop dielectric layer
122,216: groove
124,224: connector
126, BL: bit line
128, PL: program line
204: dielectric layer
206,220: conductor layer
208,208a, 208b, 210: doped region
212,222: interlayer insulating film
214: mask layer
226: lead
WL: word line
Embodiment
Figure 1A illustrate is the section of structure of the non-volatility memorizer of a preferred embodiment of the present invention.
Please refer to Figure 1A, show storage unit A, the memory cell B of two shared source 112 among the figure.Non-volatility memorizer of the present invention also can use the mode of source 112 to constitute by single memory cell.At this,, in following explanation, only explain at storage unit A because storage unit A is identical with the structure of memory cell B.
Storage unit A is by substrate 100, p type wells district 102, selects transistor 104 and plough groove type transistor 106 to be constituted.
Select transistor 104 to be arranged in the substrate 100.This selects transistor 104 to be made of grid 108, gate dielectric layer 110, source/drain regions 112, source/drain regions 114.
Plough groove type transistor 106 is arranged in the substrate 100.This plough groove type transistor is made of grid 116, composite dielectric layer 118, source/drain regions 114, source/drain regions 120.
Non-volatility memorizer of the present invention selects transistor to be used for reading store information and the sequencing of traffic bit line end or the information of erasing that electric charge causes that writes.The plough groove type transistor is used for storing the information that writes or erase, and has the function of non-volatile memory.And, the memory cell structure of the similar DRAM of non-volatility memorizer of the present invention, by storage node, and make memory cell of the present invention have non-volatile characteristic with the existing DRAM of SONOS (silicon/oxidative silicon/nitrogenize silicon/oxidative silicon/silicon) element (plough groove type transistor) replacement.
Figure 1B illustrate is the section of structure of the non-volatility memorizer of another preferred embodiment of the present invention.In the non-volatility memorizer of the present invention, being used to store and writing or the transistor of the information of erasing, be not limited to the plough groove type transistor, also can be the transistor that is arranged in the substrate 100.In Figure 1B, the identical person with Figure 1A of member gives identical label, and omits its detailed description.
Please refer to Figure 1B, transistor 106a is arranged in the substrate.This transistor 106a is made of grid 116, composite dielectric layer 118, source/drain regions 114, source/drain regions 120.Grid 116 is arranged in the substrate 100.Composite dielectric layer 118 is arranged between grid 116 and the substrate 100.Source/drain regions 114, source/drain regions 120 are arranged at respectively in grid 116 substrate on two sides 100, and its dopant profile for example is the N type.Select transistor 104 and transistor 106a to share source/drain regions 114.
Non-volatility memorizer of the present invention selects transistor to be used for reading store information and the sequencing of traffic bit line end or the information of erasing that electric charge causes that writes.Transistor is used for storing the information that writes or erase, and has the function of non-volatile memory.And, the memory cell structure of the similar DRAM of non-volatility memorizer of the present invention, by storage node, and make memory cell of the present invention have non-volatile characteristic with the existing DRAM of SONOS (silicon/oxidative silicon/nitrogenize silicon/oxidative silicon/silicon) element (plough groove type transistor) replacement.
Fig. 2 A～Fig. 2 E illustrate is the manufacturing process profile of the non-volatility memorizer of the preferred embodiment of the present invention.
Please refer to Fig. 2 A, a substrate 200 is provided, substrate 200 for example is a silicon base, has been formed with p type wells district 202 in this substrate 200.Then, in substrate 200, form dielectric layer 204, conductor layer 206 in regular turn.The material of dielectric layer 204 for example is a silica, and the formation method of dielectric layer 204 for example is a thermal oxidation method.The material of conductor layer 206 for example is the polysilicon that mixes, the formation method of this conductor layer 206 for example be form in the mode of injecting admixture when participating in the cintest or utilize chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer after, carry out the ion implantation step to form it.
Please refer to Fig. 2 B, patterning conductor layer 206 and dielectric layer 204 are to form grid 206a and door dielectric layer 204a.Then, carry out the admixture implantation step, to form doped region 208 and doped region 210 in grid 206a substrate on two sides 200.Wherein, the admixture of injection for example is a N type admixture.
Please refer to Fig. 2 C, after forming interlayer insulating film 212 in the substrate 200, on this interlayer insulating film 212, form one deck patterned mask layer 214.Be that mask removes part interlayer insulating film 212 and part substrate 200 with patterned mask layer 214 then, to form groove 216.Wherein the degree of depth of groove 216 need be dark than the degree of depth of doped region 208, and doped region 208 is separated into doped region 208a and doped region 208b.The material of interlayer insulating film for example is a silica, its formation method for example be with four-ethyl-neighbour-esters of silicon acis (Tetra Ethyl Ortho Silicate, TEOS)/ozone (O
3) be reacting gas source, utilize chemical vapour deposition technique and form it.The material of mask layer 214 for example is a photo anti-corrosion agent material.
Please refer to Fig. 2 D, remove patterned mask layer 214 after, in substrate 200, form tunneling dielectric layer 218a, charge immersing layer 218b in regular turn and stop dielectric layer 218c (composite dielectric layer 218).The material of tunneling dielectric layer 218a for example is a silica, and the formation method of tunneling dielectric layer 218a for example is a thermal oxidation method.The material of charge immersing layer 218b for example is a silicon nitride, and the formation method of charge immersing layer 218b for example is a chemical vapour deposition technique.The material that stops dielectric layer 218c for example is a silica, and the formation method that stops dielectric layer 218c for example is a chemical vapour deposition technique.Certainly, tunneling dielectric layer 218a and stop that dielectric layer 218c also can be other materials similar.The material of charge immersing layer 218b is not limited to silicon nitride, also can be that other can make electric charge be absorbed in material wherein, for example tantalum oxide layer, strontium titanate layer and hafnium oxide layer etc.Then form conductor layer 220 in substrate 200, this conductor layer 220 fills up groove 216, and does not insert part in the groove 216 as the usefulness of program line.The material of conductor layer 220 for example is the polysilicon that mixes, the formation method of this conductor layer 220 for example be form in the mode of injecting admixture when participating in the cintest or utilize chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer after, carry out the ion implantation step to form it.
Please refer to Fig. 2 E, after patterning conductor layer 220 and the composite dielectric layer 218, in form in the substrate 200 another layer by layer between insulating barrier 222, the material of interlayer insulating film 222 for example is a silica, its formation method for example be with four-ethyl-neighbour-esters of silicon acis (Tetra Ethyl Ortho Silicate, TEOS)/ozone (O
3) be reacting gas source, utilize chemical vapour deposition technique and form it.Be electrically connected the connector 224 of doped region 210 with formation among the interlayer insulating film 212 in interlayer insulating film 222 afterwards, and on interlayer insulating film 222, form the lead 226 (bit line) that is electrically connected with connector 224.
The manufacture method of non-volatility memorizer of the present invention, can with existing DRAM manufacturing process compatibility, and manufacturing process is simple, and can reduce cost.
Then, method of operation of the present invention is described.Fig. 3 A to Fig. 3 C is for being illustrated in the programming operations schematic flow sheet that non-volatility memorizer of the present invention writes " 1 ".Fig. 4 A to Fig. 4 C is for being illustrated in the programming operations schematic flow sheet that non-volatility memorizer of the present invention writes " 0 ".Fig. 5 A to Fig. 5 C is for being illustrated in non-volatility memorizer read operation schematic flow sheet of the present invention.Fig. 6 is for being illustrated in non-volatility memorizer erase operation for use schematic flow sheet of the present invention.
At first, illustrate that non-volatility memorizer of the present invention writes the programming operations of " 1 ".
Please refer to Fig. 3 A, applying in bit line BL (select transistor drain district) for example is 3.3 volts voltage, and applying in program line PL (the transistorized grid of plough groove type) for example is 5 volts voltage, and makes the transistorized channel region counter-rotating of plough groove type.
Please refer to Fig. 3 B, applying in word line WL (selecting transistorized grid) for example is 3.3 volts of voltages, make and select transistorized passage to open, so select the electronics in transistor drain district to arrive the plough groove type transistor, and voltage is reduced to about 2.7 volts by 3.3 volts via the transistorized passage of selection.
Please refer to Fig. 3 C, the bias voltage of program line PL (the transistorized grid of plough groove type) is promoted to 10 volts by 5 volts, the voltage of plough groove type transistor channels is promoted to about 7.7 volts by 2.7 volts, produce to avoid the F-N tunneling effect, so electronics can enter charge immersing layer.And make the memory cell program turn to the state of " 1 ".
Then, illustrate that non-volatility memorizer of the present invention writes the programming operations of " 0 ".
Please refer to Fig. 4 A, applying in bit line BL (select transistor drain district) for example is 0 volt voltage, and applying in program line PL (the transistorized grid of plough groove type) for example is 5 volts voltage, and makes the transistorized channel region counter-rotating of plough groove type.
Please refer to Fig. 4 B, applying in word line WL (selecting transistorized grid) for example is 3.3 volts voltage, make and select transistorized passage to open, then select the electronics in transistor drain district to arrive the plough groove type transistor via the transistorized passage of selection, and voltage is 0 volt.
Please refer to Fig. 4 C, the bias voltage of program line PL (the transistorized grid of plough groove type) is promoted to 10 volts by 5 volts, and makes the big pressure reduction of generation between the substrate of plough groove type transistor AND gate, and the F-N tunneling effect is produced.Therefore, electronics can enter charge immersing layer, and makes the memory cell program turn to the state of " 0 ".
The read operation of non-waving property memory of the present invention then, is described.
Please refer to Fig. 5 A, applying in bit line BL (select transistor drain district) for example is 2.5 volts voltage, and applying in program line PL (the transistorized grid of plough groove type) for example is 1 volt voltage.
Then, applying in word line WL (selecting transistorized grid) for example is 3.3 volts voltage, makes to select transistorized passage to open.When charge immersing layer does not have electronics, owing to can make charge immersing layer be the state or the positive electricity condition of sky, and make the P wellblock produce surface counter-rotating (surface inversion), so the passage of slot type capacitor meeting conducting, the electric capacity that is brought out is bigger, shown in Fig. 5 B.When charge immersing layer has electronics, because the electronics that stores can make charge immersing layer be the negative electricity state, and make the P wellblock produce the surface to lack (surface depletion), so the passage of slot type capacitor can conducting, the electric capacity that is brought out is less, shown in Fig. 5 C.Because total charge dosage is the negative transistorized pathway closure of plough groove type in the charge immersing layer, the electric capacity that is brought out is less; And in the charge immersing layer the slightly positive transistorized passage of plough groove type of total charge dosage open and the electric capacity that brought out bigger, so can judge that the digital code information that is stored in this memory cell is " 1 " or " 0 " by the capacitance size of being brought out.
The erase operation for use of non-waving property memory of the present invention then, is described.
Please refer to Fig. 6, for example applying in program line PL (the transistorized grid of plough groove type) is-10 volts voltage, and the electronics in the charge immersing layer is drained in the substrate via the F-N tunneling effect.And the data in the memory cell are erased.
In the operator scheme of non-volatility memorizer of the present invention, it utilizes whether there is electronics in the charge immersing layer, and the capacitance size that is caused is judged digital code information.Therefore the interpretation of non-volatility memorizer of the present invention mechanism is also inequality with existing DRAM or flash memory.And, deposit the electronics of charge immersing layer in and be not easy and omit, therefore non-volatility memorizer of the present invention is compared the action that does not need to upgrade again (Refresh) with existing DRAM.Therefore, current drain is little, can effectively reduce the power loss of whole memory.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (26)
1, a kind of non-volatility memorizer has one first memory cell, and this first memory cell comprises:
One substrate;
One the first transistor, this first transistor are arranged in this substrate, and this first transistor comprises:
One first grid is arranged in this substrate;
One first source/drain regions and one second source/drain regions are arranged at respectively in this substrate of these first grid both sides; And
One transistor seconds, this transistor seconds are arranged at by this first transistor, and this transistor seconds comprises:
One second grid is arranged in this substrate;
One charge immersing layer is arranged between this second grid and this substrate; And
One the 3rd source/drain regions and this second source/drain regions are arranged at respectively in this substrate of these second grid both sides, and wherein this transistor seconds and this first transistor are shared this second source/drain regions.
2, non-volatility memorizer as claimed in claim 1 comprising a word line, connects this first grid of this first transistor.
3, non-volatility memorizer as claimed in claim 1 comprising a bit line, connects this first source/drain regions of this first transistor.
4, non-volatility memorizer as claimed in claim 1 comprising a program line, connects this second grid of this transistor seconds.
5, non-volatility memorizer as claimed in claim 1, comprising:
One stops dielectric layer, is arranged between this charge immersing layer and this second grid; And
One tunneling dielectric layer is arranged between this charge immersing layer and this substrate.
6, non-volatility memorizer as claimed in claim 1, wherein the material of this charge immersing layer comprises silicon nitride.
7, non-volatility memorizer as claimed in claim 1, wherein this material that stops dielectric layer and this tunneling dielectric layer comprises silica.
8, non-volatility memorizer as claimed in claim 1, wherein the material of this first grid and this second grid comprises doped polycrystalline silicon.
9, non-volatility memorizer as claimed in claim 1, wherein this transistor seconds is a plough groove type transistor, this second grid is arranged in the groove of this substrate, and this charge immersing layer is arranged between this second grid and this groove.
10, non-volatility memorizer as claimed in claim 9, comprising:
One stops dielectric layer, is arranged between this charge immersing layer and this second grid; And
One tunneling dielectric layer is arranged between this charge immersing layer and this groove.
11, non-volatility memorizer as claimed in claim 1, wherein also comprise one second memory cell, this second memory cell has the structure identical with this first memory cell, and the first transistor of the first transistor of this second memory cell and this first memory cell is shared this first source/drain regions.
12, a kind of method of operation of non-volatility memorizer, this non-volatility memorizer comprises at least: be arranged at a selection transistor AND gate one plough groove type transistor in the substrate, this selects transistorized one first source area to be connected with this plough groove type transistor one second drain region, transistorized one second source area of this plough groove type is floated, the transistorized second grid of this plough groove type fills up the groove in this substrate, and be provided with a charge immersing layer between this groove and this second grid, this method comprises:
Carrying out programming operations,, comprising with when this memory writes " 1 ":
Apply one first positive voltage in transistorized this first drain region of this selection, apply one second positive voltage, make the transistorized channel region counter-rotating of this plough groove type in transistorized this second grid of this plough groove type;
Apply one the 3rd positive voltage in transistorized this first grid of this selection, make this select transistorized passage to open; And
The bias voltage that makes this plough groove type transistor put on this second grid is promoted to one the 4th positive voltage by this second positive voltage, and the transistorized passage of this plough groove type is boosted, and produces to avoid the F-N tunneling effect, makes electronics can not enter this charge immersing layer; And
Carrying out programming operations,, comprising with when this memory writes " 0 ":
Apply 0 volt bias voltage in transistorized this first drain region of this selection, apply this second positive voltage, make the transistorized channel region counter-rotating of this plough groove type in transistorized this second grid of this plough groove type;
Apply the 3rd positive voltage in transistorized this first grid of this selection, make this select transistorized passage to open; And
The bias voltage that makes this plough groove type transistor put on this second grid is promoted to the 4th positive voltage by this second positive voltage, so that the F-N tunneling effect produces, makes electronics enter this charge immersing layer.
13, the method for operation of non-volatility memorizer as claimed in claim 12 wherein when carrying out read operation, comprising:
Apply one the 5th positive voltage in transistorized this first drain region of this selection, apply one the 6th positive voltage in transistorized this second grid of this plough groove type; And
Apply one the 7th positive voltage in transistorized this first grid of this selection, make this select transistorized passage to open.
14, the method for operation of non-volatility memorizer as claimed in claim 12 wherein when carrying out erase operation for use, comprising:
Apply one first negative voltage in transistorized this second grid of this plough groove type, the electronics in this charge immersing layer is drained in this substrate via the F-N tunneling effect.
15, the method for operation of non-volatility memorizer as claimed in claim 12, wherein this first positive voltage, the 3rd positive voltage and the 7th positive voltage are 3.3 volts.
16, the method for operation of non-volatility memorizer as claimed in claim 12, wherein this second positive voltage is 5 volts.
17, the method for operation of non-volatility memorizer as claimed in claim 12, wherein the 4th positive voltage is 10 volts.
18, the method for operation of non-volatility memorizer as claimed in claim 12, wherein the 5th positive voltage is 2.5 volts.
19, the method for operation of non-volatility memorizer as claimed in claim 12, wherein the 6th positive voltage is 1 volt.
20, the method for operation of non-volatility memorizer as claimed in claim 12, wherein this first negative voltage is-10 volts.
21, a kind of manufacture method of non-volatility memorizer, this method comprises:
One substrate is provided, has formed a grid structure in this substrate, this grid structure comprise a first grid and be arranged at this first grid and this substrate between a gate dielectric layer;
In this substrate of these grid structure both sides, form one first doped region and one second doped region;
In this substrate, form one first interlayer insulating film;
Remove this first interlayer insulating film of part, this substrate of part, to form a groove, this groove is separated into one the 3rd doped region and one the 4th doped region with this second doped region;
Formation one tunneling dielectric layer, a charge immersing layer and stop dielectric layer in this groove; And
In this substrate, form a second grid that fills up this groove.
22, the manufacture method of non-volatility memorizer as claimed in claim 21 also comprises:
In this substrate, form one second interlayer insulating film; And
On this second interlayer insulating film, form a bit line that is electrically connected with this first doped region.
23, the manufacture method of non-volatility memorizer as claimed in claim 21 wherein forms in this substrate in the step of this second grid that fills up this groove, also comprises forming a program line that is electrically connected this second grid.
24, the manufacture method of non-volatility memorizer as claimed in claim 21, wherein the material of this charge immersing layer comprises silicon nitride.
25, the manufacture method of non-volatility memorizer as claimed in claim 21, wherein this material that stops dielectric layer and this tunneling dielectric layer comprises silica.
26, the manufacture method of non-volatility memorizer as claimed in claim 21, wherein the material of this first grid and this second grid comprises doped polycrystalline silicon.
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| CNB2004100897244A CN100438038C (en) | 2004-11-02 | 2004-11-02 | Non-volatile memory and its manufacturing method and operating method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106653762A (en) * | 2015-10-30 | 2017-05-10 | 联华电子股份有限公司 | Non-volatile memory and manufacture method therefor |
| CN109979943A (en) * | 2017-12-28 | 2019-07-05 | 联华电子股份有限公司 | Semiconductor element and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5912842A (en) * | 1995-11-14 | 1999-06-15 | Programmable Microelectronics Corp. | Nonvolatile PMOS two transistor memory cell and array |
| US6661053B2 (en) * | 2001-12-18 | 2003-12-09 | Infineon Technologies Ag | Memory cell with trench transistor |
| KR100446308B1 (en) * | 2002-09-11 | 2004-09-01 | 삼성전자주식회사 | Non-volatile memory device having select transistor structure and SONOS(Silicon-Oxide-Nitride-Oxide-Silicon) cell structure and method for fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106653762A (en) * | 2015-10-30 | 2017-05-10 | 联华电子股份有限公司 | Non-volatile memory and manufacture method therefor |
| CN106653762B (en) * | 2015-10-30 | 2020-04-21 | 联华电子股份有限公司 | Non-volatile memory and manufacturing method thereof |
| CN109979943A (en) * | 2017-12-28 | 2019-07-05 | 联华电子股份有限公司 | Semiconductor element and its manufacturing method |
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