CN1767594A

CN1767594A - Sum of absolute difference circuit

Info

Publication number: CN1767594A
Application number: CN 200410086991
Authority: CN
Inventors: 杨行健; 陈晋明; 袁论贤
Original assignee: Novatek Microelectronics Corp
Current assignee: Novatek Microelectronics Corp
Priority date: 2004-10-27
Filing date: 2004-10-27
Publication date: 2006-05-03
Anticipated expiration: 2024-10-27
Also published as: CN100384214C

Abstract

This invention relates to an absolute sum of absolute difference (SAD) circuit including an absolute difference circuit, a first adder, a first buffer storage and a first selection circuit, among which, the absolute difference circuit receives a first datum and a second datum and outputs the absolute difference data: ADi.j=lPMi.j-PSi.jl, the first adder receives and adds the total absolute difference data and first accumulated data to be output to a first add-sum value, the first buffer storage receives and locks the first sum value according to the first preset time sequence to output a first SAD data and the first selection circuit receives and selects the first SAD data or zero to be output as the first accumulated data.

Description

Absolute difference and circuit

Technical field

The present invention relates to a kind of mobile estimation (motion estimation) circuit, and particularly relate to a kind of absolute difference and (sum of absolute difference is hereinafter to be referred as SAD) circuit.

Background technology

Generally speaking, the data of digital video (data are data, below all be called data) amount is very huge usually.In order to save the space that stores video signal data, and the transmitting bandwidth when saving the transmission video signal data, therefore must carry out data compression to video signal data.Data compression normally removes redundant information in the video signal data and reaches the purpose of data reduction.For example, if a last picture (or being called picture frame frame) and ensuing picture be similar each other, can keep first picture and thereafter in each picture identical part remove (information that only keeps part inequality gets final product).Therefore, can reduce the data volume of digital video in a large number.For example MPEG video signal compression standard is the video encoding method of normal use.

When desire is made comparisons present picture and desire comparison picture, present picture can be cut into a plurality of image blocks usually.Typical image block size is 16 * 16 or 8 * 8.Then, select one of them image block (being called present image block) back to compare in desire whether search (search) has similar image block in the picture one by one.Relatively in the picture, the position identical with present image block is the center in desire, to around the zone that constituted of a preset distance be called and search window (search window).Aforesaid preset distance promptly is called search area (search range).In searching window, appoint and get relatively image block (size with image block is identical at present) and do with present image block and compare of a desire, so that find out the most similar image block.This is to move estimates.

When more present image block and desire comparison image block, normally the two is carried out pixel to the absolute difference of pixel and (SAD) computing.In other words, promptly be to take absolute value after relatively all corresponding pixel (pixel) data subtract in twos mutually in the image block with present image block and desire, then the absolute difference of each pixel data added the General Logistics Department and promptly obtain present image block and the desire comparison image block sad value between the two.Can judge relatively the two similarity degree of image block of present image block and desire by the size of sad value.

Yet existing known technology must will have all buffer reset alls (reset) in the known circuit now after computing finishes when carrying out the SAD computing, so that the carrying out of SAD computing next time.For the mobile estimation of SAD computings in a large number, intact promptly need the replacement of each SAD computing once will influence efficient.

For recently H.264 standard revise and enlarge 8 * 16,16 * 8,8 * 4,4 * 8 and 4 * 4 image block, present known techniques and can't accomplishing.Moreover existing known technology can only be done computing at 16 * 16 or 8 * 8 image block individually, and can't support that tree moves estimation.

This shows that above-mentioned existing absolute difference and circuit obviously still have inconvenience and defective, and demand urgently further being improved in structure and use.In order to solve the problem that absolute difference and circuit exist, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.

Because the defective that above-mentioned existing absolute difference and circuit exist, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of absolute difference and the circuit of founding a kind of new structure, can improve general existing absolute difference and circuit, make it have more practicality.Through constantly research, design, and after studying sample and improvement repeatedly, create the present invention who has practical value finally.

Summary of the invention

The objective of the invention is to, overcome the defective that existing absolute difference and circuit exist, and provide a kind of new absolute difference and circuit, technical problem to be solved is to make it need input once image block data and desire comparison image block data at present, can be in proper order or calculate the sad value of different images square sizes such as 16 * 16,16 * 8,8 * 16,8 * 8,8 * 4,4 * 8,4 * 4 abreast.Simultaneously, absolute difference provided by the present invention and circuit need not reset (reset) can proceed SAD computing next time, therefore can increase operation efficiency, thereby be suitable for practicality more.

The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of absolute difference and circuit that the present invention proposes, it comprises: an absolute difference (absolute difference) circuit, and in order to receive one first data PM _{I, j}And one second data PS _{I, j}, and export an absolute difference audio data AD _{I, j}, PM wherein _{I, j}, PS _{I, j}With AD _{I, j}Represent i row (row) j this first data, these second data and this absolute difference data respectively, and AD _{I, j}=| PM _{I, j}-PS _{I, j}|, wherein i and j are all the integer more than or equal to 0; One first adder in order to receiving and to add up these absolute difference data and one first cumulative data, and will add overall result and be output as one first and add total value; One first buffer, in order to receive according to one first scheduled timing and breech lock this first add output one first absolute difference and (sum of absolute difference) data after the total value; And one first select circuit, in order to receiving and to select this first absolute difference and data and a remainder according to one of them, and data selected is output as this first cumulative data, and wherein the value of this remainder certificate is 0.

The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.

Aforesaid absolute difference and circuit, wherein said absolute difference circuit comprises: a subtracter, in order to receive these first data and this second data and the two subtracted each other back output one difference; One second buffer is coupled to this subtracter, in order to comply with one second this difference of scheduled timing breech lock; One complementary circuit is coupled to this second buffer, in order to produce the complement code of this difference; And one second select circuit, is coupled to this second buffer and this complementary circuit, in order to select the positive number person to be output as this absolute difference data in the complement code of this difference that is received and this difference in the two.

Aforesaid absolute difference and circuit, wherein said complementary circuit comprises: an inverter, in order to reception and this difference is anti-phase, to export an anti-phase difference; And a second adder, be coupled to this inverter, in order to receive and to add up this anti-phase difference and one one data to export the complement code of this difference, wherein the value of these one data is 1.

Aforesaid absolute difference and circuit, wherein said first absolute difference and data are to be AD _{I, j}To AD _{I+3, j+3}The accumulation result of 4 * 4 arrays.

Aforesaid absolute difference and circuit, wherein said first buffer do not have replacement (reset) function.

Aforesaid absolute difference and circuit, it more comprises at least one summation circuit,, and adds up again according to scheduled timing exporting one second absolute difference and data in order to receive and add up this first absolute difference and data.

Aforesaid absolute difference and circuit, wherein said summation circuit comprises: one the 3rd adder in order to receiving and to add up this first absolute difference and data and one the 3rd cumulative data, and will add overall result and be output as one the 3rd and add total value; One the 3rd buffer is exported these second absolute difference and data after adding total value according to reception of one the 3rd scheduled timing and breech lock the 3rd; And one the 3rd select circuit, in order to receiving and to select this second absolute difference and data and this remainder according to one of them, and data selected is output as the 3rd cumulative data.

Aforesaid absolute difference and circuit, wherein said first absolute difference and data are to be AD _{I, j}To AD _{I+3, j+3}The accumulation result of 4 * 4 arrays and AD _{I, j+4}To AD _{I+3, j+7}The accumulation result of 4 * 4 arrays the two one of, and this second absolute difference and data are to be AD _{I, j}To AD _{I+3, j+7}The accumulation result of 4 * 8 arrays.

Aforesaid absolute difference and circuit, wherein said first absolute difference and data are to be AD _{I, j}To AD _{I+3, j+3}And AD _{I+4, j}To AD _{I+7, j+3}The two one of the accumulation result of 4 * 4 arrays, and this second absolute difference and data are to be AD _{I, j}To AD _{I+7, j+3}The accumulation result of 8 * 4 arrays.

Aforesaid absolute difference and circuit, wherein said first absolute difference and data are to be AD _{I, j}To AD _{I+3, j+3}, AD _{I+4, j}To AD _{I+7, j+3}, AD _{I, j+4}To AD _{I+3, j+7}And AD _{I+4, j+4}To AD _{I+7, j+7}The accumulation result of one of them 4 * 4 array, and this second absolute difference and data are to be AD _{I, j}To AD _{I+7, j+7}The accumulation result of 8 * 8 arrays.

Aforesaid absolute difference and circuit, wherein said first absolute difference and data are to be AD _{I, j}To AD _{I+3, j+3}, AD _{I+4, j}To AD _{I+7, j+3}, AD _{I, j+4}To AD _{I+3, j+7}, AD _{I+4, j}+ 4 to AD _{I+7, j+7}, AD _{I, j+8}To AD _{I+3, j+11}, AD _{I+4, j+8}To AD _{I+7, j+11}, AD _{I, j+12}To AD _{I+3, j+15}And AD _{I+4, j+12}To AD _{I+7, j+15}The accumulation result of one of them 4 * 4 array, and this second absolute difference and data are to be AD _{I, j}To AD _{I+7, j+15}The accumulation result of 8 * 16 arrays.

Aforesaid absolute difference and circuit, wherein said first absolute difference and data are to be AD _{I, j}To AD _{I+3, j+3}, AD _{I+4, j}To AD _{I+7, j+3}, AD _{I, j+4}To AD _{I+3, j+7}, AD _{I+4, j+4}To AD _{I+7, j+7}, AD _{I+8, j}To AD _{I+11, j+3}, AD _{I+12, j}To AD _{I+15, i+3}, AD _{I+8, j+4}To AD _{I+11, j+7}And AD _{I+12, j+4}To AD _{I+15, j+7}The accumulation result of one of them 4 * 4 array, and this second absolute difference and data are to be AD _{I, j}To AD _{I+15, j+7}The accumulation result of 16 * 8 arrays.

Aforesaid absolute difference and circuit, wherein said first absolute difference and data are to be AD _{I, j}To AD _{I+3, j+3}, AD _{I+4, j}To AD _{I+7, j+3}, AD _{I, j+4}To AD _{I+3, j+7}, AD _{I+4, j+4}To AD _{I+7, j+7}, AD _{I+8, j}To AD _{I+11, j+3}, AD _{I+12, j}To AD _{I+15, j+3}, AD _{I+8, j+4}To AD _{I+11, j+7}, AD _{I+12, j+4}To AD _{I+15, j+7}, AD _{I, j+8}To AD _{I+3, j+11}, AD _{I+4, j+8}To AD _{I+7, j+11}, AD _{I, j+12}To AD _{I+3, j+15}, AD _{I+4, j+12}To AD _{I+7, j+15}, AD _{I+8, j+8}To AD _{I+11, j+11}, AD _{I+12, j+8}To AD _{I+15, j+11}, AD _{I+8, j+12}To AD _{I+11, j+15}And AD _{I+12, j+12}To AD _{I+15, j+15}The accumulation result of one of them 4 * 4 array, and this second absolute difference and data are to be AD _{I, j}To AD _{I+15, j+15}The accumulation result of 16 * 16 arrays.

Aforesaid absolute difference and circuit, it more comprises: one the 4th buffer, in order to receive and this first adds total value to export one the 3rd absolute difference and data according to one the 4th scheduled timing breech lock; And one the 4th select circuit, be coupled between this absolute difference circuit and this first adder, and connect the 4th buffer, in order to receive and to select these absolute difference data, the 3rd absolute difference and data and this remainder to be sent to this first adder so that carry out add operation with this first cumulative data according to one of them.

Aforesaid absolute difference and circuit, wherein said first absolute difference and data are to be AD _{I, j}To AD _{I+3, j+3}, AD _{I+4, j}To AD _{I+7, j+3}, AD _{I, j+4}To AD _{I+3, j+7}, AD _{I+4, j+4}To AD _{I+7, j+7}, AD _{I+8, j}To AD _{I+11, j+3}, AD _{I+12, j}To AD _{I+15, j+3}, AD _{I+8, j+4}To AD _{I+11, j+7}, AD _{I+12, j+4}To AD _{I+15, j+7}, AD _{I, j+8}To AD _{I+3, j+11}, AD _{I+4, j+8}To AD _{I+7, j+11}, AD _{I, j+12}To AD _{I+3, j+15}, AD _{I+4, j+12}To AD _{I+7, j+15}, AD _{I+8, j+8}To AD _{I+11, j+11}, AD _{I+12, j+8}To AD _{I+15, j+11}, AD _{I+8, j+12}To AD _{I+11, j+15}And AD _{I+12, j+12}To AD _{I+15, j+15}The accumulation result of one of them 4 * 4 array, and the 3rd absolute difference and data are to be AD _{I, j}To AD _{I+7, j+7}, AD _{I+8, j}To AD _{I+15, j+7}, AD _{I, j+8}To AD _{I+7, j+15}And AD _{I+8, j+8}To AD _{I+15, j+15}The accumulation result of one of them 8 * 8 array.

Aforesaid absolute difference and circuit, it more comprises: a slender acanthopanax musical instruments used in a Buddhist or Taoist mass in order to receiving and to add up the 3rd absolute difference and data and one the 5th cumulative data, and will add overall result and be output as a slender acanthopanax total value; One the 5th buffer is exported one the 4th absolute difference and data in order to receive also according to one the 5th scheduled timing after this slender acanthopanax total value of breech lock; And one the 5th select circuit, in order to receiving and to select the 4th absolute difference and data and this remainder according to one of them, and data selected is output as the 5th cumulative data.

Aforesaid absolute difference and circuit, wherein said the 4th absolute difference and data are to be AD _{I, j}To AD _{I+7, j+15}And AD _{I+8, j}To AD _{I+15, j+15}The accumulation result of one of them 8 * 16 array.

Aforesaid absolute difference and circuit, wherein said the 4th absolute difference and data are to be AD _{I, j}To AD _{I+15, j+7}And AD _{I, j+8}To AD _{I+15, j+15}The accumulation result of one of them 16 * 8 array.

Aforesaid absolute difference and circuit, wherein said the 4th absolute difference and data are to be AD _{I, j}To AD _{I+15, j+15}The accumulation result of 16 * 16 arrays.

Aforesaid absolute difference and circuit, wherein said first data and this second data are respectively present image block data and desire compares the image block data.

The present invention compared with prior art has tangible advantage and beneficial effect.By above technical scheme as can be known, the invention relates to a kind of absolute difference and circuit, comprise absolute difference (absolute difference) circuit, first adder, first buffer and the first selection circuit.The absolute difference circuit receives the first data PM _{I, j}And the second data PS _{I, j}, and output absolute difference audio data AD _{I, j}=| PM _{I, j}-PS _{I, j}|.First adder receives and adds up the absolute difference data and first cumulative data, and will add overall result and be output as first and add total value.First buffer is exported first absolute difference and (SAD, sum of absolute difference) data after adding total value according to reception of first scheduled timing and breech lock first.First selects the circuit reception and selects first absolute difference and data or " 0 ", and data selected is output as first cumulative data.

By technique scheme, the absolute difference of special construction of the present invention and circuit, only need input once at present the image block data compare the image block data with desire, can be in proper order or calculate the sad value of different images square sizes such as 16 * 16,16 * 8,8 * 16,8 * 8,8 * 4,4 * 8,4 * 4 abreast.Simultaneously, absolute difference provided by the present invention and circuit need not reset (reset) can proceed SAD computing next time, therefore can increase operation efficiency.It has above-mentioned many advantages and practical value, and in like product, do not see have similar structural design to publish or use and really genus innovation, no matter it structurally or bigger improvement all arranged on the function, have large improvement technically, and produced handy and practical effect, and more existing absolute difference and circuit have the multinomial effect of enhancement, thereby are suitable for practicality more, really are a new and innovative, progressive, practical new design.

Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by a plurality of preferred embodiments, and conjunction with figs., be described in detail as follows.

Description of drawings

Fig. 1 is a kind of absolute difference and the circuit block diagram that illustrates according to a preferred embodiment of the present invention.

Fig. 2 A illustrates the graph of a relation that present image block and desire comparison image block carry out the absolute difference computing according to preferred embodiment of the present invention.

Fig. 2 B is the sequential schematic of a kind of 4 * 4 pixel square serial arrangement of illustrating according to a preferred embodiment of the present invention.

Fig. 3 is another kind of absolute difference and the circuit block diagram that illustrates according to preferred embodiment of the present invention.

Fig. 4 is another absolute difference and the circuit block diagram that illustrates according to preferred embodiment of the present invention.

110,310,410: absolute difference (absolute difference) circuit

111: subtracter

112,114: image block data and desire compare the difference of image block data at present

113, REG1～REG11: buffer

115: complementary circuit

116: complement code

117,320,420,440, SEL1: select circuit

118: inverter

119,430, ADD1: adder

121: cumulative data

122,322: add total value

AD: absolute difference data

PM: present image block data

PS: desire is the image block data relatively

SAD1～SAD11: absolute difference and (sum of abso lute difference) data

SUM2～SUM11: summation circuit

Embodiment

Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to absolute difference and its embodiment of circuit, structure, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.

Seeing also shown in Figure 1ly, is a kind of absolute difference and the circuit block diagram that illustrates according to a preferred embodiment of the present invention.As shown in Figure 1, first data (following will with the present image block data instance) PM and second data (following will with desire image block data instance relatively) PS is respectively present image block and relatively image block pixel data serial separately of desire.Absolute difference (absolute difference) circuit 110 receives relatively image block data PS of present image block data PM and desire, and output absolute difference audio data AD, makes AD=|PM-PS|.

Above-mentioned absolute difference circuit 110 can be implemented with reference to present embodiment.At first receive present image block data PM and desire comparison image block data PS and the two is subtracted each other back output difference 112 with subtracter 111.Buffer 113 is coupled to subtracter 111, with according to scheduled timing breech lock difference 112 and export difference 114.Complementary circuit 115 is coupled to buffer 113, produces the complement code 116 of difference with foundation difference 114.Select circuit 117 to be coupled to buffer 113 and complementary circuit 115, to select positive number to be output as the absolute difference audio data AD in the two in the complement code 116 of difference 114 that is received and difference.

Above-mentioned this complementary circuit for example comprises inverter 118 and adder 119.Inverter 118 receives and difference 114 is anti-phase.Adder 119 is coupled to inverter 118, with receive after anti-phase difference 114 and with the complement code 116 of " 1 " addition and output difference 114.

Adder ADD1 receives and adds up absolute difference audio data AD and cumulative data 121, and will add overall result and be output as and add total value 122.Buffer REG1 receives according to scheduled timing and breech lock adds total value 122 back output absolute difference and (sum of absolute difference) data SAD1.Select circuit SEL1 to receive and selection absolute difference and data SAD1 or " 0 ", and data selected is output as cumulative data 121.

When beginning to produce first absolute difference audio data AD, select circuit SEL1 to select " 0 " to be sent to adder ADD1.Even this moment buffer REG1 breech lock adder AD+0 that ADD1 exports operation result.Therefore, buffer REG1 must not have the result that function of reset can be noted down the SAD computing.In other words, no matter the content of the original lock bolt of buffer REG1 lock why, select circuit SEL1 to select " 0 " to be sent to adder ADD1 can to make the correct breech lock of the first stroke absolute difference audio data AD in buffer REG1 and must not remove its content in advance when cooperating.Therefore, the processing time of replacement buffer REG1 can be saved, but function of reset can be reached.

At this, suppose the sad value of buffer REG1 in order to temporary 4 * 4 pixels.Fig. 2 A is the graph of a relation that carries out the absolute difference computing according to present image block and desire comparison image block shown in the preferred embodiment of the present invention.Please consult simultaneously shown in Fig. 1 and Fig. 2 A, present image block data PM and desire that absolute difference circuit 110 receives serial respectively compare image block data PS.At this, the order of image block data for example is PM at present _{I, j}～PM _{I+3, j}, PM _{I, j+1}～PM _{I+3, j+1}, PM _{I, j+2}～PM _{I+3, j+2}PM then _{I, j+3}～PM _{I+3, j+3}In like manner, the order of desire comparison image block data for example is PS _{I, j}～PS _{I+3, j}, PS _{I, j+1}～PS _{I+3, j+1}, PS _{I, j+2}～PS _{I+3, j+2}PS then _{I, j+3}～PS _{I+3, j+3} Absolute difference circuit 110 receive present image block data PM and desire relatively behind the image block data PS promptly according to formula AD _{I, j}=| PM _{I, j}-PS _{I, j}| produce the absolute difference audio data AD of series form in regular turn _{I, j}～AD _{I+3, j+3}

When producing the first stroke absolute difference audio data AD _{I, j}The time, select circuit SEL1 to select " 0 " to be sent to adder ADD1.This seasonal buffer REG1 breech lock adder AD that ADD1 exports _{I, j}+ 0 operation result.When absolute difference circuit 110 produces second absolute difference audio data AD _{I+1, j}The time, the data SAD1 that order selects circuit SEL1 to select buffer REG1 to be exported (is AD _{I, j}) be sent to adder ADD1.Make buffer REG1 breech lock adder AD that ADD1 exports then _{I, j}+ AD _{I+1, j}Operation result.By that analogy, produce the finishing touch absolute difference audio data AD of 4 * 4 pixels when absolute difference circuit 110 _{I+3, j+3}The time, the data SAD1 that order is selected circuit SEL1 to select buffer REG1 and exported (is AD this moment _{I, j}+ ... + AD _{I+2, j+3}) be sent to adder ADD1.Make buffer REG1 breech lock adder AD that ADD1 exports then _{I, j}+ ... + AD _{I+2, j+3}+ AD _{I+3, j+3}Operation result.Promptly finish the SAD computing of one 4 * 4 pixel this moment.

Yet the present invention can provide the SAD operation values of multiple image block size simultaneously, and is not limited to 4 * 4 pixel sizes in the foregoing description.Therefore present embodiment more more couples many group summation circuit SUM2～SUM11 at the output of buffer REG1, in order to receiving 4 * 4 pixel sad values (being absolute difference and data SAD1) that computing is finished, and institute's absolute difference that receives and data SAD1 absolute difference and the data with the image block size of exporting its desire calculating that add up separately.For example, summation circuit SUM2～SUM11 respectively in order to 4 * 8 (left sides) of adding up, 4 * 8 (right sides), 8 * 4 (on), 8 * 4 (descending), 8 * 8,8 * 16 (left sides), 8 * 16 (right sides), 16 * 8 (on), the absolute difference and the data SAD2～SAD11 of 16 * 8 (descending) and 16 * 16 pixel square sizes, and add up again according to scheduled timing separately.

Allly have the knack of this skill person and should know, the visual actual needs of present embodiment and determine the number of summation circuit.For example, if the designer only need calculate the absolute difference and the data of 4 * 4,8 * 8 and 16 * 16 pixel square sizes simultaneously, then can omit summation circuit SUM2～SUM5 and SUM7～SUM10 in Fig. 1 circuit.Perhaps, if the designer only need calculate the absolute difference and the data of 8 * 8 pixel square sizes, then can omit summation circuit SUM2～SUM11 in Fig. 1 circuit, a sequential that needs to revise selection circuit SEL1 selection " 0 " in the foregoing description can make buffer REG1 export the absolute difference and the data of 8 * 8 pixel square that added up.The result of above-mentioned various modifications also belongs to category of the present invention.

In the present embodiment, summation circuit SUM2～SUM11 for example is similar circuit, is the representative explanation with summation circuit SUM11 only therefore.Summation circuit SUM11 for example comprises adder, buffer and selects circuit that its operation is similar in appearance to adder ADD1, buffer REG1 and select circuit SEL1, so do not give unnecessary details at this.Wherein, the order of the absolute difference that received of summation circuit SUM11 and data SAD1 (referring to finish the SAD computing of 4 * 4 pixels) is shown in Fig. 2 B.

Seeing also shown in Fig. 2 B, is the sequential schematic according to a kind of 4 * 4 pixel square serial arrangement shown in a preferred embodiment of the present invention.Each grid is represented the absolute difference and the data (for example being calculated acquisition by the output of absolute difference circuit 110 among Fig. 1) of one 4 * 4 pixel square among the figure, and the numeral in the grid produces the order of these data.Therefore, for example summation circuit SUM6 according to this order receive one by one and the absolute difference and the data of the 1st～4 4 * 4 pixel square that add up earlier, to obtain the absolute difference and the data of the first stroke 8 * 8 pixel square; Continue to receive the absolute difference and the data of the 5th～8 4 * 4 pixel square that also add up again then, with absolute difference and the data that obtain second 8 * 8 pixel square; By that analogy, continue the absolute difference and the data of the reception and the 13rd～16 4 * 4 pixel square that add up again, to obtain the absolute difference and the data of the 4th 8 * 8 pixel square.At the same time, summation circuit SUM11 also receives simultaneously and the absolute difference and the data of the 1st～16 4 * 4 pixel square that add up one by one, thereby obtains the absolute difference and the data of 16 * 16 pixel square.

The absolute difference and the data of several different images square sizes can be provided in the shortest time in the foregoing description simultaneously.If consider circuit area, then the present invention can apply with reference to following embodiment.

Seeing also shown in Figure 3ly, is another kind of absolute difference and the circuit block diagram that illustrates according to preferred embodiment of the present invention.As shown in Figure 3, absolute difference circuit 310 receives present image block data PM and desire compares image block data PS, and output absolute difference audio data AD.At this, absolute difference circuit 310, adder ADD1, buffer REG1 and selection circuit SEL1 are for example identical with absolute difference circuit 110, adder ADD1, buffer REG1 and the selection circuit SEL1 of Fig. 1 in the previous embodiment respectively, so do not give unnecessary details at this.

See also shown in Figure 3ly, select circuit 320 to be coupled between absolute difference circuit 310 and the adder ADD1.At this, suppose the sad value of buffer REG1 in order to temporary 4 * 4 pixels.The present invention can provide the SAD operation values of multiple image block size simultaneously, and is not limited to 4 * 4 pixel sizes in the foregoing description.Therefore present embodiment more more couples many group buffer REG2～REG11 at the output of adder ADD1, in order to receiving 4 * 4 pixel sad values (being absolute difference and data SAD1) that computing is finished, and institute's absolute difference that receives and data SAD1 absolute difference and the data with the image block size of exporting its desire calculating that add up separately.For example, buffer REG2～REG11 respectively in order to 4 * 8 (left sides) of adding up, 4 * 8 (right sides), 8 * 4 (on), 8 * 4 (descending), 8 * 8,8 * 16 (left sides), 8 * 16 (right sides), 16 * 8 (on), the absolute difference and the data SAD2～SAD11 of 16 * 8 (descending) and 16 * 16 pixel square sizes, and add up again according to scheduled timing separately.

Allly have the knack of this skill person and should know, the visual actual needs of present embodiment and determine the number of buffer.For example, if the designer only need calculate the absolute difference and the data of 4 * 4,8 * 8 and 16 * 16 pixel square sizes simultaneously, then can omit buffer REG2～REG5 and REG7～REG10 in Fig. 1 circuit.Perhaps, if the designer only need calculate the absolute difference and the data of 8 * 8 pixel square sizes, then can omit buffer road REG 2～REG11 in Fig. 1 circuit, a sequential that needs to revise selection circuit SEL1 selection " 0 " can make buffer REG1 export the absolute difference and the data of 8 * 8 pixel square that added up.The result of above-mentioned various modifications also belongs to category of the present invention.

In the present embodiment, the order of 4 * 4 pixel square serial arrangement is also according to shown in Fig. 2 B.Please consult Fig. 2 B and shown in Figure 3 simultaneously.For example, if adder ADD1 has finished the SAD computing (adding absolute difference and the data that total value 322 is complete 4 * 4 image blocks this moment) of the 1st 4 * 4 image blocks, even buffer REG2, REG4, REG6, REG7, REG9, REG11 and REG1 breech lock add total value 322.Treat that adder ADD1 finishes the SAD computing of the 2nd 4 * 4 image blocks, even buffer REG3 and REG1 breech lock add total value 322.Then, order selects circuit 320 to select data SAD4, SAD6, SAD7, SAD9, SAD11 to export adder ADD1 to carry out add operation with the absolute difference and the data (SAD1) of the 2nd 4 * 4 image blocks separately, so that store its accumulation result separately one by one.This moment, buffer REG4 was the absolute difference and the data SAD4 of exportable its first 8 * 4 image blocks.All the other can be analogized according to above-mentioned, so repeat no more.

Absolute difference and the circuit of Fig. 1 and Fig. 3 differ from one another, and for example the absolute difference of Fig. 1 and circuit can provide the absolute difference and the data of several different images square sizes simultaneously in the shortest time, and it is long-pending that the absolute difference of Fig. 3 and circuit are then economized most circuit face.Below again for an embodiment, making circuit area and operation efficiency is between the absolute difference and circuit of Fig. 1 and Fig. 3.

Seeing also shown in Figure 4ly, is another absolute difference and the circuit block diagram that illustrates according to preferred embodiment of the present invention.As shown in Figure 4, absolute difference circuit 410 receives present image block data PM and desire compares image block data PS, and output absolute difference audio data AD.At this, absolute difference circuit 410, adder ADD1, buffer REG1～REG6, select circuit SEL1 and 420 for example respectively with previous embodiment in Fig. 3 absolute difference circuit 310, adder ADD1, buffer REG1～REG6, select circuit SEL1 and 320 identical, so do not give unnecessary details at this.

See also shown in Figure 4ly, adder 430 is coupled to the output of buffer REG6, and receives absolute difference and data SAD6 so that carry out add operation with the data of selecting circuit 440 selected outputs.After the SAD computing of finishing one 8 * 8 image block (be among the buffer REG6 absolute difference and the data of breech lock 8 * 8 image blocks), do not export as yet at adder ADD1 before the absolute difference and data of 4 * 4 complete image blocks, can utilize this by the switching of selecting circuit 440 absolute difference and data SAD6 to be added in the corresponding cache device during one.Therefore, compared to Fig. 3, though present embodiment has increased selection circuit 440 and adder 430, can be more efficient than absolute difference and the circuit of Fig. 3.

The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.

Claims

1, a kind of absolute difference and circuit is characterized in that it comprises:

One absolute difference (absolute difference) circuit is in order to receive one first data PM _{I, j}And one second data PS _{I, j}, and export an absolute difference audio data AD _{I, j}, PM wherein _{I, j}, PS _{I, j}With AD _{I, j}Represent i row (row) j this first data, these second data and this absolute difference data respectively, and AD _{I, j}=| PM _{I, j}-PS _{I, j}|, wherein i and j are all the integer more than or equal to 0;

One first adder in order to receiving and to add up these absolute difference data and one first cumulative data, and will add overall result and be output as one first and add total value;

One first buffer, in order to receive according to one first scheduled timing and breech lock this first add output one first absolute difference and (sum of absolute difference) data after the total value; And

One first selects circuit, in order to receiving and to select this first absolute difference and data and a remainder according to one of them, and data selected is output as this first cumulative data, and wherein the value of this remainder certificate is 0.

2, absolute difference according to claim 1 and circuit is characterized in that wherein said absolute difference circuit comprises:

One subtracter is in order to receive these first data and this second data and the two is subtracted each other back output one difference;

One second buffer is coupled to this subtracter, in order to comply with one second this difference of scheduled timing breech lock;

One complementary circuit is coupled to this second buffer, in order to produce the complement code of this difference; And

One second selects circuit, is coupled to this second buffer and this complementary circuit, in order to select the positive number person to be output as this absolute difference data in the complement code of this difference that is received and this difference in the two.

3, absolute difference according to claim 2 and circuit is characterized in that wherein said complementary circuit comprises:

One inverter is in order to reception and this difference is anti-phase, to export an anti-phase difference; And

One second adder is coupled to this inverter, and in order to receive and to add up this anti-phase difference and one one data to export the complement code of this difference, wherein the value of these one data is 1.

4, absolute difference according to claim 1 and circuit is characterized in that wherein said first absolute difference and data are to be AD _{I, j}To AD _{I+3, j+3}The accumulation result of 4 * 4 arrays.

5, absolute difference according to claim 1 and circuit is characterized in that wherein said first buffer does not have replacement (reset) function.

6, absolute difference according to claim 1 and circuit is characterized in that it more comprises at least one summation circuit,, and add up again according to scheduled timing exporting one second absolute difference and data in order to receive and add up this first absolute difference and data.

7, absolute difference according to claim 6 and circuit is characterized in that wherein said summation circuit comprises:

One the 3rd adder in order to receiving and to add up this first absolute difference and data and one the 3rd cumulative data, and will add overall result and be output as one the 3rd and add total value;

One the 3rd buffer is exported these second absolute difference and data after adding total value according to reception of one the 3rd scheduled timing and breech lock the 3rd; And

One the 3rd selects circuit, in order to receiving and to select this second absolute difference and data and this remainder according to one of them, and data selected is output as the 3rd cumulative data.

8, absolute difference according to claim 6 and circuit is characterized in that wherein said first absolute difference and data are to be AD _{I, j}To AD _{I+3, j+3}The accumulation result of 4 * 4 arrays and AD _{I, j+4}To AD _{I+3, j+7}The accumulation result of 4 * 4 arrays the two one of, and this second absolute difference and data are to be AD _{I, j}To AD _{I+3, j+7}The accumulation result of 4 * 8 arrays.

9, absolute difference according to claim 6 and circuit is characterized in that wherein said first absolute difference and data are to be AD _{I, j}To AD _{I+3, j+3}And AD _{I+4, j}To AD _{I+7, j+3}The two one of the accumulation result of 4 * 4 arrays, and this second absolute difference and data are to be AD _{I, j}To AD _{I+7, j+3}The accumulation result of 8 * 4 arrays.

10, absolute difference according to claim 6 and circuit is characterized in that wherein said first absolute difference and data are to be AD _{I, j}To AD _{I+3, j+3}, AD _{I+4, j}To AD _{I+7, j+3}, AD _{I, j+4}To AD _{I+3, j+7}And AD _{I+4, j+4}To AD _{I+7, j+7}The accumulation result of one of them 4 * 4 array, and this second absolute difference and data are to be AD _{I, j}To AD _{I+7, j+7}The accumulation result of 8 * 8 arrays.

11, absolute difference according to claim 6 and circuit is characterized in that wherein said first absolute difference and data are to be AD _{I, j}To AD _{I+3, j+3}, AD _{I+4, j}To AD _{I+7, j+3}, AD _{I, j+4}To AD _{I+3, j+7}, AD _{I+4, j+4}To AD _{I+7, j+7}, AD _{I, j+8}To AD _{I+3, j+11}, AD _{I+4, j+8}To AD _{I+7, j+11}, AD _{I, j+12}To AD _{I+3, j+15}And AD _{I+4, j+12}To AD _{I+7, j+15}The accumulation result of one of them 4 * 4 array, and this second absolute difference and data are to be AD _{I, j}To AD _{I+7, j+15}The accumulation result of 8 * 16 arrays.

12, absolute difference according to claim 6 and circuit is characterized in that wherein said first absolute difference and data are to be AD _{I, j}To AD _{I+3, j+3}, AD _{I+4, j}To AD _{I+7, j+3}, AD _{I, j+4}To AD _{I+3, j+7}, AD _{I+4, j+4}To AD _{I+7, j+7}, AD _{I+8, j}To AD _{I+11, j+3}, AD _{I+12, j}To AD _{I+15, j+3}, AD _{I+8, j+4}To AD _{I+11, j+7}And AD _{I+12, j+4}To AD _{I+15, j+7}The accumulation result of one of them 4 * 4 array, and this second absolute difference and data are to be AD _{I, j}To AD _{I+15, j+7}The accumulation result of 16 * 8 arrays.

13, absolute difference according to claim 6 and circuit is characterized in that wherein said first absolute difference and data are to be AD _{I, j}To AD _{I+3, j+3}, AD _{I+4, j}To AD _{I+7, j+3}, AD _{I, j+4}To AD _{I+3, j+7}, AD _{I+4, j+4}To AD _{I+7, j+7}, AD _{I+8, j}To AD _{I+11, j+3}, AD _{I+12, j}To AD _{I+15, j+3}, AD _{I+8, j+4}To AD _{I+11, j+7}, AD _{I+12, j+4}To AD _{I+15, j+7}, AD _{I, j+8}To AD _{I+3, j+11}, AD _{I+4, j+8}To AD _{I+7, j+11}, AD _{I, j+12}To AD _{I+3, j+15}, AD _{I+4, j+12}To AD _{I+7, j+15}, AD _{I+8, j+8}To AD _{I+11, j+11}, AD _{I+12, j+8}To AD _{I+15, j+11}, AD _{I+8, j+12}To AD _{I+11, j+15}And AD _{I+12, j+12}To AD _{I+15, j+15}The accumulation result of one of them 4 * 4 array, and this second absolute difference and data are to be AD _{I, j}To AD _{I+15, j+15}The accumulation result of 16 * 16 arrays.

14, absolute difference according to claim 1 and circuit is characterized in that it more comprises:

One the 4th buffer is in order to receive and this first adds total value to export one the 3rd absolute difference and data according to one the 4th scheduled timing breech lock; And

One the 4th selects circuit, be coupled between this absolute difference circuit and this first adder, and connect the 4th buffer, in order to receive and to select these absolute difference data, the 3rd absolute difference and data and this remainder to be sent to this first adder so that carry out add operation with this first cumulative data according to one of them.

15, absolute difference according to claim 14 and circuit is characterized in that wherein said first absolute difference and data are to be AD _{I, j}To AD _{I+3, j+3}, AD _{I+4, j}To AD _{I+7, j+3}, AD _{I, j+4}To AD _{I+3, j+7}, AD _{I+4, j+4}To AD _{I+7, j+7}, AD _{I+8, j}To AD _{I+11, j+3}, AD _{I+12, j}To AD _{I+15, j+3}, AD _{I+8, j+4}To AD _{I+11, j+7}, AD _{I+12, j+4}To AD _{I+15, j+7}, AD _{I, j+8}To AD _{I+3, j+11}, AD _{I+4, j+8}To AD _{I+7, j+11}, AD _{I, j+12}To AD _{I+3, j+15}, AD _{I+4, j+12}To AD _{I+7, j+15}, AD _{I+8, j+8}To AD _{I+11, j+11}, AD _{I+12, j+8}To AD _{I+15, j+11}, AD _{I+8, j+12}To AD _{I+11, j+15}And AD _{I+12, j+12}To AD _{I+15, j+15}The accumulation result of one of them 4 * 4 array, and the 3rd absolute difference and data are to be AD _{I, j}To AD _{I+7, j+7}, AD _{I+8, j}To AD _{I+15, j+7}, AD _{I, j+8}To AD _{I+7, j+15}And AD _{I+8, j+8}To AD _{I+15, j+15}The accumulation result of one of them 8 * 8 array.

16, absolute difference according to claim 15 and circuit is characterized in that it more comprises:

One slender acanthopanax musical instruments used in a Buddhist or Taoist mass in order to receiving and to add up the 3rd absolute difference and data and one the 5th cumulative data, and will add overall result and be output as a slender acanthopanax total value;

One the 5th buffer is exported one the 4th absolute difference and data in order to receive also according to one the 5th scheduled timing after this slender acanthopanax total value of breech lock; And

One the 5th selects circuit, in order to receiving and to select the 4th absolute difference and data and this remainder according to one of them, and data selected is output as the 5th cumulative data.

17, absolute difference according to claim 16 and circuit is characterized in that wherein said the 4th absolute difference and data are to be AD _{I, j}To AD _{I+7, j+15}And AD _{I+8, j}To AD _{I+15, j+15}The accumulation result of one of them 8 * 16 array.

18, absolute difference according to claim 16 and circuit is characterized in that wherein said the 4th absolute difference and data are to be AD _{I, j}To AD _{I+15, j+7}And AD _{I, j+8}To AD _{I+15, j+15}The accumulation result of one of them 16 * 8 array.

19, absolute difference according to claim 16 and circuit is characterized in that wherein said the 4th absolute difference and data are to be AD _{I, j}To AD _{I+15, j+15}The accumulation result of 16 * 16 arrays.

20, absolute difference according to claim 1 and circuit is characterized in that wherein said first data and this second data are respectively present image block data and desire compares the image block data.