CN1763917A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- CN1763917A CN1763917A CN 200410088232 CN200410088232A CN1763917A CN 1763917 A CN1763917 A CN 1763917A CN 200410088232 CN200410088232 CN 200410088232 CN 200410088232 A CN200410088232 A CN 200410088232A CN 1763917 A CN1763917 A CN 1763917A
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- Prior art keywords
- layer
- dielectric layer
- opening
- substrate
- semiconductor element
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- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 229910052751 metal Inorganic materials 0.000 claims abstract description 77
- 239000002184 metal Substances 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000004020 conductor Substances 0.000 claims description 30
- 239000003990 capacitor Substances 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 28
- 230000004888 barrier function Effects 0.000 claims description 21
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- 239000000565 sealant Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 238000003701 mechanical milling Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000007789 sealing Methods 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims 2
- 229910052782 aluminium Inorganic materials 0.000 claims 2
- 239000010410 layer Substances 0.000 description 102
- 239000011229 interlayer Substances 0.000 description 16
- 238000005516 engineering process Methods 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 238000004528 spin coating Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 2
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010406 interfacial reaction Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical group [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
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Abstract
The manufacture method for a semiconductor element comprises: providing a substrate with formed first and second metal layers, forming by turns the first and second dielectric layers, an etching-end layer with a first and second openings on upper of first and second metal layers, respectively; removing dielectric layers to form the first groove to expose the first metal layer; forming capacity dielectric layer on substrate with the third opening on upper of second metal layer; removing the capacity dielectric layer and said two dielectric layers to form opening to expose the second metal layer; then, filling metal in first groove and opening.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor element, particularly relate to a kind of manufacture method that is applicable to the semiconductor element that forms double-embedded structure and MIM capacitor simultaneously.
Background technology
Along with the increase of semiconductor element integrated level, and when entering the technology of deep-sub-micrometer (Deep Sub-Micron), size of component is dwindled gradually, and relative making as the space of capacitor is more and more little.And capacitor volume is the size that depends on the surface area between top electrode and the bottom electrode.Therefore, mainly contain two kinds with solving the method that the semiconductor capacitor size is dwindled and capacity must increase at present, i.e. the dielectric layer that selection has the high capacitance ability, and the surface area that increases capacitor lower electrode.
When use high dielectric constant materials in capacitor when addressing the above problem, the material of relative upper/lower electrode also needs to change gradually, with the usefulness (Performance) that highlights capacitor, metal-insulator-metal (metal-insulator-metal wherein, MIM) structure is because have the characteristic of low interface reaction (Low InterfacialReaction), can promote the usefulness of capacitor, use widely so be subjected to industry.
On the other hand, after semiconductor technology enters the deep-sub-micrometer field, often utilize copper to make intraconnections.Yet,, therefore utilize damascene process An to replace traditional lead technology and make copper conductor because etch copper is very very difficult.At present industry has proposed the manufacture method of the semiconductor element of a succession of relevant formation MIM capacitor and metal damascene structure, as United States Patent (USP) the 6th, 025, and No. 226 cases and the 6th, 649, No. 464 cases of United States Patent (USP).
Figure 1A to Figure 1B is for disclosing a kind of manufacturing process profile with semiconductor element of capacitor and metal damascene structure of existing (United States Patent (USP) the 6th, 025, No. 226 cases).
At first, please refer to Figure 1A, the substrate 105 that is formed with metal level 110 and metal level 115 is provided.Then, in substrate 105, form dielectric layer 107, in dielectric layer 107, form opening 120 again and, and in substrate 105, form conformal insulating barrier 122 as the opening 130 of interlayer window opening.
Then, please refer to Figure 1B, patterned insulation layer 122 and dielectric layer 107 and go up to form groove 132 in opening 130 (interlayer window opening).Afterwards, insert metal level 124 and form double-metal inlaid structure in opening 130 (interlayer window opening) and groove 132, and in opening 120, insert metal level 126.Wherein metal level 126, insulating barrier 122 constitute MIM capacitor with metal level 110.
In above-mentioned technology, owing in opening 130 (interlayer window opening), also can form insulating barrier 122, and it is narrower that opening 130 (interlayer window opening) is become, and causes opening 130 (interlayer window opening) depth-width ratio (aspect ratio) but relatively to increase.When the depth-width ratio of opening 130 (interlayer window opening) increases, the degree of difficulty of inserting metal will increase, cause and in opening 130 (interlayer window opening), to insert metal fully, and be easy to form in the opening 130 (interlayer window opening) cavity, cause plain conductor easily to omit electric current, and its usefulness is reduced.
Fig. 2 A to Fig. 2 C is for disclosing a kind of manufacturing process profile with semiconductor element of capacitor and metal damascene structure of existing (United States Patent (USP) the 6th, 649, No. 464 cases).
At first, please refer to Fig. 2 A, the substrate 200 that is formed with barrier layer 204 and metal level 214, barrier layer 202 and metal level 212 is provided.In this substrate 200, form sealant 210 then, and in substrate 200, form the dielectric layer 220 of opening 230 with exposing metal layer 212.In substrate 200, form dielectric layer 222 afterwards, and in opening 230, form barrier layer 232 and metal level 242.Then, in substrate 200, form sealant 240.Wherein metal level 212, dielectric layer 222 constitute MIM capacitor with metal level 242.
Please refer to Fig. 2 B, then, in dielectric layer 220, sealant 210, form the opening 260 (interlayer window opening) of exposing metal layer 214, and in opening 260, form barrier layer 234 and metal level 244.Then, in substrate 200, form sealant 270.
Please refer to Fig. 2 C, after forming dielectric layer 280 in the substrate 200, in dielectric layer 280, form opening 274 (groove) and opening 272.Then, in opening 274, form barrier layer 254 and metal level 264, and in opening 272, form barrier layer 252 and metal level 262.Wherein, metal level 264 and metal level 234 constitute double-embedded structure.
In above-mentioned technology, after forming MIM capacitor earlier, form metal interconnecting (double-embedded structure) again, owing to need repeatedly layer metal deposition technology, chemical mechanical milling tech and photoengraving carving technology, therefore make the step of manufacturing process more complicated and can raise the cost.
Summary of the invention
Understand the shortcoming of above-mentioned prior art, therefore, the invention provides a kind of manufacture method of semiconductor element, solve these problems.
A purpose of the present invention provides a kind of manufacture method of semiconductor element, can directly use mosaic technology to make metal-insulator-metal capacitor, and can reduce the manufacturing process step, makes technology comparatively easy and can reduce cost.
The present invention proposes a kind of manufacture method of semiconductor element, is applicable to form conductor structure and capacitor simultaneously, and the method provides substrate, and this substrate has formed first conductor layer and second conductor layer.Then, in substrate, form first dielectric layer, and on first dielectric layer, form etch stop layer.Then, this etch stop layer of patterning is positioned at first opening and second opening that is positioned at second conductor layer top of first conductor layer top with formation.Afterwards, in substrate, form second dielectric layer, and remove part second dielectric layer and first dielectric layer to form first groove of exposure first conductor layer.Then, form capacitance dielectric layer in substrate, and form patterned mask layer on capacitance dielectric layer, this patterned mask layer has the 3rd opening that is positioned at second conductor layer top.Then, remove the 3rd opening exposed portions capacitance dielectric layer, second dielectric layer and first dielectric layer, to form the opening that exposes second conductor layer.Afterwards, remove patterning photoresist layer, and in substrate, form the 3rd conductor layer.Then, remove first groove and the 4th opening the 3rd conductor layer in addition.
Because the present invention can only need carry out the deposition of a metal level simultaneously when forming MIM capacitor and double-embedded structure, therefore can reduce the manufacturing process step, and then reduce production costs.And, the present invention is when forming the dual-inlaid opening, use etch stop layer as alignment mask voluntarily, as long as therefore carrying out an etching can form groove and interlayer hole opening, the while also can be avoided inserting capacitance dielectric layer in the interlayer hole opening and the problem that causes the interlayer hole opening to dwindle.
For above and other objects of the present invention, feature and advantage can be become apparent, following conjunction with figs. and preferred embodiment are to illustrate in greater detail the present invention.
Description of drawings
Figure 1A to Figure 1B illustrates existing a kind of manufacturing process profile with semiconductor element of capacitor and metal damascene structure.
Fig. 2 A to Fig. 2 C illustrates the manufacturing process profile that existing another kind has the semiconductor element of capacitor and metal damascene structure.
Fig. 3 A to Fig. 3 G is the manufacturing process generalized section that illustrates according to a kind of semiconductor structure of embodiments of the invention.
The simple symbol explanation
105,200,300: substrate
107,220,222,280,308,316,322: dielectric layer
120,130,230,260,272,274,312,314,324,330: opening
122: insulating barrier
124,126,110,115,212,214,234,242,244,262,264,302,304: metal level
132,320,328: groove
202,204,232,234,252,254,334: the barrier layer
210,240,270,306: sealant
310,310a: etch stop layer
318,326: photoresist
330: the interlayer window opening
332: opening
336: double-embedded structure
The 338:MIM capacitor
Embodiment
Next embodiments of the invention are described in detail in detail, and embodiment will explain with accompanying drawing.Under situation as much as possible, same or analogous reference number in the diagram is used to describe same or similar part.It should be noted that depiction is the skeleton symbol form, is not the accurate dimensions size.
Fig. 3 A to 3F figure illustrates the manufacturing process profile of the semiconductor element of one embodiment of the present invention.
Please refer to Fig. 3 A, the present invention proposes a kind of manufacture method of semiconductor element.At first, provide a substrate 300, formed metal level 302 and metal level 304 in this substrate 300.The material of metal level 302 and metal level 304 for example is copper metal or aluminum metal.
Then, in substrate 300, form sealant (sealing layer) 306, to cover metal level 302 and metal level 304.The material of sealant 306 is included as silicon nitride or other suitable nitride and oxide, in order to avoiding the surface oxidation of metal level 302 and metal level 304, the method for its formation for example be chemical vapour deposition technique (chemical vapor deposition, CVD).Certainly, the formation of this sealant 306 is selectable, if the material of metal level 302 and metal level 304 is the conductor material that is difficult for oxidation, does not then need to form sealant 306.
Then, on sealant 306, form dielectric layer 308.The material of dielectric layer 308 for example is a silica, and the method for its formation for example is a chemical vapour deposition technique.Certainly, the material of dielectric layer 308 also can be advanced low-k materials or other material that is fit to, and form the kind difference of the method for dielectric layer 308 according to selected advanced low-k materials, for example be chemical vapour deposition technique or method of spin coating (SpinCoating).
Then, on dielectric layer 308, form an etch stop layer 310.And the material of etch stop layer 310 comprises with dielectric layer 308 having different etching selectivity persons, for example is silicon nitride.
Then, please refer to Fig. 3 B, form the mask layer (not illustrating) of one deck patterning on etch stop layer 310, this mask layer for example is the photoresist layer.Use mask layer as etching mask, the etch stop layer 310 that removal exposes, surface until first dielectric layer 308 that exposes part, to form pattern etched stop layer 310a, comprising forming the position at opening above the metal level 302 312 and the opening 314 of position above metal level 304.Then, remove mask layer.
Afterwards, please refer to Fig. 3 C, in substrate 300, form one dielectric layer 316.The material of dielectric layer 316 for example is a silica, and the method for its formation for example is a chemical vapour deposition technique.Certainly, the material of dielectric layer 316 also can be advanced low-k materials or other material that is fit to, and form the kind difference of the method for dielectric layer 316 according to selected advanced low-k materials, can be chemical vapour deposition technique or method of spin coating (Spin Coating).Then, on dielectric layer 316, form patterning photoresist layer 318.
Afterwards, please refer to Fig. 3 D, use patterning photoresist layer 318 (asking for an interview Fig. 3 C), remove the dielectric layer 316 and the dielectric layer down 308 and the groove 320 of sealant 306 that expose with formation exposing metal layer 304 as etching mask.Then, in substrate 300, form one deck capacitance dielectric layer (capacitor dielectric layer) 322.The material of this capacitance dielectric layer 322 for example is silica, silicon nitride, tantalum pentoxide (Ta
2O
5), barium strontium titanate (Ba
xSr
(1-x)TiO
3) or barium titanate (BaTiO
3) etc., the formation method of capacitance dielectric layer 322 for example is a chemical vapour deposition technique.
Then, please refer to Fig. 3 E, form the patterning photoresist layer 326 with an opening 324 on capacitor dielectric 322, this opening 324 is positioned at metal level 302 tops.
Continuing, please refer to Fig. 3 F, removing the capacitance dielectric layer 322 that opening 324 exposes part.Secondly, remove part dielectric layer 316, dielectric layer 308 and sealant 306, in dielectric layer 316 and dielectric layer 308, to form the opening 332 of exposing metal layer 302.Remove patterning photoresist 326 (asking for an interview Fig. 3 E) afterwards.In the formation step of opening 332, be included in and form groove 328 and formation opening 330 in dielectric layer 308 in the dielectric layer 316.The step that in dielectric layer 308, forms opening 330 with etch stop layer 310a as alignment mask voluntarily.
Then, please refer to Fig. 3 G, form a barrier layer 334 in substrate 300, the effect on this barrier layer 334 is to prevent that metal diffusing is to dielectric layer 316, dielectric layer 308.The material on barrier layer 334 for example is tantalum nitride (TaN), titanium nitride or titanium silicon nitride.Then, form a Seed Layer (not illustrating) on barrier layer 334, follow, form a metal level (not illustrating) in substrate 300, this metal level fills up groove 320 (asking for an interview Fig. 3 F) and opening 332 (asking for an interview Fig. 3 F).Afterwards, utilize chemical mechanical milling method, carry out planarization until expose capacitance dielectric layer 322 or worn it, to form a semiconductor element with double-embedded structure 336 and MIM capacitor 338.
In the above-described embodiments, owing to when forming MIM capacitor and double-embedded structure, only need carry out the deposition of a metal level, therefore can reduce the manufacturing process step, and then reduce production costs.And, the present invention is when forming the dual-inlaid opening, use etch stop layer as alignment mask voluntarily,, also can avoid in the interlayer hole opening, inserting capacitance dielectric layer simultaneously and the problem that causes the interlayer hole opening to dwindle as long as therefore carrying out an etching can form the dual-inlaid opening.
In the above-described embodiments, the zone of double-metal inlaid structure contact is that example explains with the metal level with the bottom electrode of capacitor, certainly the bottom electrode of the zone that contacts of double-metal inlaid structure and capacitor so long as conductor layer get final product.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (20)
1, a kind of manufacture method of semiconductor element is applicable to form a conductor structure and a capacitor simultaneously, and this method comprises:
One substrate is provided, and this substrate has formed one first conductor layer and one second conductor layer;
In this substrate, form one first dielectric layer;
On this first dielectric layer, form an etch stop layer;
This etch stop layer of patterning is positioned at one first opening and one second opening that is positioned at this second conductor layer top of this first conductor layer top with formation;
In this substrate, form one second dielectric layer;
Remove this second dielectric layer of part and this first dielectric layer to form one first groove that exposes this first conductor layer;
In this substrate, form a capacitance dielectric layer;
Form a patterned mask layer on this capacitance dielectric layer, this patterned mask layer has one the 3rd opening that is positioned at this second conductor layer top;
Remove the 3rd this capacitance dielectric layer of opening exposed portions, this second dielectric layer and this first dielectric layer, to form one the 4th opening that exposes this second conductor layer;
Remove this patterned mask layer;
In this substrate, form one the 3rd conductor layer; And
Remove this first groove and the 4th opening the 3rd conductor layer in addition.
2, the manufacture method of semiconductor element as claimed in claim 1 wherein before the step of this first dielectric layer of formation, also is included in and forms a sealant in this substrate in this substrate.
3, the manufacture method of semiconductor element as claimed in claim 2, wherein the sealing layer comprises silicon nitride.
4, the manufacture method of semiconductor element as claimed in claim 1 wherein forms in this first dielectric layer in the step of the 4th opening, comprises with this etch stop layer as alignment mask voluntarily.
5, the manufacture method of semiconductor element as claimed in claim 1, wherein the material of this etch stop layer comprises silicon nitride.
6, the manufacture method of semiconductor element as claimed in claim 1, the method that wherein removes this first groove and the 4th opening the 3rd conductor layer in addition comprises chemical mechanical milling method.
7, the manufacture method of semiconductor element as claimed in claim 1, wherein the material of this first dielectric layer and this second dielectric layer comprises silica.
8, the manufacture method of semiconductor element as claimed in claim 1, wherein the material of this first conductor layer, this second conductor layer and the 3rd conductor layer comprises one of them of aluminium and copper.
9, the manufacture method of semiconductor element as claimed in claim 1, before wherein in this substrate, forming the step of the 3rd conductor layer, also be included in and form a barrier layer in this substrate, then in the step of the 3rd conductor layer beyond removing this first groove and the 4th opening, also comprise removing this barrier layer of part.
10, the manufacture method of semiconductor element as claimed in claim 9, wherein the material on this barrier layer comprises titanium nitride.
11, the manufacture method of semiconductor element as claimed in claim 1, wherein the material of this patterned mask layer comprises photoresist.
12, a kind of manufacture method of semiconductor element is applicable to form a metal damascene structure and a capacitor simultaneously, and this method comprises:
One substrate is provided, and this substrate has formed a first metal layer and one second metal level;
In this substrate, form one first dielectric layer;
On this first dielectric layer, form an etch stop layer;
This etch stop layer of patterning is positioned at one first opening and one second opening that is positioned at this second metal level top of this first metal layer top with formation;
In this substrate, form one second dielectric layer;
Remove this first dielectric layer of part and this second dielectric layer to form one first groove that exposes this first metal layer;
In this substrate, form a capacitance dielectric layer;
Form one the 3rd opening on this capacitance dielectric layer, the 3rd opening is positioned at this second metal level top;
Remove the 3rd opening institute this second dielectric layer of exposed portions, in this second dielectric layer, formed one second groove;
Remove this first dielectric layer of part with this etch stop layer for alignment mask voluntarily, to form one the 4th opening that exposes this second metal level; And
In this substrate, form one the 3rd metal level; And
Remove this first groove, the 4th opening and this second groove the 3rd metal level in addition.
13, the manufacture method of semiconductor element as claimed in claim 12 wherein before the step of this first dielectric layer of formation, also is included in and forms a sealant in this substrate in this substrate.
14, the manufacture method of semiconductor element as claimed in claim 13, wherein the sealing layer comprises silicon nitride.
15, the manufacture method of semiconductor element as claimed in claim 12, wherein the material of this etch stop layer comprises silicon nitride.
16, the manufacture method of semiconductor element as claimed in claim 12, the method that wherein removes this first groove, the 4th opening and this second groove the 3rd metal level in addition comprises chemical mechanical milling method.
17, the manufacture method of semiconductor element as claimed in claim 12, wherein the material of this first dielectric layer and this second dielectric layer comprises silica.
18, the manufacture method of semiconductor element as claimed in claim 12, wherein the material of this first metal layer, this second metal level and the 3rd metal level comprises one of them of aluminium and copper.
19, the manufacture method of semiconductor element as claimed in claim 12, before wherein in this substrate, forming the step of the 3rd metal level, also be included in and form a barrier layer in this substrate, then in the step of the 3rd metal level beyond removing this first groove, the 4th opening and this second groove, also comprise removing this barrier layer of part.
20, the manufacture method of semiconductor element as claimed in claim 12, wherein the material on this barrier layer comprises titanium nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100882323A CN100394545C (en) | 2004-10-21 | 2004-10-21 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100882323A CN100394545C (en) | 2004-10-21 | 2004-10-21 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1763917A true CN1763917A (en) | 2006-04-26 |
| CN100394545C CN100394545C (en) | 2008-06-11 |
Family
ID=36747975
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100882323A Expired - Fee Related CN100394545C (en) | 2004-10-21 | 2004-10-21 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100394545C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105070642A (en) * | 2015-06-30 | 2015-11-18 | 上海华力微电子有限公司 | Metal insulator metal (MIM) capacitor manufacturing method |
| CN108140730A (en) * | 2015-10-12 | 2018-06-08 | 应用材料公司 | The structure and method of three-dimensional (3D) metal-insulator-metal type (MIM) capacitor of manufacture and resistor are connected up with half addition plating metal |
| CN110473886A (en) * | 2018-05-11 | 2019-11-19 | 联华电子股份有限公司 | The manufacturing method of semiconductor element |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6329234B1 (en) * | 2000-07-24 | 2001-12-11 | Taiwan Semiconductor Manufactuirng Company | Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow |
| US6413815B1 (en) * | 2001-07-17 | 2002-07-02 | Macronix International Co., Ltd. | Method of forming a MIM capacitor |
| KR100429877B1 (en) * | 2001-08-04 | 2004-05-04 | 삼성전자주식회사 | Method for semiconductor device having metal-insulator-metal capacitor and via contact |
| CN1202569C (en) * | 2002-01-09 | 2005-05-18 | 中芯国际集成电路制造(上海)有限公司 | Method for forming capacitor for metel-insulation-metal structure in process of insertting copper |
| CN1532911A (en) * | 2003-03-19 | 2004-09-29 | 矽统科技股份有限公司 | Method for producing metal-insulator-metal type capacitor in integratied mosaic process |
-
2004
- 2004-10-21 CN CNB2004100882323A patent/CN100394545C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105070642A (en) * | 2015-06-30 | 2015-11-18 | 上海华力微电子有限公司 | Metal insulator metal (MIM) capacitor manufacturing method |
| CN108140730A (en) * | 2015-10-12 | 2018-06-08 | 应用材料公司 | The structure and method of three-dimensional (3D) metal-insulator-metal type (MIM) capacitor of manufacture and resistor are connected up with half addition plating metal |
| CN108140730B (en) * | 2015-10-12 | 2022-06-03 | 应用材料公司 | Substrate and method of processing substrate |
| CN110473886A (en) * | 2018-05-11 | 2019-11-19 | 联华电子股份有限公司 | The manufacturing method of semiconductor element |
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| Publication number | Publication date |
|---|---|
| CN100394545C (en) | 2008-06-11 |
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