CN1758542A - Phase-locked control method of clock phaselocked loop - Google Patents
Phase-locked control method of clock phaselocked loop Download PDFInfo
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Abstract
This invention relates to a method for controlling phase-lock of a clock phase-locked loop, in which, the clock phase-locked loop includes a processor, a phase discriminator, a filter and a crystal oscillator, the method includes: 1, designing the operation steps for entering into a free state, a quick catching state, a tracking state, a keeping state and a lock-lost state, 2, designing the control state to determine the jumping condition to other states from the control state and the condition jumping to the control state from other states to distinguish the jumping conditions among the states, 3, after the clock phase-locked loop is turned on, the processor enters into the control state first then enters into related states according to the jumping condition designed in step 2 to execute the steps in step 1 to realize the phase lock control of the loop.
Description
Technical field
The present invention relates to the simultaneous techniques of the communications field, relate in particular to a kind of phase-locked control method of clock phase-locked loop.
Background technology
Be the basis of the intercommunication of various device in the communication system synchronously, good then information just phenomenons such as error code, slip can occur inevitably in transmittance process synchronously if communicating pair is not set up, thus the consequence that causes communication quality to descend.For example, for voice call, just do not begin conversation synchronously if both call sides is set up, both sides probably can hear clatter, even the consequence that causes both sides to communicate by letter; If consequences such as communicating pair not foundation does not well just carry out fax sending and receiving synchronously, and the information that probably causes the recipient to receive is incomplete or smudgy therefore in order to ensure the communication quality of the every business of communicating pair, are absolutely necessary in communication system synchronously.
Clock phase-locked loop is a device of realizing clock synchronization.Can the good ring of its realization clock synchronization effect is directly connected to communication system proper communication.The operation principle of tradition clock phase-locked loop is that relatively the reference clock that receives of this device and this device are exported the frequency plot of clock, obtain the output frequency of a difference control clock phase-locked loop, consistent to realize the reference clock source frequency with the clock frequency of clock phase-locked loop output.
See also Fig. 1, it is a kind of structural representation of realizing the clock phase-locked loop of clock synchronization.It comprises phase discriminator 11, filter 12, D/A (D/A) transducer 13, crystal oscillator 14, frequency divider 15 and processor 16.The phase place degeneration factor that phase discriminator 11, filter 12, D/A converter 13, crystal oscillator 14 and frequency divider 15 are formed, main consistent for the clock frequency f1 of the clock frequency f0 that realizes reference clock source output and crystal oscillator output, wherein f1 is obtained through frequency divider 15 frequency divisions by crystal oscillator 14 output frequency f.
According to current international regulation, clock phase-locked loop must have free state (free), catch state (fast), tracking mode (follow), hold mode (hold) and out-of-lock condition (loss) soon, and the switching between those states is promptly controlled in phase-locked control, so that clock phase-locked loop is reliablely and stablely worked.
Free state is the operating state of the clock phase-locked loop when not being locked in reference clock source.Under this operating state, the output frequency of clock phase-locked loop is the centre frequency of crystal oscillator.
The state of catching is the operating state of clock phase-locked loop when beginning the clock signal in track reference clock source soon, prior art adopts the numerical value of digitized RC (resistance capacitance filtering) filtering or PID (proportion integration differentiation control) method control filters output usually, so that the quick frequency values near the External Reference clock signal of the clock signal of crystal oscillator output.
Tracking mode is that clock phase-locked loop is being caught under the state soon, if the output clock frequency of clock phase-locked loop and reference clock frequency near the time (usually difference less than etc. a certain threshold value that sets in advance), then enter tracking mode, realize that the reference clock signal of input and the clock signal that this clock phase-locked loop is exported are synchronous.
Hold mode is that the reference clock signal of input clock phase-locked loop is when losing, the numerical value of filter output is kept the numerical value that reference clock signal is not lost preceding last filter output, the frequency values of clock phase-locked loop output when losing the External Reference clock signal to keep.
Out-of-lock condition is to cause that clock phase-locked loop can not lock reference clock in tracking mode under the situations such as clock signal deterioration of reference clock source outside, then resets new argument, so that can lock the operating state of new reference clock again.
In the implementation procedure of the phase-locked control of prior art, normally in the processor of clock phase-locked loop, finish, may further comprise the steps (seeing also Fig. 2):
At first carry out step S110, set in advance the criterion that operation that each state of phase-locked loop should finish and each state jump to other states.Criterion comprises: sets and to enter the criterion of other state after initially powering on, as exist reference clock signal then to enter to catch state soon, otherwise the freedom of entry state; The state of catching soon of being provided with jumps to the redirect condition of other states, the redirect condition that jumps to tracking mode as the state of catching soon be the phase difference of the clock frequency of phase-locked loop output and reference clock frequency less than a predefined threshold value, catch state to the decision condition of free state soon and be reference clock signal and lose etc.; Comprise that also tracking mode, hold mode, out-of-lock condition jump to the decision condition of other states.That is, need set all possible redirect of each state and corresponding decision condition according to each situation that phase-locked process may be run into;
Then carry out step S120, carry out phase-locked operation, carry out the criterion of step S110 setting and the operation that each state should be finished according to the actual situation of running into of phase-locked loop, so that carry out phase-locked control.
In the step of said method, owing to need preestablish all possible redirect of each state and corresponding decision condition according to the situation that phase-locked process may be run into, therefore cause each state except the operating procedure that this state should be carried out, its criterion is also very complicated, be operated in tracking mode such as clock phase-locked loop, when the difference of the clock frequency of clock phase-locked loop output and reference clock frequency jumps to the state of catching soon during greater than predefined time of a threshold value and this condition satisfied one, jump to out-of-lock condition in addition, the redirect condition of hold mode etc., thereby mistake appears in stateful switchover process easily, cause system's instability, and then influence synchronous effect.And these control procedures are to finish under processor control, because the control procedure complexity requires height thereby cause to performance of processors, and then have improved the hardware cost of control.
Summary of the invention
The problem that the present invention solves is that each state not only needs to be provided with corresponding operating procedure, but also need to be provided with the complicated criterion that jumps to other states, thereby mistake appears in stateful switchover process easily, cause system's instability, and then influence synchronous effect, and the control procedure complexity, thereby cause performance of processors is required height, and then improved the technical problem of the hardware cost of control.
For addressing the above problem, the invention discloses a kind of phase-locked control method of clock phase-locked loop, described clock phase-locked loop comprises processor, phase discriminator, filter and crystal oscillator at least, said method comprising the steps of:
(1) on described processor, be provided with respectively clock phase-locked loop freedom of entry state, catch the operating procedure that state, tracking mode, hold mode and out-of-lock condition are finished separately soon;
(2) on described processor, state of a control is set, determine that described state of a control jumps to the redirect condition of other each states and the redirect condition that other each states jump to described state of a control, described state of a control is in order to realize the differentiation of redirect between each state;
(3) after described clock phase-locked loop initially powers on, described processor is introduced into state of a control, and the redirect condition of setting according to step (2) enters corresponding state then, the operating procedure of correspondence in the execution in step (1), and then the phase-locked control of realization clock phase-locked loop.
And step (3) can also comprise:
When described clock phase-locked loop be in free state, when catching state, tracking mode, hold mode or out-of-lock condition soon, if satisfy be provided with in the step (2) jump to the redirect condition of described state of a control the time, jump to state of a control;
Jump to corresponding state by state of a control according to the redirect condition that is provided with in the step (2).
The redirect condition that definite described state of a control jumps to other each states in the step (2) specifically comprises:
A1: clock phase-locked loop has just powered on and phase discriminator does not receive reference clock signal, or
Previous state is to catch state soon and phase discriminator does not receive reference clock signal, then the freedom of entry state;
B1: clock phase-locked loop has just powered on and phase discriminator receives reference clock signal, or
Previous state is that free state, out-of-lock condition or hold mode and phase discriminator receive reference clock signal, or
Previous state is tracking mode and Δ θ＞M
Fast, then enter and catch state soon, wherein Δ θ is the phase difference of phase discriminator, M
FastSecond threshold value for phase difference;
C1: previous state is the state of catching soon and Δ θ＜M
Follow, then enter tracking mode, wherein, Δ θ is the phase difference of phase discriminator, M
FollowFirst threshold value for phase difference;
D1: previous state is that tracking mode and phase discriminator do not receive reference clock signal, then enters hold mode;
E1: previous state is hold mode and T＞t
Hold, then enter out-of-lock condition, wherein, T represents that phase-locked loop is in the running time of hold mode, t
HoldBe in the threshold value of hold mode for phase-locked loop.
The redirect condition that other each states described in the step (2) jump to described state of a control specifically comprises:
A2: when the clock phase-locked loop is in free state and phase discriminator and receives reference clock signal, jump to state of a control;
B2: when the clock phase-locked loop is in the state of catching soon, if Δ θ＜M
FollowSet up, or phase discriminator do not receive reference clock signal, then jump to state of a control, wherein Δ θ is the phase difference of phase discriminator, M
FollowFirst threshold value for phase difference;
C2: when the clock phase-locked loop is in tracking mode, if Δ θ＞M
FastSet up, or phase discriminator do not receive reference clock signal, then jump to state of a control, wherein Δ θ is the phase difference of phase discriminator, M
FastSecond threshold value for phase difference;
D2: when the clock phase-locked loop is in hold mode, if T＞t
Hold, or phase discriminator do not receive reference clock signal, then jumps to state of a control, and wherein T represents that phase-locked loop is in the running time of hold mode, t
HoldBe in the threshold value of hold mode for phase-locked loop;
E2: handle out-of-lock condition when the clock phase-locked loop,, then jump to state of a control if phase discriminator receives reference clock signal.
In addition, the free state complete operation step that is provided with in the step (1) comprises that the clock frequency of clock phase-locked loop output is the centre frequency of crystal oscillator.
The operating procedure that state of catching soon that is provided with in the step (1) and tracking mode are finished comprises according to y (n)=a
1Y (n-1)+a
2Y (n-2)+b
0X (n)+b
1X (n-1)+b
2X (n-2), the numerical value of calculating filter output is with the clock frequency of control crystal oscillator output, wherein a
1, a
2, b
0, b
1, b
2Be the loop gain parameter, x (n) is the phase difference of input, and y (n) is the numerical value of filter output, and n is a number of times.
The operating procedure of described hold mode comprises y[n]={ y
Follow| follow=0,1.....n} are as the input crystal oscillator parameter of filter, and wherein y (n) is the numerical value of filter output, and n is a number of times.
Step also comprises in (3), when detecting described clock phase-locked loop and just powered on, after the predefined time of delaying time, just carries out the redirect of various states, so that the crystal oscillator steady operation.
Compared with prior art, the present invention has the following advantages:
Carry out phase-locked control according to method of the present invention, free state, to catch the redirect of state, tracking mode, hold mode and out-of-lock condition soon fairly simple, directly jump to state of a control, judge which state that jumps to by state of a control, omit free state, caught the mutual switching between them of state, tracking mode, hold mode and out-of-lock condition soon, improve the stability of system, and then promoted synchronous effect.
In free state, catch under those states of state, tracking mode, hold mode and out-of-lock condition soon, the topmost task of each state is to finish the preset operation step, improve control efficiency, also reduced requirement simultaneously, and then reduce hardware cost processor performance.
Description of drawings
Fig. 1 is a kind of structural representation of realizing the clock phase-locked loop of clock synchronization;
Fig. 2 is the phase-locked control flow chart of existing clock phase-locked loop;
Fig. 3 is the phase-locked control flow chart of clock phase-locked loop of the present invention;
The contrast figure of the filter output numerical value that the algorithm that Fig. 4 is existing and hold mode of the present invention is taked obtains.
Embodiment
Below in conjunction with accompanying drawing, specify the present invention.
In order to say clearly the present invention better, the present invention still adopts clock phase-locked loop shown in Figure 1 to carry out phase-locked control, but the disclosed clock phase-locked loop structure of Fig. 1 is not in order to restriction the present invention.
See also Fig. 3, it is the phase-locked control flow chart of a kind of clock phase-locked loop disclosed by the invention.It may further comprise the steps:
S210: clock phase-locked loop freedom of entry state is set respectively on processor 16, catches the operating procedure that state, tracking mode, hold mode and out-of-lock condition are finished separately soon;
S220: on processor 16, state of a control is set, determine that described state of a control jumps to the redirect condition of other each states and the redirect condition that other each states jump to described state of a control, described state of a control is in order to realize the differentiation of redirect between each state;
S230: after described clock phase-locked loop initially powers on, described processor 16 is introduced into state of a control, the redirect condition of setting according to step S220 enters corresponding state then, the operating procedure of correspondence among the execution in step S210, and then the phase-locked control of realization clock phase-locked loop.
In step S230, also be included in clock phase-locked loop and be in free state, catch state, tracking mode, hold mode and out-of-lock condition following time soon, run into when satisfying this state and jumping to the redirect condition of state of a control, jump to state of a control.That is, free state, catch each state in state, tracking mode, hold mode and the out-of-lock condition by the redirect between the state of a control completion status soon.
In step S210, each state can be provided with the operating procedure of this state as follows:
(1) free state is the operating state of clock phase-locked loop when not being locked in External Reference clock source, and the operating procedure that is provided with under this free state comprises: the output frequency of processor control clock phase-locked loop is the centre frequency of crystal oscillator.
(2) state of catching is the operating state of clock phase-locked loop when beginning to follow the tracks of the External Reference clock soon, and it can adopt traditional digitlization RC filtering or PID control method, the numerical value of calculating filter 12 outputs.In the assignment procedure of operating procedure of catching state soon of the present invention, adopt bigger loop gain parameter, so that make the clock of crystal oscillator 14 outputs capture the External Reference clock signal fast.
Such as, the filter equation of original employing is a formula
The present invention adopts and uses the second order network design, and it is rewritten into following formula
y(n)＝a
1y(n-1)+a
2y(n-2)+b
0x(n)+b
1x(n-1)+b
2x(n-2) (2)
Wherein, a
1, a
2, b
0, b
1, b
2Be the loop gain parameter that is provided with, x (n) is the phase difference of phase discriminator 11 outputs, and y (n) is the output numerical value of filter 12, and n is a numerical value.
The operating procedure of catching state soon comprises the output numerical value of processor according to formula (2) control filters 12, with the clock frequency of control crystal oscillator 14 outputs.
In order to guarantee to capture fast the clock frequency of input, can adopt bigger pull-in range bandwidth.When n=0, clock phase-lock-ring output frequency is the centre frequency of crystal oscillator 14 in the present invention.
(3) tracking mode is to catch soon under the running status, if the operating state that the phase difference that detects phase discriminator 11 output enters during less than predefined first threshold value.In this operating state, the operating procedure of finishing comprises that processor 16 control filters adopt the numerical value of formula (2) calculating output, follows the tracks of running status and adopts less loop gain parameter, realizes the synchronous of frequency in and out in narrower bandwidth.Used formula with catch the same of state soon, that different is loop gain parameter a
1, a
2, b
0, b
1, b
2Parameter value.
(4) hold mode is a kind of operating state of External Reference clock source signals when losing, operating procedure under this state comprises: the numerical value of filter 12 outputs can be set at the numerical value that reference clock signal is not lost preceding last filter output, the frequency values of clock phase-locked loop output when losing the External Reference clock signal to keep.
In the present invention, the filter 12 output numerical value that keep in advance under this state utilization tracking mode are exported successively, and formula is as follows:
y[n]＝{y
follow|follow＝0，1.....n} ------------ (4)
See also Fig. 4, this figure is in " digital synchronous network nodal clock series and regularly characteristic " to netting the index request of synchronous 3 grades of nodal clock retention performances in People's Republic of China's communication industry standard.Curve a is the index that requirement is satisfied.Curve b is the operating procedure acquired character curve that adopts traditional hold mode.Curve c is the characteristic curve after the operating procedure of the identical hardware hold mode of having used this invention.Change algorithm for design by this figure explanation in the situation that does not change hardware circuit, obviously improved system index.
(5) out-of-lock condition is former thereby cause clock phase-locked loop can not lock the operating state that enters following the tracks of running status owing to External Reference clock signal deterioration etc., and the operating procedure that should finish in out-of-lock condition comprises: change parameter and catch new reference clock signal again with convenient.
In step S220, the redirect condition that state of a control jumps to other each states specifically comprises:
A1: clock phase-locked loop has just powered on and phase discriminator 11 does not receive reference clock signal, or
Previous state is that the state of catching soon and phase discriminator 11 do not receive reference clock signal, then the freedom of entry state;
B1: clock phase-locked loop has just powered on and phase discriminator 11 receives reference clock signal, or
Previous state is that free state, out-of-lock condition or hold mode and phase discriminator 11 receive reference clock signal, or
Previous state is tracking mode and Δ θ＞M
Fast, then enter and catch state soon, wherein Δ θ is the phase difference of phase discriminator 11, M
FastSecond threshold value for phase difference;
C1: previous state is the state of catching soon and Δ θ＜M
Follow, then enter tracking mode, wherein, Δ θ is the phase difference of phase discriminator 11, M
FollowFirst threshold value for phase difference;
D1: previous state is that tracking mode and phase discriminator 11 do not receive reference clock signal, then enters hold mode;
E1: previous state is hold mode and T＞t
Hold, then enter out-of-lock condition, wherein, T represents that phase-locked loop is in the running time of hold mode, t
HoldBe in the threshold value of hold mode for phase-locked loop.
The redirect condition that other each states jump to described state of a control specifically comprises:
A2: when the clock phase-locked loop is in free state and phase discriminator 11 and receives reference clock signal, jump to state of a control;
B2: when the clock phase-locked loop is in the state of catching soon, if Δ θ＜M
FollowSet up, or phase discriminator 11 do not receive reference clock signal, then jump to state of a control, wherein Δ θ is the phase difference of phase discriminator 11, M
FollowFirst threshold value for phase difference;
C2: when the clock phase-locked loop is in tracking mode, if Δ θ＞M
FastSet up, or phase discriminator 11 do not receive reference clock signal, then jump to state of a control, wherein Δ θ is the phase difference of phase discriminator, M
FastSecond threshold value for phase difference;
D2: when the clock phase-locked loop is in hold mode, if T＞t
Hold, or phase discriminator 11 do not receive reference clock signal, then jumps to state of a control, and wherein T represents that phase-locked loop is in the running time of hold mode, t
HoldBe in the threshold value of hold mode for phase-locked loop;
E2:,, then jump to state of a control if phase discriminator 11 receives reference clock signal when the clock phase-locked loop is in out-of-lock condition.
After below an act concrete example illustrates completing steps S210-S220, be how to carry out phase-locked control operation among the step S230.
After initially powering on, wait for the time of setting in advance, so that crystal oscillator can stably be worked, because the crystal oscillator of different manufacturers is different warm-up time, the time of setting can be set according to the crystal oscillator parameter that different manufacturers provides, after the time of processor 16 delay adjustmentses, just enter state of a control and judge;
Whether the phase discriminator 11 of judging clock phase-locked loop receives reference clock signal, catches state soon if then enter, otherwise the freedom of entry state;
If there is the clock source that to follow the tracks of, then enter and catch state soon, respective phases of operation among the execution in step S210 comprises the numerical value that utilization (2) formula calculating filter 12 is exported, output clock frequency with control crystal oscillator 14 can be more and more near reference clock frequency, when detecting Δ θ＜M
Follow(wherein, Δ θ is the phase difference of phase discriminator output, M in establishment
FollowFirst threshold value for phase difference), then enter state of a control;
State of a control is judged according to the decision condition that step S220 sets, is determined to enter tracking mode;
When the clock phase-locked loop entered tracking mode, the operating procedure that execution in step S210 is provided with was promptly according to the output numerical value of (2) formula calculating filter, with the output of control crystal oscillator 14.
That is, carry out redirect according to the redirect condition that step S220 sets, if jump to other states of non-control state, then the operating procedure of setting according to step S210 is carried out, and then finishes whole phase-locked control.Carry out phase-locked control according to method of the present invention, because the redirect of other states of non-control state is fairly simple, directly jump to state of a control, judge to jump to which state by state of a control, and under this state, as long as finish the preset operation step, improve control efficiency, and reduce the processing speed of processor, also reduced requirement simultaneously, and then reduce hardware cost processor performance.
The invention discloses several specific embodiments, but be not that any this area is carried out conspicuous improvement on this basis, all should fall into protection scope of the present invention in order to restriction the present invention.
Claims (8)
1, a kind of phase-locked control method of clock phase-locked loop, described clock phase-locked loop comprises processor, phase discriminator, filter and crystal oscillator at least, it is characterized in that, said method comprising the steps of:
(1) on described processor, be provided with respectively clock phase-locked loop freedom of entry state, catch the operating procedure that state, tracking mode, hold mode and out-of-lock condition are finished separately soon;
(2) on described processor, state of a control is set, determine that described state of a control jumps to the redirect condition of other each states and the redirect condition that other each states jump to described state of a control, described state of a control is in order to realize the differentiation of redirect between each state;
(3) after described clock phase-locked loop initially powers on, described processor is introduced into state of a control, and the redirect condition of setting according to step (2) enters corresponding state then, the operating procedure of correspondence in the execution in step (1), and then the phase-locked control of realization clock phase-locked loop.
2, the phase-locked control method of clock phase-locked loop as claimed in claim 1, step (3) also comprises:
When described clock phase-locked loop be in free state, when catching state, tracking mode, hold mode or out-of-lock condition soon, if satisfy be provided with in the step (2) jump to the redirect condition of described state of a control the time, jump to state of a control;
Jump to corresponding state by state of a control according to the redirect condition that is provided with in the step (2).
3, the phase-locked control method of clock phase-locked loop as claimed in claim 1 or 2 is characterized in that, the redirect condition that definite described state of a control jumps to other each states in the step (2) specifically comprises:
A1: clock phase-locked loop has just powered on and phase discriminator does not receive reference clock signal, or
Previous state is to catch state soon and phase discriminator does not receive reference clock signal, then the freedom of entry state;
B1: clock phase-locked loop has just powered on and phase discriminator receives reference clock signal, or
Previous state is that free state, out-of-lock condition or hold mode and phase discriminator receive reference clock signal, or
Previous state is tracking mode and Δ θ＞M
Fast, then enter and catch state soon, wherein Δ θ is the phase difference of phase discriminator, M
FastSecond threshold value for phase difference;
C1: previous state is the state of catching soon and Δ θ＜M
Follow, then enter tracking mode, wherein, Δ θ is the phase difference of phase discriminator, M
FollowFirst threshold value for phase difference;
D1: previous state is that tracking mode and phase discriminator do not receive reference clock signal, then enters hold mode;
E1: previous state is hold mode and T＞t
Hold, then enter out-of-lock condition, wherein, T represents that phase-locked loop is in the running time of hold mode, t
HoldBe in the threshold value of hold mode for phase-locked loop.
4, the phase-locked control method of clock phase-locked loop as claimed in claim 3 is characterized in that, the redirect condition that other each states described in the step (2) jump to described state of a control specifically comprises:
A2: when the clock phase-locked loop is in free state and phase discriminator and receives reference clock signal, jump to state of a control;
B2: when the clock phase-locked loop is in the state of catching soon, if Δ θ＜M
FollowSet up, or phase discriminator do not receive reference clock signal, then jump to state of a control, wherein Δ θ is the phase difference of phase discriminator, M
FollowFirst threshold value for phase difference;
C2: when the clock phase-locked loop is in tracking mode, if Δ θ＞M
FastSet up, or phase discriminator do not receive reference clock signal, then jump to state of a control, wherein Δ θ is the phase difference of phase discriminator, M
FastSecond threshold value for phase difference;
D2: when the clock phase-locked loop is in hold mode, if T＞t
Hold, or phase discriminator do not receive reference clock signal, then jumps to state of a control, and wherein T represents that phase-locked loop is in the running time of hold mode, t
HoldBe in the threshold value of hold mode for phase-locked loop;
E2: handle out-of-lock condition when the clock phase-locked loop,, then jump to state of a control if phase discriminator receives reference clock signal.
5, the phase-locked control method of clock phase-locked loop as claimed in claim 1 or 2 is characterized in that, the free state complete operation step that is provided with in the step (1) comprises that the clock frequency of clock phase-locked loop output is the centre frequency of crystal oscillator.
6, the phase-locked control method of clock phase-locked loop as claimed in claim 1 or 2 is characterized in that, the operating procedure that state of catching soon that is provided with in the step (1) and tracking mode are finished comprises according to y (n)=a
1Y (n-1)+a
2Y (n-2)+b
0X (n)+b
1X (n-1)+b
2X (n-2), the numerical value of calculating filter output is with the clock frequency of control crystal oscillator output, wherein a
1, a
2, b
0, b
1, b
2Be the loop gain parameter, x (n) is the phase difference of input, and y (n) is the numerical value of filter output, and n is a number of times.
7, the phase-locked control method of clock phase-locked loop as claimed in claim 1 or 2 is characterized in that, the operating procedure of described hold mode comprises y[n]={ y
Follow| follow=0,1.....n} are as the input crystal oscillator parameter of filter, and wherein y (n) is the numerical value of filter output, and n is a number of times.
8, the phase-locked control method of clock phase-locked loop as claimed in claim 1 is characterized in that, step also comprises in (3), when detecting described clock phase-locked loop and just powered on, delay time after the predefined time, just carry out the redirect of various states, so that the crystal oscillator steady operation.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108418579A (en) * | 2018-04-08 | 2018-08-17 | 中船重工（武汉）凌久电气有限公司 | A kind of output sine wave phose-lock phase shifter and sinusoidal locking phase Phase-shifting algorithm |
| CN110581742A (en) * | 2018-06-08 | 2019-12-17 | 大唐移动通信设备有限公司 | clock synchronization method, system and base station |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1283021C (en) * | 2003-06-30 | 2006-11-01 | 风帆股份有限公司 | A novel electrolyte |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108418579A (en) * | 2018-04-08 | 2018-08-17 | 中船重工（武汉）凌久电气有限公司 | A kind of output sine wave phose-lock phase shifter and sinusoidal locking phase Phase-shifting algorithm |
| CN108418579B (en) * | 2018-04-08 | 2024-02-13 | 中船重工（武汉）凌久电气有限公司 | Output sine wave phase-locking phase-shifting device and sine phase-locking phase-shifting algorithm |
| CN110581742A (en) * | 2018-06-08 | 2019-12-17 | 大唐移动通信设备有限公司 | clock synchronization method, system and base station |
| CN110581742B (en) * | 2018-06-08 | 2020-12-04 | 大唐移动通信设备有限公司 | Clock synchronization method, system and base station |
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| Publication number | Publication date |
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| CN1758542B (en) | 2010-04-14 |
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