CN1755762A - Timing generating circuit for display and display having the same - Google Patents

Abstract

A timing generation circuit ( 15 ) is formed integrally on the same glass substrate ( 11 ) together with a display area section ( 12 ) similarly to an H driver ( 13 U) and a V driver ( 14 ), and timing pulses to be used by the H driver ( 13 U) and the V driver ( 14 ) are produced based on timing data produced by a shift register ( 31 U) of the H driver ( 13 U) and a shift register ( 14 A) of the V driver ( 14 ). The invention thereby provides a timing generation circuit which can contribute to miniaturization and reduction of the cost of the set and a display apparatus of the active matrix type in which the timing generation circuit is incorporated.

Description

Display device timing signal generator circuit and the display device that comprises this timing signal generator circuit

Technical field

The present invention relates to the timing signal generator circuit and the display device that comprises timing signal generator circuit of display device, more precisely, relate to a kind of timing signal generator circuit, its produces the various timing pips of the drive system be used to control active matrix type display, and the active matrix type display that comprises timing signal generator circuit.

Technical background

In recent years, portable terminal, for example, pocket telephone and PDA(Personal Digital Assistant) have obtained to popularize greatly.The output display part that the reason that portable terminal is popularized so rapidly is exactly a portable terminal has comprised liquid crystal indicator.Its reason is that liquid crystal indicator does not need the high power driving basically and is a kind of low power consumption display device.

Have that pixel is arranged in rows and columns in (matrix) and the display device of driven configuration respectively, for example above-mentioned liquid crystal indicator comprises with behavior unit and selects the vertical drive system of pixel and information is write horizontal driving system in each pixel of the row of being chosen by the vertical drive system.They are used for the various timing pips of the described drive system of drive controlling.

According to horizontal-drive signal HD, vertical synchronizing signal VD and master clock signal MCK, use special-purpose timing signal for generating counter circuit etc. with the described timing pip of suitable timing sequence generating.The timing pulse generator circuit that produces timing pip is formed on the monocrystalline silicon substrate usually, and this substrate is isolated with the substrate of formation viewing area part on it.

Wherein, be in the display device of representative with the liquid crystal indicator, as mentioned above, the timing signal generator circuit that generation is used for the various timing signals of display driver be formed on its on form the substrate that the substrate of viewing area part separates, therefore, the parts that are used to constitute this device have increased, and they must produce by technological process separately.Therefore, there is the problem microminiaturized and the reduction installation cost that hinders.

Therefore, the purpose of this invention is to provide a kind of display device timing signal generator circuit, it helps the microminiaturized of device and reduces cost, and the display device that comprises this timing signal generator circuit.

Summary of the invention

In order to achieve the above object, according to the present invention, a kind of display device comprises following each several part: the viewing area part, and wherein, the pixel that has electrooptic cell separately is arranged in rows and columns; Vertical drive circuit is used for the pixel with behavior unit's selection viewing area part; And horizontal drive circuit, be used for picture signal is offered each pixel of row of being chosen by vertical drive circuit, in this display device, dispose timing signal generator circuit like this, make its according to the timing signal that produces by the timing information of at least one generation in vertical drive circuit and the horizontal drive circuit by at least one use in vertical drive circuit and the horizontal drive circuit.

In the timing signal generator circuit of above-mentioned configuration or comprising in the display device of described timing signal generator circuit, produce timing signal according to timing information, this means that the part of at least one is used to produce timing signal in vertical drive circuit and the horizontal drive circuit by at least one generation in vertical drive circuit and the horizontal drive circuit.Therefore, can assign to simplify the circuit arrangement of timing signal generator circuit by means of the circuit part that also is used to produce timing signal.

Description of drawings

Fig. 1 is the configuration view of demonstration according to the signal of the profile instance of display device of the present invention;

Fig. 2 is the circuit diagram that shows liquid crystal indicator viewing area part profile instance;

Fig. 3 is the block scheme that shows the concrete profile instance of H driver;

Fig. 4 is the block scheme of demonstration according to the profile instance of the active matrix type display of first embodiment of the invention;

Fig. 5 is the block scheme of the concrete configuration example of Displaying timer signal generating circuit;

Fig. 6 is the sequential chart of the operation of the described timing signal generator circuit of graphic extension;

Fig. 7 is the block scheme of demonstration according to the profile instance of the active matrix type display of second embodiment of the invention;

Fig. 8 is the circuit diagram that shows the profile instance of negative voltage generation type charge-pump type D/D converter;

Fig. 9 is the sequential chart of the operation of graphic extension negative voltage generation type charge-pump type D/D converter;

Figure 10 is the circuit diagram that shows the profile instance of boosting type charge-pump type D/D converter;

Figure 11 is the sequential chart of the operation of graphic extension boosting type charge-pump type D/D converter;

Figure 12 is the block scheme that shows according to the active array type LCD profile instance of third embodiment of the invention, shows the situation that the H driver only is set at viewing area part upside among the figure;

Figure 13 is the block scheme that shows shift register concrete configuration example;

Figure 14 is the sequential chart of graphic extension shift register operation;

Figure 15 is the block scheme that shows according to the active array type LCD profile instance of third embodiment of the invention, is presented at the situation that viewing area part upside and downside all are provided with the H driver among the figure;

Figure 16 is the sequential chart of graphic extension according to the operation of the active array type LCD of the 3rd embodiment;

Figure 17 shows the block scheme that electrode voltage is produced the concrete configuration example of circuit;

Figure 18 is graphic extension produces the operation of circuit to electrode voltage a sequential chart;

Figure 19 is the block scheme that shows DC level shifting circuit profile instance;

Figure 20 shows that dc voltage produces the circuit diagram of circuit concrete configuration first example;

Figure 21 shows that dc voltage produces the circuit diagram of circuit concrete configuration second example;

Figure 22 shows that dc voltage produces the circuit diagram of circuit concrete configuration the 3rd example;

Figure 23 shows that dc voltage produces the circuit diagram of circuit concrete configuration the 4th example;

Figure 24 shows that dc voltage produces the circuit diagram of circuit concrete configuration the 5th example;

Figure 25 is the circuit diagram that shows the element circuit profile instance of reference voltage selection type D/A converter circuit;

Figure 26 is the circuit diagram that shows the general profile instance of generating circuit from reference voltage;

Figure 27 is the block scheme that shows generating circuit from reference voltage layout example;

Figure 28 is the circuit diagram that shows generating circuit from reference voltage concrete configuration example;

Figure 29 is the sequential chart of graphic extension generating circuit from reference voltage operation;

Figure 30 shows the block scheme that electrode voltage is produced the circuit application example;

Figure 31 is the view with TFT plane pattern of double-grid structure;

Figure 32 is the view of cross-section structure with TFT of bottom-gate structure;

Figure 33 is the view of cross-section structure with TFT of top grid structure;

Figure 34 is the view of cross-section structure with TFT of double-grid structure;

Figure 35 is the circuit diagram that shows the concrete configuration example of sampling latch circuit;

Figure 36 is the arrangement plan of demonstration according to the signal of another example of the configuration of display device of the present invention; And

Figure 37 is the external view that shows the common configuration of pocket telephone, and described pocket telephone is that the present invention is applied to portable terminal wherein.

Embodiment

Describe each embodiment of the present invention in detail below with reference to accompanying drawing.

Fig. 1 is the arrangement plan of demonstration according to the signal of the profile instance of display device of the present invention.As an example, only the present invention is used for a kind of situation of active array type LCD and is illustrated, in this device, comprise liquid crystal cell as the electrooptic cell of each pixel.

With reference to figure 1, on transparent insulation substrate, for example glass substrate 11, form viewing area part 12, a large amount of pixels of each self-contained liquid crystal cell are arranged in matrix in this viewing area part 12.This glass substrate 11 is made of first substrate and second substrate, in first substrate, a large amount of image element circuits that comprise active device (for example, transistor) are separately arranged with the form of row and column, second substrate is arranged on the opposite of first substrate, leaves predetermined slit in the middle of them.Liquid crystal material is sealed in the space between first and second substrates, forms LCD panel.

The concrete configuration example of the part of viewing area shown in Fig. 2 12.Here, in order to simplify pixels arrangement that accompanying drawing only illustrates 3 row (it is capable that n-1 walks to n+1) and 4 row (m-2 be listed as to m+1 be listed as) as an example.In Fig. 2, vertical scan line ..., 21n-1,21n, 21n+1 ..., and data line ..., 22m-2,22m-1,22m, 22m+1 ..., with the form wiring of matrix, and unit pixel 23 is arranged on each point of crossing of vertical scan line and data line.

Unit pixel 23 comprises: thin film transistor (TFT) (thin film transistor (TFT); TFT) 24, it is a pixel transistor; Liquid crystal cell 25, it is an electrooptic cell; And holding capacitor 26.Here, liquid crystal cell 25 mean the pixel electrode that constitutes by thin film transistor (TFT) (back is referred to as TFT) 24 and the pixel electrode opposite constitute to electrode between the liquid crystal capacitor that produces.

The grid of TFT 24 is connected to vertical scan line ..., 21n-1,21n, 21n+1 ..., and the source electrode of TFT 24 is connected to data line ..., 22m-2,22m-1,22m, 22m+1 ....The pixel electrode of liquid crystal cell 25 is connected to the drain electrode of TFT 24, and liquid crystal cell 25 electrode is connected to common line 27.Holding capacitor 26 is connected between the drain electrode and common line 27 of TFT 24.Voltage (common electric voltage) Vcom to electrode offers common line 27.Therefore,, common electric voltage Vcom be added to liquid crystal cell LC, each pixel is common on the electrode.

Upper and lower a pair of H driver (horizontal drive circuit) 13U and 13D and V driver (vertical drive circuit) 14 are formed on the glass base 11 in integrated mode with viewing area part 12.Each bar vertical scan line of viewing area part 12 ..., 21n-1,21n, 21n+1 ... a terminal be connected to the lead-out terminal of the V driver 14 of delegation corresponding in each row.

V driver 14 is formed by for example shift register and synchronously produces vertical strobe pulse continuously and it is added to vertical scan line with vertical transmission clock VCK (not shown) ..., 21n-1,21n, 21n+1 ..., to carry out vertical scanning.Simultaneously, in viewing area part 12, for example, each odd data line ..., 21m-1,21m+1, ... a terminal be connected to the lead-out terminal of the H driver 13U of row corresponding in each row, and even data line ..., 22m-2,22m ... other each terminal be connected to the lead-out terminal of the H driver 13D of row corresponding in each row.

In active array type LCD, if the sweep signal from V driver 14 is transported to vertical scan line ..., 21n-1,21n, 21n+1 ..., so, the drain electrode of the TFT 24 of each pixel that is connected with vertical scan line and the resistance decreasing between the source electrode, answer the response image signal and the voltage that provides from each H driver 13U and 13D by each data line ..., 22m-2,22m-1,22m, 22m+1, ..., be added to the pixel electrode of liquid crystal cell.So, utilize described voltage finish to be enclosed in pixel electrode and to the modulation of the liquid crystal material optical characteristics between the electrode so that display image.

Fig. 3 has shown the concrete configuration of H driver 13U and 13D.As shown in Figure 3, H driver 13U comprises: shift register 31U; Sampling latch circuit (data signal input circuit) 32U; Line ordering latch cicuit 33U; And D/A translation circuit 34U.Shift register 31U sequentially synchronously exports dfisplacement pulse from its each transport level with horizontal tranmitting data register HCK (not shown), scans with executive level.Sampling latch circuit 32U with point sequence response is offered its shift pulse and the Digital Image Data of the predetermined bit imported is sampled, so that latch described Digital Image Data.

Line ordering latch cicuit 33U latchs the Digital Image Data that is latched with point sequence by sampling latch circuit 32U with behavior unit once more, and delegation's ground output digital image data.D/A translation circuit 34U has a kind of configuration, for example, and reference voltage selection type circuit, and will be transformed into analog picture signal from delegation's Digital Image Data of line ordering latch cicuit 33U output and offer the data line of pixel region part 12 ..., 22m-2,22m-1,22m, 22m+1 ....

Equally, downside H driver 13D comprises: shift register 31D; Sampling latch circuit 32D; Line ordering latch cicuit 33D; And reference voltage selection type D/ A translation circuit 34D, 13U is quite similar with upside H driver.Should be understood that, though the configuration of adopting upside and downside in viewing area part 12 that H driver 13U and 13D are set according to the active array type LCD of this example, but, active array type LCD does not have these restrictions, and can take another kind of configuration, wherein, a upside or a downside in viewing area part 12 are provided with H driver 13U and 13D.

Equally, peripheral circuit, for example, timing signal generator circuit 15, power circuit 16 produces circuit 17 and generating circuit from reference voltage 18 is integrated on the glass substrate 11 with viewing area part 12 to electrode voltage, and this and H driver 13U and 13D and V driver 14 are similar.According to this integrated morphology, constitute all circuit components of foregoing circuit, perhaps the active component (or active/passive element) in them is formed on the glass substrate 11 at least.Therefore, owing to do not have active (or not having the active/passive element) to appear at outside the glass substrate 11, so thereby the configuration that can simplify the peripheral cell of substrate can realize microminiaturization and reduction installation cost.

Here, for example, liquid crystal indicator has such configuration, wherein, H driver 13U and 13D are arranged on the upside and the downside of viewing area part 12, peripheral circuit, for example timing signal generator circuit 15, power circuit 16, electrode voltage are produced frame (frame) district (outer peripheral areas of viewing area part 12) that circuit 17 and generating circuit from reference voltage 18 are preferably disposed on the one or both sides that H driver 13U and 13D are not set.

Its reason is, because when relatively and under great majority have the situation of very large circuit region (these circuit are arranged in frame (frame) district of one or both sides with above-mentioned V driver 14, H driver 13U and 13D are not disposed thereon), H driver 13U and 13D comprise a large amount of elements, so, peripheral circuit, for example timing signal generator circuit 15, power circuit 16, can be integrated on the same glass substrate 11 electrode voltage generation circuit 17 and generating circuit from reference voltage 18, as viewing area part 12, do not change effective ratio (useful area part 12 compares with the area of glass substrate 11) of screen.

Active array type LCD according to this example adopts following configuration, wherein, because V driver 14 is installed in the side in the both sides that H driver 13U and 13D are not set of rim area, so, peripheral circuit, for example timing signal generator circuit 15, power circuit 16, electrode voltage is produced the relative side that circuit 17 and generating circuit from reference voltage 18 just are installed in a side described in the rim area.

[first embodiment]

Fig. 4 is the block scheme of demonstration according to the profile instance of the active matrix type display of first embodiment of the invention.Here, for simplifying accompanying drawing, the H driver 13U of upside only is shown.Yet, the relation of and H driver 13U also similar with the relation of another H driver 13D of downside.

Timing signal generator circuit 15 receives from the outside horizontal-drive signal HD that offers it as input signal, vertical synchronizing signal VD and major clock MCK, and reference-input signal, at first form horizontal enabling pulse HST and the horizontal transmission clock HCK of the shift register 31U offer H driver 13U and the vertical enabling pulse VST and vertical transmission clock VCK that offer the shift register 14A of V driver 14.

Here, horizontal enabling pulse HST is that pre-after producing horizontal-drive signal HD determined the pulse signal that produces after the period, and horizontal transmission clock HCK is the pulse signal by major clock MCK frequency division is obtained for example.Vertical enabling pulse VST is the pulse signal that produces behind the scheduled time slot after producing vertical synchronizing signal VD, and vertical transfer pulse VCK is the pulse signal by horizontal transmission clock HCK frequency division is obtained for example.

Therefore, be used in the timing signal generator circuit 15 according to horizontal-drive signal HD, vertical synchronizing signal VD with major clock MCK and the circuit of the horizontal enabling pulse HST of generation, horizontal transmission clock HCK, vertical enabling pulse VST and vertical transfer pulse VCK can utilize the simple counter circuit with some grades to realize.

Also dispose timing signal generator circuit 15 like this, make it receive the timing data that obtains from the suitable transport level of the shift register 31U of H driver 13U with the form of input signal, and the timing data (temporal information) that obtains from the suitable transport level of the shift register 14A of V driver 14, and produce the time pulse that time pulse that H driver 13U uses and V driver 14 use according to the timing data of input.

Here, the same with the timing pip that uses by H driver 13U, for example can obtain the gating pulse that latchs that line ordering latch cicuit 33U that Fig. 3 shows uses.Yet timing pip is not limited to this.Simultaneously, the same with the timing pip that uses by V driver 14, for example can obtain the display cycle gating pulse, it is used for (wherein only carrying out demonstration in some cycle on the vertical direction of viewing area part 12) when display device is in the part display mode and determines the display cycle.But timing pip is not limited to this.

Fig. 5 is the block scheme of Displaying timer signal generating circuit 15 concrete configuration examples.Here, only a kind of situation is described, wherein, timing signal generator circuit 15 produces the gating pulse that latchs by line ordering latch cicuit 33U use, the described gating pulse that latchs is to produce to its timing data that provides according to the shift register 31U from H driver 13U

Referring to Fig. 5, the shift register 31U of H driver 13U comprises M level D class trigger (hereinafter being referred to as DFFs) 41-1 to 41-M, and wherein M is greater than the number of pixels N on viewing area part 12 horizontal directions.When horizontal enabling pulse HST is provided to it, has synchronously executable operations of the shift register 31U of the configuration that has just illustrated and horizontal transmission clock HCK.Like this, export and the synchronous train pulse (timing information) of horizontal transmission clock HCK from each Q output terminal of DFFs 41-1 to 41-M.

The Q output pulse of DFFs 41-1 to 41-M offers sampling latch circuit 32U continuously as sampling pulse.And, in suitable transport level, some pulses in the Q of DFFs 41-1 to the 41-M output pulse, here as an example, the Q output pulse B of the DFF 41-M of the Q of first order DFF 41-1 output pulse A and M-1 level is provided for timing signal generator circuit 15.

In timing signal generator circuit 15, produce the gating pulse generation circuit 42 that latchs that latchs gating pulse and comprise for example DFF 43 and impact damper 44.DFF 43 receives on the first order by shift register 31U Q output pulse A as the DFF 41-1 of input clock (CK) is provided, and the Q output pulse B that receives the DFF 41-M-1 on the M-1 level is as removing (CLR) input, and the Q output that receives the paraphase of DFF 43 itself is imported as data (D).

Therefore, as what can obviously see from the sequential chart of Fig. 6, after the time to the time of the rising edge of the Q output pulse B of DFF 41-M-1 of the rising edge of the Q of DFF 41-1 output pulse A in the one-period, can obtain to present by buffer zone 44 from the Q lead-out terminal of DFF 43 " H " pulse of level (high level), as latching gating pulse C.

As mentioned above, in the timing signal generator circuit 15 of display device, in order to produce timing pip by H driver 13U and 13D and 14 uses of V driver, usually use H driver 13U and the shift register 31U of 13D and the shift register 14A of 31D and V driver 14, and produce timing pip according to the time data that obtains from shift register.Therefore, need be such as the special circuit of counter circuit, thereby can simplify circuit arrangement.Like this, microminiaturization that can implement device, cost reduce and power consumption reduces.

Particularly, because the circuit arrangement of timing signal generator circuit 15 is very simple and low in energy consumption, so, timing signal generator circuit 15 and viewing area part 12 are integrated on the same glass substrate 11 as H driver 13U and 13D and V driver 14 together, thereby can realize reducing border width, reduce cost and reducing the power consumption of display device.

Should be understood that, though being described in the present embodiment, the circuit component that is used for reference levels synchronizing signal HD, vertical synchronizing signal VD and the horizontal enabling pulse HST of major clock MCK generation, horizontal transmission clock HCK, vertical enabling pulse VST and vertical transfer pulse VCK is integrated in glass substrate 11, but the foregoing circuit element can be formed on the independent glass substrate that separates with glass substrate.This is because realize that owing to circuit component can use simple counter circuit therefore, separate on the substrate even be formed on, the configuration of peripheral circuit can be very not complicated yet.

In addition, though being described, present embodiment supposed such configuration, wherein, utilize shift register to form H driver 13U and 13D and V driver 14, but the present invention is not limited to the situation of using shift register, and can be applied to other configuration equally, wherein, dissimilar counter circuits is used for H driver 13U and 13D and V driver 14, unique condition is that they are to the counting operation of H driver 13U and 13D and 14 implementation address controls of V driver and execution generation time data.

[second embodiment]

Fig. 7 is the block scheme of demonstration according to the profile instance of the active matrix type display of second embodiment of the invention, among Fig. 7, represents with identical reference character with the components identical of Fig. 4.Equally, in order to simplify accompanying drawing, the H driver 13U of upside only is shown here.Yet, be similar to relation with H driver 13U with the relation object of another H driver 13D of downside.

Like this configuration according to the active matrix type display of present embodiment, make timing signal generator circuit 15 also produce the timing pip that uses by power circuit 16.Power circuit 16 is made of the power supply voltage converting circuit (DC-DC converter) of for example charge-pump type, and the single DC supply voltage VCC that the outside provides is converted to the dc voltage that multichannel has different magnitudes of voltage mutually, and these dc voltages are offered internal circuit as supply voltage, such as H driver 13U and 13D and V driver 14.

The following describes the concrete configuration of power circuit 16.As an example, only a kind of situation of charge-pump type power supply voltage converting circuit (hereinafter being referred to as charge-pump type D/D converter) as power circuit 16 described here.

Fig. 8 is the circuit diagram that shows negative voltage generation type charge-pump type D/D converter.For charge-pump type D/D converter, from timing signal generator circuit 15 provide as timing pip be used to carry out the time clock of blocked operation and be used to carry out the clamped pulse of clamped operation.

Referring to Fig. 8, P channel MOS transistor Qp11 and N-channel MOS transistor Qn11 are connected between the power supply and ground wire (GND) that single DC supply voltage VCC is provided, and its grid connects by usual method, thereby constitute CMOS phase inverter 45.The timing pip that timing signal generator circuit 15 provides is as the switch pulse of the grid common node of CMOS phase inverter 45.

The terminal of capacitor C11 is connected to the drain electrode common node (node B) of CMOS phase inverter 45.Another terminal of capacitor C11 is connected to the drain electrode of N-channel MOS transistor Qn12 and the source electrode of P channel MOS transistor Qp12.Load capacitor C12 is connected between the source electrode and ground wire of N-channel MOS transistor Qn12.

The terminal of capacitor C13 is connected with the grid common node of CMOS phase inverter 45.Another terminal of capacitor C13 is connected with the positive pole of diode D11.In addition, the grid of N-channel MOS transistor Qn12 and P channel MOS transistor Qp12 is connected with another terminal of capacitor C13.The grounded drain of P channel MOS transistor Qp12.

P channel MOS transistor Qp13 is connected between another terminal and ground of capacitor C13.The timing pip that provides by timing signal generator circuit 15, be clamped pulse, after carrying out level shift, offer the grid of P channel MOS transistor Qp13 by level shift circuit 46.The switch pulse voltage that P channel MOS transistor Qp13 and level shift circuit 46 constitute switching transistor (N-channel MOS transistor Qn12 and P channel MOS transistor Qp12) carries out clamped clamped circuit.

In described clamped circuit, level shift circuit 46 uses the DC supply voltage VCC that is input to the D/D converter as positive lateral circuit power supply, and use the D/D converter output voltage Vout that derives from the relative terminal of viewing area part 12 as the minus side circuit power, be Vcc-O[V to the amplitude that provides from timing signal generator circuit 15 then] clamped pulse carry out level shift, becoming another amplitude is Vcc-Vout[V] clamped pulse, and the clamped pulse behind the level shift is added to the grid of P channel MOS transistor Qp13.Like this, the blocked operation of P channel MOS transistor Qp13 is just realized with higher reliability.

The circuit operation of the negative voltage generation type charge-pump type D/D converter with above-mentioned configuration is described with reference to the sequential chart of figure 9 now.In this sequential chart, the waveform of the signal of node A to G in waveform A to G difference presentation graphs 8 circuit.

When startup power supply (when starting), the starting voltage Vth that utilizes diode D11 to based on the output potential of the capacitor C13 of the switch pulse that provides by timing signal generator circuit 15, promptly, that current potential on the node D carries out " H " level is clamped, with its clamped current potential after carrying out level shift from ground (GND) level, described ground level is the power supply potential of minus side circuit.

Therefore, when the switch pulse level be that " L " is (0V) time, because P channel MOS transistor Qp11 and Qp12 are in on-state, so capacitor C11 is recharged.At this moment, because N-channel MOS transistor Qn11 is in cut-off state, so the current potential on the node B equals the Vcc level.Therefore, when switch pulse was changed into " H " level (Vcc), N-channel MOS transistor Qn11 and Qn12 were in on-state, and the current potential on the node B just equals earth potential (0V).Therefore, the current potential on the node C equals-the Vcc level.Current potential on the node C by N-channel MOS transistor Qn12 and produce output voltage V out (=-Vcc).

Then, when output voltage V out rose to a certain degree (finishing up to starting process), the level shift circuit 46 of clamped pulse brought into operation.After level shift circuit 46 brings into operation, the amplitude that is provided by timing signal generator circuit 15 is Vcc-0[V] clamped pulse, is Vcc-Vout[V by level shift circuit 46 level shifts to amplitude] clamped pulse, just be added on the grid of P channel MOS transistor Qp13 later.

At this moment and since " L " level of clamped pulse be output voltage V out, promptly-Vcc, be in on-state really so P channel MOS transistor Qp13 can think.Therefore, the current potential on the node D is by on the clamped current potential behind level shift of the starting voltage Vth of the diode D11 of ground level, but clamped on ground level (power supply potential of minus side circuit).Therefore, in service in the later pumping of charge-pump type circuit, P channel MOS transistor Qp12 can obtain enough driving voltages.

In the charge-pump type D/D of above-mentioned configuration converter, clamped operation in the controlling impulse voltage (switched voltage) of the switching device (N-channel MOS transistor Qn12 and P channel MOS transistor Qp12) of the output of charge-pump type D/D converter divides two steps to realize, comprise at first clamped by diode D11, the clamped circuit that is made of P channel MOS transistor Qp13 and level shift circuit 46 is clamped after finishing starting process then.Therefore, P channel MOS transistor Qp12 can obtain enough driving voltages.

Like this, owing to can obtain enough switch currents, just can realize stable DC-DC conversion operations, and can improve conversion efficiency from P channel MOS transistor Qp12.Particularly, even the transistor size of P channel MOS transistor Qp12 does not increase, owing to can obtain enough switch currents, the power supply voltage converting circuit of high current capacity can be realized by enough small size circuit.To having the transistor of high starting voltage Vth, for example, the application of thin film transistor (TFT) is effective especially for this effect.

The configuration of boosting type charge-pump type D/D converter is shown in Figure 10.Equally, boosting type D/D converter is similar to negative voltage generation type D/D converter in basic circuit configuration and circuit operation.

In more detail, referring to Figure 10, dispose boosting type charge-pump type D/D converter like this, make switching transistor and clamped transistor (MOS transistor Qp14, Qn14 and Qn13) have a conduction type opposite with Qp13 with MOS transistor Qn12, the Qp12 of Fig. 8 circuit, and diode D11 is connected between another terminal and power supply (VCC) of capacitor C11, in addition, the power supply of the positive lateral circuit of output voltage V out conduct of the current circuit of level shift circuit 46 uses also uses the power supply of ground level as the minus side circuit, is different from the configuration of Fig. 8 circuit in this respect.

Boosting type charge-pump type D/D converter and Fig. 8 circuit are identical basically aspect circuit operation.Described circuit operation is only gone up different at switch pulse voltage (controlling impulse voltage), the switch pulse voltage of this circuit when starting at first by diode clamping, then after starting process is finished by clamped on VCC level (positive lateral circuit power supply potential), and the magnitude of voltage 2 * VCC that derives supply voltage VCC twice is as output voltage V out.The sequential chart of signal waveform A to G in the circuit of Figure 10 on the node A to G is shown in Figure 11.

The circuit arrangement of above-mentioned charge-pump type D/D converter is example only, and the circuit arrangement of described charge pump circuit can be used multi-form modification, is not limited to the foregoing circuit profile instance.

Should be understood that, in above-mentioned first and second embodiment, the clamped pulse of being used by the latch cicuit 27U of H driver 13U and 13D and 27D of latching gating pulse and switch pulse and being used by the power circuit 16 that charge-pump type power supply voltage converter circuit constitutes is all as the example of the timing pip that is produced by timing signal generator circuit 15, and the timing pip that is produced by timing signal generator circuit 15 is not limited to these.

As an example, dispose V driver 14 like this, make it comprise that output allows circuit, this circuit is the output scanning pulse when receiving output permission pulse, the output that described output allows circuit to use allows pulse to be produced by timing signal generator circuit 15, perhaps, like this configuration display device, make its operating part screen display mode selectively, only with a part of regional display message of viewing area part, this is a kind of power saving mode, and the control signal of described part screen display mode (gating pulse) can be produced by timing signal generator circuit 15.

By the way, usually, two kinds of tranmitting data registers with phases opposite are used to each transmit status of the shift register that is made of the 13U of H driver and 13D or V driver 14.Yet, here adopt such configuration, wherein send each transport level that quarter-phase transmission clocks and described quarter-phase transmission clock are provided for shift register by two clock lines, since they send to the quarter-phase tranmitting data register shift register each send stage in, two clock lines must cross one another, so there is such possibility: may increase the consumption of power supply and because the increase of the load capacitance of the cross section of wiring route may cause the delay of phase place.

In addition, in H driver 13U and 13D, for example, under digital interface driving circuit situation, as mentioned above, owing to dispose described digital interface driving circuit like this, make it except shift register 31U and 31D, also comprise sampling latch circuit 32U and 32D, line ordering latch cicuit 33U and 33D and D/A change- over circuit 34U and 34D, so, two lines that transmit the quarter-phase transmission clock respectively intersect on many positions mutually, thereby, there is such possibility: may increase power consumption, and the load capacitance of crossover location may cause the delay of phase place.For H driver 13U and 13D, because the transmission frequency height, this influence is obvious especially.

Under the circumstances, according to the display device of following the 3rd embodiment, for example, will dispose source matrix type lcd device.Figure 12 is the block scheme that shows according to the active array type LCD example of third embodiment of the invention configuration, and in Figure 12, is similar to those elements of Fig. 4 with similar reference character representation class.

In active array type LCD, suppose that in H driver 13, shift register 31 is arranged at the ragged edge with respect to viewing area part 12 according to present embodiment.And in the various timing signals by timing signal generator circuit 15 generations, horizontal transmission clock HCK is the single-phase clock that is divided into two and obtains by with major clock MCK.Here, the clock of major clock MCK (Dot Clock) frequency depends on pixel (point) number on the horizontal direction of viewing area part 12.

Single-phase horizontal transmission clock HCK is added to by buffer circuit 52 and is routed in respect to the shift register 31 of viewing area part 12 clock line 51 of outside more.Clock line 51 connects up along transmission (displacement) direction of shift register 31, and single-phase horizontal transmission clock HCK is added to each transport level of shift register 31.

Here, dispose source matrix type lcd device like this, make shift register 31 be arranged in ragged edge with respect to viewing area part 12, like this, the clock line 51 that is used to send single-phase horizontal transmission clock HCK is routed in than shift register 31 outside more, and clock line 51 can not have across the next stage that is connected to shift register 31 from shift register 31 with the output wiring route and samples on the clamped circuit 32.Therefore, the wiring route electric capacity of clock line 51 can reduce, so the frequency of horizontal transmission clock HCK can improve, and can reduce power consumption.

Particularly, because single-phase horizontal transmission clock HCK is the clock signal that is divided into two and obtains by with Dot Clock, so the frequency of horizontal transmission clock HCK just is Dot Clock half, thereby, can further reduce power consumption by reducing clock frequency.In addition, because the high speed circuit operation is possible, expectation further improves resolution, single H driver just can be handled these, do not need to be provided with the H driver of a plurality of parallel processings, thereby, can not increase the numbers of terminals of interface or do not carry out parallel processing and just can realize high-definition display device.

(instantiation of shift register 31)

Figure 13 is the block scheme that shows the physical circuit configuration of shift register 31.Here, in order to simplify accompanying drawing, the transport level 31n of n level and another transport level 31n+1 level of n+1 level only are shown.Yet other transport level also has very identical configuration.And for concrete configuration is described, as an example, only the transport level 31n to the n level is described.

Referring to Figure 13, switch 51 is connected between the transport level 31n of clock line 51 and n level.Under the control of clock selecting control circuit (explanation hereinafter), switch 53 is carried out logical (connection)/disconnected (disconnection) operation, thereby optionally offering n level transport level 31n by clock line 51 to the horizontal transmission clock HCK of its transmission.

The transport level 31n of n level comprises: latch cicuit 54 is used to latch by switch 53 optionally to its horizontal transmission clock HCK that provides; Buffer circuit 55 is used for the latch pulse of latch cicuit 54 is offered the sampling latch circuit 32U of next stage; And the clock selecting control circuit, for example, OR circuit, be used for according to the latch pulse Ain of previous stage and latch pulse Aout at the corresponding levels switch 56 be controlled at logical and disconnected between.

With reference now to the sequential chart of Figure 14,, the circuit operation of the shift register 31 with above-mentioned configuration is described.

When from previous stage (n-1 level) transport level input and latch pulse Ain, latch pulse Ain is by OR circuit 56 and offer switch 53 so that make switch 53 carry out making operation.Therefore, the horizontal transmission clock HCK that is sent by clock line 51 offers n level transport level 31n by switch 53 and is latched by latch cicuit 54.

After latch pulse Ain disappeared, the latch pulse Aout of latch cicuit 54 at the corresponding levels offers switch 53 by OR circuit 56 made switch 53 keep on-state.Then, after latch pulse Aout at the corresponding levels also disappeared, switch 53 switched to off-state.Should be understood that, as what can obviously see from the sequential chart of Figure 14, some delays (Δ t) appear between the latch pulse Aout of horizontal transmission clock HCK and each grade or Bout, described delay corresponding to horizontal transmission clock HCK by the switch 54 needed times of 53 latch cicuits.

Switch 53 is connected between each transport level of the clock line 51 that is used to transmit single-phase horizontal transmission clock HCK and shift register 31, and only in the transport level that needs horizontal transmission clock HCK, switch 53 is just carried out making operation by this way, because only clock line 51 just is connected to each transport level selectively in needs, so can further reduce the wiring capacitance of the clock line 51 of each transport level.Therefore, can realize the circuit operation more at a high speed and the further power consumption that reduces of shift register 31.

Should be understood that, because the transport level 31n of n level latchs the positive pulse of horizontal transmission clock HCK, so the output of latching of its latch cicuit directly produces latch pulse Aout, but, because next transport level 31n+1 latchs the negative pulse of horizontal transmission clock HCK,, the latch pulse of its latch cicuit is inverted, produces latch pulse Bout so being made polarity by phase inverter 57.Equally, in this practical circuit, Dot Clock is divided into two the clock that obtains as single-phase horizontal transmission clock HCK.

In addition, though in this practical circuit, constitute by latch cicuit and clock selecting control circuit and described shift register as an example with each transport level, but it also is possible that the phase inverter of use clock control replaces latch cicuit to constitute each transport level.Yet, when latch cicuit has the circuit arrangement that two phase inverters walk abreast and connect with opposite directions usually, owing to dispose described timing phase inverter like this, make switching transistor be arranged in the mains side of latch cicuit/ground wire side, so the former circuit arrangement has the following advantages: can realize the more circuit of high speed because its transistor size is less.

Should be understood that, though in the present embodiment with the present invention be used for liquid crystal indicator, wherein 13 upsides that are arranged on respect to viewing area part 12 of H driver are described as an example, but, the present invention also can be used for another kind of liquid crystal indicator, wherein, be similar among first and second embodiment like that, H driver 13U and 13D are arranged on respect to the upside of viewing area part 12 and downside.Figure 15 has shown the ios dhcp sample configuration IOS DHCP under this situation.

Like this, take described configuration, wherein, with respect to viewing area part 12 a pair of upside and downside H driver 13U and 13D are set, it has the advantage that can compress common frame (frame) zone.This be because, because frame (frame) zone is basic requirement, here, each H driver of the circuit region that need be equal to each other is arranged on relative both sides discretely, this can more effectively utilize desired minimum frame area than these H drivers only being arranged on a side, therefore, can compress the total area of the frame region of relative both sides.

In addition, because can be with the data line of viewing area part 12 ..., 22m-2,22m-1,22m, 22m+1 ... driving distribute to a pair of H driver 13U and 13D, therefore can force down the shift register 31U that is included among H driver 13U and the 13D and the transmitted frequency of 31D, this just allows to enlarge opereating specification and handle the high resolving power display unit.

Here, in described a pair of H driver 13U and 13D, shift register 31U and 31D are arranged on respect to the outermost of viewing area part 12 and the clock line 51U and the 51D that transmit two kinds of horizontal transmission clock HCK1 and HCK2 and are set at the more lateral.Two kinds of horizontal transmission clock HCK1 and HCK2 are the single-phase clocks, and, they produce and H driver 13U and 13D driving data lines alternately because being divided into four by timing signal generator circuit 15 with Dot Clock one ..., 22m-2,22m-1,22m, 22m+1 ..., so they have a kind of like this relation: the phase place of a clock is with respect to another phase shift 90 degree.

The sequential of the output pulse of first, second of output pulse of first, second of Figure 16 graphic extension Dot Clock, data-signal, two horizontal transmission clock CHK1 and CHK2, enabling pulse HST1 and HST2, shift register 1 (31U) and the third level and shift register 2 (31D) and the third level.

As mentioned above, in having the active array type LCD of described configuration, wherein, H driver 13U and 13D be arranged in pairs in the upside of viewing area part 12 and downside, there, shift register 31U and 31D be set at respect to the outermost of viewing area part 12 and be used to transmit the clock line 51U of two varying level transmission clock HCK1 and HCK2 and the more lateral that 51D is routed in shift register 31U and 31D, realized following operation and effect.Specifically, because H driver 13U and 13D be provided with in couples, so the transmitted frequency of shift register 31U and 31D can reduce.In addition, because the wiring capacitance of clock line 51U and 51D can reduce as mentioned above, just can expect the frequency of transmission clock HCK1 and HCK2 of improving the standard, and can reduce power consumption.

Should be understood that, though be described as an example with following situation in the present embodiment: H driver 13,13U and 13D have by the digital interface drive arrangements that constitutes with lower member: shift register, sampling latch circuit, line ordering latch cicuit and D/A change-over circuit, but, similarly, the present invention also can be applicable to the occasion of the analog interface drive arrangements that employing is made of shift register and analog sampling circuit.

By the way, as one of driving method of active array type LCD, known a kind of general reverse drive method.Here, described general reverse drive method is a kind of like this driving method, wherein, be added to each pixel liquid crystal cell, described each pixel is common on the electrode to electrode voltage (utility voltage) Vcom paraphase during each 1H (H is a horizontal scanning period).Here, described general reverse drive method is used with for example 1H reverse drive method, in described 1H reverse drive method, be added to polarity paraphase during each 1H of the picture signal of each pixel, since during each 1H, to the polarity of electrode voltage Vcom also with 1H during the reversed polarity paraphase together of picture signal, so can reduce the supply voltage of horizontal driving system ( H driver 13U and 13D).

Described electrode voltage Vcom is produced by electrode voltage being produced circuit 17 (referring to Fig. 1).Traditionally, electrode voltage being produced circuit 17 is to utilize monocrystalline silicon IC to constitute on the chip that separates or be made of the discrete parts that separates with the glass substrate 11 that has formed viewing area part 12 thereon on printed circuit board.

Yet, if electrode voltage is produced circuit 17 to be formed on chip separately or the printed circuit board, so, because the part count of this device increases and they must be made independent of one another by different technological processs, this has hindered the microminiaturization of device and has reduced cost.From this viewpoint that has just illustrated, the configuration that the present invention adopts is: be similar to H driver 13U and 13D and V driver 14, will produce circuit 17 to electrode voltage and be integrated on the identical glass substrate 11 with viewing area part 12.

(electrode voltage being produced the profile instance of circuit)

Figure 17 shows the block scheme that electrode voltage is produced circuit 17 profile instance.Electrode voltage is produced circuit 17 comprise according to this example: on-off circuit 61 is used for switching positive side supply voltage VCC and minus side supply voltage VSS so that export one of them in the fixing cycle; And DC level shifting circuit 62, be used for described on-off circuit 61 output voltage V A the DC level and with the voltage that obtains as electrode voltage Vcom is exported.

On-off circuit 61 comprises the switch SW 1 and reception minus side supply voltage VSS another switch SW 2 as its input of the positive side supply voltage VCC of reception as its input.Utilize phase place is opposite each other gating pulse φ 1 and φ 2 change-over switch SW1 and SW2 so that in the fixed cycle, for example have in the cycle at 1H and alternately export positive side supply voltage VCC and minus side supply voltage VSS.Therefore, from on-off circuit 61 output amplitudes be the voltage VA of VSS or VCC.

The amplitude of 62 pairs of on-off circuits 61 of DC level shifting circuit be the output voltage V A of VSS or VCC carry out level conversion, for example convert to amplitude be VSS-Δ V or VCC-Δ V dc voltage and with this dc voltage as electrode voltage Vcom is exported.Electrode voltage Vcom is offered the common line 27 of Fig. 2 to what reverse at 1H cycle Semi-polarity so that carry out general reverse drive.Figure 18 graphic extension gating pulse φ 1 and φ 2, output voltage V A and to the sequential of electrode voltage Vcom.Should be pointed out that and some delays (Δ t) between gating pulse φ 1 and φ 2 and output voltage V A, occur.

DC level shifting circuit 62 can constitute with various circuit arrangement.A kind of specific profile instance shown in Figure 19 in them.DC level shifting circuit 62 according to this example has simple configuration, and it comprises: capacitor 621 is used to remove the DC component of the voltage VA that provides from on-off circuit 61; And dc voltage generation circuit 622, be used to produce the predetermined dc voltage that offers by the voltage VA of capacitor 621.

Comprise the DC level shifting circuit 62 that utilizes capacitor 621 electrode voltage is produced circuit 17 resemble above-mentioned and viewing area part 12 be integrated under the situation on the same glass substrate 11, because capacitor 621 needs big area, therefore, if capacitor 621 and viewing area part 12 are not integrated but it are constituted as a discrete parts, so, this in most of the cases all is favourable.Therefore, have only capacitor 621 should be formed on glass substrate 11 outsides, and other circuit component, be that on-off circuit 61 and dc voltage produce circuit 622 and all be integrated on the same glass substrate 11 with viewing area part 12.

In this case, because TFT is as the pixel transistor of viewing area part 12, so described TFT also should be as forming the transistor that electrode voltage is produced the on-off circuit 61 of circuit 17.Because improvement and the reduction of power consumption, the integrated TFT of performance become lead-pipe cinch in recent years, therefore, if electrode voltage is produced circuit 17, specifically is can use same technological process to be formed on the glass substrate 11 with viewing area part 12 to the transistor circuit that electrode voltage produces circuit 17 at least, so, can reduce cost and reduce thickness and realize miniaturization by simplifying production run by integrated.

Figure 20 to Figure 24 illustrates five physical circuit examples that dc voltage produces circuit 622.Practical circuit shown in Figure 20 is like this configuration, make that being connected in series in the node that voltage grading resistor R11 between positive side power supply VCC and the minus side power supply VSS (earth potential in this example) and R12 be used between them obtains component voltage, and with this component voltage as described DC level.Practical circuit shown in Figure 21 is configuration like this, makes variohm VR be connected between divider resistance R11 and the R12 so that regulate described DC level by variohm VR.Practical circuit shown in Figure 22 is configuration like this, makes it comprise that resistance R 13 and DC power supply 623 are also depending on that the voltage of this DC power supply 623 is as described DC level.If the form with the variable voltage power supply forms this DC power supply 623, so, just can regulate described DC level.

Practical circuit shown in Figure 23 is configuration like this, makes it use D/A change-over circuit 624 to replace the DC power supply 623 of Figure 22.Under the situation of this practical circuit, the digital dc voltage data of adjusting are imported into D/A change-over circuit 624 to determine described DC level.Like this, can utilize digital signal to adjust this DC level.Practical circuit shown in Figure 24 is like this configuration, make it also comprise except that the configuration of Figure 23 is used to store the dc voltage memory of data 625 of adjusting.Under the situation of described circuit arrangement,, also can determine described DC level even without repeating to import the described dc voltage data of adjusting.

Above-mentioned electrode voltage is produced in the circuit 17, under the situation of reference voltage selection type D/A change-over circuit as the D/A change-over circuit 34U of the 13U of H driver and 13D and 34D, might output voltage V A or by electrode voltage is produced circuit 17 produces to electrode voltage Vcom itself as with reference to one of voltage, that is, be used as the reference voltage of white signal or black signal.

(profile instance of reference voltage selection type D/A change-over circuit)

The following describes reference voltage selection type D/A change-over circuit 28U and 28D.Figure 25 is the circuit diagram that shows the element circuit profile instance of reference voltage selection type D/A change-over circuit 28U and 28D.Here the Digital Image Data of wherein input be for example the 3-bit (b0) data conditions illustrates described configuration as an example for b2, b1, and be described 3 bit image data preparation 8 (=2 ³) individual reference voltage V0 to V7.Each data line for viewing area part 12 ..., 22m-2,22m-1,22m, 22m+1 ... element circuit is set seriatim.

Be used to produce the common configuration example of the generating circuit from reference voltage of this reference voltage V0 to V7 shown in Figure 26.Generating circuit from reference voltage according to this profile instance comprises: two on-off circuits 63 and 64 are used for switching positive side supply voltage VCC and the minus side supply voltage VSS with phases opposite in the fixed cycle; And n+1 resistor R0 be to Rn, and they are connected in series between on-off circuit 63 and 64 lead-out terminals.Therefore, generating circuit from reference voltage by resistance R 0 to Rn with the such dividing potential drop of voltage VCC-VSS so that derive n reference voltage V0 to Vn-1 from the common node between each resistance, and export described reference voltage by buffer circuit 65-1 to 65-n.

In having the generating circuit from reference voltage of above-mentioned configuration, buffer circuit 65-1 to 65-n has the impedance conversion function.They prevent to occur write performance and disperse between upper and lower H driver 13U and 13D, this generating circuit from reference voltage is being formed on the substrate that separates with glass substrate 11, making reference voltage send under the situation of the D/A change-over circuit on the glass substrate 11, because wiring route length from generating circuit from reference voltage to D/A change- over circuit 34U and 34D is very long, so that the impedance of wiring route becomes is very big.

On the other hand, on active array type LCD according to present embodiment, because generating circuit from reference voltage 18 is integrated on the same glass substrate 11 with H driver 13U and 13D, so can the wiring route length between generating circuit from reference voltage 18 and H driver 13U and the 13D is set very short.Specifically, as shown in figure 27, in integrated generating circuit from reference voltage 18, in the roughly centre position on the vertical direction that generating circuit from reference voltage 18 is arranged on viewing area part 12, promptly be arranged under the situation of the position that equates basically with upside and the following lateral extent of H driver 13U and 13D, can be set to be substantially equal to one another to the wiring route length of H driver 13U and 13D.

Therefore, when configuration generating circuit from reference voltage 18, with regard to the buffer circuit 65-1 to 65-n that does not need to use in the omnibus circuit example shown in Figure 26, as seeing from Figure 28 circuit diagram.In more detail, as what obviously see from circuit arrangement shown in Figure 28, the n that the common node from resistor R0 to Rn obtains reference voltage V0 to Vn-1 can directly offer upside and downside H driver 13U and 13D.Like this, owing to can save buffer circuit 65-1 to 65-n, so can simplify the circuit arrangement of generating circuit from reference voltage 18.

Should be pointed out that in Figure 28 the element that is similar to Figure 26 is represented with similar reference character.And in Figure 28, the switch SW 3 to SW6 that forms on-off circuit 63 and 64 is made of for example transistor.In Figure 29, the waveform of graphic extension gating pulse φ 1 and φ 2, upside and downside deboost VA and VB and reference voltage V0 and Vn-1.

In on-off circuit 63 and 64, utilize gating pulse φ 1 to come change-over switch SW3 and SW6, and utilize the gating pulse φ 2 that has with gating pulse φ 1 opposite phase to come change-over switch SW4 and SW5.Why in the fixed cycle, for example utilize the gating pulse that phase place is opposite each other to switch positive side supply voltage VCC and minus side supply voltage VSS in the cycle at 1H, its reason is: expectation is carried out AC to liquid crystal and is driven (being the 1H reverse drive in this example) so that prevent the degeneration of liquid crystal.

In addition, when integrated described generating circuit from reference voltage 18, because TFT is as the pixel transistor of viewing area part 12, if TFT also as the transistor of the on-off circuit 63 that constitutes generating circuit from reference voltage 18 and 64 and at least the transistor circuit of generating circuit from reference voltage 18 be formed on the glass substrate 11 with viewing area part 12, so, generating circuit from reference voltage 18 can be easily with low-cost production.In addition, by using the same process process of the TFT the same with the pixel transistor that is used for viewing area part 12, with generating circuit from reference voltage 18, specifically, at least the transistor circuit of generating circuit from reference voltage 18 is integrated on the glass substrate 11, can reduce cost by simplifying production run, and can be by improving integrated reduce thickness and realization miniaturization.

In having the generating circuit from reference voltage of above-mentioned configuration, the output voltage V A of on-off circuit 63 is as the reference voltage V7 of white signal under the normal white level condition, and the output voltage V B of on-off circuit 64 is as the reference voltage V0 of black signal under the normal white level condition.And, if the difference signal between the reference voltage V7 of the reference voltage V0 of black signal and white signal by divider resistance R1 to R7 dividing potential drop, so, will produce shadow tone reference voltage V1 to V6.For normal black level condition, output voltage V B is used as the reference voltage V0 of white signal to output voltage V A as the reference voltage V7 of black signal.

In described active array type LCD, wherein, comprise that the reference voltage selection type D/A change-over circuit of the generating circuit from reference voltage with above-mentioned configuration is used as D/A change-over circuit 34U and the 34D of H driver 13U and 13D, can be by the output voltage V A that electrode voltage is produced circuit 17 generations as one of each reference voltage that is added to D/A change- over circuit 34U and 34D from generating circuit from reference voltage 18, as shown in figure 30.

More precisely, as mentioned above, the reference voltage of white signal (reference voltage of black signal under the perhaps normal black level condition) is by switch the voltage that positive voltage VCC and negative supply voltage VSS obtain in the fixed cycle under the normal white level condition of preparing to be used by reference voltage selection type D/A change-over circuit.Electrode voltage is being produced in the circuit 17, by in one-period and with identical phase place switch positive side supply voltage VCC and minus side supply voltage VSS obtain output voltage V A, and can be used as the reference voltage (the perhaps reference voltage of black signal) of white signal.

Under the situation of one of each reference voltage that is added to D/A change- over circuit 34U and 34D from generating circuit from reference voltage 18 with preparing by the output voltage V A that electrode voltage is produced circuit 17 generations, because some functions of generating circuit from reference voltage 18 can replace by electrode voltage being produced circuit 17, so the on-off circuit 63 of generating circuit from reference voltage shown in Figure 28 just can omit.Therefore, because compressor circuit scale greatly, so can realize the further microminiaturization of this liquid crystal indicator and the reduction of cost.Though the reference voltage (the perhaps reference voltage of black signal) as white signal with output voltage V A has been described in this example,, also might will be used as the reference voltage (the perhaps reference voltage of black signal) of white signal to electrode voltage VCOM itself.

By the way, in active matrix type display, wherein there is a kind of trend in multi-crystal TFT as the on-off element of pixel, as mentioned above, uses the driving circuit and the viewing area part 12 of multi-crystal TFT to be integrated on the same glass substrate 11.The active matrix type display of the driving circuit of integrated after this manner use multi-crystal TFT promises to be a kind of microminiaturization, high definition and high reliability technology very much.Because multi-crystal TFT has the mobility of high two digits during with the non-crystalline silicon tft comparison, so, its allow with the same substrate of viewing area part on integrated drive electronics.

Simultaneously, because the mobility of multi-crystal TFT is lower relatively the time with the single crystal silicon pipe, starting voltage Vth is higher and the dispersion of starting voltage Vth is bigger, therefore, there is following problem in it: the circuit that can not be used to constitute the high-speed cruising circuit or use low-voltage.It is difficult to the concrete right difference channel of transistor that requirement has identical characteristics that constitutes because starting voltage Vth changes ambassador, and this has brought very big problem to circuit design.

The dispersion of starting voltage Vth has higher resistance relevant with the back gate current potential of TFT.In more detail, because traditional TFT has one of bottom-gate structure and top grid structure as its grid structure, transistorized back gate has represented higher impedance and has made that the dispersion of starting voltage Vth is big.Therefore, it is very difficult using the TFT production low voltage circuit with this specific character or the small signal circuit that have just illustrated.

Simultaneously, advised a kind of structure, wherein, grid is set and is connected to normal-gate in transistorized back gate one side, i.e. structure as shown in figure 31, wherein, the relative both sides of channel region 73 are provided with a pair of grid, are normal-gate 74 and back gate 75 between source region 71 and drain region 72, and by contact region 72 they are connected to each other (being called double-grid structure below the described structure).The TFT of double-grid structure has the following advantages: can be reduced to the dispersion pressure of its starting voltage Vth very little.

Yet,, under the situation of the TFT of described double-grid structure, comprise and being used for owing to need to be provided with, so the needed zone of configuration of device is very big the contact region of grid to 74 and 75 interconnective contact portions 76 as what obviously see from Figure 31.Therefore, the TFT that is used to produce the double-grid structure of driving circuit requires very big circuit region, thereby the frame of display device (outer peripheral areas of viewing area part 12) becomes very big.

Here, in display device shown in Figure 1, H driver 13U and 13D, V driver 14 and timing signal generator circuit 15 all are the circuit of handling small amplitude signal.Should be understood that, though Fig. 1 do not show, the clock I/F circuit that provides from the substrate outside and the synchronizing signal I/F circuit, horizontal-drive signal circuit HD and the vertical synchronizing signal circuit VD that read major clock MCK are arranged on the input stage of timing signal generator circuit 15.Equally, the I/F circuit also is a circuit of handling small amplitude signal.In addition, I/F circuit of CPU or the like is also listed as handling the small amplitude signal circuit.As mentioned above, this processing small amplitude signal circuit all is the circuit that need make the dispersion minimum of transistor threshold Vth.

On the other hand, power circuit 16, electrode voltage is produced circuit 17 and generating circuit from reference voltage 18 all is a circuit of handling supply voltage.As mentioned above, the circuit of this processing supply voltage all is that the highland promotes the circuit of transistorized current capacity as far as possible.

Like this, in active array type LCD according to present embodiment, the circuit that at least one is handled the circuit of this small amplitude signal or handles this supply voltage, the TFT that perhaps handles the circuit of this small amplitude signal or circuit that some handle this supply voltage and be with double-grid structure makes, and other circuit then uses top grid structure or the manufacturing of bottom-gate structure.

Because having starting voltage Vth, the TFT of double-grid structure disperses little super characteristic, so the transistor circuit that constitutes with bigrid TFT has improved reliability, thereby, the TFT of double-grid structure is used to make the circuit of handling small amplitude signal, the particularly paired transistor circuit of moving (promptly comprising the essentially identical transistor of a pair of performance), for example difference channel or current mirror circuit are very useful.

Yet the TFT of double-grid structure need be provided for the big zone with normal-gate and back interconnective contact region of grid thereby the described element of needs formation.Therefore, if bigrid TFT is used to make all circuit, so, circuit size is very big.Therefore, in the circuit of handling small amplitude signal, minimized number circuit in the circuitry needed, the transistor circuit that for example comprises paired operation all use bigrid TFT to make, and other circuit then is with requiring zone very little top grid structure or the manufacturing of bottom-gate structure.This just can produce starting voltage Vth and disperse the little circuit of circuit scale little and that have high reliability.

In addition, though it has less plane domain and has the advantage of high current capacity because the TFT of double-grid structure is equivalent to the transistor that forms with large-size, so, when forming the circuit of handling supply voltage with bigrid TFT, can improve the current capacity of circuit.Yet, similar with above-mentioned situation, if bigrid TFT is used to form all circuit, so, because circuit size is very big, so, utilize bigrid TFT to make the circuit of needed minimal amount, and other circuit is made with the TFT of top grid structure or bottom-gate structure.Thereby, can not make the circuit that generation has high current capacity under the very big situation of circuit scale.

The concrete structure of the TFT of the TFT of TFT, top grid structure of bottom-gate structure and double-grid structure is described with reference to Figure 32 to 34 here.Figure 32 shows the part-structure of the TFT of bottom-gate structure, and Figure 33 shows the TFT part-structure of top grid structure, and Figure 34 shows the part-structure of the TFT of double-grid structure.

At first, shown in figure 32, in bottom-gate structure TFT, grid 82 is formed on the glass substrate 81, and channel region (polysilicon layer) 84 is formed on the grid 82 with the gate insulating film 83 that inserts wherein, and interlayer dielectric 85 is formed on the channel region 84.Source area 86 and drain region 87 are formed on the gate insulating film 83 of grid 82 both sides, and source electrode 88 and drain electrode 89 are connected respectively to zone 86 and 87, simultaneously, and at source electrode 88 with drain and be inserted with interlayer dielectric 85 between 89.And dielectric film 90 is formed in source electrode 88 and the drain electrode 89.

Simultaneously, as shown in figure 33, in the grid structure TFT of top, channel region (polysilicon layer) 92 is formed on the glass substrate 91, and grid 94 is formed on the channel region 92 with the gate insulating film 93 that inserts wherein, and interlayer dielectric 95 is formed on the grid 94.And source area 96 and drain region 97 are formed on the glass substrate 91 of channel region 92 both sides, and source electrode 98 and drain electrode 99 are respectively formed in the zone 96 and 97, simultaneously at the source electrode 98 and the insertion interlayer dielectric 95 between 99 that drains.And dielectric film 100 is formed in source electrode 98 and the drain electrode 99.

At last, as shown in figure 34, in the TFT of double-grid structure, normal-gate 102 is formed on the glass substrate 101, channel region (polysilicon layer) 104 is formed on the normal-gate 102 with the gate insulating film 103 that inserts wherein, and interlayer dielectric 105 is formed on the channel region 104.And back grid 106 is formed on the normal-gate 102 with channel region 104 and insertion interlayer dielectric 105 wherein.Source area 107 and drain region 108 are formed on the gate insulating film 103 of normal-gate 102 both sides, and source electrode 109 and drain electrode 110 are connected respectively to zone 107 and 108, simultaneously, and at the source electrode 109 and the insertion interlayer dielectric 105 between 110 that drains.In addition, dielectric film 111 is formed in source electrode 109 and the drain electrode 110.

(profile instance of sampling latch circuit)

Here, the object lesson as handling the small amplitude signal circuit can use sampling latch circuit (corresponding with sampling latch circuit 32U and the 32D of Fig. 3), and this sampling latch circuit for example can use difference channel.Figure 35 is the circuit diagram of instantiation of the configuration of sampling latch circuit.

Sampling latch circuit according to this example has comparator arrangement, comprises that comprising the CMOS phase inverter 121 of its grid and the N-channel MOS transistor Qn11 that links together separately of drain electrode and P channel MOS transistor Qp11 and another N-channel MOS transistor Qn12 that its grid and drain electrode link together separately and the CMOS phase inverter 122 of P channel MOS transistor Qp12 are connected in parallel.

Here, the output terminal (the drain electrode common node of MOS transistor Qn12 and Qp12) of input end of described CMOS phase inverter 121 (the grid common node of MOS transistor Qn11 and Qp11) and described CMOS phase inverter 122 interconnects.And the output terminal (the drain electrode common node of MOS transistor Qn12 and Qp12) of input end of CMOS phase inverter 122 (the grid common node of MOS transistor Qn11 and Qp11) and CMOS phase inverter 121 interconnects.

In addition, data-signal is input to the input end of CMOS phase inverter 121 from signal source 123 by switch SW 7, and is added to the input end of CMOS phase inverter 122 by switch SW 8 from the comparative voltage of voltage source 124.CMOS phase inverter 121 is connected with power vd D by switch SW 3 with the common node of 122 power supplys, one side.Switch SW 7 and SW8 directly control with sampling pulse (being provided by shift register 31U and 31D among Fig. 3) and switch, and switch SW 9 usefulness are switched by the paraphase pulse control of the sampling pulse of phase inverter 145.

The current potential of (promptly on node A) on the grid node of CMOS phase inverter 121 is by phase inverter 126 paraphase and offer ordering latch cicuit (corresponding with line ordering latch cicuit 33U or 33D among Fig. 3) in the next stage.The current potential of (promptly on node B) on the grid common node of CMOS phase inverter 122 is by another phase inverter 127 paraphase and offer the ordering latch cicuit of next stage.

In the sampling latch circuit of above-mentioned configuration, CMOS phase inverter 121 and CMOS phase inverter 122 usefulness difference channels constitute comparer.Therefore, N-channel MOS transistor Qn11 and N-channel MOS transistor Qn12 move in pairs, and P channel MOS transistor Qp11 and P channel MOS transistor Qp12 move in pairs.

Like this, at transistor in pairs in the transistor circuit of operation, difference channel for example, it is right to need the identical transistor of operating characteristic to make described transistor.Therefore, have in the sampling latch circuit of comparer of difference channel configuration in use, the MOS transistor Qn12 of the MOS transistor Qn11 of CMOS phase inverter 121 and Qp11 and CMOS phase inverter 122 and Qp12 use starting voltage Vth to disperse the TFT configuration of little double-grid structure, and the reliability of circuit can improve and can realize stable operation.

Should be understood that, though dispose sampling latch circuit in this example like this, make the MOS transistor Qn11 of CMOS phase inverter 121 and the MOS transistor Qn12 of Qp11 and CMOS phase inverter 122 and the TFT that Qp12 uses double-grid structure form, but, the application of double-grid structure TFT is not limited to this, and with the transistor that the TFT of double-grid structure is used as switch SW 7 and SW8, can improve the reliability of circuit and can realize stable operation.

As the instantiation of the circuit of handling supply voltage, be power circuit 16, electrode voltage is produced circuit 17 and generating circuit from reference voltage 18, can use above-mentioned configuration.

Though sampling latch circuit 32U and 32D are classified as the practical circuit of handling small amplitude signal, and classify the practical circuit of handling above-mentioned supply voltage as power circuit 16, to electrode voltage generation circuit 17 and generating circuit from reference voltage 18, but, they only are some examples, the circuit object that the TFT that also has other circuit can classify the usefulness double-grid structure as naturally forms.

As mentioned above, in multi-crystal TFT active array type and driving circuit integrated-type liquid crystal indicator, at least these are handled small amplitude signal circuit or those and handle in the circuit of supply voltages one or these and handle small amplitude signal circuit or these to handle in the supply voltage circuit some all be that TFT with double-grid structure forms, and other circuit all is to use the TFT of top grid structure or bottom-gate structure to form, and also can form the circuit with high reliability or have the circuit that increases current capacity, reduces starting voltage Vth dispersion.

In addition, because these circuit and these circuit of handling supply voltage of handling small amplitude signal can be integrated on the same substrate with viewing area part 12, this just can reduce the numbers of terminals of interface, thereby can realize microminiaturization and reduce cost compression IC numbers of terminals and noise.In addition, the TFT of double-grid structure and the top grid structure or/and the TFT both of bottom-gate structure can use, the size of circuit also can be compressed.So, can realize narrow frame driving circuit integrated-type display device.

Should be understood that, though in display device according to the present invention, timing signal generator circuit 15, power circuit 16, electrode voltage is produced circuit 17 and generating circuit from reference voltage 18 all is listed in peripheral circuit, be integrated on the same glass substrate 11 with viewing area part 12, but, except them, other peripheral circuit that can list has cpu interface circuit 131, image storage circuit 132, optical sensor circuit 133 and light source driving circuit 134.

Here, cpu interface circuit 131 is the circuit that are used for from outer CPU input data and output data to outer CPU.Image storage circuit 132 is to be used to store from the outside by the view data of cpu interface circuit 131 inputs, the circuit of for example Still image data.Optical sensor circuit 133 be used to detect external light intensity, for example wherein use this liquid crystal indicator environment brightness and detection information is offered the sensor of light source driving circuit 134.Light source driving circuit 134 is circuit that the strength information that is used to drive the exterior light photograph that provides for the back light of viewing area part 12 illuminations or preceding irradiation and according to optical sensor circuit 133 is adjusted light-source brightness.

Equally, under such peripheral circuit 131 to 134 and viewing area part 12 are integrated in situation on the same glass substrate 11, if constitute all circuit components of foregoing circuit or be that active component (perhaps active/passive element) all is formed on the glass substrate 11 at least, microminiaturization that just can implement device also reduces its cost.

Should be understood that, though describe as an example with the situation that the present invention is applied to active array type LCD in the above-described embodiments, but, the present invention is not limited thereto, but can apply to other active matrix type display similarly, and for example, electroluminescence (EL) display device, wherein, EL element is as the electrical-optical element of each pixel.

In addition, the display part that is used as OA equipment according to the active matrix type display of the foregoing description, for example, the display part of personal computer or word processor or television receiver etc. also also is suitable as the output display part of portable terminal, for example, pocket telephone or PDA, and proceeding the microminiaturization and the densification of apparatus main body.

Figure 37 is the external view that shows portable terminal configuration profile, and for example, the present invention is used for pocket telephone wherein.

Like this configuration according to the pocket telephone of this example, make speaker portion 142, output display part 143, operation part 144 and microphone part 145 be successively set on the front of crust of the device 141 from the top.In having the pocket telephone that resembles the configuration that has just illustrated, for example, liquid crystal indicator is used as output display part 143, and the same with this liquid crystal indicator, can use according to any one active array type LCD in the various embodiments described above.

In the portable terminal of for example pocket telephone, according in the various embodiments described above any one, active array type LCD is by this way as output display part 143, in this case, the circuit arrangement that can simplify the timing signal circuit that is included in the liquid crystal indicator also can realize microminiaturization, reduces cost and reduce power consumption.And, because liquid crystal indicator has narrow frame, branch circuit has good performance characteristic, microminiaturization that therefore can the implement device main body, reduce cost, reduce power consumption and improve performance.

The industry scope of application

As mentioned above, according to the present invention, owing to timing signal generator circuit, comprise this timing The active matrix type display of signal generating circuit or wherein aobvious with this display unit conduct The portable terminal that shows part is that like this configuration is so that driven by vertical drive circuit and level The timing signal of at least one use is that basis is by this vertical drive circuit and this water in the moving circuit The temporal information of at least one generation forms in the flat drive circuit, so, describedly vertically drive The Circnit Layout of the part of at least one, passable in moving circuit and the described horizontal drive circuit Jointly simplify for generation of the amount of timing signal according to this part, thereby, can realize dress The microminiaturization of putting, reduce cost and reduce power consumption.

Claims (43)

1. display device, wherein, the viewing area part, vertical drive circuit and horizontal drive circuit are integrated on the same substrate, the pixel that has electrooptic cell separately in the part of described viewing area becomes to arrange row and column, described vertical drive circuit is used for selecting with behavior unit the described pixel of described viewing area part, and described horizontal drive circuit is used for picture signal is offered each pixel by described vertical drive circuit selected line, it is characterized in that: the shift register that constitutes described horizontal drive circuit is arranged on the outermost with respect to described viewing area part, and is used for the clock line that the single-phase transmission clock sends to the transport level of described shift register is routed in the more lateral of described shift register.

2. display device as claimed in claim 1 is characterized in that: at each described transport level of described shift register be used for selectively described single-phase transmission clock being offered between the described clock line of transport level of described shift register and insert switch.

3. display device as claimed in claim 2 is characterized in that: the described transport level of each of described shift register comprises: latch cicuit is used to latch by corresponding switch to its described single-phase transmission clock that provides; And the clock selecting control circuit, be used for controlling described switch according to the output of latching of latching output and described transport level itself of previous transport level.

4. active matrix type display as claimed in claim 1 is characterized in that: be used for Dot Clock is divided into two and the clock generation circuit that produces described single-phase transmission clock is arranged on described same substrate.

5. display device as claimed in claim 1 is characterized in that: the both sides along described viewing area part are provided with a pair of described horizontal drive circuit.

6. display device as claimed in claim 5 is characterized in that: in described a pair of horizontal drive circuit, described shift register is according to two kinds that have 90 degree phase differential each other different transmission clock operations.

7. display device as claimed in claim 6 is characterized in that: be used for Dot Clock one is divided into four and the described clock generation circuit that produces described two kinds of different transmission clocks is arranged on described same substrate.

8. display device as claimed in claim 1 is characterized in that: described electrooptic cell is a liquid crystal cell.

9. display device as claimed in claim 1 is characterized in that: described electrooptic cell is an electroluminescent cell.

10. display device, it is characterized in that comprising: the viewing area part wherein, comprises that separately the pixel of liquid crystal cell is arranged in rows and columns; Electrode voltage is produced circuit, be used to produce described each pixel of preparing to be added to described liquid crystal cell shared on the electrode to electrode voltage; Vertical drive circuit is used for selecting with behavior unit the described pixel of described viewing area part; And horizontal drive circuit, be used for picture signal is offered each pixel by described vertical drive circuit selected line, and described at least some circuit components that electrode voltage produced circuit with described viewing area part, use same technological process to be formed on the same substrate.

11. display device as claimed in claim 10 is characterized in that: described vertical drive circuit and described horizontal drive circuit use same technological process to be formed on the described same substrate with described viewing area.

12. display device as claimed in claim 11 is characterized in that: described at least some circuit components to electrode voltage generation circuit are arranged on a side described substrate, that described horizontal drive circuit is not set on it.

13. display device as claimed in claim 10 is characterized in that: describedly electrode voltage is produced circuit comprise: on-off circuit is used for switching in the fixing cycle and output positive voltage and negative supply voltage; And level shifting circuit, be used to change described on-off circuit output voltage the DC level and the voltage that obtains exported electrode voltage as described.

14. display device as claimed in claim 13 is characterized in that: described level shifting circuit can be regulated its switching levels.

15. display device as claimed in claim 13, it is characterized in that: described on-off circuit uses same technological process to be formed on the described same substrate with described viewing area part, and some circuit components of described level shifting circuit are formed on the outside of described substrate.

16. display device as claimed in claim 13 is characterized in that: described level shifting circuit comprises: capacitor is used to eliminate the DC component of the described output voltage of described on-off circuit; And dc voltage generation circuit, being used to produce predetermined dc voltage, described predetermined dc voltage prepares to offer the described output voltage that passes through described capacitor of described on-off circuit.

17. display device as claimed in claim 16, it is characterized in that: the described capacitor of described level shifting circuit is formed on the described outside of described substrate, and all residual circuit elements use same technological process to be formed on the described same substrate with described viewing area part.

18. display device as claimed in claim 13, it is characterized in that: described horizontal drive circuit comprises reference voltage selection type D/A change-over circuit composition, be used for from a plurality of reference voltages select with input on it Digital Image Data corresponding reference voltage and the reference voltage of described selection exported as analog picture signal, and in described a plurality of reference voltage, the output voltage of the described described on-off circuit that electrode voltage is produced circuit or the output voltage of described level shifting circuit are as the reference signal of white signal or black signal.

19. a display device is characterized in that comprising: the viewing area part, wherein, the pixel that has electrooptic cell separately is arranged in rows and columns; Vertical drive circuit is used for selecting with behavior unit the described pixel of described viewing area part; Generating circuit from reference voltage is used to produce a plurality of reference voltages; Reference voltage selection type D/A change-over circuit is used for selecting and numerical data corresponding reference voltage from described a plurality of reference voltages; And horizontal drive circuit, be used for to offer each pixel of the described row of choosing by described vertical drive circuit as picture signal by the reference voltage that described D/A change-over circuit is selected, and described generating circuit from reference voltage uses same technological process to be formed on the described same substrate with described display part, described vertical drive circuit and described horizontal drive circuit.

20. display device as claimed in claim 19, it is characterized in that: in each described pixel of described viewing area part, the active component that is used to drive described electrooptic cell is made of thin film transistor (TFT), and described vertical drive circuit, described horizontal drive circuit and described generating circuit from reference voltage all constitute with thin film transistor (TFT).

21. display device as claimed in claim 19 is characterized in that: described generating circuit from reference voltage is arranged on a side described substrate, that described horizontal drive circuit is not set on it.

22. display device as claimed in claim 19, it is characterized in that: upside and downside in described viewing area part are provided with a pair of described horizontal drive circuit, and described generating circuit from reference voltage is arranged on separately on the position of the distance that equates basically apart from described a pair of horizontal drive circuit.

23. display device as claimed in claim 19 is characterized in that: described electrooptic cell is a liquid crystal cell.

24. display device as claimed in claim 19 is characterized in that: described electrooptic cell is an electroluminescent cell.

25. a display device is characterized in that comprising: the viewing area part, wherein, the pixel that has electrooptic cell separately is arranged in rows and columns; Vertical drive circuit is used for selecting with behavior unit the described pixel of described viewing area part; Generating circuit from reference voltage is used to produce a plurality of reference voltages; Horizontal drive circuit, it comprises reference voltage selection type D/A change-over circuit, be used for selecting and numerical data corresponding reference voltage from described a plurality of reference voltages, described horizontal drive circuit will be offered each pixel of the described row of being chosen by described vertical drive circuit by the reference voltage that described D/A change-over circuit is selected as picture signal; Timing signal generator circuit, each branch circuit that is used to produce some timing signals and these timing signals is offered described display device; And power supply voltage converting circuit, be used for single dc voltage convert to a plurality of different dc voltages with the magnitude of voltage that differs from one another and and these dc voltages are offered each branch circuit of described display device, and described vertical drive circuit, described generating circuit from reference voltage, described horizontal drive circuit, described timing signal generator circuit and described power supply voltage converting circuit all use same technological process to be formed on the same substrate with described viewing area part.

26. display device as claimed in claim 25 is characterized in that also comprising the image storage circuit of storing image data, described video memory uses same technological process to be formed on the described same substrate with described viewing area part.

27. display device as claimed in claim 25 is characterized in that also comprising the interface circuit that is used for being undertaken by it the input and output data, described interface circuit uses same technological process to be formed on the described same substrate with described viewing area part.

28. display device as claimed in claim 25 is characterized in that also comprising the optical sensor circuit that is used to detect external light intensity, described optical sensor circuit uses same technological process to be formed on the described same substrate with described viewing area part.

29. the active matrix type display as claim 25 is characterized in that, described photovalve is a liquid crystal cell.

30. display device as claimed in claim 29, it is characterized in that also comprising be used to produce be added to described liquid crystal cell to the voltage of electrode electrode voltage is produced circuit, and described electrode voltage is produced circuit and described viewing area part delayer uses same technological process to be formed on the described same substrate.

31. display device as claimed in claim 25 is characterized in that: described electrooptic cell is an electroluminescent cell.

32. display device, it is characterized in that: wherein have viewing area part that the pixel of electrooptic cell is arranged in rows and columns separately and comprise that the transistorized transistor circuit of paired operation is formed on the same substrate in integrated mode, and described transistor circuit is made of each thin film transistor (TFT) with double-grid structure, and a pair of grid of each double-grid structure is arranged on the both sides of raceway groove and interconnects.

33. display device as claimed in claim 32, it is characterized in that also comprising horizontal drive circuit, described horizontal drive circuit is formed on the described same substrate with described viewing area part and comprises and be used for the view data of input is carried out sequential sampling and latched the sampling latch circuit of the view data of described input, and described transistor circuit is the difference channel that constitutes described sampling latch circuit.

34. display device as claimed in claim 32 is characterized in that: described electrooptic cell is a liquid crystal cell.

35. display device as claimed in claim 32 is characterized in that: described electrooptic cell is an electroluminescent cell.

36. display device, it is characterized in that: wherein have viewing area part that the pixel of electrooptic cell is arranged in rows and columns separately and be formed on the same substrate in integrated mode with first circuit of handling small amplitude signal and the second circuit of handling supply voltage, and one of described at least first and second circuit are made of each thin film transistor (TFT) with double-grid structure, and a pair of grid of each double-grid structure is arranged on the both sides of raceway groove and interconnects.

37. display device as claimed in claim 36 is characterized in that: described first circuit is the circuit that extracts data-signal, master clock signal or synchronizing signal from the outside.

38. display device as claimed in claim 36, it is characterized in that also comprising horizontal drive circuit, described horizontal drive circuit is formed on the described same substrate with described viewing area part and comprises and be used for the view data that is input to this circuit is carried out sequential sampling and latched the sampling latch circuit of the view data of described input, and described first circuit is the difference channel that constitutes described sampling latch circuit.

39. display device as claimed in claim 36 is characterized in that: described second circuit is power supply voltage converting circuit, is used for converting single dc voltage to a plurality of dc voltages with the magnitude of voltage that differs from one another.

40. display device as claimed in claim 36, it is characterized in that also comprising: horizontal drive circuit, it comprises with described viewing area part and is formed on described same on-chip sampling latch circuit, and the latter is used for the view data that is input to this circuit is carried out sequential sampling and latched the view data of described input; The line ordering latch cicuit is used for the latch data of described sampling latch circuit is carried out line ordering; And reference voltage selection type D/A change-over circuit, be used for the Digital Image Data of being undertaken behind the line ordering by described line ordering latch cicuit is converted to analog picture signal, and described second circuit is a generating circuit from reference voltage, and it produces a plurality of reference voltages that described reference voltage selection type D/A change-over circuit uses.

41. display device as claimed in claim 36 is characterized in that: described electrooptic cell is a liquid crystal cell.

42. display device as claimed in claim 41, it is characterized in that: described second circuit is that electrode voltage is produced circuit, it with described viewing area part be formed on the described same substrate, be used to produce be added to described liquid crystal cell to the voltage on the electrode.

43. display device as claimed in claim 36 is characterized in that: described electrooptic cell is an electroluminescent cell.

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