CN1753309A - Level conversion circuit for converting voltage amplitude of signal - Google Patents
Level conversion circuit for converting voltage amplitude of signal Download PDFInfo
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- CN1753309A CN1753309A CN 200510108951 CN200510108951A CN1753309A CN 1753309 A CN1753309 A CN 1753309A CN 200510108951 CN200510108951 CN 200510108951 CN 200510108951 A CN200510108951 A CN 200510108951A CN 1753309 A CN1753309 A CN 1753309A
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Abstract
In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the ''L'' level to the ''H'' level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the ''L'' level to the ''H'' level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the ''H'' level, which prevents the potential of the node from becoming unstable.
Description
Technical field
The present invention relates to level-conversion circuit, specifically, relate to the level-conversion circuit of the voltage amplitude of figure signal.
Background technology
In recent years, in semiconductor device, wish more highly integrated, miniaturization, the high speed of action, low consumpting powerization.Especially, in LSI (large scale integrated circuit), require the lower voltage of internal electric source and high speed two aspects of action simultaneously.In the present situation, the lower voltage of the internal electric source of LSI is lower than the lower voltage of the interface voltage of LSI.Thereby, in the occasion that connects a plurality of LSI, the level-conversion circuit of the voltage amplitude of the output signal of use conversion LSI.In addition, in the inner occasion that connects the different circuit of supply voltage of LSI, also use level-conversion circuit.
Should " L " level be earthing potential GND (0V), should " H " level be power supply potential VDDL (for example, 1.2V) signal transformation become, should " L " level be earthing potential GND (0V), should " H " level be power supply potential VDDH (for example, 3.3V) traditional level-conversion circuit of signal in, the time that has the level translation action to need is long, the problem that consumed power is big.In addition, input signal is elevated to the occasion of " H " level and is reduced to the occasion of " L " level from " H " level from " L " level, is difficult to make the time of level translation action needs identical.Like this, in the big occasion of difference of power supply potential VDDL and power supply potential VDDH, the time that the level translation action needs is easy to generate difference.
In the Te Kaiping 06-209256 communique, proposed and 5V can be transformed into 1V～7V, 1V～7V has been transformed into the level-conversion circuit of 5V.In this occasion, studied the transistorized β value (current amplification degree) that constitutes level-conversion circuit.
In addition, open in the flat 07-086913 communique, proposed to reduce the impulse level translation circuit of current sinking the spy.In this occasion, raise the necessary delay time, can prevent the deterioration of high amplitude output pulse by the current potential of setting output node.
In addition, open in the flat 05-308274 communique, during the circuit that has proposed withstand voltage little MOS transistor between gate-source constitutes, obtain the CMOS level shifting circuit of the signal output of high-voltage level with constant current the spy.
But above-mentioned spy opens in flat 06-209256 communique and the flat 07-086913 communique of Te Kai, can not fully realize the high speed and the low consumpting powerization of level translation action.In addition, open in the flat 05-308274 communique the spy, the occasion that level that can not corresponding input signal changes with low speed, the versatility of level-conversion circuit is low.
Summary of the invention
Therefore, main purpose of the present invention provides, and can carry out high-speed level conversion action, the level-conversion circuit that low consumpting power and versatility are high.
In the level-conversion circuit of the present invention, be provided with: its 1st electrode receives the 2nd power supply potential, the 1st transistor of its gate electrode and interconnective the 1st conductivity type of the 2nd electrode; Its 1st electrode receives the 2nd power supply potential, and its gate electrode is connected with the 1st transistorized gate electrode, the 2nd transistor of the 1st conductivity type that its 2nd electrode is connected with the node of regulation; Its gate electrode receives the 3rd transistor of the 2nd conductivity type of the 1st signal; Between the 1st transistorized the 2nd electrode and reference potential line, the 1st switch element that is connected with the 3rd transistor series; Its 1st electrode is connected with the node of regulation, and its gate electrode receives the inversion signal of the 1st signal, and its 2nd electrode receives the 4th transistor of the 2nd conductivity type of reference potential; Be connected the 2nd switch element between the node of the 2nd power supply potential line and regulation; The node potential occasion lower when regulation than specified level, make the 1st switch element conducting, it is non-conduction that the 2nd switch element is in, output node is made as reference potential, the node potential occasion higher when regulation than specified level, it is non-conduction that the 1st switch element is in, and makes the 2nd switch element conducting simultaneously, output node is made as the output circuit of the 2nd power supply potential.Thereby, constitute current mirror to circuit by the 1st and the 2nd transistor, owing to be provided with the 1st and the 2nd switch element, can realize the high speed and the low consumpting powerization of level translation action.And, can corresponding the 1st signal level arrive the occasion that changes with at a high speed with the occasion that low speed changes, the versatility of level-conversion circuit uprises.
Above-mentioned and other purpose of the present invention, feature, situation and advantage, the following detailed description of being correlated with by the related the present invention of understanding with accompanying drawing becomes clear.
Description of drawings
Fig. 1 is the circuit diagram that the level-conversion circuit of the expression embodiment of the invention 1 constitutes
Fig. 2 is the sequential chart of the action of expression level-conversion circuit shown in Figure 1.
Fig. 3 is the circuit diagram that the traditional level-conversion circuit of expression constitutes.
Fig. 4 is the plane graph of the layout of expression level-conversion circuit shown in Figure 1.
Fig. 5 is the partial enlarged drawing of P channel MOS transistor 3 shown in Figure 4.
Fig. 6 is the sectional view of Fig. 5 along the VI-VI line.
Fig. 7 is the circuit diagram of formation of level-conversion circuit of the variation of the expression embodiment of the invention 1.
Fig. 8 is the circuit diagram of formation of the level-conversion circuit of the expression embodiment of the invention 2.
Fig. 9 is the circuit diagram of the level-conversion circuit formation in grid and the occasion that node N2 is connected of expression P channel MOS transistor 31.
Figure 10 is the plane graph of the layout of expression level-conversion circuit shown in Figure 9.
Figure 11 is the circuit diagram that the level-conversion circuit of the variation of the expression embodiment of the invention 2 constitutes.
Embodiment
Among Fig. 1, this level-conversion circuit has: input terminal 1, lead-out terminal 2, P channel MOS transistor 3～5, N-channel MOS transistor 6～8 and inverter 9～11.
P channel MOS transistor 3 is connected between voltage potential VDDH line and the node N1.P channel MOS transistor 4 is connected between voltage potential VDDH line and the node N2.The grid of P channel MOS transistor 3,4 all is connected with node N1.P channel MOS transistor 3,4 constitutes current mirror to circuit, if flow through electric current in P channel MOS transistor 3, then the corresponding electric current of component size size with P channel MOS transistor 3,4 flows through in P channel MOS transistor 4.
N- channel MOS transistor 6,7 is connected in series between node N1 and the earthing potential GND line.N-channel MOS transistor 8 is connected between node N2 and the earthing potential GND line.Input terminal 1 is connected with the grid of N-channel MOS transistor 7, is connected with the grid of N-channel MOS transistor 8 by inverter 9 simultaneously.
Here, power supply potential VDDH be high potential (for example, 3.3V), power supply potential VDDL be electronegative potential (for example, 1.2V).Inverter 9 is driven by power supply potential VDDL, and inverter 10,11 is driven by power supply potential VDDH.Inverter 9～11, the anti-phase and output with logical level of input signals.
In Fig. 2, represent input signal and the potential change of output signal and the situation of change of current sinking of level-conversion circuit shown in Figure 1.In addition, the current sinking shown in is here, and the frequency setting of input signal is 25MHz, the analog result when the additional electrical capacity of lead-out terminal 2 is set at the occasion of 1pF.
At moment t1, input signal is elevated to " H " level (VDDL) by " L " level (0V).Corresponding therewith, 7 conductings of N-channel MOS transistor, N-channel MOS transistor 8 becomes non-conduction.
Here, at moment t1, the current potential of node N3 is the occasion of " H " level, because 6 conductings of N-channel MOS transistor, the current potential of node N1 reduces, and flows through electric current at P channel MOS transistor 3.Corresponding therewith, flow through electric current in the P channel MOS transistor 4.In addition, because this moment, N-channel MOS transistor 8 became non-conductionly, the current potential of node N2 rises.If the current potential of node N2 becomes than the threshold voltage height of inverter 10, then inverter 10 makes the current potential of node N3 be declined to become " L " level (0V), and inverter 11 makes the current potential of lead-out terminal 2 raise " H " level (VDDH).And, be declined to become " L " level corresponding to the current potential of node N3,5 conductings of P channel MOS transistor, the current potential of node N2 is set to " H " level (VDDH).In addition, N-channel MOS transistor 6 becomes non-conduction, and the electric current that flows through in the P channel MOS transistor 3,4 becomes 0A.Thereby the current sinking of this level-conversion circuit after the moment change greatly, reduces to 0A in moment t1.
On the other hand, though it is not shown, at moment t1, the current potential of node N3 is the occasion of " L " level, because N-channel MOS transistor 6 becomes non-conduction, no current flows through in the P channel MOS transistor 3,4, because 5 conductings of P channel MOS transistor, then the current potential of node N2 is set to " H " level (VDDH).Thereby the current potential of inverter 10 node N3 is set to " L " level (0V), and the current potential of inverter 11 lead-out terminals 2 is set to " H " level (VDDH).
Then, at moment t2, input signal drops to " L " level (0V) from " H " level (VDDL).Corresponding therewith, N-channel MOS transistor 7 becomes non-conduction, 8 conductings of N-channel MOS transistor.Here, because that N-channel MOS transistor 7 becomes is non-conduction, irrelevant with the conducting state of N-channel MOS transistor 6, no current flows through in the P channel MOS transistor 3,4.At this moment, corresponding to 8 conductings of N-channel MOS transistor, the current potential of node N2 drops to " L " level (0V).Corresponding therewith, inverter 10 makes the current potential of node N3 be elevated to " H " level (VDDH), and inverter 11 makes the current potential of lead-out terminal 2 drop to " L " level (0V).And, being elevated to " H " level corresponding to the current potential of node N3, P channel MOS transistor 5 becomes non-conduction.In addition, 6 conductings of N-channel MOS transistor are elevated to the getting ready of action of the occasion of " H " level (VDDL) from " L " level (0V) for next input signal.Thereby the current sinking of this level-conversion circuit after moment t2 moment ground becomes greatly, reduces to 0A.
Fig. 3 is the circuit diagram that the traditional level-conversion circuit of expression constitutes, and with the figure of Fig. 1 contrast.With reference to the level-conversion circuit of figure 3, with the level-conversion circuit difference of Fig. 1 be, deleted N-channel MOS transistor 6 and P channel MOS transistor 5, the grid of P channel MOS transistor 3 is connected with node N2.In addition, in Fig. 3, use identical symbol, do not repeat its detailed explanation with the part that Fig. 1 is corresponding.
Refer again to Fig. 2, the potential change of the output signal of traditional level-conversion circuit and the situation of change of current sinking are represented by dotted lines.At moment t1, input signal is elevated to " H " level (VDDL) from " L " level (0V).Corresponding therewith, 7 conductings of N-channel MOS transistor, N-channel MOS transistor 8 becomes non-conduction.Here, corresponding to 7 conductings of N-channel MOS transistor, the current potential of node N1 reduces, and flows through electric current in the P channel MOS transistor 4.At this moment, because that N-channel MOS transistor 8 becomes is non-conduction, the current potential of node N2 rises.Corresponding therewith, P channel MOS transistor 3 becomes non-conduction, and the current potential of node N1 is reduced to " L " level (0V).In addition, the electric current that flows through in the P channel MOS transistor 4 increases, and the current potential of node N2 rises to " H " level (VDDH).
Moment t11 after passing through the stipulated time since moment t1, current potential corresponding to node N2 becomes higher than the threshold voltage of inverter 10, inverter 10 makes the current potential of node N3 drop to " L " level (0V), and inverter 11 makes the current potential of lead-out terminal 2 be elevated to " H " level (VDDH).Thereby, the current sinking of this level-conversion circuit, from moment t1 to moment t11 during, be set to the level of regulation, moment t11 moment ground become big after, reduce to 0A.
Then, at moment t2, input signal is reduced to " L " level (0V) from " H " level (VDDL).Corresponding therewith, N-channel MOS transistor 7 becomes non-conduction, 8 conductings of N-channel MOS transistor.Here, corresponding to 8 conductings of N-channel MOS transistor, the current potential of node N2 reduces, and flows through electric current in the P channel MOS transistor 3.At this moment, because that N-channel MOS transistor 7 becomes is non-conduction, the current potential of node N1 rises.Corresponding therewith, P channel MOS transistor 4 becomes non-conduction, and the current potential of node N2 is reduced to " L " level (0V).In addition, the electric current that flows through in the P channel MOS transistor 3 increases, and the current potential of node N1 rises to " H " level (VDDH).
Moment t12 after passing through the stipulated time from moment t2, current potential corresponding to node N2 becomes lower than the threshold voltage of inverter 10, inverter 10 makes the current potential of node N3 be elevated to " H " level (VDDH), and inverter 11 makes the current potential of lead-out terminal 2 drop to " L " level (0V).Thereby, the current sinking of this level-conversion circuit, from moment t2 to moment t12 during be set to the level of regulation, moment t12 moment ground become big after, reduce to 0A.
Thereby, in traditional level-conversion circuit, the problem that time is long, consumed power is big that has the level translation action to need.And, be difficult to make the occasion that is elevated to " H " level at input signal from " L " level, the logic level of output signal is switched the time (t11-t1) that needs, with drop to the occasion of " L " level at input signal from " H " level, it is identical that the logic level of output signal is switched the time (t12-t2) that needs.The reasons are as follows.
Among the t1, when input signal is elevated to " H " level from " L " level,, reduce the current potential of node N1 constantly, need the current driving ability of N-channel MOS transistor 7 bigger than the current driving ability of P channel MOS transistor 3 in order to make 7 conductings of N-channel MOS transistor.This is because in during the moment t1,3 conductings of P channel MOS transistor, and at moment t1,7 two in P channel MOS transistor 3 and N-channel MOS transistor all become to moment conducting state.
Then, at moment t2, when input signal is reduced to " L " level from " H " level, in order to make 8 conductings of N-channel MOS transistor, reduce the current potential of node N2, need the current driving ability of N-channel MOS transistor 8 bigger than the current driving ability of P channel MOS transistor 4.This be because, from moment t1 to moment t2 during, P channel MOS transistor 4 conductings, thereby at moment t2,8 two in P channel MOS transistor 4 and N-channel MOS transistor all become to moment conducting state.
But, like this, have difference by making each transistorized current driving ability, input signal is elevated to the occasion of " H " level from " L " level, drop to the occasion of " L " level from " H " level with input signal, the characteristic of level translation action produces difference.Like this, the big occasion of difference of power supply potential VDDL and power supply potential VDDH, the time that the level translation action needs is easy to generate difference.
Thereby, in present embodiment 1, constitute current mirror to circuit by P channel MOS transistor 3,4, append N-channel MOS transistor 6 and P channel MOS transistor 5.Thereby, compare with traditional level-conversion circuit, can realize high speed, and the low consumpting powerization (with reference to figure 2) of level translation action.More specifically, input signal is elevated to the occasion of " H " level from " L " level, because that N-channel MOS transistor 6 becomes is non-conduction, can prevent to flow through leakage current in the P channel MOS transistor 3,4, and consumed power diminishes.In addition, input signal is elevated to the occasion of " H " level from " L " level, and the conducting by P channel MOS transistor 5 makes the current potential of node N2 be fixed to " H " level (VDDH), thereby the current potential that can prevent node N2 becomes unsure state.This is to transfer to the effect that the corresponding occasion of the LSI of function of low consumpting power pattern has with possessing from common pattern.That is, the occasion (low-frequency signals) that changes with low speed from the level of input signal, to occasion (high-frequency signal) to change at a high speed, can low current loss and high-speed response, the versatility of level-conversion circuit improves.
In addition, in order not influence the responsiveness of level translation, the current driving ability of P channel MOS transistor 5 is arranged to enough littler than the current driving ability of N-channel MOS transistor 8.Thereby input signal drops to " L " level from " H " level, and during 8 conductings of N-channel MOS transistor, the current potential of node N2 reduces rapidly.
In addition, describe at the occasion that N-channel MOS transistor 6 is set between P channel MOS transistor 3 and N-channel MOS transistor 7 here, but also can between N-channel MOS transistor 7 and earthing potential GND line, N-channel MOS transistor 6 be set.This occasion also can obtain same effect.
And, describe at the occasion that inverter 9 is set between the grid of input terminal 1 and N-channel MOS transistor 8 here, but also can between the grid of input terminal 1 and N-channel MOS transistor 7, inverter 9 be set.This occasion also can obtain same effect.
Fig. 4 is the plane graph of the layout of expression level-conversion circuit shown in Figure 1.Among Fig. 4, in p well area 101, be provided with N- channel MOS transistor 6,7,8.In n well area 102, be provided with P channel MOS transistor 10a, the 11a of P channel MOS transistor 3,4,5 and formation inverter 10,11.In p well area 103, be provided with the N-channel MOS transistor 10b, the 11b that constitute inverter 10,11.In p well area 101,103 and n well area 102, active region AF, gate electrode GE, the 1st layer of metal line ML1 and the 2nd layer of metal line ML2 have been formed.The 1st layer and the 2nd layer of metal line are for example aluminium wirings.
In p well area 101, the gate electrode GE of N-channel MOS transistor 6 is connected with the gate electrode GE of P channel MOS transistor 5 by the 1st layer and the 2nd layer of metal line ML1, ML2.The drain electrode of N-channel MOS transistor 6 is connected with the gate electrode GE of P channel MOS transistor 3 by the 1st layer and the 2nd layer of metal line ML1, ML2, and the source electrode of N-channel MOS transistor 6 is connected with the drain electrode of N-channel MOS transistor 7.The gate electrode GE of N-channel MOS transistor 7 is connected with input terminal 1 by the 1st layer of metal line ML1.The source electrode of N-channel MOS transistor 7 is connected with earthing potential GND line by the 1st layer and the 2nd layer of metal line ML1, ML2.The gate electrode GE of N-channel MOS transistor 8 is connected with the output node of inverter 9 by the 1st layer of metal line ML1.The drain electrode of N-channel MOS transistor 8 is connected with the drain electrode of P channel MOS transistor 5 by the 1st layer and the 2nd layer of metal line ML1, ML2, and the source electrode of N-channel MOS transistor 8 is connected with earthing potential GND line by the 1st layer and the 2nd layer of metal line ML1, ML2.This N-channel MOS transistor 8 is arranged to 2 row.
In n well area 102, the gate electrode GE of P channel MOS transistor 5 is connected with the gate electrode GE of the P channel MOS transistor 11a of formation inverter 11 by the 1st layer and the 2nd layer of metal line ML1, ML2.The source electrode of P channel MOS transistor 5, be connected with power supply potential VDDH line by the 1st layer and the 2nd layer of metal line ML1, ML2, the drain electrode of P channel MOS transistor 5 is connected with the gate electrode GE of the P channel MOS transistor 10a of formation inverter 10 by the 1st layer and the 2nd layer of metal line ML1, ML2.The gate electrode GE of P channel MOS transistor 3 is connected with this drain electrode by the 1st layer and the 2nd layer of metal line ML1, ML2.The source electrode of P channel MOS transistor 3 is connected with power supply potential VDDH line by the 1st layer and the 2nd layer of metal line ML1, ML2.The gate electrode GE of P channel MOS transistor 4 is connected with the gate electrode GE of P channel MOS transistor 3 by the 1st layer of metal line ML1.The source electrode of P channel MOS transistor 4, be connected with power supply potential VDDH line by the 1st layer and the 2nd layer of metal line ML1, ML2, the drain electrode of P channel MOS transistor 4, by the 1st layer and the 2nd layer of metal line ML1, ML2 is connected with the gate electrode GE of the P channel MOS transistor 10a that constitutes inverter 10.
In n well area 102 and p well area 103, constitute the gate electrode GE of the P channel MOS transistor 10a of inverter 10, be connected with the gate electrode GE of N-channel MOS transistor 10b by the 1st layer and the 2nd layer of metal line ML1, ML2.The source electrode of P channel MOS transistor 10a, be connected with power supply potential VDDH line by the 1st layer and the 2nd layer of metal line ML1, ML2, the drain electrode of P channel MOS transistor 10a is connected with the drain electrode of N-channel MOS transistor 10b by the 1st layer and the 2nd layer of metal line ML1, ML2.The source electrode of N-channel MOS transistor 10b is connected with earthing potential GND line by the 1st layer and the 2nd layer of metal line ML1, ML2.Constitute the gate electrode GE of the P channel MOS transistor 11a of inverter 11, be connected with the gate electrode GE of N-channel MOS transistor 11b by the 1st layer and the 2nd layer of metal line ML1, ML2.The source electrode of P channel MOS transistor 11a, be connected with power supply potential VDDH line by the 1st layer and the 2nd layer of metal line ML1, ML2, the drain electrode of P channel MOS transistor 11a is connected with the drain electrode of N-channel MOS transistor 11b by the 1st layer and the 2nd layer of metal line ML1, ML2.The source electrode of N-channel MOS transistor 1 1b is connected with earthing potential GND line by the 1st layer and the 2nd layer of metal line ML1, ML2, and the drain electrode of N-channel MOS transistor 11b is connected with lead-out terminal 2.
In addition, each transistorized gate electrode GE is all arranged (being horizontal direction among the figure) in the same direction.Thereby, can suppress the deviation that transistor is made.
Though not shown, the P channel MOS transistor 9a and the N-channel MOS transistor 9b of formation inverter 9 are arranged on other zones.Inverter 9 uses the power-supply system of the power supply potential VDDL different with the power-supply system of power supply potential VDDH.
Here, if the grid length of transistor 3～8 is L3～L8, the grid length of transistor 10a, 10b, 11a11b is L10a, L10b, L11a, L11b, if the grid width of transistor 3～8 is W3～W8, the grid width of transistor 10a, 10b, 11a11b is W10a, W10b, W11a, W11b.
Fig. 5 is the partial enlarged drawing of P channel MOS transistor 3 shown in Figure 4.With reference to figure 5, the grid width W3 of P channel MOS transistor 3 is equivalent to the gate electrode GE of P channel MOS transistor 3 and the length of active region AF lap (length of horizontal direction among Fig. 5).
Fig. 6 is the sectional view along the VI-VI line of Fig. 5.With reference to figure 6, on n well region 102, form p+ zone, i.e. source electrode and drain electrode.And, on n trap 102, stacked oxide-film, the gate electrode GE of stacked polysilicon etc. on oxide-film.In the P+ zone is the top of source electrode and drain electrode, forms the 1st layer of metal line ML1 by contact hole CH respectively.And, on the top of the 1st layer metal line ML1, form the 2nd layer metal line ML2 by through hole TH.The grid length L3 of P channel MOS transistor 3 is equivalent to the P+ zone and is the distance between source electrode and drain electrode.
Table 1 expression, an example of transistorized grid length of shown in Figure 4 each and grid width.In addition, transistor 9a, 9b, expression constitutes the P channel MOS transistor 9a and the N-channel MOS transistor 9b of inverter 9 shown in Figure 1 respectively.
Table 1
| Grid width W (μ m) | Grid length L (μ m) | |
| | 1.0 | 0.4 |
| | 7.0 | 0.4 |
| | 0.4 | 0.5 |
| | 2.0 | 0.4 |
| | 2.0 | 0.4 |
| | 7.0 | 0.4 |
| Transistor 9a | 3.36 | 0.1 |
| Transistor 9b | 1.3 | 0.1 |
| | 4.9 | 0.4 |
| | 2.1 | 0.4 |
| | 4.9 | 0.4 |
| | 2.1 | 0.4 |
Reference table 1, the grid width W4 of P channel MOS transistor 4 (for example, 7.0 μ m), the grid width W3 (for example, 1.0 μ m) that is arranged to than P channel MOS transistor 3 is long.Best, be set to about about 3～8 times.Thereby the current mirror that P channel MOS transistor 3,4 constitutes is in circuit, and input current is exaggerated into proper level.In addition, the grid width W8 of N-channel MOS transistor 8 (for example, 7.0 μ m), the grid width W7 (for example, 2.0 μ m) that is arranged to than N-channel MOS transistor 7 is long.Best, be provided with into about about 1.1～4 times.In addition, the grid width W6 of N-channel MOS transistor 6 and the grid width W7 of N-channel MOS transistor 7 are arranged to identical (for example, 2.0 μ m).
The grid width W5 of P channel MOS transistor 5 (for example, 0.4 μ m), the grid width W8 (for example, 7.0 μ m) that is arranged to than N-channel MOS transistor 8 is enough little.Best, be provided with into about about 0.03～0.2 times.In addition, the grid length L5 of P channel MOS transistor 5 (for example, 0.5 μ m), the grid length L8 (for example, 0.4 μ m) that is arranged to than N-channel MOS transistor 8 is long.Best, be provided with into about about 1.1～1.5 times.Thereby the current driving ability of P channel MOS transistor 5 becomes enough littler than the current driving ability of N-channel MOS transistor 8.Thereby as using Fig. 2 explanation, input signal is lowered into " L " level from " H " level, and during 8 conductings of N-channel MOS transistor, the current potential of node N2 reduces rapidly.
Constitute the P channel MOS transistor 9a of inverter 9 and grid length L9a, the L9b (for example, 0.1 μ m) of N-channel MOS transistor 9b, be arranged to shorter than other transistorized grid lengths (for example, 0.4 μ m).Best, be provided with into about about 0.2～0.5 times.This is because inverter 9 uses the power-supply system of the power supply potential VDDL lower than power supply potential VDDH.
The variation of embodiment 1
With reference to the level-conversion circuit of figure 7, with the level-conversion circuit difference of Fig. 1 be to have replaced N-channel MOS transistor 6 with P channel MOS transistor 21.In addition, in Fig. 7, use identical symbol, do not repeat its detailed description with the part that Fig. 1 is corresponding.
P channel MOS transistor 21, its source electrode is connected with node N1, and its drain electrode is connected with the drain electrode of N-channel MOS transistor 7, and its grid is connected with output auspicious sub 2.This P channel MOS transistor 21 is elevated to " H " level (VDDL) corresponding to input signal from " L " level (0V), if the current potential of lead-out terminal 2 is elevated to " H " level (VDDH) from " L " level (0V), then becomes non-conduction.In addition, be reduced to " L " level (0V) from " H " level (VDDL) corresponding to input signal, if the current potential of lead-out terminal 2 is when " H " level (VDDH) is reduced to " L " level (0V), then conducting.
Thereby level-conversion circuit shown in Figure 7 is carried out the level translation action identical with level-conversion circuit shown in Figure 1, represents that the sequential chart of this action is identical with Fig. 2.Thereby, identical in the variation of present embodiment 1 with the occasion of embodiment 1, can realize level translation action at a high speed, the level-conversion circuit that low consumpting power and versatility are high.
With reference to the level-conversion circuit of figure 8, with the difference of the level-conversion circuit of Fig. 1 be to have appended P channel MOS transistor 31.In addition, in Fig. 8, use identical symbol, do not repeat its detailed description with the part that Fig. 1 is corresponding.
P channel MOS transistor 31 is connected between power supply potential VDDH line and the node N1.The grid of P channel MOS transistor 31 is connected with lead-out terminal 2.Drop to the occasion of " L " level (0V) at input signal from " H " level (VDDL), N-channel MOS transistor 7 becomes non-conduction, 8 conductings of N-channel MOS transistor.Here, because that N-channel MOS transistor 7 becomes is non-conduction, thereby irrelevant with the conducting state of N-channel MOS transistor 6, no current flows through in the P channel MOS transistor 3,4.
But, because the deviation of transistorized manufacture craft and the layout of circuit have characteristics of transistor (threshold voltage etc.) occasion different with design load.This occasion flows through even constitute current mirror no current in the P of circuit channel MOS transistor 3, also has very little leakage current to flow through in the P channel MOS transistor 4.
Thereby, in the present embodiment 2, P channel MOS transistor 31 is set, prevent to flow through leakage current in the P channel MOS transistor 4.More specifically, input signal drops to the occasion of " L " level (0V) from " H " level (VDDL), and corresponding to 8 conductings of N-channel MOS transistor, the current potential of node N2 reduces.Current potential corresponding to node N2 becomes lower than the threshold voltage of inverter 10, and inverter 10 makes the current potential of node N3 be elevated to " H " level (VDDH), and inverter 11 makes the current potential of lead-out terminal 2 drop to " L " level (0V).Corresponding therewith, 31 conductings of P channel MOS transistor, node N1 is set to " H " level (VDDH).Thereby P channel MOS transistor 3,4 can be set at non-conduction reliably.Thereby, can prevent to flow through leakage current in the P channel MOS transistor 4.Thereby, can realize the more low consumpting powerization of level-conversion circuit.
In addition, in order not influence the responsiveness of level translation, the current driving ability that P channel MOS transistor 31 is set is for enough little.
In addition, the grid at P channel MOS transistor 31 describes with the occasion that lead-out terminal 2 is connected here, and the grid of P channel MOS transistor 31 also can be connected with node N2.
Fig. 9 is the circuit diagram of the level-conversion circuit formation of the occasion that is connected with node N2 of the grid of expression P channel MOS transistor 31.Node N2 is connected with the grid of P channel MOS transistor 31 by inverter 10,11 among Fig. 8, and among this Fig. 9, node N2 directly is connected with the grid of P channel MOS transistor 31.Thereby what no inverter 10,11 caused delays, and can apply feedback to P channel MOS transistor 31 in earlier stage.
Figure 10 is the plane graph of the layout of expression level-conversion circuit shown in Figure 9.Among Figure 10, in n well area 111, be provided with the P channel MOS transistor 10a of P channel MOS transistor 3,4,5,31 and formation inverter 10.In p well area 112, be provided with the N-channel MOS transistor 10b of P channel MOS transistor 6,7,8 and formation inverter 10.In n well area 111 and p well area 112, active region AF, gate electrode GE, the 1st layer of metal line ML1 and the 2nd layer of metal line ML2 have been formed.In addition, constitute the formation that is provided with of the P channel MOS transistor 11a of inverter 11 and N-channel MOS transistor 11b,, omit here owing to constitute identically with being provided with of P channel MOS transistor 10a that constitutes inverter 10 and N-channel MOS transistor 10b.
In n well area 111, the gate electrode GE of P channel MOS transistor 3 is connected with its drain electrode by the 1st layer of metal line ML1.The source electrode of P channel MOS transistor 3 is connected with power supply potential VDDH line by the 1st and the 2nd layer of metal line ML1, ML2.The gate electrode GE of P channel MOS transistor 4 is connected with the gate electrode GE of P channel MOS transistor 3 by the 1st layer of metal line ML1.The source electrode of P channel MOS transistor 4 is connected with power supply potential VDDH line by the 1st layer and the 2nd layer of metal line ML1, ML2, and the drain electrode of P channel MOS transistor 4 is connected with the drain electrode of N-channel MOS transistor 8 by the 1st layer and the 2nd layer of metal line ML1, ML2.
The gate electrode GE of P channel MOS transistor 5 by the 1st layer and the 2nd layer of metal line ML1, ML2, is connected with the gate electrode GE of N-channel MOS transistor 6.The source electrode of P channel MOS transistor 5 is connected with power supply potential VDDH line by the 1st layer and the 2nd layer of metal line ML1, ML2, and the drain electrode of P channel MOS transistor 5 is connected with the drain electrode of P channel MOS transistor 4 by the 1st layer and the 2nd layer of metal line ML1, ML2.The gate electrode GE of P channel MOS transistor 31 by the 1st layer of metal line ML1, is connected with the drain electrode of P channel MOS transistor 5.The source electrode of P channel MOS transistor 31 by the 1st layer and the 2nd layer of metal line ML1, ML2, is connected with power supply potential VDDH line, and the drain electrode of P channel MOS transistor 31 by the 1st layer of metal line ML1, is connected with the drain electrode of P channel MOS transistor 3.
In n well area 111 and p well area 112, constitute the gate electrode GE of the P channel MOS transistor 10a of inverter 10, by the 1st and the 2nd layer of metal line ML1, ML2, be connected with the gate electrode GE of N-channel MOS transistor 10b.The source electrode of P channel MOS transistor 10a, by the 1st layer and the 2nd layer of metal line ML1, ML2, be connected with power supply potential VDDH line, the drain electrode of P channel MOS transistor 10a, by the 1st layer and the 2nd layer of metal line ML1, ML2, be connected with the drain electrode of N-channel MOS transistor 10b, also be connected simultaneously with the input node of inverter 11.The source electrode of N-channel MOS transistor 10b by the 1st layer and the 2nd layer of metal line ML1, ML2, is connected with earthing potential GND line.P channel MOS transistor 10a is arranged to 4 row, and N-channel MOS transistor 10b is arranged to 2 row.
In p well area 112, the gate electrode GE of N-channel MOS transistor 6 by the 1st layer and the 2nd layer of metal line ML1, ML2, is connected with the drain electrode of N-channel MOS transistor 10b.The drain electrode of N-channel MOS transistor 6 by the 1st layer and the 2nd layer of metal line ML1, ML2, is connected with the gate electrode GE of P channel MOS transistor 4, and the source electrode of N-channel MOS transistor 6 is connected with the drain electrode of N-channel MOS transistor 7.The gate electrode GE of N-channel MOS transistor 7 by the 1st layer and the 2nd layer of metal line ML1, ML2, is connected with input terminal 1.The source electrode of N-channel MOS transistor 7 by the 1st layer and the 2nd layer of metal line ML1, ML2, is connected with earthing potential GND line.The gate electrode GE of N-channel MOS transistor 8 by the 1st layer and the 2nd layer of metal line ML1, ML2, is connected with the output node of inverter 9.The drain electrode of N-channel MOS transistor 8 by the 1st layer and the 2nd layer of metal line ML1, ML2, is connected with the drain electrode of P channel MOS transistor 4, and the source electrode of N-channel MOS transistor 8 is connected with earthing potential GND line by the 1st layer and the 2nd layer of metal line ML1, ML2.
In addition, each transistorized gate electrode GE is all arranged (being vertical direction among the figure) in the same direction.Thereby, can suppress transistorized manufacture deviation.
An each transistorized grid length that table 2 expression is shown in Figure 10 and an example of grid width.In addition, transistor 9a, 9b, expression constitutes the P channel MOS transistor 9a and the N-channel MOS transistor 9b of inverter 9 shown in Figure 9 respectively.In addition, transistor 11a, 11b, expression constitutes the P channel MOS transistor 11a and the N-channel MOS transistor 11b of inverter 11 shown in Figure 9 respectively.
Table 2
| Grid width W (μ m) | Grid length L (μ m) | |
| | 4.0 | 0.4 |
| | 16.0 | 0.4 |
| | 0.32 | 0.5 |
| | 5.5 | 0.4 |
| | 5.5 | 0.4 |
| | 7.0 | 0.4 |
| Transistor 9a | 3.36 | 0.1 |
| Transistor 9b | 1.3 | 0.1 |
| | 20.0 | 0.4 |
| | 8.3 | 0.4 |
| | 20.0 | 0.4 |
| | 8.3 | 0.4 |
| | 0.4 | 0.4 |
Reference table 2, the grid width W31 of P channel MOS transistor 31 (for example, 0.4 μ m), the grid width W7 (for example, 5.5 μ m) that is arranged to than N-channel MOS transistor 7 is enough little.Best, be provided with into about about 0.03～0.2 times.Thereby the current driving ability of P channel MOS transistor 31 becomes enough littler than the current driving ability of N-channel MOS transistor 7.Thereby input signal is elevated to " H " level from " L " level, and during 7 conductings of N-channel MOS transistor, the current potential of node N1 reduces rapidly.
In addition, because the magnitude relationship of other transistorized grid width W and grid length L is identical with the occasion of using table 1 explanation, omit explanation here.
The variation of embodiment 2
With reference to the level-conversion circuit of Figure 11, with the level-conversion circuit difference of Fig. 9 be to have replaced N-channel MOS transistor 6 with P channel MOS transistor 41.In addition, in Fig. 7, use identical symbol, do not repeat its detailed description with the part that Fig. 9 is corresponding.
P channel MOS transistor 41, its source electrode is connected with node N1, and its drain electrode is connected with the drain electrode of N-channel MOS transistor 7, and its grid is connected with lead-out terminal 2.This P channel MOS transistor 41 is elevated to " H " level (VDDL) corresponding to input signal from [L] level (0V), if the current potential of lead-out terminal 2 is elevated to " H " level (VDDH) from " L " level (0V), then becomes non-conduction.In addition, drop to " L " level (0V) from " H " level (VDDL) corresponding to input signal, if the current potential of lead-out terminal 2 is when " H " level (VDDH) drops to " L " level (0V), then conducting.
Thereby level-conversion circuit shown in Figure 11 is carried out the level translation action identical with level-conversion circuit shown in Figure 9.Thereby, identical in the modification of this embodiment 2 with the occasion of embodiment 2, can prevent flowing of leakage current in the P channel MOS transistor 4.Thereby level-conversion circuit can be realized lower consumed power.
Here, though the occasion that the grid of expression P channel MOS transistor 31 is connected with lead-out terminal 2 also can be that the grid of P channel MOS transistor 31 is connected with node N2.
In addition, though among the embodiment shown in this, (＞VDDL) level-conversion circuit describes, and also can exchange two power-supply systems at the voltage level of input signal is transformed into power supply potential VDDH from power supply potential VDDL.That is also can be that the voltage level of input signal is transformed into power supply potential VDDL (＜VDDH) level-conversion circuit from power supply potential VDDH.In addition, the power supply potential of two power-supply systems also can be identical.Even in any one occasion, by utilizing the formation of current mirror to circuit, with constituent ratio shown in Figure 3, can realize speed-sensitive switch action and low consumpting power.
In addition, also can on same semiconductor chip, make up the level-conversion circuit that a plurality of kinds are set.For example, use the power supply potential occasion of 3 different power-supply systems respectively,, can separately use and be provided with level-conversion circuit shown in Figure 1 and level-conversion circuit shown in Figure 8 according to each power supply potential.
The present invention is described in detail, is construed as: this only is used for illustration, rather than limits, and the spirit and scope of the present invention are limited by additional claim.
Claims (11)
1. level-conversion circuit, with the 1st logic level is that reference potential, the 2nd logic level are the 1st signal of the 1st power supply potential, being transformed into the 1st logic level is that described reference potential, the 2nd logic level are the 2nd signal of the 2nd power supply potential, and offers output node, it is characterized in that possessing:
The 1st electrode receives the 1st transistor of described the 2nd power supply potential, gate electrode and interconnective the 1st conductivity type of the 2nd electrode;
The 1st electrode receives the 2nd transistor of described the 2nd power supply potential, gate electrode and the 1st conductivity type that the described the 1st transistorized gate electrode is connected, the 2nd electrode is connected with the node of regulation;
Gate electrode receives the 3rd transistor of the 2nd conductivity type of described the 1st signal;
Between the described the 1st transistorized the 2nd electrode and described reference potential line, the 1st switch element that is connected with described the 3rd transistor series;
The 1st electrode is connected with the node of described regulation, and gate electrode receives the inversion signal of described the 1st signal, and the 2nd electrode receives the 4th transistor of the 2nd conductivity type of described reference potential;
Be connected the 2nd switch element between the node of described the 2nd power supply potential line and described regulation;
Output circuit when the node potential of the described regulation occasion lower than specified level, makes described the 1st switch element conducting, and it is non-conduction that described the 2nd switch element is in, and described output node is set as described reference potential; When the current potential occasion higher than described specified level of the node of described regulation, it is non-conduction that described the 1st switch element is in, and makes described the 2nd switch element conducting simultaneously, and described output node is set as described the 2nd power supply potential.
2. the described level-conversion circuit of claim 1 is characterized in that,
Described output circuit comprises:
When the node potential of the described regulation occasion lower than described specified level, export described the 2nd power supply potential, when the node potential of the described regulation occasion higher, export the 1st inverter of described reference potential than described specified level;
When the output potential of described the 1st inverter is the occasion of described the 2nd power supply potential, with described output node as described reference potential, when the output potential of described the 1st inverter is the occasion of described reference potential, with 2nd inverter of described output node as described the 2nd power supply potential;
Described the 1st switch element is, gate electrode receives the 5th transistor of the 2nd conductivity type of the output potential of described the 1st inverter,
Described the 2nd switch element is, the 1st electrode receives described the 2nd power supply potential, and gate electrode receives the output potential of described the 1st inverter, the 6th transistor of the 1st conductivity type that the 2nd electrode is connected with the node of described regulation.
3. the described level-conversion circuit of claim 1 is characterized in that,
Described output circuit comprises:
When the node potential of the described regulation occasion lower than specified level, export described the 2nd power supply potential, when the node potential of the described regulation occasion higher, export the 1st inverter of described reference potential than described specified level;
When the output potential of described the 1st inverter is the occasion of described the 2nd power supply potential, described output node is made as described reference potential, when the output potential of described the 1st inverter is the occasion of described reference potential, described output node is made as the 2nd inverter of described the 2nd power supply potential
Described the 1st switch element is, the 5th transistor of the 1st conductivity type that any one node is connected in the node of gate electrode and described regulation or the described output node;
Described the 2nd switch element is, the 1st electrode receives described the 2nd power supply potential, and gate electrode receives the output potential of described the 1st inverter, the 6th transistor of the 1st conductivity type that the 2nd electrode is connected with the node of described regulation.
4. the described level-conversion circuit of claim 1 is characterized in that also possessing:
Be connected the 3rd switch element between described the 2nd power supply potential line and the described the 1st and the 2nd transistorized gate electrode;
Described output circuit when the node potential of the described regulation occasion lower than described specified level, makes described the 3rd switch element conducting, and when the node potential of the described regulation occasion higher than described specified level, it is non-conduction that the 3rd switch element is in.
5. the described level-conversion circuit of claim 4 is characterized in that:
Described the 3rd switch element is, the 1st electrode receives described the 2nd power supply potential, gate electrode is connected with the node of described regulation or any one node of described output node, the 7th transistor of the 1st conductivity type that the 2nd electrode is connected with the described the 1st and the 2nd transistorized gate electrode.
6. the described level-conversion circuit of claim 2 is characterized in that: the described the 6th transistorized current driving ability is littler than the described the 4th transistorized current driving ability.
7. the described level-conversion circuit of claim 6 is characterized in that: the described the 6th transistorized grid width is littler than the described the 4th transistorized grid width.
8. the described level-conversion circuit of claim 6 is characterized in that: the described the 6th transistorized grid length, and longer than the described the 4th transistorized grid length.
9. the described level-conversion circuit of claim 5 is characterized in that: the described the 7th transistorized current driving ability is littler than the described the 3rd transistorized current driving ability.
10. the described level-conversion circuit of claim 9 is characterized in that: the described the 7th transistorized grid width is littler than the described the 3rd transistorized grid width.
11. the described level-conversion circuit of claim 1 is characterized in that: described the 2nd power supply potential, than the 1st power supply potential height.
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| Application Number | Priority Date | Filing Date | Title |
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| JP273007/04 | 2004-09-21 | ||
| JP2004273007 | 2004-09-21 | ||
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510108951 Pending CN1753309A (en) | 2004-09-21 | 2005-09-21 | Level conversion circuit for converting voltage amplitude of signal |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102006053A (en) * | 2009-08-26 | 2011-04-06 | 瑞萨电子株式会社 | Level shift circuit, and driver and display device using the same |
| CN103138740A (en) * | 2011-11-29 | 2013-06-05 | 精工爱普生株式会社 | Level shifter circuit, integrated circuit device and electronic watch |
| CN109713900A (en) * | 2018-12-25 | 2019-05-03 | 广东浪潮大数据研究有限公司 | A kind of electric potential transfer circuit and system low-speed backplane module |
| WO2020057138A1 (en) * | 2018-09-20 | 2020-03-26 | 北京嘉楠捷思信息技术有限公司 | Full swing voltage conversion circuit and operation unit, chip, hashboard, and computing device using same |
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2005
- 2005-09-21 CN CN 200510108951 patent/CN1753309A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102006053A (en) * | 2009-08-26 | 2011-04-06 | 瑞萨电子株式会社 | Level shift circuit, and driver and display device using the same |
| CN102006053B (en) * | 2009-08-26 | 2014-04-02 | 瑞萨电子株式会社 | Level shift circuit, and driver and display device using the same |
| CN103138740A (en) * | 2011-11-29 | 2013-06-05 | 精工爱普生株式会社 | Level shifter circuit, integrated circuit device and electronic watch |
| WO2020057138A1 (en) * | 2018-09-20 | 2020-03-26 | 北京嘉楠捷思信息技术有限公司 | Full swing voltage conversion circuit and operation unit, chip, hashboard, and computing device using same |
| US11409314B2 (en) | 2018-09-20 | 2022-08-09 | Canaan Creative Co., Ltd. | Full swing voltage conversion circuit and operation unit, chip, hash board, and computing device using same |
| CN109713900A (en) * | 2018-12-25 | 2019-05-03 | 广东浪潮大数据研究有限公司 | A kind of electric potential transfer circuit and system low-speed backplane module |
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