CN1747177A - Solid-state image sensor - Google Patents

Solid-state image sensor Download PDF

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Publication number
CN1747177A
CN1747177A CN 200510099187 CN200510099187A CN1747177A CN 1747177 A CN1747177 A CN 1747177A CN 200510099187 CN200510099187 CN 200510099187 CN 200510099187 A CN200510099187 A CN 200510099187A CN 1747177 A CN1747177 A CN 1747177A
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mentioned
gate electrode
extrinsic region
distance
camera head
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CN100394609C (en
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海田孝行
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Abstract

A solid-state image sensor capable of improving detection sensitivity for an output signal is provided. This solid-state image sensor comprises a first gate electrode formed on a semiconductor substrate, a first impurity region formed on the semiconductor substrate at a first distance from the first gate electrode for receiving the signal charges and a second gate electrode formed at a second distance from the first impurity region for discharging unnecessary signal charges after extraction of a voltage signal from the first impurity region. The first distance between the first impurity region and the first gate electrode is larger than the second distance between the first impurity region and the second gate electrode.

Description

Solid camera head
Technical field
The present invention relates to solid camera head, particularly relate to the solid camera head that possesses when signal charge flows into, takes out the extrinsic region of voltage signal.
Background technology
In the past, the common solid camera head that possesses when signal charge flows into, takes out the extrinsic region of voltage signal.Such solid camera head is disclosed in for example speciallys permit in No. 3263197 communique.
Figure 24 be show have with No. 3263197 communique of above-mentioned special permission in the profile of solid camera head of an existing example of disclosed solid camera head same structure.Figure 25 is the potential diagram of the solid camera head of an existing example shown in Figure 24.With reference to Figure 24, the solid camera head of an existing example has n type silicon substrate (n-sub) 101.Certainly this above n type silicon substrate 101 in the zone of prescribed depth, be formed with p type well area (p-well) 102.Surface at this p type well area 102 is formed with the N that is used for the transmission signals electric charge while storing -Type transmission channel region 103.In addition, on transmission channel region 103,, be formed with multistage transmission gate electrode 105 and output gate electrode 106 by the distance of gate insulating film 104 across regulation.Multistage transmission gate electrode 105 is made of the 1st layer of transmission gate electrode 105a and the 2nd layer of transmission gate electrode 105b respectively.
In addition, so-called the 1st layer of transmission gate electrode 105a and the 2nd layer of transmission gate electrode 105b are so that the mode of adjacency is provided with by dielectric film 107.And output gate electrode 106 is with the 1st layer of transmission gate electrode 105a by last level and dielectric film 107 and the mode of adjacency is provided with.And, in transmission gate electrodes 105 at different levels, as shown in figure 25, alternately apply 2 phase clock pulse signal Φ H1 and Φ H2.Constitute and utilize this 2 phase clock pulse signal Φ H1 and Φ H2, about the channel potential that makes the current potential well in the transmission channel region 103 that is formed under the transmission gate electrodes 105 at different levels, transfer to zone under the output gate electrode 106 and will transmit signal charges in the channel region 103.And, output gate electrode 106 is applied the regulation direct voltage V that is used for output gate electrode 106 is remained on on-state OG
And, on the p type well area 102 of n type silicon substrate 101, as shown in figure 24, N ++Type suspension diffusion zone 108 connects transmission channel region 103 and forms.Constitute when signal charge by the output of transmission channel region 103 flows into this suspension diffusion zone 108 and put aside.And, on the p type well area 102 of n type silicon substrate 101, form N ++The drain region 109 of type, so as between itself and suspension diffusion zone 108 clamping N -Type channel region 110.In addition, on this channel region 110, be formed with reset gate electrode 111 by gate insulating film 104.The reseting pulse signal Φ R that these reset gate electrode 111 inputs is used for reset gate electrode 111 is switched to on-state and cut-off state.By above-mentioned suspension diffusion zone 108, drain region 109, channel region 110, gate insulating film 104 and reset gate electrode 111, be configured for discharging from suspension diffusion zone 108 and take out voltage signal V OutAfter resetting of unwanted signal electric charge use MOS transistor.Promptly, constitute: after taking out voltage signal from suspension diffusion zone 108, by making reset gate electrode 111 be in the reseting pulse signal Φ R input reset gate electrode 111 of on-state, thereby the channel region 110 by under the reset gate electrode 111 of on-state is discharged to drain region 109 with the unwanted signal electric charge from suspension diffusion zone 108.
Moreover suspension diffusion zone 108 forms across the distance L of stipulating with output gate electrode 106.Like this, the electric capacity between suspension diffusion zone 108 and the output gate electrode 106 is lowered.And, form interlayer dielectric 112, so that cover on the 2nd layer transmission gate electrode 105b, dielectric film 107, output gate electrode 106, reset gate electrode 111 and the gate insulating film 104.And, in the zone corresponding to suspension diffusion zone 108 of interlayer dielectric 112 and gate insulating film 104, be formed with the contact hole 112a that reaches suspension diffusion zone 108 surfaces.In addition, the mode that extends on the interlayer dielectric 112 when imbedding contact hole 112a forms wiring layer 113.In addition, wiring layer 113 is connecting source electrode follower type output amplifier 114 (with reference to Figure 25).This source electrode follower type output amplifier 114 is in the signal charge that takes out savings by wiring layer 113 in suspension diffusion zone 108, amplifies the signal charge of this taking-up, and is transformed to voltage signal V OutAnd be provided with.And, the voltage signal V of this conversion OutOutput to the outside by output amplifier 114.
Moreover, be fetched into the signal voltage of output amplifier 114 by suspension diffusion zone 108, according to the total capacitance C of suspension diffusion zone 108 FdChange.That is, along with the total capacitance C of suspension diffusion zone 108 FdChange big, the signal voltage that is fetched into output amplifier 114 by suspension diffusion zone 108 reduces.Otherwise, along with the total capacitance C of suspension diffusion zone 108 FdDiminish, the signal voltage that is fetched into output amplifier 114 by suspension diffusion zone 108 increases.The total capacitance C of suspension diffusion zone 108 FdRepresent by following formula (1).
C fd＝C d+C 1+C 2+C g …(1)
In this formula (1), C dBe the electric capacity between suspension diffusion zone 108 and the p type well area 102; C 1Be the electric capacity between suspension diffusion zone 108 and the output gate electrode 106.In addition, C 2Be the electric capacity between suspension diffusion zone 108 and the reset gate electrode 111; C gBe the electric capacity between suspension diffusion zone 108 and the output amplifier 114.
In the solid camera head of an existing example shown in Figure 24, by reduce the capacitor C between suspension diffusion zone 108 and the output gate electrode 106 in the distance L that regulation is set between suspension diffusion zone 108 and the output gate electrode 106 1, but be considered to only with the total capacitance C of this method to abundant reduction suspension diffusion zone 108 FdBe difficult.Thus, owing to fully increase the signal voltage that takes out to output amplifier 114 from suspension diffusion zone 108 difficulty that becomes, so in output amplifier 114, often have the signal that takes out from suspension diffusion zone 108 difficult this problem that becomes that detects.Consequently, low this problem of detection sensitivity that has output signal.
Summary of the invention
The present invention carries out in order to solve above-mentioned problem, and one of purpose of the present invention provides a kind of solid camera head that improves the detection sensitivity of output signal.
In order to achieve the above object, the solid camera head of one aspect of the present invention, possessing has: be formed on the 1st gate electrode on the semiconductor substrate; Be formed on the semiconductor substrate with the 1st gate electrode interval the 1st distance, and flow into the 1st extrinsic region of signal charge; With the 1st extrinsic region the 2nd distance and forming at interval, be used to discharge the 2nd gate electrode that takes out the unwanted signal electric charge behind the voltage signal from the 1st extrinsic region.In addition, the distance of the 1st between the 1st extrinsic region and the 1st gate electrode is also bigger than the distance of the 2nd between the 1st extrinsic region and the 2nd gate electrode.
In the solid camera head aspect this, as mentioned above, by when the 1st distance forms the 1st extrinsic region at interval with the 1st gate electrode, form the 2nd gate electrode with the 1st extrinsic region interval the 2nd distance, thereby can reduce electric capacity between the 1st extrinsic region and the 1st gate electrode and the electric capacity between the 2nd gate electrode and the 1st extrinsic region, so with only compare in the situation that predetermined distance is set between the 1st extrinsic region and the 1st gate electrode, can further reduce to relate to the relevant electric capacity of the 1st extrinsic region.Like this, owing to can increase the signal voltage that takes out from the 1st extrinsic region, so can improve the detection sensitivity of output signal.
In the solid camera head aspect above-mentioned one, preferably also possesses the electric charge savings portion that is formed on the semiconductor substrate and has the function of savings signal charge, the 1st gate electrode has the function that is used for from electric charge savings portion output signal electric charge, and the signal charge of exporting from electric charge savings portion flows into the 1st extrinsic region.According to this formation, by the 1st gate electrode, can easily make signal charge from the output of electric charge savings portion, the electric charge of this output can be flowed into first extrinsic region simultaneously.And, even because guarantee electric charge savings portion signal charge the savings capacity and electric charge is put aside long-pending increase the in plane of portion, compare with the electric capacity between the 1st extrinsic region and the 2nd gate electrode, electric capacity between the 1st extrinsic region and the 1st gate electrode becomes under the big situation, as long as make the distance of the 1st between the 1st extrinsic region and the 1st gate electrode also bigger than the distance of the 2nd between the 1st extrinsic region and the 2nd gate electrode, just can make the reduction of the electric capacity between the 1st extrinsic region and the 1st gate electrode also bigger, therefore can effectively reduce the electric capacity between the 1st extrinsic region and the 1st gate electrode than the reduction of the electric capacity between the 1st extrinsic region and the 2nd gate electrode.
In the solid camera head aspect above-mentioned one, preferably, be set at than the distance that on the zone between the 1st extrinsic region and the 1st gate electrode, forms potential barrier (potential barrier) and also want little distance the 1st distance between the 1st extrinsic region and the 1st gate electrode; The 2nd distance between the 1st extrinsic region and the 2nd gate electrode is set at than the also little distance of distance that forms potential barrier on the zone between the 1st extrinsic region and the 2nd gate electrode.According to this formation, even owing between the 1st extrinsic region and the 1st gate electrode, be provided with under the situation of the 1st distance, zone between the 1st extrinsic region and the 1st gate electrode can not form potential barrier yet, so can suppress the state of affairs that the inflow to the signal charge of the 1st extrinsic region is stoped by potential barrier.Like this, even between the 1st extrinsic region and the 1st gate electrode, be provided with under the situation of the 1st distance, also can suppress to transmit the problem of the efficient reduction of signal charge to the 1st extrinsic region.And, by with the 2nd distance between the 1st extrinsic region and the 2nd gate electrode, be set at than the also little distance of distance that on the zone between the 1st extrinsic region and the gate electrode, forms potential barrier, even thereby between the 1st extrinsic region and the 2nd gate electrode, be provided with under the situation of the 2nd distance, can not form potential barrier in the zone between the 1st extrinsic region and the 2nd gate electrode.Like this, though discharge the unwanted signal electric charge by the zone between the 1st extrinsic region and the 2nd gate electrode, can suppress the prevention that causes by potential barrier from the 1st extrinsic region.Therefore, even between the 1st extrinsic region and the 2nd gate electrode, be provided with under the situation of the 2nd distance, also can fully discharge the unwanted signal electric charge from the 1st extrinsic region.
In the solid camera head aspect above-mentioned one, preferably in the part in the 1st extrinsic region of semiconductor substrate and the zone between the 1st gate electrode, also possess and the 1st gate electrode the 3rd distance and the 2nd extrinsic region that forms at interval; The 2nd extrinsic region has more taller than the impurity concentration in the zone beyond the 1st extrinsic region of semiconductor substrate and the 2nd extrinsic region between the 1st gate electrode, and than the also low impurity concentration of impurity concentration of the 1st extrinsic region.According to this formation, utilize the 2nd extrinsic region can reduce the channel potential (channel potential) in the 1st extrinsic region of semiconductor substrate and the part zone between the 1st gate electrode, the zone that therefore can be suppressed between the 1st extrinsic region and the 1st gate electrode forms potential barrier.Like this, owing to make the distance of the 1st between the 1st extrinsic region and the 1st gate electrode bigger, so can make the electric capacity between the 1st extrinsic region and the 1st gate electrode littler.In addition, form by making the 2nd extrinsic region have the impurity concentration lower than the 1st extrinsic region, and form with the 1st gate electrode interval the 3rd distance, even thereby the zone between the 1st extrinsic region and the 1st gate electrode forms under the situation of the 2nd extrinsic region, the electric capacity that also can suppress between the 2nd extrinsic region and the 1st gate electrode becomes big.And in this case, the 2nd extrinsic region also can form continuously with the 1st extrinsic region.
Be provided with in the formation of the 3rd distance between above-mentioned the 2nd extrinsic region and the 1st gate electrode, preferably the 3rd distance setting between the 2nd extrinsic region and the 1st gate electrode is than the also little distance of distance that forms potential barrier in the zone between the 2nd extrinsic region and the 1st gate electrode.Constitute according to this,, can suppress to flow into the phenomenon that signal charge is stoped by potential barrier by the 2nd extrinsic region to the 1st extrinsic region owing to do not form potential barrier in the zone between the 2nd extrinsic region and the 1st gate electrode.Like this, can suppress the problem that reduces to the efficient of the 1st extrinsic region transmission signals electric charge.
In the formation that comprises above-mentioned the 2nd extrinsic region, preferably be about 1/2 width of the 1st distance between the 1st extrinsic region and the 1st gate electrode along the direction length setting of the signal charge transmission direction of the 2nd extrinsic region.Constitute according to this, can easily be equivalent to about 1/2 the 3rd distance of the 1st distance between the 1st extrinsic region and the 1st gate electrode at interval, and the 1st gate electrode between form the 2nd extrinsic region.
In the solid camera head aspect above-mentioned one, preferably also possess: be formed on the semiconductor substrate by the zone under the 1st extrinsic region and the 2nd gate electrode, and discharge the 3rd extrinsic region of unwanted signal electric charge by the 1st extrinsic region, after taking out voltage signal by the 1st extrinsic region, by making the 2nd gate electrode be in on-state, and the unwanted signal electric charge is discharged to the 3rd extrinsic region from the zone of the 1st extrinsic region under the 2nd gate electrode.According to this formation, utilize the 2nd gate electrode easily the unwanted signal electric charge to be discharged to the 3rd extrinsic region from the 1st extrinsic region.
In this case, the 1st signal that preferably will be used to make the 2nd gate electrode switch to on-state and cut-off state is input to the 2nd gate electrode.According to this formation, after taking out voltage signal from the 1st extrinsic region by the 1st signal, by the 2nd gate electrode is switched to on-state, thereby can easily control, so that take out unwanted signal electric charge behind the voltage signal, be discharged to the 3rd extrinsic region from the 1st extrinsic region from the 1st extrinsic region.
In the formation that comprises above-mentioned electric charge savings portion, preferably electric charge savings portion comprises the transmission raceway groove of the transmission signals electric charge while storing.Constitute according to this, relate to inflow and become littler owing to can make, so can make the signal voltage increase of taking out by the 1st extrinsic region by the electric capacity of the 1st extrinsic region of the signal charge of transmission raceway groove output.Like this, in comprising the solid camera head that transmits raceway groove, can improve the detection sensitivity of the output signal of exporting by the 1st extrinsic region by the transmission raceway groove.In addition, even because guarantee to transmit raceway groove signal charge memory capacity and make long-pending increase the in plane of transmission raceway groove, compare with the electric capacity between the 1st extrinsic region and the 2nd gate electrode, electric capacity between the 1st extrinsic region and the 1st gate electrode becomes under the big situation, also can make the reduction amount of the electric capacity between the 1st extrinsic region and the 1st gate electrode also bigger, therefore can reduce inflow effectively from the 1st extrinsic region of the signal charge of transmission raceway groove and the electric capacity between the 1st gate electrode than the reduction amount of the electric capacity between the 1st extrinsic region and the 2nd gate electrode.
In this case, preferably also possess the multistage transmission gate electrode of the transmission of being formed on the raceway groove, by alternately applying 2 phase transmission signals, thereby can the signal charge in the transmission raceway groove be transmitted to transmission gate electrodes at different levels.According to this formation,, can easily transmit the signal charge that transmits raceway groove by multistage transmission gate electrode.
In the formation that comprises above-mentioned multistage transmission gate electrode, preferably also possess the signal charge that is used for by the transmission of transmission raceway groove and be fetched into the 1st outside efferent; The 1st efferent comprises: with the transmission gate electrode of the most last utmost point in abutting connection with setting, and be used for from corresponding to the 1st gate electrode of the transmission raceway groove output signal electric charge of the transmission gate electrode of the last utmost point; Inflow is from the 1st extrinsic region corresponding to the signal charge of the transmission raceway groove output of the most last utmost point transmission gate electrode; Be connected the 1st extrinsic region, and be used for signal charge being fetched into outside distribution from the 1st extrinsic region.According to this formation, utilize the 1st efferent, can through the 1st extrinsic region, signal charge be fetched into the outside easily from transmission raceway groove corresponding to the most last utmost point transmission gate electrode.
In this case, preferably also possess: connect distribution, and amplifying in the signal charge that the 1st extrinsic region takes out, be transformed to the output enlarging section of voltage signal.According to this formation, owing to utilize the output enlarging section can obtain the signal charge that takes out through the 1st extrinsic region from the transmission raceway groove has been carried out the voltage signal that amplifies, even so under the situation little, also can obtain big voltage signal from the signal charge of transmission raceway groove.
Comprising inflow, preferably will be used to make the 1st gate electrode to keep the assigned voltage of on-state to be applied to the 1st gate electrode by corresponding in the constituting of the 1st extrinsic region of the signal charge of the transmission raceway groove output of above-mentioned the most last utmost point transmission gate electrode.Constitute according to this, can be easily by the zone under the 1st gate electrode of on-state, make signal charge from corresponding to the transmission raceway groove of the transmission gate electrode of the last utmost point, flow into the 1st extrinsic region.
In the formation that comprises above-mentioned electric charge savings portion, preferably electric charge savings portion comprises: generated the photoelectric conversion department of putting aside in the signal charge by light-to-current inversion.Constitute according to this,, the signal voltage that is taken out by the 1st extrinsic region is increased because inflow is reduced by the electric capacity of the 1st extrinsic region of the signal charge of photoelectric conversion department output.Therefore, in comprising the solid camera head of photoelectric conversion department, can improve by the detection sensitivity of photoelectric conversion department by the output signal of the 1st extrinsic region output.In addition, even because guarantee photoelectric conversion department signal charge memory capacity and to increase the plane of photoelectric conversion department long-pending, compare with the electric capacity between the 1st extrinsic region and the 2nd gate electrode, electric capacity between the 1st extrinsic region and the 1st gate electrode becomes under the big situation, owing to can make the electric capacity reduction amount between the 1st extrinsic region and the 1st gate electrode also bigger, so can effectively reduce inflow from the 1st extrinsic region of the signal charge of photoelectric conversion department and the electric capacity between the 1st gate electrode than the reduction amount of the electric capacity between the 1st extrinsic region and the 2nd gate electrode.
In this case, a plurality of photoelectric conversion departments are set preferably, also possess: the signal charge that be arranged in each photoelectric conversion department, is used for being generated by photoelectric conversion department is fetched into the 2nd outside efferent; The 2nd efferent comprises: with photoelectric conversion department in abutting connection with setting, and be used for from the 1st gate electrode of photoelectric conversion department output signal electric charge; Inflow is by the 1st extrinsic region of the signal charge of photoelectric conversion department output; Be connected the 1st extrinsic region, can not be used for signal charge being fetched into outside distribution from the 1st extrinsic region.According to this formation, utilize the 2nd efferent, can easily by each the 1st extrinsic region signal charge be fetched into the outside from a plurality of photoelectric conversion departments.
Comprising the formation that is used for above-mentioned signal charge is fetched into outside distribution, preferably also possessing: connecting distribution, and when the signal charge that will be taken out by the 1st extrinsic region amplifies, be transformed to the output enlarging section of voltage signal.According to this formation, owing to utilize the output enlarging section can obtain the signal charge that takes out by the 1st extrinsic region from photoelectric conversion department was carried out the voltage signal of amplification, even so under the situation little, also can obtain big signal voltage from the signal charge of photoelectric conversion department.
Comprise in the formation of photoelectric conversion department in above-mentioned electric charge savings portion, preferably when carrying out light-to-current inversion by photoelectric conversion department, make the 1st gate electrode be in cut-off state, when signal charge being transferred to the 1st extrinsic region, make the 1st gate electrode be in on-state simultaneously from photoelectric conversion department.According to this formation, when carrying out light-to-current inversion by photoelectric conversion department, can suppress signal charge exports by the zone under the 1st gate electrode of cut-off state, and when signal charge being transferred to the 1st extrinsic region, can export signal charge to photoelectric conversion department by the zone under the 1st gate electrode of on-state from photoelectric conversion department.Like this, can easily when light-to-current inversion, signal charge be put aside photoelectric conversion department, and when transmission, signal charge can be transferred to the 1st extrinsic region from photoelectric conversion department.
In this case, the 2nd signal that preferably will be used to make the 1st gate electrode switch to on-state and cut-off state is input to the 1st gate electrode.According to this formation, utilize the 2nd signal when carrying out light-to-current inversion, can easily the 1st gate electrode be placed cut-off state by photoelectric conversion department, and, can easily the 1st gate electrode be placed on-state when photoelectric conversion department transfers to the 1st extrinsic region with signal charge.
Comprise in the formation of photoelectric conversion department in above-mentioned electric charge savings portion, preferably also possess the surperficial screen that is formed on the photoelectric conversion department surface and is used to suppress the exhausting of photoelectric conversion department near surface.
Description of drawings
Fig. 1 is the profile of structure of the solid camera head of expression the 1st execution mode of the present invention.
Fig. 2 is the potential diagram of the solid camera head of the 1st execution mode shown in Figure 1.
Fig. 3 is the potential diagram of comparative example of effect that is used to illustrate the solid camera head of the 1st execution mode shown in Figure 1.
Fig. 4～Fig. 8 is the profile of manufacturing process that is used to illustrate the solid camera head of the 1st execution mode of the present invention.
Fig. 9 is the profile of structure of the solid camera head of expression the 2nd execution mode of the present invention.
Figure 10 is the potential diagram of the solid camera head of the 2nd execution mode shown in Figure 9.
Figure 11 is the potential diagram of comparative example of effect that is used to illustrate the solid camera head of the 2nd execution mode shown in Figure 9.
Figure 12 and Figure 13 are the profiles of manufacturing process that is used to illustrate the solid camera head of the 2nd execution mode of the present invention.
Figure 14～Figure 17 is the profile of manufacturing process of solid camera head that is used to illustrate the variation of the 2nd execution mode of the present invention.
Figure 18 is the profile of structure of the cmos image sensor of expression the present invention the 3rd execution mode.
Figure 19 is the potential diagram of the cmos image sensor of expression the present invention the 3rd execution mode.
Figure 20 is the profile of structure of the cmos image sensor of expression the present invention the 4th execution mode.
Figure 21 is the potential diagram of the cmos image sensor of expression the present invention the 4th execution mode.
Figure 22 is the profile of structure of solid camera head of the variation of expression the 3rd execution mode of the present invention.
Figure 23 is the profile of structure of solid camera head of the variation of expression the 4th execution mode of the present invention.
Figure 24 is the profile of the structure of the existing routine solid camera head of expression.
Figure 25 is the potential diagram of an existing routine solid camera head shown in Figure 24.
Embodiment
Below, embodiments of the present invention are described with reference to the accompanying drawings.
(the 1st execution mode)
At first, with reference to Fig. 1 and Fig. 2, the structure of the solid camera head of the 1st execution mode is described.
The solid camera head of the 1st execution mode has n type silicon substrate 1 as shown in Figure 1.And this n type silicon substrate 1 example that is the present invention's " semiconductor substrate ".In addition, the depth areas beginning above n type silicon substrate 1 more than about 0.5 μ m, below about 4 μ m is formed with p type well area 2.In addition, on the surface of p type well area 2, be formed with and have about 10 16Cm -3The N of impurity concentration -Type transmission channel region 3.This transmission channel region 3 is examples of the present invention " electric charge savings portion ".And transmission channel region 3 is formed at above n type silicon substrate 1 zone of the degree of depth of about 0.5 μ m.And transmission channel region 3 has the function of storage signal electric charge limit, limit transmission.And, on transmission channel region 3, by by SiO with about 50nm thickness 2The gate insulating film 4 that constitutes, the distance of regulation is formed with multistage transmission gate electrode 5 and output gate electrode 6 at interval.And this output gate electrode 6 is examples of the present invention's " the 1st gate electrode ".In addition, multistage transmission gate electrode 5 and output gate electrode 6 are formed by polysilicon.In addition, multistage transmission gate electrode 5 is made of with the 2nd layer of gate electrode 5b with about 300nm thickness the 1st layer of transmission gate electrode 5a with about 70nm thickness respectively.Have, output gate electrode 6 has the thickness of about 300nm again.
In addition, ground floor transmission gate electrode 5a and the 2nd layer of transmission gate electrode 5b pass through by SiO 2Constitute dielectric film 7 in abutting connection with being provided with.And output gate electrode 6 is by the 1st layer of transmission gate electrode 5a of final stage with by SiO 2The dielectric film 7 that constitutes is in abutting connection with being provided with.In addition, dielectric film 7 forms to cover the 1st layer of mode of transmitting the top and side of gate electrode 5a.Moreover, on transmission gate electrode 5 at different levels, as shown in Figure 2, alternately apply 2 phase clock pulse signal Φ H1 and Φ H2.And this clock pulse signal Φ H1 and Φ H2 are the present invention's's " transmission signals " examples.In addition, constitute: by utilizing 2 phase clock pulse signal Φ H1 and Φ H2, make about the channel potential of the current potential well in the transmission channel region 3 that is formed under the transmission gate electrodes 5 at different levels, thereby the savings of the zone under transmission gate electrodes 5 at different levels transmits the signal charge in the channel region 3 on one side, Yi Bian be transferred to the zone under the output gate electrode 6 successively.In addition, on output gate electrode 6, apply the regulation direct voltage V that is used for output gate electrode 6 is remained on on-state OCLike this, constitute: by the transmission channel region 3 under the output gate electrode 6, be transferred to suspension diffusion zone 8 described later by the signal charge that transmits gate electrode 5 transmission.
In addition, on the p type well area 2 of n type silicon substrate 1, be formed with continuously and have about 10 with transmission channel region 3 20Cm -3The N of above impurity concentration ++Type suspension diffusion zone 8.And this suspension diffusion zone 8 is examples of the present invention's " the 1st extrinsic region ".And, constitute when suspension diffusion zone 8 flows into the signal charge of being exported by transmission channel region 3 and put aside.In addition, on the p type well area 2 of n type silicon substrate 1, with at clamping N between itself and the suspension diffusion zone 8 -The mode of type channel region 10 is formed with and has about 10 20Cm -3The N of above impurity concentration ++Type drain region 9.And this drain region 9 is examples of the present invention's " the 3rd extrinsic region ".In addition, N - Type channel region 10 has about 10 16Cm -3Impurity concentration.In addition, on channel region 10,, be formed with the reset gate electrode 11 that constitutes by polysilicon with about 300nm thickness by gate insulating film 4.And this reset gate electrode 11 is examples of the present invention's " the 2nd gate electrode ".In addition, be used for reset gate electrode 11 is switched to the reseting pulse signal Φ R of on-state and cut-off state to reset gate electrode 11 inputs.By above-mentioned suspension diffusion zone 8, drain region 9, channel region 10, gate insulating film 4 and reset gate electrode 11, be configured for discharging the resetting of unwanted signal electric charge of taking out behind the voltage signals from suspension diffusion zone 8 and use MOS transistor.That is, behind suspension diffusion zone 8 taking-up voltage signals, will make reset gate electrode 11 be in the reseting pulse signal Φ R input reset gate electrode 11 of on-state.Like this, constitute: the channel region 10 by under the reset gate electrode 11 of on-state is discharged to drain region 9 with the unwanted signal electric charge from suspension diffusion zone 8.And above-mentioned reseting pulse signal Φ R is an example of " the 1st signal " of the present invention.
At this, in the 1st execution mode, suspension diffusion zone 8 forms with output gate electrode 6 spacing distance L1, simultaneously, forms with reset gate electrode 11 spacing distance L2.And this distance L 1 is an example of the present invention's " the 1st distance "; Distance L 2 is examples of the present invention's " the 2nd distance ".Thus, can reduce electric capacity between suspension diffusion zone 8 and the output gate electrode 6; And the electric capacity between suspension diffusion zone 8 and the reset gate electrode 11.In addition, the distance L 1 between suspension diffusion zone 8 and the output gate electrode 6 constitutes: also bigger than the distance L between suspension diffusion zone 8 and the reset gate electrode 11 2.
In addition, in the 1st execution mode, shown in the potential diagram of Fig. 2, distance L 1 and L2 are set at respectively than the also little distance of distance that forms potential barrier in the zone of 11 of the zone of 6 of suspension diffusion zone 8 and output gate electrodes and suspension diffusion zone 8 and reset gate electrodes.In addition, as shown in Figure 1, form by SiO 2The interlayer dielectric 12 that constitutes is so that cover the 2nd layer transmission gate electrode 5b, dielectric film 7, output gate electrode 6, reset gate electrode 11 and gate insulating film 4.And, in the zone corresponding to suspension diffusion zone 8 of interlayer dielectric 12 and gate insulating film 4, be formed with the contact hole 12a that reaches suspension diffusion zone 8 surfaces.In addition, when imbedding contact hole 12a, to extend to the mode on the interlayer dielectric 12, form the wiring layer 13 that constitutes by tungsten.Thus, wiring layer 13 constitutes: be connected to suspension diffusion zone 8, by wiring layer 13, can signal charge be fetched into the outside from suspension diffusion zone 8.And, by above-mentioned output gate electrode 6, suspension diffusion zone 8 and wiring layer 13, be configured for the signal charge by 3 transmission of transmission channel region is fetched into outside efferent 50.And this efferent 50 is examples of the present invention's " the 1st efferent ".
In addition, wiring layer 13 is connected with source follower type output amplifier 14 (with reference to Fig. 2).This source follower type output amplifier 14 is for the signal charge that will put aside in suspension diffusion zone 8 takes out by wiring layer 13, amplifies the signal charge of this taking-up simultaneously, and is transformed to voltage signal V OutAnd be provided with.And, the voltage signal V of this conversion Out, output to the outside from output amplifier 14.Moreover, be fetched into the signal voltage V of output amplifier 14 from suspension diffusion zone 8 OutaRepresent by following formula (2).
V outa＝Q s/C fda …(2)
And, in following formula (2), Q sIt is the quantity of electric charge of the signal charge of savings in suspension diffusion zone 8.In addition, C FdaBe the total capacitance of suspension diffusion zone 8, represent by following formula (3).
C fda＝C da+C 1a+C 2a+C ga …(3)
And, in this formula (3), C DaBe the electric capacity between suspension diffusion zone 8 and the p type well area 2; C 1aBe the electric capacity between suspension diffusion zone 8 and the output gate electrode 6.In addition, C 2aBe the electric capacity between suspension diffusion zone 8 and the reset gate electrode 11, C GaBe the electric capacity between suspension diffusion zone 8 and the output amplifier 14.
In the 1st execution mode, by forming suspension diffusion zone 8 in mode with output gate electrode 6 spacing distance L1, thereby compare the capacitor C between suspension diffusion zone 8 and the output gate electrode 6 between suspension diffusion zone 8 and output gate electrode 6 with the situation that distance is not set 1Diminish.In addition, by forming suspension diffusion zone 8, thereby compare the capacitor C between suspension diffusion zone 8 and the reset gate electrode 11 between suspension diffusion zone 8 and reset gate electrode 11 with the situation that distance is not set in mode with reset gate electrode 11 spacing distance L2 2Diminish.Like this, because the total capacitance C of suspension diffusion zone 8 FdaDiminish, so be fetched into the signal voltage V of output amplifier 14 from suspension diffusion zone 8 OutaBecome big.
Secondly, with reference to Fig. 2, the action of the solid camera head of the 1st execution mode is described.In the solid camera head of the 1st execution mode, alternately transmission gate electrodes 5 at different levels are applied 2 phase clock pulse Φ H1 and Φ H2 respectively.Like this, about the channel potential that makes the current potential well in the transmission channel region 3 that is formed under the transmission gate electrodes 5 at different levels, thereby the signal charge in the transmission channel region 3 under the transmission gate electrode 5 is sequentially transferred to the transmission channel region 3 under the output gate electrode 6.And by on output gate electrode 6, applying the direct voltage V that makes output gate electrode 6 keep on-state OGThereby signal charge flows into suspension diffusion zone 8 from the transmission channel region 3 under the output gate electrode 6.At this moment because the distance L 1 between output gate electrode 6 and the suspension diffusion zone 8, be set at also littler than the distance that forms potential barrier, the transmission channel region 3 inflow suspension diffusion zones 8 so signal charge is not stoped by potential barrier under the output gate electrode 6.And the signal charge that flows into suspension diffusion zone 8 is put aside in suspension diffusion zone 8.And the signal charge of savings in suspension diffusion zone 8 is fetched to output amplifier 14 by wiring layer 13.Like this, signal charge is transformed to voltage signal V when being amplified by output amplifier 14 OutAnd, the voltage signal V of this conversion OutOutput to the outside from output amplifier 14.
From suspension diffusion zone 8 take out voltage signal V thereafter, OutAfter, the reseting pulse signal Φ R of H level is applied on the reset gate electrode 11.Thus, the channel potential of the channel region 10 under the reset gate electrode 11, the A level from Fig. 2 is reduced to the B level.Therefore, the signal charge of savings in suspension diffusion zone 8 is discharged to drain region 9 by channel region 10.At this moment, in the 1st execution mode, because the distance L 2 between suspension diffusion zone 8 and the reset gate electrode 11 is set at the also little distance of distance than the formation potential barrier, so signal charge is not discharged to drain region 9 from suspension diffusion zone 8 by potential barrier with stoping.
In the 1st execution mode, as mentioned above, because by suspension diffusion zone 8 is formed in the mode with output gate electrode 6 spacing distance L1, simultaneously, form in mode with reset gate electrode 11 spacing distance L2, thereby electric capacity between suspension diffusion zone 8 and the output gate electrode 6 and the electric capacity between suspension diffusion zone 8 and the reset gate electrode 11 are diminished, so compare, can make the electric capacity relevant littler with the diffusion zone 8 of suspending with the distance of only between suspension diffusion zone 8 and output gate electrode 6, setting regulation.Like this, owing to make the signal voltage that takes out from suspension diffusion zone 8 become big, so can improve the detection sensitivity of output signal.
In addition, in the 1st execution mode, by making the distance L 1 between suspension diffusion zone 8 and the output gate electrode 6, also bigger than the distance L between suspension diffusion zone 8 and the reset gate electrode 11 2, thereby make the reduction amount of the electric capacity between suspension diffusion zone 8 and the output gate electrode 6, reduction amount than the electric capacity between suspension diffusion zone 8 and the reset gate electrode 11 is also big, even therefore because guarantee to transmit the memory capacity of the signal charge of channel region 3, and the plane that increases transmission channel region 3 is long-pending, compare with the electric capacity between suspension diffusion zone 8 and the reset gate electrode 11, electric capacity between suspension diffusion zone 8 and the output gate electrode 6 becomes under the big situation, also can reduce the electric capacity between suspension diffusion zone 8 and the output gate electrode 6 effectively.
In addition, in the 1st execution mode, by the distance L 1 between suspension diffusion zone 8 and the output gate electrode 6 being set at than the also little distance of distance that forms potential barrier in the zone between suspension diffusion zone 8 and output gate electrode 6, thereby do not form potential barrier in the zone between suspension diffusion zone 8 and output gate electrode 6, therefore can suppress signal charge and flow into the phenomenon that suspension diffusion zone 8 is stoped by potential barrier from transmission channel region 3.Like this, can suppress signal charge from of the reduction of transmission channel region 3 to the efficiency of transmission of suspension diffusion zone 8.
In addition, in the 1st execution mode, by the distance L 2 between suspension diffusion zone 8 and the reset gate electrode 11 is set at, than the also little distance of distance that forms potential barrier in the zone between suspension diffusion zone 8 and reset gate electrode 11, thereby in suspension diffusion zone 8 and the zone between the output gate electrode 11 of resetting, do not form potential barrier, therefore can suppress to be stoped the phenomenon that the unwanted signal electric charge is discharged to drain region 9 from suspension diffusion zone 8 by potential barrier.Like this, can fully get rid of the unwanted signal electric charge from suspension diffusion zone 8.
And, with the distance between suspension diffusion zone 8 and the reset gate electrode 11, be set under the situation of the distance L 3 more than the distance that forms potential barrier in the zone between suspension diffusion zone 8 and reset gate electrode 11, as shown in Figure 3, form potential barrier in the zone between suspension diffusion zone 8 and reset gate electrode 11.In this case, even make the A level of channel potential from Fig. 3 of the channel region 10 under the reset gate electrode 11 be reduced to the B level, also owing to stoped from suspension diffusion zone 8 to drain region 9 discharge signal charges, so can not carry out the discharge of signal charge fully by potential barrier.
Below, with reference to Fig. 1, Fig. 2 and Fig. 4～Fig. 8, the manufacturing process of the solid camera head of the 1st execution mode is described.
In the 1st execution mode, at first, as shown in Figure 4, by p type foreign ion is injected into n type silicon substrate, thereby above n type silicon substrate 1 to the degree of depth of about 4 μ m, form p type well area.Thereafter, with following condition: inject energy: about 50keV, dosage: about 1 * 10 12Cm -2, to p type well area 2, ion injects phosphorus (P).Thus, above n type silicon substrate 1 to the zone of about 0.5 μ m degree of depth, form and have about 10 16Cm -3The N of impurity concentration -Type extrinsic region 3a.And, utilize the CVD method, at N -On the type extrinsic region 3a, form by SiO with about 50nm thickness 2The gate insulating film 4 that constitutes.
Secondly, as shown in Figure 5, utilize photoetching technique and etching technique, the interval predetermined distance forms a plurality of the 1st layer of transmission gate electrode 5a that are made of polysilicon in the regulation zone on gate insulating film 4.At this moment, the 1st layer of transmission gate electrode 5a forms the thickness with about 70nm., utilize photoetching technique and etching technique, form by SiO thereafter 2The gate insulating film 7 that constitutes is so that cover the top and side of the 1st layer of transmission gate electrode 5a.
Below, as shown in Figure 6, utilize photoetching technique and etching technique, on gate insulating film 4, predetermined distance forms a plurality of the 2nd layer of transmission gate electrode 5b, output gate electrode 6 and reset gate electrode 11 at interval.At this moment, the 2nd layer of transmission gate electrode 5b, output gate electrode 6 and reset gate electrode 11 all form the thickness with about 300nm by polysilicon.In addition, a plurality of the 2nd layer of transmission gate electrode 5b form respectively: be situated between by the 1st layer of transmission gate electrode 5a and dielectric film 7, be adjacent to the zone of the 1st layer of transmission gate electrode 5a.In addition, output gate electrode 6 forms: the 1st layer of transmission gate electrode 5a that is adjacent to final stage by dielectric film 7.
Below, as shown in Figure 7, form etchant resist 15, so that cover the zone beyond the zone that forms suspension diffusion zone 8 and drain region 9.At this moment, in the 1st execution mode, the zone between output gate electrode on the gate insulating film 46 and reset gate electrode 11 forms etchant resist 15, so that cover from output gate electrode 6 to distance L 1 zone and 2 the zone from reset gate electrode 11 to distance L.Thereafter, be mask with etchant resist 15, injecting energy: about 60keV, dosage: about 3 * 10 15Cm -2Under the condition, arsenic (As) ion is injected into n type silicon substrate 1.Like this, on output gate electrode 6 and the zone between the reset gate electrode 11 corresponding to n type silicon substrate 1, formation has about 10 20Cm -3The N of above impurity concentration ++Type suspension diffusion zone 8.In addition, on n type silicon substrate 1, and suspension diffusion zone 8 between, pass through N -Type channel region 10, formation has about 10 20Cm -3The N of above impurity concentration ++Type drain region 9.In addition, when suspension diffusion zone 8 forms with output gate electrode 6 spacing distance L1, form with reset gate electrode 11 spacing distance L2.In addition, in the transmission gate electrode 5 and the zone under the output gate electrode 6 of n type silicon substrate 1, conjointly form with suspension diffusion zone 8 and to have about 10 16Cm -3The transmission channel region 3 of impurity concentration.Remove etchant resist 15 thereafter.
Below, as shown in Figure 8, utilize the CVD method, form by SiO to cover comprehensive mode 2The interlayer dielectric 12 that constitutes.At last, as shown in Figure 1, utilize photoetching technique and etching technique, in the zone corresponding to suspension diffusion zone 8 of interlayer dielectric 12 and gate insulating film 4, form the contact hole 12a on the surface that reaches suspension diffusion zone 8.Be formed on imbed wiring layer 13 lip-deep, that by tungsten constitute that contact hole 12a time extend to interlayer dielectric 12 thereafter.And, source electrode follower type output amplifier 14 (with reference to Fig. 2) is connected to this wiring layer.As mentioned above, form the solid camera head of the 1st execution mode shown in Figure 1.
(the 2nd execution mode)
Below, with reference to Fig. 9 and Figure 10, the structure of the solid camera head of the 2nd execution mode is described.
In the solid camera head of the 2nd execution mode shown in Figure 9, different with the solid camera head of above-mentioned the 1st execution mode, in the suspension diffusion zone 8 and the zone between the output gate electrode 6 of n type silicon substrate 1, formation has about 10 18Cm -3The N of impurity concentration +Type extrinsic region 16.And, this N +Extrinsic region 16 is examples of the present invention's " the 2nd extrinsic region ".In other words, in the suspension diffusion zone 8 and the zone between the output gate electrode 6 of n type silicon substrate 1, formation has the N of ratio -The impurity concentration (about 10 of type transmission channel region 3 16Cm -3) taller and compare N ++The impurity concentration (about 10 of type suspension diffusion zone 8 20Cm -3) also will be low impurity concentration (about 10 18Cm -3) N +Type extrinsic region 16.Like this, as shown in figure 10, corresponding to the N between suspension diffusion zone 8 and the output gate electrode 6 +The part channel potential of type extrinsic region 16 is lowered.And, N +Type extrinsic region 16 forms with suspension diffusion zone 8 with being connected.In addition, N +The width of type extrinsic region 16 is set to about 1/2 width of distance L 4 between suspension diffusion zone 8 and the output gate electrode 6.And, N +Type extrinsic region 16 is set to and output gate electrode 6 spacing distance L5.And this distance L 5 is examples of the present invention's " the 3rd distance ".In addition, distance L 5 is set to than at N +The distance that forms potential barrier in the zone between type extrinsic region 16 and the output gate electrode 6 is also wanted little distance.The above-mentioned formation in addition of the solid camera head of the 2nd execution mode is identical with the formation of the solid camera head of above-mentioned the 1st execution mode.
In the 2nd execution mode, as mentioned above, because by forming suspension diffusion zone 8 with output gate electrode 6 spacing distance L4, simultaneously, by forming suspension diffusion zone 8 with reset gate electrode 11 spacing distance L2, thereby it is identical with the 1st execution mode, can make electric capacity between suspension diffusion zone 8 and the output gate electrode 6, and suspension diffusion zone 8 and reset gate electrode 11 between electric capacity diminish, so and only between suspension diffusion zone 8 and output gate electrode 6, set comparing of regulation apart from situation, can make the electric capacity relevant littler with the diffusion zone 8 of suspending.Like this, owing to make the signal voltage that takes out from suspension diffusion zone 8 become big, so can improve the detection sensitivity of output signal.
In addition, in the 2nd execution mode, owing to, form the taller and also lower N of impurity concentration that has than transmission channel region 3 than the impurity concentration of suspension diffusion zone 8 by in the suspension diffusion zone 8 and the zone between the output gate electrode 6 of n type silicon substrate 1 +Type extrinsic region 16, thus the channel potential in zone between suspension diffusion zone 8 and the output gate electrode 6 is reduced, so the zone that can be suppressed between suspension diffusion zone 8 and the output gate electrode 6 forms potential barrier.Like this, owing to can make the distance L 4 between suspension diffusion zone 8 and the output gate electrode 6 bigger, so can make the electric capacity between suspension diffusion zone 8 and the output gate electrode 6 littler.In addition, even by forming N in mode with impurity concentration also lower than suspension diffusion zone 8 +Type extrinsic region 16, and and output gate electrode 6 spacing distance L5 and forming, thereby even the zone between suspension diffusion zone 8 and output gate electrode 6 forms N +Under the situation of type extrinsic region 16, also can suppress N +It is big that electric capacity between type extrinsic region 16 and the output gate electrode 6 becomes.
Moreover, in the suspension diffusion zone 8 of spacing distance L4 setting and the zone between the output gate electrode 6, do not forming N +Under the situation of type extrinsic region 16, as shown in figure 11, the zone between suspension diffusion zone 8 and output gate electrode 6 can form potential barrier sometimes.In this case, because potential barrier stops signal charge to flow into to suspension diffusion zone 8 from transmission channel region 3, so the efficiency of transmission of signal charge reduces.
In addition, in the 2nd execution mode, by with N +Distance L 5 between type extrinsic region 16 and the output gate electrode 6 is set at: ratio is at N +Zone between type extrinsic region 16 and the output gate electrode 6 forms the distance of potential barrier and also wants little distance, stops signal charge from transmission channel region 3 so can suppress potential barrier, passes through N +Type extrinsic region 16 flow into suspension diffusion zone 8.Therefore, can suppress from of the reduction of transmission channel region 3 to the efficiency of transmission of the signal charge of suspension diffusion zone 8.
Below, with reference to Fig. 9, Figure 12 and Figure 13, the solid camera head manufacturing process of the present invention's the 2nd execution mode is described.
In the manufacturing process of the 2nd execution mode, at first adopt and Fig. 4～the identical technology of manufacturing process of above-mentioned the 1st execution mode shown in Figure 6 the structure of formation Fig. 6.Thereafter, in the 2nd execution mode, as shown in figure 12, to cover suspension diffusion zone 8 (with reference to Figure 10), drain region 9 and to form N +The mode in the zone beyond the zone of type extrinsic region 16 forms etchant resist 17.At this moment, in the 2nd execution mode, in the output gate electrode 6 and the zone of 11 of reset gate electrodes of etchant resist 17 on gate insulating film 4, with cover from output gate electrode 6 to distance L 5 zone and from the reset gate electrode to the distance L mode in 2 zone form.Thereafter, be mask with etchant resist 17, injecting energy: about 30keV, dosage: about 2 * 10 12Cm -2Condition under, phosphorus (P) ion is injected n type silicon substrate 1.Thus, finally forming suspension diffusion zone 8 (with reference to Figure 10) and N +In the zone of type extrinsic region 16, formation has about 10 18Cm -3The N of impurity concentration +Type extrinsic region 16a, simultaneously, finally in the zone that forms drain region 9 (with reference to Figure 10), formation has about 10 18Cm -3The N of impurity concentration +Type extrinsic region 9a.In addition, N +Type extrinsic region 16a when forming with output gate electrode 6 spacing distance L5, forms with reset gate electrode 11 spacing distance L2.In addition, in the transmission gate electrode 5 and the zone under the output gate electrode 6 of n type silicon substrate 1, with N +Type extrinsic region 16a conjointly forms has about 10 16Cm -3The transmission channel region 3 of impurity concentration.Remove etchant resist 17 thereafter.
Below, as shown in figure 13, form etchant resist 18, so that the zone in addition, zone that covers suspension diffusion zone 8 (with reference to Figure 10) and form drain region 9.At this moment, distance L 4 is set at about 2 times of distance L 5.In addition, form etchant resist 18, so that cover zone corresponding to the extrinsic region 9a (with reference to Figure 12) on the gate insulating film 4.Thereafter, be mask with etchant resist 18, injecting energy: about 60keV, dosage: about 3 * 10 15Cm -2Condition under, arsenic (As) ion is injected n type silicon substrate 1.Thus, at the N of n type silicon substrate 1 +(with reference to Figure 12) forms and has about 10 in the type extrinsic region 16a 20Cm -3The N of above impurity concentration ++Type suspension diffusion zone 8.When this suspension diffusion zone 8 and output gate electrode 6 spacing distance L4 form, form with reset gate electrode 11 spacing distance L2.In addition, conjointly form with suspension diffusion zone 8 and have about 10 18Cm -3The N of impurity concentration +Type extrinsic region 16.This N +Type extrinsic region 16 forms in the mode of about 1/2 width with distance L 4 between suspension diffusion zone 8 and the output gate electrode 6.In addition, N +Type extrinsic region 16 forms with output gate electrode 6 spacing distance L5.In addition, have about 10 in 1 formation of n type silicon substrate 20Cm -3The N of above impurity concentration ++Type drain region 9 is so that with N -Between 10 insertions of type channel region and the suspension diffusion zone 8., in 2nd execution mode, utilize and above-mentioned 1st execution mode identical manufacturing process,, and form the solid camera head of the 2nd execution mode shown in Figure 9 by formation interlayer dielectric 12 and wiring layer 13 thereafter.
Below, with reference to Figure 14～Figure 17, the manufacturing process of the solid camera head of the variation of the present invention's the 2nd execution mode is described.And, in the variation of the 2nd execution mode, describe adopting contact to inject the manufacturing process that forms suspension diffusion zone 8.
At first,, proceed to till the manufacturing process shown in Figure 12, thereby form N by adopting the technology identical with the manufacturing process of above-mentioned the 2nd execution mode +Type extrinsic region 16a and N +Type extrinsic region 9a.
Secondly, as shown in figure 14, form etchant resist 19, so that cover the zone beyond the zone that forms drain region 9.Thereafter, be mask with etchant resist 19, injecting energy: about 60keV, dosage: about 3 * 10 15Cm -2Condition under, arsenic (As) ion is injected n type silicon substrate 1.Like this, formation has about 10 20Cm -3The N of above impurity concentration ++Type drain region 9.Remove etchant resist 19 thereafter.
Moreover, as shown in figure 15, utilize the CVD method, form by SiO 2The interlayer dielectric 12 that constitutes is so that cover comprehensively.Secondly, as shown in figure 16, utilize photoetching technique and etching technique, at N corresponding to interlayer dielectric 12 and gate insulating film 4 +In the zone of type extrinsic region 16a, form contact hole 12b.This contact hole 12b when the distance of L4 forms at interval with output gate electrode 6, forms with reset gate electrode 11 spacing distance L2.With interlayer dielectric 12 and gate insulating film 4 be mask, to inject energy: about 60keV, dosage: about 3 * 10 thereafter, 15Cm -2Condition, arsenic (As) ion is injected n type silicon substrate 1.Like this, by contact hole 12b, arsenic (As) is imported in the n type silicon substrate 1.Therefore, formation has about 10 on n type silicon substrate 1 20Cm -3The N of above impurity concentration ++Type suspension diffusion zone 8.When the distance of this suspension diffusion zone 8 and output gate electrode 6 interval L4 forms, form with reset gate electrode 11 spacing distance L2.And, conjointly form N with suspension diffusion zone 8 +Type extrinsic region 16.This N +Type extrinsic region 16 and the output gate electrode 6 distance formation of L5 at interval.
At last, as shown in figure 17, when imbedding contact hole 12b, the mode that extends on the interlayer dielectric forms the wiring layer 13 that is made of tungsten.As mentioned above, form the solid camera head of the variation of the 2nd execution mode.
(the 3rd execution mode)
Below, with reference to Figure 18 and Figure 19, the structure of the COMS imageing sensor of the present invention's the 3rd execution mode is described.
In the COMS of the 3rd execution mode imageing sensor, different with the solid camera head of above-mentioned the 1st execution mode as shown in figure 18, on the surface of the p type well area 2 of n type silicon substrate 1, replace transmission channel region 3 shown in Figure 1, be formed with N -Type photodiode layer 23.And this photodiode layer 23 is that the present invention's " photoelectric conversion department " reaches an example of " electric charge savings portion ".Photodiode layer 23 has: by accepting light, carry out light-to-current inversion, thereby generate signal charge, the function of the signal charge that generated of savings simultaneously.In addition, photodiode layer 23 on the surface of p type well area 2 a plurality of form rectangular.In addition, in the 3rd execution mode, in each photodiode layer 23, be provided with the signal charge that is used for generating and be fetched into outside efferent 60 by photodiode layer 23.And this efferent 60 is examples of the present invention's " second efferent ", and in addition, this efferent 60 is made of output gate electrode 26, suspension diffusion zone 8 and wiring layer 13.And output gate electrode 26 is examples of the present invention's " the 1st gate electrode ".In addition, photodiode layer 23 relative output gate electrodes 26 can form from coupling ground.That is, constitute: the lateral attitude of photodiode layer 23 ends becomes identical position with the lateral attitude of output gate electrode 26 ends.In addition, be positioned at output gate electrode 26 times by making p type well area, and be formed with p type channel region 27.And, and channel region 27 between, spacing distance L1 and be formed with N ++Type suspension diffusion zone 8.In the zone between this channel region 27 and suspension diffusion zone 8, be formed with the N that has with photodiode layer 23 identical impurity concentrations -Type extrinsic region 28.
In addition, in the 3rd execution mode, as shown in figure 19, constitute: will be used to make output gate electrode 26 to switch to the signal Phi of conducting state and cut-off state OGBe input to output gate electrode 26.And, this signal Phi OGIt is an example of the present invention's " the 2nd signal ".Utilize this signal, when in photodiode layer 23, carrying out light-to-current inversion, be in cut-off state, thereby the regional current potential under the output gate electrode 26 is risen by making output gate electrode 26.And, with signal charge when photodiode layer 23 is transferred to suspension diffusion zone 8, by output gate electrode 26 is switched to conducting state, thereby the regional current potential under the output gate electrode 26 is reduced.Like this, when light-to-current inversion, as shown in figure 19, constitute: form potential barrier by the zone under output gate electrode 26, thereby in photodiode layer 23, put aside signal charge.In addition, when signal charge transmits, constitute: the signal charge of savings in photodiode layer 23 is transferred to suspension diffusion zone 8 by the zone under the output gate electrode 26.In addition, in the 3rd execution mode, be formed with p type channel region 30 for 11 times by making p type well area 2 be positioned at reset gate electrode.
Structure beyond the cmos image sensor of the 3rd execution mode above-mentioned is identical with the structure of the solid camera head of above-mentioned the 1st execution mode.
In the 3rd execution mode, constitute like that by above-mentioned, thereby in the cmos image sensor that comprises photodiode layer 23, can improve the detection sensitivity of the signal of exporting by suspension diffusion zone 8 by photodiode layer 23, simultaneously, can effectively reduce electric capacity between suspension diffusion zone 8 and the output gate electrode 26 etc., can obtain and the identical effect of above-mentioned the 1st execution mode.
(the 4th execution mode)
Below, with reference to Figure 20 and Figure 21, the structure of the cmos image sensor of the 4th execution mode of the present invention is described.
The cmos image sensor of the 4th execution mode in the solid camera head of above-mentioned the 2nd execution mode, replaces transmission channel region 3 shown in Figure 9 as shown in figure 20, forms N and have on the surface of the p type well area 2 of n type silicon substrate 1 -The structure of type photodiode layer 23.In addition, the cmos image sensor of the 4th execution mode has: the efferent 60 that constitutes with the same photodiode layer 23 that constitutes of the cmos image sensor of above-mentioned the 3rd execution mode and output gate electrode 26, by suspension diffusion zone 8 and wiring layer 13.
In addition, identical with above-mentioned the 3rd execution mode as shown in figure 21 in the 4th execution mode, constitute: will be used to make output gate electrode 26 to switch to the signal Phi of conducting state and cut-off state OGBe input to output gate electrode 26.Like this, constitute: when light-to-current inversion, form potential barrier by the zone under the output gate electrode 26 of cut-off state, and in photodiode layer 23, put aside signal charge, simultaneously, when signal charge transmitted, by the zone under the output gate electrode 26 of conducting state, and the signal charge that will put aside in photodiode layer 23 was transferred to suspension diffusion zone 8.In addition, identical with above-mentioned the 3rd execution mode in the 4th execution mode, by making p type well area 2 be positioned at output gate electrode 26 and reset gate electrode 11 times and form p type channel region 27 and 30 respectively.In addition, with N ++The N that type suspension diffusion zone 8 conjointly forms +In distance L 5 The corresponding area between the p type channel region 27 under type extrinsic region 16 and the output gate electrode 26, form the N that has with photodiode layer 23 identical impurity concentrations -Type extrinsic region 29.
Structure beyond the cmos image sensor of the 4th execution mode above-mentioned is identical with the structure of the solid camera head of above-mentioned the 2nd execution mode.
In the 4th execution mode, constitute as described above, thereby in the cmos image sensor that comprises photodiode layer 23, can improve the detection sensitivity of the signal of exporting by suspension diffusion zone 8 by photodiode layer 23, simultaneously, can effectively reduce electric capacity between suspension diffusion zone 8 and the output gate electrode 26 etc., can obtain and the identical effect of above-mentioned the 2nd execution mode.
In addition, this disclosed execution mode all is example in all respects, should regard as not to be restriction.Scope of the present invention is not the explanation performance by above-mentioned execution mode, but is showed by the technical scheme scope, and comprises and the meaning of technical scheme scope equalization and all changes in the scope.
For example, in the 2nd and the 4th execution mode, to conjointly forming N with the suspension diffusion zone +The example of type extrinsic region is illustrated, but the invention is not restricted to this, also can form N with the distance that the suspension diffusion zone is stipulated at interval +The type extrinsic region.
In addition, in above-mentioned the 1st～the 4th execution mode, adopt tungsten to form wiring layer, but the invention is not restricted to this, also can adopt tungsten material in addition to form wiring layer.For example, also can adopt various metal materials beyond the tungsten or polysilicon etc. to form wiring layer.
Moreover, in the above-mentioned the 3rd and the 4th execution mode, form only by N -The photodiode layer that the type extrinsic region constitutes, but the present invention does not limit this, in order to suppress the exhausting of photodiode layer near surface, can P be set on the surface of photodiode layer yet +The sealer of type.For example, the cmos image sensor of the 3rd execution mode variation as shown in figure 22, and the cmos image sensor of the 4th execution mode variation shown in Figure 23 also can be at N -The surface of type photodiode layer 23 forms P by inject p type impurity with high concentration ion +The sealer 23a of type.

Claims (20)

1. solid camera head is characterized in that possessing:
Be formed on the 1st gate electrode on the semiconductor substrate;
On above-mentioned semiconductor substrate and above-mentioned the 1st gate electrode at interval the 1st distance form, and flow into the 1st extrinsic region of signal charge; With
With above-mentioned the 1st extrinsic region at interval the 2nd distance form, and be used to discharge the 2nd gate electrode that takes out the unwanted above-mentioned signal charge behind the voltage signal from above-mentioned the 1st extrinsic region;
Above-mentioned the 1st distance between above-mentioned the 1st extrinsic region and above-mentioned the 1st gate electrode is also bigger than the distance of the 2nd between above-mentioned the 1st extrinsic region and above-mentioned the 2nd gate electrode.
2. solid camera head according to claim 1, wherein,
Also possesses the electric charge savings portion that is formed on the semiconductor substrate and has the function of the above-mentioned signal charge of savings;
Above-mentioned the 1st gate electrode has and is used to make the function of signal charge from the output of above-mentioned electric charge savings portion;
Flow into above-mentioned the 1st extrinsic region from the above-mentioned signal charge of above-mentioned electric charge savings portion output.
3. solid camera head according to claim 1, wherein,
Above-mentioned the 1st distance between the 1st extrinsic region and above-mentioned the 1st gate electrode is set at than the also little distance of distance that forms potential barrier in the zone between above-mentioned the 1st extrinsic region and above-mentioned the 1st gate electrode;
Above-mentioned the 2nd distance between above-mentioned the 1st extrinsic region and above-mentioned the 2nd gate electrode is set at than the also little distance of distance that forms potential barrier in the zone between above-mentioned the 1st extrinsic region and above-mentioned the 2nd gate electrode.
4. solid camera head according to claim 1, wherein,
Also possess: on the part in above-mentioned the 1st extrinsic region of above-mentioned semiconductor substrate and the zone between above-mentioned the 1st gate electrode, with above-mentioned the 1st gate electrode the 3rd distance and the 2nd extrinsic region that forms at interval;
Above-mentioned the 2nd extrinsic region has: ratio is in above-mentioned the 1st extrinsic region of above-mentioned semiconductor substrate and taller and also lower than the impurity concentration of above-mentioned the 1st extrinsic region impurity concentration of impurity concentration in the zone beyond above-mentioned the 2nd extrinsic region between above-mentioned the 1st gate electrode.
5. solid camera head according to claim 4, wherein,
Above-mentioned the 2nd extrinsic region and above-mentioned the 1st extrinsic region conjointly form.
6. solid camera head according to claim 4, wherein,
Above-mentioned the 3rd distance between above-mentioned the 2nd extrinsic region and above-mentioned the 1st gate electrode is set at than the also little distance of distance that forms potential barrier in the zone between above-mentioned the 2nd extrinsic region and above-mentioned the 1st gate electrode.
7. solid camera head according to claim 4, wherein,
Along the direction length setting of the above-mentioned signal charge transmission direction of above-mentioned the 2nd extrinsic region is about 1/2 width of the 1st distance between above-mentioned the 1st extrinsic region and above-mentioned the 1st gate electrode.
8. solid camera head according to claim 1, wherein,
Also possess: be formed on the semiconductor substrate by the zone under above-mentioned the 1st extrinsic region and above-mentioned the 2nd gate electrode, and discharge the 3rd extrinsic region of above-mentioned unwanted signal electric charge by above-mentioned the 1st extrinsic region;
After taking out above-mentioned voltage signal, be in conducting state by making the 2nd gate electrode, and above-mentioned unwanted signal electric charge is discharged to above-mentioned the 3rd extrinsic region from the zone of above-mentioned the 1st extrinsic region under above-mentioned the 2nd gate electrode by above-mentioned the 1st extrinsic region.
9. solid camera head according to claim 8, wherein,
The 1st signal that will be used to make above-mentioned the 2nd gate electrode switch to conducting state and cut-off state is input to above-mentioned the 2nd gate electrode.
10. solid camera head according to claim 2, wherein,
Above-mentioned electric charge savings portion comprises the transmission raceway groove that the transmission of above-mentioned signal charge limit is put aside on the limit.
11. solid camera head according to claim 10, wherein,
Also possesses the multistage transmission gate electrode that is formed on the above-mentioned transmission raceway groove;
By alternately applying 2 phase transmission signals, thereby transmit above-mentioned signal charge in the above-mentioned transmission raceway groove to transmission gate electrodes at different levels.
12. solid camera head according to claim 11, wherein,
Also possess the above-mentioned signal charge that is used for coming and be fetched into the 1st outside efferent by above-mentioned transmission raceway groove transmission,
Above-mentioned the 1st efferent comprises: with the above-mentioned transmission gate electrode of the most last utmost point in abutting connection with setting, and be used for from export above-mentioned the 1st gate electrode of above-mentioned output signal electric charge corresponding to the most above-mentioned transmission raceway groove of the above-mentioned transmission gate electrode of the last utmost point; Inflow is by above-mentioned the 1st extrinsic region of the above-mentioned signal charge of exporting corresponding to the transmission raceway groove of the most last above-mentioned utmost point transmission gate electrode; Be connected above-mentioned the 1st extrinsic region, and be used for above-mentioned signal charge is fetched into outside distribution from above-mentioned the 1st extrinsic region.
13. solid camera head according to claim 12, wherein,
Also possess: connect above-mentioned distribution, and when the above-mentioned signal charge that takes out from above-mentioned the 1st extrinsic region is amplified, be transformed to the output enlarging section of voltage signal.
14. solid camera head according to claim 12, wherein,
On above-mentioned the 1st gate electrode, apply and be used to make above-mentioned the 1st gate electrode to remain on the assigned voltage of conducting state.
15. solid camera head according to claim 2, wherein,
The photoelectric conversion department that above-mentioned electric charge savings portion puts aside when being included in and generating signal charge by light-to-current inversion.
16. solid camera head according to claim 15, wherein,
Be provided with a plurality of above-mentioned photoelectric conversion departments,
Also possess: be arranged in each above-mentioned photoelectric conversion department, and the above-mentioned signal charge that is used for being generated by above-mentioned photoelectric conversion department is fetched into the 2nd outside efferent;
Above-mentioned the 2nd efferent comprises: with above-mentioned photoelectric conversion department in abutting connection with setting, and be used for from the 1st gate electrode of photoelectric conversion department output signal electric charge; Inflow is by above-mentioned the 1st extrinsic region of the above-mentioned signal charge of the above-mentioned electric transformation component output of light; Be connected above-mentioned the 1st extrinsic region, and be used for signal charge being fetched into outside distribution from above-mentioned the 1st extrinsic region.
17. solid camera head according to claim 16, wherein,
Also possess: connect above-mentioned distribution, when the above-mentioned signal charge that will be taken out by above-mentioned the 1st extrinsic region amplifies, be transformed to the output enlarging section of voltage signal.
18. solid camera head according to claim 15, wherein,
When carrying out light-to-current inversion, when above-mentioned the 1st gate electrode is changed to cut-off state, when above-mentioned signal charge is transferred to above-mentioned the 1st extrinsic region from above-mentioned photoelectric conversion department, above-mentioned the 1st gate electrode is placed conducting state by above-mentioned photoelectric conversion department.
19. solid camera head according to claim 18, wherein,
The 2nd signal that will be used to make above-mentioned the 1st gate electrode switch to conducting state and cut-off state is input to above-mentioned the 1st gate electrode.
20. solid camera head according to claim 15, wherein,
Also possess: be formed on above-mentioned photoelectric conversion department surface and be used to suppress the sealer of the exhausting of above-mentioned photoelectric conversion department near surface.
CNB2005100991876A 2004-09-07 2005-09-07 Solid-state image sensor Expired - Fee Related CN100394609C (en)

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