CN1741194A - Nonvolatile semiconductor memory device and read method - Google Patents

Abstract

This device comprises a memory cell selecting circuit 17 for selecting the memory cell from the memory cell array 15 in units of row, column or memory cell, a read voltage application circuit 22a for applying a read voltage to the variable resistor element of the selected memory cell selected by the memory cell selecting circuit 17, and a read circuit 23 for detecting the amount of the read current flowing in accordance with the resistance value of the variable resistor element with respect to the memory cell to be read of the selected memory cells and reading the information stored in the memory cell to be read. The read voltage application circuit 22a applies a dummy read voltage having reversed polarity from the read voltage to the variable resistor element of the selected memory cell.

Description

Nonvolatile semiconductor memory device and reading method

Technical field

The present invention relates to a kind of semiconductor storage, it has respectively at line direction and column direction arranges a plurality of memory cell arrays of storage unit of utilizing changes in resistance to come the variable resistor element of canned data that comprise, more detailed theory relates to the quality that prevents and suppress to store data and follows the work of reading of memory cell array and the technology of variation.

Background technology

In recent years, but the nonvolatile RAM of future generation of the high speed operation of flash memory (NVRAM:Nonvolatile Random Access Memory) as an alternative, ferroelectric RAM), MRAM (Magnetic RAM: magnetic resistance RAM) and OUM (Ovonic Unified Memory: various device architectures such as phase transition storage) FeRAM (Ferroelectric RAM: has been proposed, aspect high-performance, high reliability, low cost and technology matching, launched fierce exploitation competition.

In addition, for these prior arts, the Shangquing Liu of houston, u.s.a university and Alex Ignatiev etc. disclose by the perovskite material with giant magnetoresistance effect being added the method that pulse voltage makes the reversible variation of resistance and (have opened 2002-8369 communique, Liu with reference to United States Patent (USP) No. 6204139 instructions, spy, S.Q etc., " Electric-pulse-inducedreversible Resistance change effect in magnetoresistivefilms ", Applied Physics Letter, Vol.76, pp.2749-2751,2000).This is to use perovskite material with giant magnetoresistance effect, does not add the epoch-making great discovery that the resistance variations of several magnitude at room temperature just can appear in magnetic field.Used resistive nonvolatile memory RRAM (the Resistance RandomAccess Memory: resistive ram) have following advantageous feature: different of the variable resistor element that utilizes this phenomenon with MRAM, because of not needing to add magnetic field, so power consumption is extremely low, realize easily miniaturization and highly integrated, the dynamic range of resistance variations compare with MRAM especially wide, can many-valuedly store.The basic structure of practical devices is simple especially, is the structure of stacked in order lower electrode material, perovskite type metal oxide and upper electrode material on the direction vertical with substrate.Have, in No. 6204139 instructions of United States Patent (USP) in the illustrative component structure, the lower electrode material is by at lanthanum aluminum oxide LaAlO again ₃(LAO) the yttrium barium copper oxide YBa that precipitates on the single crystallization base plate ₂Cu ₃O ₇(YBCO) film forms, and perovskite type metal oxide is by crystalline praseodymium calcium Mn oxide Pr _1-xCa _xMnO ₃(PCMO) film forms, and upper electrode material is formed by the Ag film that utilizes the sputter precipitation.The principle of work of this memory element is the potential pulse that adds positive and negative 51V between the electrode of upper and lower, can make the reversible variation of resistance.This means by reading the resistance value in this resistance possibility of reversal work (below, suitably be called " switch work "), can realize novel Nonvolatile semiconductor memory device.

Has the variable resistor element that constitutes by above-mentioned PCMO film etc., being rectangular comes the storage unit of canned data and forms memory cell array at line direction and a plurality of resistance variations of variable resistor element of utilizing of column direction arrangement respectively, circumferential arrangement control in this memory cell array is carried out the circuit that data write, wipe and read to each storage unit of memory cell array, thus, can constitute Nonvolatile semiconductor memory device.

As the formation of storage unit, each storage unit is arranged by a situation that variable resistor element and the series circuit of selecting transistor series to be connected are constituted and a situation about constituting by variable resistor element etc. with this variable resistor element.The storage unit that the former is constituted is called the 1T/1R storage unit, and the storage unit that the latter is constituted is called 1R type storage unit.

Configuration example when using description of drawings to form memory cell array and reconstruct jumbo Nonvolatile semiconductor memory device by 1T/1R type storage unit.

Fig. 1 is the synoptic diagram of a configuration example of the memory cell array of 1T/1R type storage unit, has proposed the formation with the same memory cell array of the applicant's patented claim (the special 2003-168223 of hope).In the formation of this memory cell array, the formation of memory cell array 1 is at the m root bit line that extends along column direction (BL1～BLm) and follow the n root word line that direction extends and (dispose m * n storage unit 2 on the intersection point of WL1～WLn).In addition, with word line configured in parallel n root polar curve (SL1～SLn).Each storage unit makes the upper electrode of variable resistor element 3 be connected with the drain electrode of selecting transistor 4, and bit line is connected with the lower electrode of variable resistor element 3, and word line is connected with the grid of selecting transistor 4, and source electrode line is connected with the source electrode of selecting transistor 4.Have, the lower electrode of variable resistor element 3 is connected with the drain electrode of selecting transistor 4, bit line is connected with the upper electrode of variable resistor element 3, and the upper electrode of variable resistor element 3 and the relation of lower electrode are turned around.

Like this, by constituting storage unit 2 by the series circuit of selecting transistor 4 and variable resistor element 3, make the selection transistor 4 of the storage unit of selecting according to the current potential of bit line 2 become conducting state, and then, only the variable resistor element 3 of the storage unit 2 selected according to the current potential of bit line is applied selectively and write or erasing voltage, can make the resistance change of variable resistor element 3.

Fig. 2 illustrates a configuration example of the Nonvolatile semiconductor memory device of the memory cell array 1 with 1T/1R type storage unit.After being selected by bit line decoder 5, source electrode line code translator 6 and word-line decoder 7 from the particular memory location of address wire 8 in the corresponding memory cell array 1 of the address input of control circuit 10 inputs, carry out each work that writes, wipes and read of data, read out to selecteed storage unit stores data and with it.And the data input and output between the external device (ED) (not shown) are carried out through data line 9.

Word-line decoder 7 is selected the word line of the memory cell array 1 corresponding with the signal of importing to address wire 8, bit line decoder 5 is selected the bit line of the memory cell array 1 corresponding with the address signal of importing to address wire 8, and then source electrode line code translator 6 is selected the source electrode line of the memory cell array 1 corresponding with the address signal of importing to address wire 8.Control circuit 10 carries out the control of each work that writes, wipes and read of memory cell array 1.Control circuit 10 is according to from the address signal of address wire 8 inputs, from the data inputs (writing fashionable) of data line 9 inputs, from the control input signals of control signal wire 11 inputs, control word-line decoder 7, bit line decoder 5, source electrode line code translator 6, voltage switch circuit 12 and memory cell array 1 read, write and wipe work.In example shown in Figure 2, control circuit 10 has the function of general address buffering circuit, data input and output buffer circuit, control input buffer circuit (not shown).

Each voltage of voltage switch circuit 12 is corresponding with mode of operation when switching in the reading, write and wipe of memory cell array 1 required word line, bit line and source electrode line, and supply with to memory cell array 1.Here, Vcc is the supply voltage of nonvolatile semiconductor memory storage, and Vss is a ground voltage, and Vpp writes or wipe that to use voltage, V1 be read-out voltage.In addition, carry out reading of data from memory cell array 1 through bit line decoder 5 and sensing circuit 13.The state of sensing circuit 13 judgment data, and send its result to control circuit 10, and to data line 9 outputs.

Secondly, use description of drawings to form configuration example under the situation that memory cell array reconstructs the high capacity Nonvolatile semiconductor memory device by 1R type storage unit.As shown in Figure 3, storage unit 14 is made of the monomer of variable resistor element 3, and can't help to select the series circuit of transistor and variable resistor element to constitute, make this 1R type storage unit 14 be rectangular arrangement and constitute memory cell array 15, for example, the patent documentation 2 disclosed formations with following are the same.Specifically, memory cell array 15 constitutes at the m root bit line that extends along column direction (BL1～BLm) and follow the n root word line that direction extends and (dispose m * n storage unit 14 on the intersection point of WL1～WLn).Each storage unit 14 makes word line be connected with the upper electrode of variable resistor element 3, and bit line is connected with the lower electrode of variable resistor element 3.Have, word line is connected with the lower electrode of variable resistor element 3, bit line is connected with the upper electrode of variable resistor element 3, and the upper electrode of variable resistor element 3 and the relation of lower electrode are turned around.

In the memory cell array 1 (seeing figures.1.and.2) that constitutes by 1T/1R type storage unit 2, when the storage unit selected as the object of reading, writing and wipe of data, respectively to selecting word line and selecting bit line to apply the bias voltage of regulation, only make to be included in and be in conducting state with selection transistor in the select storage unit of selecting the bit line both sides to be connected with selecting word line, thus, can only make the variable resistor element that comprises in the select storage unit flow through read current.On the other hand, in the memory cell array 15 that constitutes by 1R type storage unit 14, when select as data read the storage unit of object the time, cause is to also applying same bias voltage with the word line public with reading object-storage unit, the select storage unit that bit line is connected, so the storage unit of reading outside the object-storage unit also flows through read current.Select by column selection or row, the read current that flows through with behavior unit or the select storage unit selected with the unit of classifying as can be detected as the read current of reading object-storage unit.In the memory cell array 15 that constitutes by 1R type storage unit 14, though the storage unit of reading outside the object-storage unit also flows through read current, but, but have simple in structure, the area of storage unit of storage unit and the little advantage of area of memory cell array.

When Fig. 3 and Fig. 4 are illustrated in data in the memory cell array 15 that is made of 1R type storage unit 14 and read work to each several part apply voltage order example arranged earlier.When reading the data of select storage unit, make the selection word line that is connected with select storage unit maintain earthing potential Vss, between reading duration, in the Tr, other non-selection word lines and all bit lines are all applied read-out voltage V1.Between reading duration in the Tr, because of in the voltage difference of selecting to produce between word line and all bit line read-out voltage V1, so the variable resistor element of select storage unit flows through with its resistance, is the corresponding read current of store status, can read the data of select storage unit storage.At this moment, because of flowing through each bit line, so the data that can read specific select storage unit by the read current of reading the selection bit line that flows through regulation selectively in bit line side with the read current corresponding with the store status of the select storage unit of selecting word line to be connected.Here, also can exchange the relation of bit line and word line, and read the read current that flows through each word line selectively in the word line side.

Fig. 5 illustrates a configuration example of the Nonvolatile semiconductor memory device of the memory cell array 15 with 1R type storage unit 14.After being selected by bit line decoder 16 and word-line decoder 17 from the particular memory location of address wire 18 in the corresponding memory cell array 15 of the address of control circuit 20 input input, carry out each work that writes, wipes and read of data, read out to selecteed storage unit stores data and with it.And the data input and output between the external device (ED) (not shown) are carried out through data line 19.

Word-line decoder 17 is selected the word line of the memory cell array 15 corresponding with the signal of importing to address wire 18, and bit line decoder 16 is selected the bit line of the memory cell array 15 corresponding with the address signal of importing to address wire 18.Control circuit 20 carries out the control of each work that writes, wipes and read of memory cell array 15.Control circuit 20 is according to from the address signal of address wire 18 inputs, from the data inputs (writing fashionable) of data line 19 inputs, from the control input signals of control signal wire 21 inputs, control word-line decoder 17, bit line decoder 16, voltage switch circuit 22 and memory cell array 15 read, write and wipe work.In example shown in Figure 5, control circuit 20 has the function of general address buffering circuit, data input and output buffer circuit, control input buffer circuit (not shown).

Each voltage of voltage switch circuit 22 is corresponding with mode of operation when switching in the reading, write and wipe of memory cell array 15 required word line, bit line and source electrode line, and supply with to memory cell array 15.Here, Vcc is the supply voltage of nonvolatile semiconductor memory storage, and Vss is a ground voltage, and Vpp writes or wipe that to use voltage, V1 be read-out voltage.In addition, carry out reading of data from memory cell array 15 through bit line decoder 16 and sensing circuit 23.The state of sensing circuit 23 judgment data sends its result to control circuit 20, and to data line 19 outputs.

Have as the variable resistor element that constitutes 1T/1R type storage unit and 1R type storage unit: utilize the crystallization/decrystallized state variation of perovskite compound make resistance change phase change memory device, utilize the memory element of the polymkeric substance strong dielectric RAM (PFRAM) that forms resistive element based on the MRAM element of the resistance variations of tunneling magnetoresistance, by electric conductive polymer and utilize and apply the have a resistance RRAM element etc. of variation of electric pulse.

When having the storage unit sense data of variable resistor element, variable resistor element is applied bias voltage, make it flow through read current, judge the resistance value of variable resistor element, sense data again by the size of this electric current.Therefore, can follow the work of reading that variable resistor element is applied the bias voltage of regulation, and irrelevant with the formation of storage unit.

The present application persons find: at the PCMO film (Pr with a kind of perovskite type metal oxide _1-xCa _xMnO ₃) when using,, then can make the resistance change of variable resistor element if absolute value is added to variable resistor element at the read-out voltage that writes below the voltage as the continuous impulse of same polarity as variable resistor element.As shown in Figure 6, when the upper electrode to variable resistor element was continuously applied the potential pulse (pulse width 100ns) of positive polarity, original state was that the resistance value of the variable resistor element of high resistance state descends with the increase that pulse applies number of times.In addition, if be continuously applied reverse voltage pulse (pulse width 100ns), then resistance value rises with the increase that pulse applies number of times.

Here, so-called positive polarity voltage pulse is meant lower electrode is applied ground voltage as benchmark, upper electrode applied the state of positive voltage pulse (for example 1V).And then so-called reverse voltage pulse is meant upper electrode is applied ground voltage as benchmark, lower electrode applied the state of positive voltage pulse (for example 1V).In addition, the condition determination of resistance value shown in Figure 6 be according to lower electrode apply ground voltage as benchmark, the current value when upper electrode is applied 0.5V calculates.In addition, the transverse axis of Fig. 6 applies number of times relatively with what the form of logarithm was represented potential pulse.

Fig. 7 is to be the result of study of the upper electrode of the variable resistor element of the low resistance state resistance variations when applying positive voltage pulse to original state.Have again, the condition determination of resistance value shown in Figure 7 be according to lower electrode apply ground voltage as benchmark, the current value when upper electrode is applied 0.5V calculates.In addition, the transverse axis of Fig. 7 applies number of times relatively with what the form of logarithm was represented potential pulse.As can be seen from Figure 7, be that the situation of high resistance state is compared with original state, resistance variations is little.Especially, the voltage that when reading variable resistor element is applied wishes it is about 1V usually, but for 1V or-the potential pulse resistance variations of 1V is little.Have again, when potential pulse was positive polarity, if voltage amplitude is 2V, then resistance value had with pulse and applies the tendency that the increase of number of times descends, but because of the difference that becomes more low resistance state and high resistance state from low resistance state is more remarkable, so this resistance variations is no problem on characteristic.

Conclusion is got up, and by above-mentioned experimental result as can be known, the data of cell stores, is that resistance value follows the work of reading and the potential pulse number of times that applies that the what is called of change is read disturbing phenomenon clearly.Especially, applying the positive polarity voltage pulse at the variable resistor element that when the resistance states when reading is high resistance state reads under the situation of work again, the resistance value of this variable resistor element descends, resistance difference between high resistance state and low resistance state is little, reads tolerance limit (read margin) and descends.And then, when same storage unit being repeated to read carry out when reading work the worst situation, the anxiety that has the complete obiteration of storage data not read.

And then, in the memory cell array that constitutes by 1R type storage unit, because of to also applying read-out voltage, so the above-mentioned disturbing phenomenon of reading is more obvious with the outer select storage unit of object of reading of reading object-storage unit common word line or bit line.

Summary of the invention

The present invention proposes in view of the above problems, its purpose is to provide a kind of big Nonvolatile semiconductor memory device of tolerance limit of reading, and can prevent the bad phenomenon of reading of the resistance change that makes the variable resistor element that storage unit comprises because add to the potential pulse of storage unit when memory cell array is read.

Nonvolatile semiconductor memory device of the present invention has respectively to be arranged a plurality of comprising at line direction and column direction and utilizes changes in resistance to come the storage unit of variable resistor element of canned data and the memory cell array that forms, comprise: the memory cell selecting circuit is that said memory cells is selected by unit from the said memory cells array with row, column or storage unit; Read-out voltage applies circuit, and the above-mentioned variable resistor element of being selected the select storage unit that circuit selects by said memory cells is applied read-out voltage; And sensing circuit, the said memory cells detection of object and the size of the corresponding read current that flows through of the resistance value of this variable resistor element are read in the conduct in the above-mentioned select storage unit, read the above-mentioned information of reading in the object-storage unit that is stored in again; Above-mentioned read-out voltage applies circuit will impose on the above-mentioned variable resistor element of above-mentioned select storage unit with the pseudo-read-out voltage of above-mentioned read-out voltage reversed polarity.

In addition, Nonvolatile semiconductor memory device of the present invention is characterised in that: in during 1 selection till the selection with above-mentioned select storage unit switches to other said memory cells, above-mentioned read-out voltage applies circuit same above-mentioned select storage unit is applied above-mentioned read-out voltage and above-mentioned pseudo-read-out voltage.

Have again, in the present invention, when variable resistor element is applied read-out voltage or pseudo-read-out voltage, because of be infinitely-great high resistance state in the resistance value of variable resistor element, promptly under the state so long as not insulator, during this voltage applies, make variable resistor element flow through electric current, so the state that above-mentioned voltage can be applied applies state as electric current and catches.

If according to above-mentioned Nonvolatile semiconductor memory device, because of read-out voltage applies the pseudo-read-out voltage that circuit can apply read-out voltage and reversed polarity to select storage unit, so by the variable resistor element that applies the select storage unit that resistance value may increase or reduce behind the read-out voltage being applied the pseudo-read-out voltage of reversed polarity, resistance is changed to the direction that the resistance variations that produces because of applying of read-out voltage is cancelled out each other, even increase the number of times that applies of read-out voltage, also can suppress the resistance variations that begins to accumulate from the initial resistance state, the decline of tolerance limit can be suppressed to read, and then the read-around number of the state that maybe can not read up to the disappearance of storage data can be improved significantly.

For example, if according to the measuring result who variable resistor element is applied the resistance variations of potential pulse that follows shown in Figure 6, if under the high resistance state of original state, potential pulse (the voltage amplitude 2V of positive polarity will only be applied continuously, pulse width 100ns) situation and alternately apply potential pulse (the voltage amplitude 2V of positive polarity and negative polarity, pulse width 100ns) situation relatively, significantly, can confirm to suppress positive polarity significantly and the reverse voltage pulse (is equivalent to the former and applies read-out voltage, the latter is the situation that applies pseudo-read-out voltage) time resistance variations, can confirm above-mentioned effect.

Especially, before and after during 1 selection, apply read-out voltage and pseudo-read-out voltage,, must add the pseudo-read-out voltage of reversed polarity when when particular storage adds read-out voltage, so, can suppress to follow above-mentioned resistance variations (reading disturbing phenomenon) of reading work reliably.

In addition, Nonvolatile semiconductor memory device of the present invention preferably make the above-mentioned variable resistor element to above-mentioned select storage unit add above-mentioned pseudo-read-out voltage during than above-mentioned add read-out voltage during short, the electric current that the above-mentioned read-out voltage of current ratio that flows through the above-mentioned variable resistor element of above-mentioned select storage unit when above-mentioned pseudo-read-out voltage applies flows through when applying is big.

According to this formation, by during strengthening the applying voltage and shortening and apply of pseudo-read-out voltage, shortened during total the applying of read-out voltage and pseudo-read-out voltage, can suppress to follow the resistance variations of the variable resistor element of the work of reading equally, can suppress to make readout interval elongated because of applying pseudo-read-out voltage.

Here, in storage unit is under the situation of 1R type storage unit, memory cell array has many capable selection wires that extend at line direction and many column selection lines that extend at column direction, above-mentioned each storage unit with delegation is connected a distolateral and same above line selection wire of above-mentioned variable resistor element, above-mentioned each storage unit of same row is connected another distolateral and same above-mentioned column selection line of above-mentioned variable resistor element, in storage unit is under the situation of 1T/1R type storage unit, memory cell array has many capable selection wires that extend at line direction and many column selection lines that extend at column direction, above-mentioned each storage unit with delegation makes the transistorized grid of above-mentioned selection be connected with same above line selection wire, above-mentioned each storage unit of same row is connected a distolateral and same above-mentioned column selection line of above-mentioned series circuit, above-mentioned each storage unit makes that another of above-mentioned series circuit is distolateral to be connected with source electrode line, no matter which kind of situation can be given full play to the effect of the present invention with above-mentioned feature.

In addition, the reading method of Nonvolatile semiconductor memory device of the present invention is to come the storage unit of the variable resistor element of canned data to read the method for above-mentioned information to having the resistance variations utilized, it is characterized in that, carry out: the 1st handles, to apply the read-out voltage of regulation as the above-mentioned variable resistor element of reading the said memory cells of object, judge the size of the electric current that flows through above-mentioned variable resistor element; And the 2nd handle, and the above-mentioned variable resistor element that has applied the said memory cells of above-mentioned read-out voltage in the above-mentioned the 1st handles is applied opposite polarity pseudo-read-out voltage with above-mentioned read-out voltage.And then reading method of the present invention is characterised in that: carry out the above-mentioned the 1st before and after on the time in during the said memory cells that has applied above-mentioned read-out voltage in the above-mentioned the 1st handles is being selected and handle and above-mentioned the 2nd processing.

If reading method according to above-mentioned feature, the variable resistor element of the storage unit that might increase or reduce resistance value, in the 1st handles, apply read-out voltage, in the 2nd handles, apply the pseudo-read-out voltage of reversed polarity, thus, resistance is changed to the direction that offsets with the resistance variations that applies read-out voltage.The result, even increase the 1st in handling read-out voltage apply number of times, also can suppress the resistance variations that begins to accumulate from the initial resistance state, can suppress to read the decline of tolerance limit, and then can improve significantly up to the disappear read-around number of the state that maybe can not read of storage data.

Description of drawings

Fig. 1 is the circuit diagram that schematically shows an example formation of the memory cell array that has variable resistor element and select transistorized 1T/1R type storage unit.

Fig. 2 is a block scheme of representing that an example of the Nonvolatile semiconductor memory device of the memory cell array with 1T/1R type storage unit that has earlier constitutes.

Fig. 3 only schematically shows the circuit diagram that an example of the memory cell array of the 1R type storage unit that is made of variable resistor element constitutes.

Fig. 4 is the memory cell array that is made of 1R type storage unit of representing to have earlier example applies the order of voltage to each word line and each bit line when data are read work a sequential chart.

Fig. 5 is a block scheme of representing that an example of the Nonvolatile semiconductor memory device of the memory cell array with 1R type storage unit that has earlier constitutes.

Fig. 6 is that expression is the performance plot that the variable resistor element of high resistance state applies the relation of potential pulse and resistance variations to original state.

Fig. 7 is that expression is the performance plot that the variable resistor element of low resistance state applies the relation of potential pulse and resistance variations to original state.

Fig. 8 is the block scheme that the example of Nonvolatile semiconductor memory device of the memory cell array of the expression 1R of having type storage unit of the present invention constitutes.

Fig. 9 is that the example of memory cell array that schematically shows the 1R type storage unit of Nonvolatile semiconductor memory device of the present invention constitutes and a routine voltage applies circuit diagram in proper order.

Figure 10 is memory cell array one example when data are read work that is made of 1R type storage unit of expression Nonvolatile semiconductor memory device of the present invention applies the order of voltage to each word line and each bit line a sequential chart.

Figure 11 is memory cell array another example when data are read work that is made of 1R type storage unit of expression Nonvolatile semiconductor memory device of the present invention applies the order of voltage to each word line and each bit line a sequential chart.

Figure 12 is that expression is another performance plot that the variable resistor element of high resistance state applies the relation of potential pulse and resistance variations to original state.

Figure 13 is block scheme that another example of Nonvolatile semiconductor memory device of the memory cell array of the expression 1R of having type storage unit of the present invention constitutes.

Figure 14 is that the example of memory cell array that schematically shows the 1R type storage unit of Nonvolatile semiconductor memory device of the present invention constitutes and another routine voltage applies the circuit diagram of order.

Figure 15 is memory cell array another example when data are read work that is made of 1R type storage unit of expression Nonvolatile semiconductor memory device of the present invention applies the order of voltage to each word line and each bit line a sequential chart.

Figure 16 is block scheme that another example of Nonvolatile semiconductor memory device of the memory cell array of the expression 1R of having type storage unit of the present invention constitutes.

Figure 17 is that memory cell array one example that schematically shows the 1R type storage unit of Nonvolatile semiconductor memory device of the present invention constitutes the circuit diagram that applies order with another routine voltage.

Figure 18 is memory cell array another example when data are read that is made of 1R type storage unit of expression Nonvolatile semiconductor memory device of the present invention applies the order of voltage to each word line and each bit line a sequential chart.

Figure 19 is block scheme that another example of Nonvolatile semiconductor memory device of the memory cell array of the expression 1R of having type storage unit of the present invention constitutes.

Figure 20 is memory cell array another example when data are read work that is made of 1R type storage unit of expression Nonvolatile semiconductor memory device of the present invention applies the order of voltage to each word line and each bit line a sequential chart.

Figure 21 is memory cell array another example when data are read work that is made of 1R type storage unit of expression Nonvolatile semiconductor memory device of the present invention applies the order of voltage to each word line and each bit line a sequential chart.

Figure 22 is the circuit diagram that the example of delay circuit of an embodiment of expression Nonvolatile semiconductor memory device of the present invention constitutes.

Figure 23 is the block scheme that the example of Nonvolatile semiconductor memory device of the memory cell array of the expression 1T/1R of having type storage unit of the present invention constitutes.

Figure 24 is memory cell array one example when data are read work that is made of 1T/1R type storage unit of expression Nonvolatile semiconductor memory device of the present invention applies the order of voltage to each word line, each bit line, each source electrode a sequential chart.

Figure 25 is memory cell array another example when data are read work that is made of 1T/1R type storage unit of expression Nonvolatile semiconductor memory device of the present invention applies the order of voltage to each word line, each bit line, each source electrode a sequential chart.

Embodiment

Below, the embodiment of Nonvolatile semiconductor memory device of the present invention (below, suitably be called " apparatus of the present invention ") is described with reference to the accompanying drawings.

In the present embodiment, the storage unit that constitutes the memory cell array of Nonvolatile semiconductor memory device has the resistance variations utilized and comes the variable resistor element of canned data and form, as an example of this variable resistor element, the RRAM element of the 3-tier architecture of Pt electrode has been described disposing up and down of PCMO film.Have again, as variable resistor element, if because of voltage applies the element that (or electric current applies) has a resistance and change, then no matter which type of variable resistor element can be applicable to the present invention.Have again, as variable resistor element, if because of electric pulse applies the element that (or electric current applies) has a resistance and change, no matter which type of variable resistor element can be applicable to the present invention.Even the material of variable resistor element is the metal oxide outside the PCMO film, so long as, also go for the present invention because of electric pulse applies the element that has a resistance and change.In addition, if the material of variable resistor element is a transition metal oxide, and be because of electric pulse applies the element that has a resistance and change, also go for the present invention.

The present application persons find: by the PCMO film (Pr as a kind of perovskite type metal oxide _1-xCa _xMnO ₃) and the Pt electrode is set at an upper portion thereof and at a lower portion thereof forms variable resistor element, when variable resistor element being applied to continuously certain orientation and flowing through the potential pulse of same polarity of electric current, the resistance of variable resistor element changes with the increase that pulse applies number of times.Have, the PCMO film of this variable resistor element is to use sputtering method 500 ℃ of following film forming again.

As shown in Figure 6, when the upper electrode to variable resistor element applied the pulse (pulse width 100ns) of positive polarity, original state, the state that does not promptly add pulse were that the resistance value of the variable resistor element of high resistance state descends with the increase that pulse applies number of times.The high resistance state of original state is to form by lower electrode being applied the potential pulse that writes that writes voltage Vpp=4V, pulse width 3 μ s.

When the negative pulse that is continuously applied and writes the potential pulse same polarity (pulse width 100ns), resistance value rises with the increase that pulse applies number of times.In addition, the electric current that the voltage amplitude of the potential pulse that applies is big more, promptly flow through variable resistor element is big more, the degree of resistance variations is big more, and resistance is that direction changes or change the polarity that relies on the potential pulse that flows through sense of current, promptly applies to reducing direction to increasing.

The present application persons are conceived to the resistance variations direction of variable resistor element to apply the dependence of the sense of current that flows through variable resistor element because of potential pulse, investigation is when reading work, different potential pulse when applying direction of current and reading, the method that resistance variations is offset, and attempt variable resistor element is alternately applied the different potential pulse of direction of current continuously.Fig. 6 is the exemplary of the mode of research resistance variations under situation about applying again after the pulse combined with the opposite polarity of current opposite in direction when the variable resistor element that is high resistance state applies potential pulse continuously to original state.Compare with the situation of the potential pulse that applies identical polar continuously, under the situation about alternately applying again after the potential pulse combination that polarity is different, its resistance variations diminishes.This fact has obtained checking in Fig. 6.Thus, when reading the data of the cell stores that comprises variable resistor element, by flowing through the electric current of the opposite current that direction flows through when reading forcibly, potential pulse when reading can be applied the resistance variations that causes and be suppressed to minimum, read-around number is increased.

In order to add the resistance variations that the read-out voltage pulse reduces the variable resistor element of storage unit, the method for the pseudo-read-out voltage pulse that applied the reversed polarity that makes current reversal before adding the read-out voltage pulse is arranged by variable resistor element to storage unit.

Because become big if the amplitude of potential pulse becomes the resistance variations of big then variable resistor element, so, apply the pseudo-read-out voltage pulse that applies before by being adjusted at the read-out voltage pulse, can make the resistance variations minimum, can be increased in because of reading the read-around number that tolerance limit can correctly be read from storage unit before reducing to read.

In addition, because if the narrow then resistance variations of pulse width of the pseudo-read-out voltage pulse that applies is little, so, preferably use the big pseudo-read-out voltage pulse of amplitude, can offset the resistance variations that produces because of the read-out voltage pulse by the applying of pseudo-read-out voltage pulse of short time like this, can shorten actual readout time.Have again,, also can not reduce pulse width even apply the big pseudo-read-out voltage pulse of amplitude, and to apply with the roughly the same pulse width of read-out voltage pulse.

As apply another method of resistance variations that the read-out voltage pulse reduces the variable resistor element of storage unit by variable resistor element, the method for the pseudo-read-out voltage pulse that applies the reversed polarity that makes current reversal after adding the read-out voltage pulse is arranged to storage unit.

Because become big if the amplitude of potential pulse becomes the resistance variations of big then variable resistor element, so, apply the pseudo-read-out voltage pulse that applies afterwards by being adjusted at the read-out voltage pulse, can make the resistance variations minimum, can be increased in because of reading the read-around number that tolerance limit can correctly be read from storage unit before reducing to read.

In addition, because if the narrow then resistance variations of pulse width of the pseudo-read-out voltage pulse that applies is little, so, preferably use the big pseudo-read-out voltage pulse of amplitude, can offset the resistance variations that produces because of the read-out voltage pulse by the applying of pseudo-read-out voltage pulse of short time like this, can shorten actual readout time.

Secondly, according to above new opinion to variable resistor element, explanation can suppress to follow apparatus of the present invention of the resistance variations of the variable resistor element of reading the work appearance.At first, apparatus of the present invention when adopting the 1R type storage unit that storage unit only is made of variable resistor element are described.

(the 1st embodiment)

The example that Fig. 8 illustrates apparatus of the present invention constitutes.Have again, in Fig. 8, describing with the common additional common symbol of part of the Nonvolatile semiconductor memory device that has earlier.As shown in Figure 8, apparatus of the present invention have bit line decoder 16, word-line decoder 17, voltage switch circuit 22a, sensing circuit 23 and control circuit 20a being the rectangular periphery of arranging the memory cell array 15 of 1R type storage unit (not shown).Basically the formation with the Nonvolatile semiconductor memory device that has earlier of the memory cell array with 1R type storage unit shown in Figure 5 is identical.Be the work of control circuit 20a of the work of the voltage that memory cell array 15 applied from voltage switch circuit 22a and sequential working and control voltage switch circuit 22a with the difference of the Nonvolatile semiconductor memory device that has earlier of Fig. 5.

In addition, also the formation with the memory cell array 15 of the Nonvolatile semiconductor memory device that has earlier shown in Figure 3 is identical for the formation of memory cell array 15.Specifically, the formation of memory cell array 15 is at the m root that extends along the column direction (bit line (being equivalent to the column selection line) of BL1～BLm) and follow the n root that direction extends and (dispose m * n storage unit 2 on the intersection point of the word line (being equivalent to capable selection wire) of WL1～WLn).Each storage unit 14 makes word line be connected with the upper electrode of variable resistor element 3, and bit line is connected with the lower electrode of variable resistor element 3.Have, word line is connected with the lower electrode of variable resistor element 3, bit line is connected with the upper electrode of variable resistor element 3, and the upper electrode of variable resistor element 3 and the relation of lower electrode are turned around.

Bit line decoder 16 and word-line decoder 17 from read object-storage unit from address wire 18 selection to the corresponding memory cell array 15 of the address of control circuit 20a input input.Word-line decoder 17 is selected the word line of the memory cell array 15 corresponding with the signal of importing to address wire 18, and bit line decoder 16 is selected the bit line of the memory cell array 15 corresponding with the address signal of importing to address wire 18.In the present embodiment, word-line decoder 17 has the function with behavior unit's memory cell selecting circuit of select storage unit from memory cell array 15.Control circuit 20a carries out the control of each work that writes, wipes and read of memory cell array 15.Control circuit 20a is according to from the address signal of address wire 18 input, from the data inputs (writing fashionable) of data line 19 inputs, from the control input signals of control signal wire 21 inputs, control word-line decoder 17, bit line decoder 16, voltage switch circuit 22 and memory cell array 15 read, write and wipe work.In example shown in Figure 5, control circuit 20a has the function of general address buffering circuit, data input and output buffer circuit, control input buffer circuit (not shown).

Voltage switch circuit 22a is corresponding with mode of operation when switching in the reading, write and wipe of memory cell array 15 required word line and each voltage of bit line, and supply with to memory cell array 15.Especially, under readout mode, voltage switch circuit 22a plays read-out voltage and applies circuit, the read-out voltage that the bit line that is connected with the 1 row select storage unit of being selected by word-line decoder 17 and word line are applied regulation.In the present embodiment, the storage unit that will be connected with 1 selection word line being selected by word-line decoder 17 applies the read-out voltage of regulation as select storage unit to it.Among the figure, Vcc is the supply voltage of apparatus of the present invention, and Vss is a ground voltage, and Vpp writes or wipe that to use voltage, V1 and V2 be to generate read-out voltage and the employed voltage of pseudo-read-out voltage.

Sensing circuit 23 is in the read current that flows through the bit line that is connected with select storage unit, the read current that will flow through the selection bit line of being selected by bit line decoder 16 is varied to voltage, judge state with the interior selection bit line storage data that be connected, that read object-storage unit of the select storage unit of 1 row, send its result to control circuit 20a, and to data line 19 outputs.

Secondly, the embodiment that applies the order of potential pulse from voltage switch circuit 22a to each bit line of memory cell array 15 and each word line be described when reading work.

＜embodiment 1 〉

At first, the 1st embodiment is described,, select storage unit is applied read-out voltage, then, apply the pseudo-read-out voltage of the resistance variations that is used for suppressing select storage unit in order to carry out the work of reading of data with reference to Fig. 9 and Figure 10.

In Fig. 9 and Figure 10, when the routine data that the memory cell array 15 of apparatus of the present invention is shown are read work each several part is applied the order of voltage.

At first, when reading the data of select storage unit, the selection word line that is connected with select storage unit is maintained on the earthing potential Vss, Tr between reading duration applies read-out voltage V1 to other non-selection word lines and all bit lines.Tr between reading duration, because of between selection word line and selection bit line, producing the voltage difference of read-out voltage V1, so the variable resistor element of select storage unit flows through with its resistance, is the corresponding read current of store status, can read the data that are stored in the select storage unit.At this moment, in select storage unit, the outer storage unit of object of reading that is connected with non-selection bit line is applied read-out voltage V1 too.

Secondly, after through Tr between reading duration, to select word line apply with read-out voltage V1 same polarity, magnitude of voltage be its voltage V2 of 2 times (V2=2 * V1), other non-selection word lines and all bit lines are continuously applied read-out voltage V1.As a result, magnitude of voltage is identical to all applying with read-out voltage V1 reversed polarity with all select storage units of selecting word line to connect | V2-V1| (=| pseudo-read-out voltage V1|).With reading duration between in the identical regeneration period Td of time of Tr, keep the state that applies of pseudo-read-out voltage.When switching selects word line to read other select storage unit, repeat above-mentioned work equally successively.As a result, because of each select storage unit front and back is applied the read-out voltage V1 pseudo-read-out voltage identical with polarity opposite voltage value, the resistance variations of the variable resistor element that produces so can suppress to follow the reading work of each select storage unit in couples.Have again, also can between reading duration, switch the selection bit line successively by Tr, read a plurality of storage unit continuously.

Illustrate that according to experimental data the applying method of present embodiment is effective.Fig. 6 is the result of the mode of its resistance variations of research under situation about applying again after the pulse combined with the opposite polarity of current opposite in direction when the variable resistor element that is high resistance state applies continuous potential pulse to original state.As shown in Figure 6, in original state is under the situation of high resistance state, with only apply continuously positive polarity read-out voltage pulse (voltage amplitude 2V, pulse width 100ns) situation and the pseudo-read-out voltage pulse (voltage amplitude 2V, pulse width 100ns) of read-out voltage pulse that alternately applies positive polarity and negative polarity situation relatively, clearly, resistance variations in the time of can suppressing to apply two potential pulses of positive polarity and negative polarity significantly, thus the validity of above-mentioned applying method confirmed.

＜embodiment 2 〉

Secondly, the 2nd embodiment is described,, select storage unit is applied read-out voltage, then, apply the pseudo-read-out voltage of the resistance variations that is used for suppressing select storage unit in order to carry out the work of reading of data with reference to Fig. 9 and Figure 11.At this moment, to the 2 times also big voltage V2 of the voltage switch circuit 22a of apparatus of the present invention shown in Figure 8 service voltage value than voltage V1.

In Fig. 9 and Figure 11, when the routine data that the memory cell array 15 of apparatus of the present invention is shown are read work each several part is applied the order of voltage.

At first, when reading the data of select storage unit, the selection word line that is connected with select storage unit is maintained on the earthing potential Vss, Tr between reading duration applies read-out voltage V1 to other non-selection word lines and all bit lines.Tr between reading duration, because of between selection word line and selection bit line, producing the voltage difference of read-out voltage V1, so the variable resistor element of select storage unit flows through with its resistance, is the corresponding read current of store status, can read the data that are stored in the select storage unit.At this moment, in select storage unit, the outer storage unit of object of reading that is connected with non-selection bit line is applied read-out voltage V1 too.

Secondly, after through Tr between reading duration, apply to selecting word line that (V2＞2 * V1) are continuously applied read-out voltage V1 to other non-selection word lines and all bit lines than its 2 times also big voltage V2 with read-out voltage V1 same polarity, magnitude of voltage.As a result, to all applying and read-out voltage V1 reversed polarity and magnitude of voltage height with all select storage units of selecting word line to be connected | V2-V1| (＞| pseudo-read-out voltage V1|).Wherein, when pseudo-read-out voltage | when V2-V1| is excessive, write or wipe work because of what become data, thus be set in than write or low-voltage that the lower limit of erasing voltage is also low on.In the regeneration period Td that Tr is short between than reading duration, keep the state that applies of pseudo-read-out voltage.Because of pseudo-read-out voltage | V2-V1| is than read-out voltage | and V1| is big, so even regeneration period Td is shorter than Tr between reading duration, also can suppress the resistance variations that causes because of a series of work that applying of read-out voltage V1 returned the resistance variations of variable resistor element in the other direction.When switching selects word line to read other select storage unit, repeat above-mentioned work equally successively.As a result, because of each select storage unit front and back is applied read-out voltage V1 and the high pseudo-read-out voltage of polarity opposite voltage value, the resistance variations of the variable resistor element that produces so can suppress to follow the reading work of each select storage unit in couples.Have again, also can between reading duration, switch the bit line of selection successively by Tr, read a plurality of storage unit continuously.

Illustrate that according to experimental data the applying method of present embodiment is effective.Figure 12 is to original state under situation about applying again after the pulse combined with the opposite polarity of current opposite in direction when the variable resistor element that is high resistance state applies continuous potential pulse, make the voltage amplitude and the pulse width variation of inverted pulse, study the result of the mode of its resistance variations.Have again, the condition determination of resistance value shown in Figure 12 be according to lower electrode add ground voltage as benchmark, the current value when upper electrode is added 0.5V calculates.In addition, the transverse axis of Figure 12 applies number of times relatively with what the form of logarithm was represented potential pulse.As shown in Figure 12, even the pulse width of inverted pulse is narrow, by strengthening voltage amplitude, also can be the same with read-out voltage pulsion phase situation together with the voltage amplitude and the pulse width of inverted pulse, have the effect that suppresses resistance variations.For example, as shown in Figure 12, in original state is under the situation of high resistance state, read-out voltage pulse (the voltage amplitude 2V of positive polarity will only be applied continuously, pulse width 100ns) situation with alternately apply the read-out voltage pulse of positive polarity and pseudo-read-out voltage pulse (the voltage amplitude 2V of negative polarity, pulse width 100ns) situation reaches read-out voltage pulse (the voltage amplitude 2V that alternately applies positive polarity, pulse width 100ns) and pseudo-read-out voltage pulse (the voltage amplitude 3V of negative polarity, pulse width 50ns) situation relatively, can confirm, no matter apply the potential pulse of which type of positive polarity and negative polarity, all has the effect of roughly the same inhibition resistance variations.Therefore, according to the experimental data of Figure 12, can confirm the validity of the applying method of present embodiment.

And then, in the present embodiment, because of regeneration period Td can be shorter than Tr between reading duration, so the readout interval time that determine by total ascent time of Tr between reading duration and regeneration period Td, in the same memory cell array also can lack.Have again, though regeneration period Td can be shorter than Tr between reading duration, also can be identical with Tr between reading duration.

＜embodiment 3 〉

Secondly, the 3rd embodiment is described,, select storage unit is applied read-out voltage, then, apply the pseudo-read-out voltage of the resistance variations that is used for suppressing select storage unit in order to carry out the work of reading of data with reference to Figure 13 to Figure 15.

In Figure 14 and Figure 15, when the routine data that the memory cell array 15 of apparatus of the present invention is shown are read work each several part is applied the order of voltage.Do not supply with the foregoing description 1 and the 2 voltage V2 that use to the voltage switch circuit 22b of apparatus of the present invention shown in Figure 13.The difference of the Nonvolatile semiconductor memory device that has earlier of apparatus of the present invention shown in Figure 13 and Fig. 5 is the work of control circuit 20b of the work of the voltage that applies to memory cell array 15 from voltage switch circuit 22b and sequential working and control voltage switch circuit 22b.Because of this difference can not illustrate in Figure 13, so be illustrated below.

At first, when reading the data of select storage unit, the selection word line that is connected with select storage unit is maintained on the earthing potential Vss, Tr between reading duration applies read-out voltage V1 to other non-selection word lines and all bit lines.Tr between reading duration, because of between selection word line and selection bit line, producing the voltage difference of read-out voltage V1, so the variable resistor element of select storage unit flows through with its resistance, is the corresponding read current of store status, can read the data that are stored in the select storage unit.At this moment, in select storage unit, the outer storage unit of object of reading that is connected with non-selection bit line is applied read-out voltage V1 too.

Secondly, after through Tr between reading duration, apply read-out voltage V1 to selecting word line, making remaining non-selection word line and all bit lines is earthing potential Vss.As a result, magnitude of voltage is identical to all applying with read-out voltage V1 reversed polarity with all select storage units of selecting word line to connect | pseudo-read-out voltage V1|).With reading duration between in the identical regeneration period Td of time of Tr, keep the state that applies of pseudo-read-out voltage.When switching selects word line to read other select storage unit, repeat above-mentioned work equally successively.As a result, because of each select storage unit front and back is applied the read-out voltage V1 pseudo-read-out voltage identical with polarity opposite voltage value, the resistance variations of the variable resistor element that produces so can suppress to follow the reading work of each select storage unit in couples.Have again, also can between reading duration, switch the selection bit line successively by Tr, read a plurality of storage unit continuously.

＜embodiment 4 〉

Secondly, the 4th embodiment is described,, select storage unit is applied read-out voltage, then, apply the pseudo-read-out voltage of the resistance variations that is used for suppressing select storage unit in order to carry out the work of reading of data with reference to Figure 16 to Figure 18.At this moment, replace embodiment 1 and the 2 voltage V2 that use, to the voltage switch circuit 22c of apparatus of the present invention shown in Figure 16 service voltage value voltage V3 bigger than voltage V1.

In Figure 17 and Figure 18, when the routine data that the memory cell array 15 of apparatus of the present invention is shown are read work each several part is applied the order of voltage.The difference of the Nonvolatile semiconductor memory device that has earlier of apparatus of the present invention shown in Figure 16 and Fig. 5 is the work of control circuit 20c of the work of the voltage that applies to memory cell array 15 from voltage switch circuit 22c and sequential working and control voltage switch circuit 22c.

At first, when reading the data of select storage unit, the selection word line that is connected with select storage unit is maintained on the earthing potential Vss, Tr between reading duration applies read-out voltage V1 to other non-selection word lines and all bit lines.Tr between reading duration, because of between selection word line and selection bit line, producing the voltage difference of read-out voltage V1, so the variable resistor element of select storage unit flows through with its resistance, is the corresponding read current of store status, can read the data that are stored in the select storage unit.At this moment, in select storage unit, the outer storage unit of object of reading that is connected with non-selection bit line is applied read-out voltage V1 too.

Secondly, after through Tr between reading duration, apply read-out voltage V3 to selecting word line, making remaining non-selection word line and all bit lines is earthing potential Vss.As a result, to all applying with read-out voltage V1 reversed polarity and the magnitude of voltage height with all select storage units of selecting word line to be connected | V3| (＞| pseudo-read-out voltage V1|).Wherein, when pseudo-read-out voltage | when V3| is excessive, write or wipe work because of what become data, thus be set in than write or low-voltage that the lower limit of erasing voltage is also low on.With reading duration between Tr identical or in short regeneration period Td, keep the state that applies of pseudo-read-out voltage than it.Because of pseudo-read-out voltage | V3| is than read-out voltage | and V1| is big, so even regeneration period Td is shorter than Tr between reading duration, also can suppress the resistance variations that causes because of a series of work that applying of read-out voltage V1 returned the resistance variations of variable resistor element in the other direction.When switching selects word line to read other select storage unit, repeat above-mentioned work equally successively.As a result, because of each select storage unit front and back is applied read-out voltage V1 and the high pseudo-read-out voltage of polarity opposite voltage value, the resistance variations of the variable resistor element that produces so can suppress to follow the reading work of each select storage unit in couples.Have again, also can between reading duration, switch the bit line of selection successively by Tr, read a plurality of storage unit continuously.

(the 2nd embodiment)

The example that Figure 19 illustrates the 2nd embodiment of apparatus of the present invention constitutes block diagram.Have again, in Figure 19, describing with Fig. 8, Figure 13 and the common additional common symbol of part of the 1st embodiment shown in Figure 16.As shown in figure 19, apparatus of the present invention have bit line decoder 16, word-line decoder 17, voltage switch circuit 22d, sensing circuit 23, control circuit 20d and delay circuit 24 being the rectangular periphery of arranging the memory cell array 15 of 1R type storage unit (not shown).On the basis of apparatus of the present invention of the 1st embodiment shown in Figure 13, increased delay circuit 24.The function of the each several part except that delay circuit 24 is the same with the 1st embodiment, Therefore, omited repeat specification.

In the 2nd embodiment, control by control circuit 20d and delay circuit 24 to voltage and sequential thereof that memory cell array 15 applies from voltage switch circuit 22d.In addition, control, before select storage unit is applied read-out voltage, apply the pseudo-read-out voltage of the resistance variations that is used for suppressing select storage unit in order to carry out the reading work of data.Below, with reference to Figure 20 and Figure 21, when the routine data that the memory cell array 15 of apparatus of the present invention is described are read work each several part is applied the order of voltage.

When Figure 20 illustrates an example from the work of a plurality of address read-outing datas each several part is applied the order of voltage.In addition, Figure 21 is expression applies the sequential of voltage to each bit line of memory cell array 15 and each word line a timing waveform.

At first, through address wire 18 input start addresses (#1).Secondly, making all bit lines of the memory cell array with the object-storage unit of reading and word line is earthing potential Vss (#2).In Figure 20, Vsw1, Vnw1 and Vb1 represent to select the voltage level of the voltage level of word line, non-selection word line and the voltage level of bit line respectively.

Secondly, maintain under the state of earthing potential Vss, to selecting word line to apply the 1st pulse (#3) that voltage amplitude is V1 at the voltage level that makes non-selection word line and bit line.The pulse width of the 1st pulse utilizes delay circuit 24 to adjust, and making it is the total ascent time of Tp between regeneration period Td and precharge phase described later.With rising edge than the 1st pulse daley the time that equates with regeneration period Td, negative edge than the 1st pulse daley and reading duration between equal time of Tr, the 2nd pulse of same voltage amplitude V1 add to non-selection word line and all bit lines (#4).The pulse width of the 2nd pulse utilizes delay circuit 24 to adjust, and making it is total ascent time of Tr between Tp and reading duration between precharge phase.From applying the 1st pulse (#3) in the regeneration period Td that applies the 2nd pulse (#4), carry out applying of pseudo-read-out voltage in advance so that take place in the back read work the time relax the resistance variations that select storage unit produces.Have again, Tp (from #4 to #5) between precharge phase, all bit lines and word line all apply voltage V1, and current potential equates that the potential difference (PD) of all storage unit all is 0V.

Secondly, after Tp between precharge phase, non-selection word line and bit line are applied under the state of the 2nd pulse keeping, stop to selecting word line to apply the 1st pulse (#5).Then, after Tr between reading duration, stop to apply the 2nd pulse to non-selection word line and bit line, making non-selection word line and bit line is earthing potential Vss (#6).Tr (from #5 to #6) between reading duration, because of between selection word line and selection bit line, producing the voltage difference of read-out voltage V1, so the variable resistor element of select storage unit flows through with its resistance, is the corresponding read current of store status, can read the data that are stored in the select storage unit.Specifically, though flow through read current with all select storage units of selecting word line to be connected, but only the read current that the selection bit line of wherein being selected by bit line decoder 16 is flow through is transformed into voltage, judge the store status of the storage unit of reading object, send its result to control circuit 20d, and export to data line 19.More than, by each address being carried out successively the processing of #3～#6, all storage unit of being selected by the input of a plurality of addresses are carried out 1 pair of read-out voltage (V1) and pseudo-read-out voltage (the applying V1) identical with the polarity opposite amplitudes of read-out voltage, so, can suppress to follow the resistance variations of variable resistor element of the work of reading of each select storage unit.

Have again, during 1 selection till select storage unit being switched to next select storage unit according to the address input, the electric stress that select storage unit is subjected to be magnitude of voltage and time product, be V1 * (Tr-Td), in order to reduce electric stress, preferably adjust the time delay of the 1st pulse and the 2nd pulse of delay circuit 24, make that Tr and regeneration period Td equate between reading duration.In addition, because of to the 1st pulse and the 2nd interpulse time delay and the pulse width decision of access time of each select storage unit, so corresponding setting of access time best and needs by delay circuit 24.

Figure 22 illustrates the example that the circuit of the delay circuit 24 of present embodiment constitutes.As shown in figure 22, a routine delay circuit 24 by time delay 2 different systems sequence of inverters constitute.The input end input is as the basic pulse of the benchmark of the 1st pulse and the 2nd pulse, respectively with different time delay, from exporting 1 output the 2nd pulse, from exporting 2 outputs the 1st pulse.Have, it is the circuit that only is made of the sequence of inverters of Figure 22 that the generative circuit of the 1st pulse and the 2nd pulse does not limit, and also logic gates appropriate combination such as NAND or NOR can be constituted again.

(the 3rd embodiment)

Secondly, the 3rd embodiment of apparatus of the present invention is described.The example that Figure 23 illustrates the 3rd embodiment of apparatus of the present invention constitutes block diagram.Have again, in Figure 23, describing with the common additional common symbol of part of the Nonvolatile semiconductor memory device that has earlier.In the 3rd embodiment, have bit line decoder 5, source electrode line code translator 6, word-line decoder 7, voltage switch circuit 12a, sensing circuit 13 and control circuit 10a being the rectangular periphery of arranging the memory cell array 1 of 1T/1R type storage unit (not shown).After being selected by bit line decoder 5, source electrode line code translator 6 and word-line decoder 7 from the particular storage of address wire 8 in the corresponding memory cell array 1 of the address of control circuit 10a input input, carry out each work that writes, wipes and read of data, read out to selecteed storage unit stores data and with it.And the data input and output between the external device (ED) (not shown) are carried out through data line 9.Basically the formation with the Nonvolatile semiconductor memory device that has earlier of the memory cell array with 1T/1R type storage unit shown in Figure 2 is identical.Be the work of control circuit 10a of the work of the voltage that memory cell array 1 applied from voltage switch circuit 12a and sequential working and control voltage switch circuit 12a with the difference of the Nonvolatile semiconductor memory device that has earlier of Fig. 2.

In addition, also the formation with the memory cell array 1 of the Nonvolatile semiconductor memory device that has earlier shown in Figure 1 is identical for the formation of memory cell array 1.Specifically, the formation of memory cell array 1 is at the m root bit line that extends along column direction (BL1～BLm) and follow the n root word line that direction extends and (dispose m * n storage unit 2 on the intersection point of WL1～WLn).In addition, n root polar curve (SL1～SLn) and word line configured in parallel.Each storage unit makes selects the drain electrode of transistor 4 to be connected with the upper electrode of variable resistor element 3, and bit line is connected with the lower electrode of variable resistor element 3, and word line is connected with the grid of selecting transistor 4, and source electrode line is connected with the source electrode of selecting transistor 4.Have, also can make and select the drain electrode of transistor 4 to be connected with the lower electrode of variable resistor element 3, bit line is connected with the upper electrode of variable resistor element 3, and the upper electrode of variable resistor element 3 and the relation of lower electrode are turned around.

Word-line decoder 7 is selected the word line of the memory cell array 1 corresponding with the signal of importing to address wire 8, bit line decoder 5 is selected the bit line of the memory cell array 1 corresponding with the address signal of importing to address wire 8, and then source electrode line code translator 6 is selected the source electrode line of the memory cell array 1 corresponding with the address signal of importing to address wire 8.Bit line decoder 5, source electrode line code translator 6 and word-line decoder 7 play the memory cell selecting circuit, be unit with the storage unit from to the corresponding memory cell array 1 of the address of control circuit 10a input input, select 1 storage unit from address wire 8 at least.

Control circuit 10a carries out the control of each work that writes, wipes and read of memory cell array 1.Control circuit 10a is according to from the address signal of address wire 8 input, from the data inputs (writing fashionable) of data line 9 inputs, from the control input signals of control signal wire 11 inputs, control word-line decoder 7, bit line decoder 5, source electrode line code translator 6, voltage switch circuit 12a and memory cell array 1 read, write and wipe work.In example shown in Figure 23, control circuit 10 has the function of general address buffering circuit, data input and output buffer circuit, control input buffer circuit (not shown).

Each voltage of voltage switch circuit 12a is corresponding with mode of operation when switching in the reading, write and wipe of memory cell array 1 required word line, bit line and source electrode line, and supply with to memory cell array 1.Especially, under readout mode, voltage switch circuit 12a plays read-out voltage and applies circuit, the bit line that is connected with the storage unit of selecting via bit line decoder 5, source electrode line code translator 6 and word-line decoder 7 and word line and source electrode line is applied the read-out voltage of regulation.Here, Vcc is the supply voltage of nonvolatile semiconductor memory storage, and Vss is a ground voltage, and Vpp writes or wipe that to use voltage, V1 be read-out voltage.In addition, reading from memory cell array 1 of data carried out through bit line decoder 5 and sensing circuit 13.The state of sensing circuit 13 decision data, and send its result to control circuit 10a, export to data line 9 again.

Secondly, the embodiment that from voltage switch circuit 12a each bit line, each word line and each source electrode line of memory cell array 1 is applied the order of potential pulse when reading work is described.Have again, under the situation of 1T/1R type storage unit, comprise the selection transistor in the storage unit, can be only the variable resistor element of the select storage unit of reading object be applied read-out voltage, the select storage unit that can only will apply read-out voltage is as reading object-storage unit, follow the resistance variations of the variable resistor element of the work of reading to be only limited to the storage unit of reading object, so the applying also of pseudo-read-out voltage that is used for relaxing this resistance variations can be only limited to the storage unit of reading object.

At first, before applying read-out voltage, select storage unit is applied the situation of the pseudo-read-out voltage of the resistance variations that is used for suppressing select storage unit for the work of reading of data with reference to Figure 24 explanation.

At first, be at all word lines, bit line and source electrode line under the state of earthing potential Vss, make the current potential of the selection word line that is connected with select storage unit be increased to power source voltage Vcc, make selection transistor turns with 1 line storage unit of selecting word line to be connected.Simultaneously, selection source electrode line and the non-selection bit line that is connected with storage unit with delegation applied voltage V1.Because of the current potential of selecting bit line still is earthing potential Vss, so to connecting the variable resistor element of selecting bit line and selecting the select storage unit (reading object-storage unit) of source electrode line, bit line side apply Vss (=0V), apply V1 in the source electrode line side, when with the source electrode line side during, variable resistor element is applied-the pseudo-read-out voltage of V1 as reference potential.Keep applying of this puppet read-out voltage at regeneration period Td, secondly,, make and select the current potential of source electrode line and non-selection bit line to get back to earthing potential Vss to when selecting bit line to apply voltage V1.The result, when to connect to select bit line and select the variable resistor element of the select storage unit (=read object-storage unit) of source electrode line, apply V1 in bit line side, the source electrode line side apply Vss (=during as reference potential, variable resistor element is applied the read-out voltage of voltage V1 0V) and with the source electrode line side.Tr keeps applying of this read-out voltage between reading duration, make with the resistance of the variable resistor element of select storage unit, to be the selection transistor of the corresponding read current of store status through being in conducting state flow on the bit line selecting, and can be read the data of select storage unit storage by sensing circuit 13.After through Tr between reading duration, select word line and select the current potential of bit line to get back to earthing potential Vss.Have, in the present embodiment, select storage unit is consistent with reading object-storage unit again.

If according to above processing sequence, to select word line apply power source voltage Vcc make select storage unit the selection transistor turns during, front and back are carried out applying of pseudo-read-out voltage-V1 and applying of read-out voltage V1 in pairs, so, can suppress to follow the resistance variations of variable resistor element of the work of reading of select storage unit.

Here,, be added in the voltage V1 height of selecting on the bit line than Tr between reading duration, can shorten by the voltage V1 that regeneration period Td is added on selection source electrode line and the non-selection bit line though regeneration period Td can be identical with Tr between reading duration.

Secondly, after applying read-out voltage, select storage unit is applied the situation of the pseudo-read-out voltage of the resistance variations that is used for suppressing select storage unit for the work of reading of data with reference to Figure 25 explanation.

At first, be at all word lines, bit line and source electrode line under the state of earthing potential Vss, make the current potential of the selection word line that is connected with select storage unit be increased to power source voltage Vcc, make selection transistor turns with 1 line storage unit of selecting word line to be connected.Simultaneously, to selecting bit line to apply voltage V1.The result, to connect to select bit line and select the variable resistor element of the select storage unit (=read object-storage unit) of source electrode line, apply voltage V1 in bit line side, the source electrode line side apply voltage Vss (=0V), when during as reference potential, variable resistor element being applied the read-out voltage of V1 with the source electrode line side.Tr keeps applying this read-out voltage between reading duration, make with the resistance of the variable resistor element of select storage unit, to be the selection transistor of the corresponding read current of store status through being in conducting state flow on the bit line selecting, and can be read the data of select storage unit storage by sensing circuit 13.After through Tr between reading duration, make and select the current potential of bit line to get back to earthing potential Vss, simultaneously, to applying voltage V1 with selection source electrode line and the non-selection bit line of selecting word line with delegation.Because of the current potential of selecting bit line is earthing potential Vss, so variable resistor element when the select storage unit (reading object-storage unit) of connection being selected bit line and selection source electrode line, bit line side apply voltage Vss (=0V), apply voltage V1 in the source electrode line side, and during as reference potential, variable resistor element is applied the pseudo-read-out voltage of voltage-V1 with the source electrode line side.Keep applying of this puppet read-out voltage at regeneration period Td.After through regeneration period Td, select word line and select the current potential of source electrode line and non-selection bit line to get back to earthing potential Vss.

If according to above processing sequence, to select word line apply power source voltage Vcc make select storage unit the selection transistor turns during, front and back apply read-out voltage V1 and pseudo-read-out voltage-V1 in couples, so, can suppress to follow the resistance variations of variable resistor element of the work of reading of select storage unit.

Here,, be added in the voltage V1 height of selecting on the bit line than Tr between reading duration, can shorten by the voltage V1 that regeneration period Td is added on selection source electrode line and the non-selection bit line though regeneration period Td can be identical with Tr between reading duration.

Secondly, other embodiment of apparatus of the present invention is described.

In the respective embodiments described above, structure as storage unit, with regard to 1R type storage unit and 2 kinds of situations of 1T/1R type storage unit, for example understand the formation of memory cell array, but the structure of storage unit, so long as can make the positive and negative reverse structure of the direction of current of the variable resistor element that flows through select storage unit, except 1R type storage unit and 1T/1R type storage unit, also can be any other structure.In addition, the selection transistor of 1T/1R type storage unit is not limited to N type MOSFET, also can be P type MOSFET.

In above-mentioned the 3rd embodiment, formation as the memory cell array of 1T/1R type storage unit, enumerated the capable formation example that the source electrode line that follows the direction extension is set of as shown in Figure 2 each, but the formation of the memory cell array of 1T/1R type storage unit is not limited to the formation of above-mentioned embodiment.For example, also can be the source electrode line that on column direction, extends in parallel with bit line.At this moment, it is different that voltage application method and voltage with Figure 24 and Figure 25 explanation apply order, for example, as long as the current potential of non-selection bit line is kept and non-selection source electrode line equipotential (for example earthing potential Vss).And then source electrode line can be that unit is shared with the memory cell array also.

In the above-mentioned the 1st and the 2nd embodiment, suppose and select 1 word line, select and read the read current that flows through the select storage unit that is connected with this selection word line in bit line side, but the relation that also can make word line and bit line conversely, suppose and select 1 bit line, select and read the read current that flows through the select storage unit that is connected with this selection bit line in the word line side.At this moment, sensing circuit 23 is connected word-line decoder 17 1 sides.

In above-mentioned the 3rd embodiment, suppose that the read current that Tr between reading duration flows through select storage unit flows to the source electrode line side from bit line side, but also can become make Tr between reading duration flow through select storage unit read current from the source electrode line effluent to bit line side, make the electric current that flows through select storage unit among the regeneration period Td flow to the source electrode line side, also can change the voltage that is applied to each bit line, each source electrode line and set from bit line side.At this moment, as required, also can make sensing circuit 13 be connected source electrode line code translator 6 one sides.

In the respective embodiments described above, illustrated each word line, each bit line, each source electrode line (only to the 3rd embodiment) are applied the situation of the potential pulse of certain voltage amplitude, but the voltage amplitude of the potential pulse that applies also can not be controlled on certain value.For example, the control of paired pulses can not be Control of Voltage, but Current Control.

In the respective embodiments described above, Fig. 8, Figure 13, Figure 16, Figure 19 or voltage switch circuit 22a, 22b, 22c, 22d, 12a shown in Figure 23 produce each operating voltage that writes, wipes and read by 1 circuit square frame, but the circuit that also can have above-mentioned each operating voltage of independent generation respectively.And then the read-out voltage when reading work applies circuit and also can be located in each code translator.

Though by the present invention preferred embodiment has been described, only otherwise break away from the spirit and scope of the present invention, those skilled in the art can carry out various corrections and distortion to embodiments of the present invention.The present invention is as the criterion with claims of together enclosing.

Claims (26)

1. Nonvolatile semiconductor memory device, have respectively line direction and column direction arrange a plurality of comprise utilize changes in resistance come canned data variable resistor element storage unit and the memory cell array that forms is characterized in that, comprising:

The memory cell selecting circuit is that said memory cells is selected by unit from the said memory cells array with row, column or storage unit;

Read-out voltage applies circuit, and the above-mentioned variable resistor element of being selected the select storage unit that circuit selects by said memory cells is applied read-out voltage; And

Sensing circuit is read the said memory cells detection of object and the size of the corresponding read current that flows through of the resistance value of this variable resistor element to the conduct in the above-mentioned select storage unit, reads the above-mentioned information of reading in the object-storage unit that is stored in again,

Above-mentioned read-out voltage applies circuit will impose on the above-mentioned variable resistor element of above-mentioned select storage unit with the pseudo-read-out voltage of above-mentioned read-out voltage reversed polarity.

2. the described Nonvolatile semiconductor memory device of claim 1 is characterized in that:

In said memory cells was selected during 1 selection till circuit switches to other select storage units with the selection of above-mentioned select storage unit, above-mentioned read-out voltage applied circuit same above-mentioned select storage unit is applied above-mentioned read-out voltage and above-mentioned pseudo-read-out voltage.

3. the described Nonvolatile semiconductor memory device of claim 1 is characterized in that:

In said memory cells is selected during 1 selection till circuit switches to other select storage units with the selection of above-mentioned select storage unit, above-mentioned read-out voltage apply circuit to same above-mentioned select storage unit after applying above-mentioned read-out voltage, apply above-mentioned pseudo-read-out voltage.

4. the described Nonvolatile semiconductor memory device of claim 1 is characterized in that:

In said memory cells is selected during 1 selection till circuit switches to other select storage units with the selection of above-mentioned select storage unit, above-mentioned read-out voltage apply circuit to same above-mentioned select storage unit before applying above-mentioned read-out voltage, apply above-mentioned pseudo-read-out voltage.

5. the described Nonvolatile semiconductor memory device of any one of claim 1～4 is characterized in that:

Above-mentioned variable resistor element is a perovskite type metal oxide.

6. the described Nonvolatile semiconductor memory device of any one of claim 1～4 is characterized in that:

Above-mentioned variable resistor element is to make resistance value carry out the metal oxide of reversible variation by applying of electric pulse.

7. the described Nonvolatile semiconductor memory device of claim 6 is characterized in that:

Metal oxide as the material of above-mentioned variable resistor element is a transition metal oxide.

8. the described Nonvolatile semiconductor memory device of claim 6 is characterized in that:

Metal oxide as the material of above-mentioned variable resistor element comprises Pr and Mn.

9. the described Nonvolatile semiconductor memory device of any one of claim 1～4 is characterized in that:

To the above-mentioned variable resistor element of above-mentioned select storage unit apply above-mentioned pseudo-read-out voltage during than apply above-mentioned read-out voltage during short,

The electric current that the above-mentioned read-out voltage of current ratio that flows through the above-mentioned variable resistor element of above-mentioned select storage unit when above-mentioned pseudo-read-out voltage applies flows through when applying is big.

10. the described Nonvolatile semiconductor memory device of any one of claim 1～4 is characterized in that:

The said memory cells array has at many that extend on the line direction capable selection wires and many column selection lines extending on column direction, above-mentioned each storage unit with delegation is connected a distolateral and same above line selection wire of above-mentioned variable resistor element, above-mentioned each storage unit of same row is connected another distolateral and same above-mentioned column selection line of above-mentioned variable resistor element

Said memory cells selects circuit to select the said memory cells of 1 row or 1 row from the said memory cells array.

11. the described Nonvolatile semiconductor memory device of claim 10 is characterized in that:

Above-mentioned read-out voltage applies circuit pair and said memory cells and selects 1 corresponding above-mentioned column selection line of 1 row that circuit selects or 1 row or above line selection wire to apply the 1st voltage, to selecting 1 row that circuit selects or the row outside 1 row and row corresponding above-mentioned column selection line and above line selection wire to apply the 2nd voltage with said memory cells, thus, select the above-mentioned variable resistor element of the select storage unit of 1 row that circuit selects or 1 row to apply above-mentioned read-out voltage to said memory cells

Above-mentioned read-out voltage applies circuit pair and said memory cells and selects 1 corresponding above-mentioned column selection line of 1 row that circuit selects or 1 row or above line selection wire to apply the 3rd voltage, to selecting 1 row that circuit selects or the row outside 1 row and row corresponding above-mentioned column selection line and above line selection wire to apply above-mentioned the 2nd voltage with said memory cells, thus, select the above-mentioned variable resistor element of the select storage unit of 1 row that circuit selects or 1 row to apply above-mentioned pseudo-read-out voltage to said memory cells

Above-mentioned the 2nd voltage is the magnitude of voltage between above-mentioned the 1st voltage and above-mentioned the 3rd voltage, and above-mentioned the 1st voltage equates with the absolute value of the voltage difference of above-mentioned the 2nd voltage with the absolute value and above-mentioned the 3rd voltage of the voltage difference of above-mentioned the 2nd voltage.

12. the described Nonvolatile semiconductor memory device of claim 10 is characterized in that:

Above-mentioned read-out voltage applies circuit pair and said memory cells and selects 1 corresponding above-mentioned column selection line of 1 row that circuit selects or 1 row or above line selection wire to apply the 1st voltage, to selecting 1 row that circuit selects or the row outside 1 row and row corresponding above-mentioned column selection line and above line selection wire to apply the 2nd voltage with said memory cells, thus, select the above-mentioned variable resistor element of the select storage unit of 1 row that circuit selects or 1 row to apply above-mentioned read-out voltage to said memory cells

Above-mentioned read-out voltage applies circuit pair and said memory cells and selects 1 corresponding above-mentioned column selection line of 1 row that circuit selects or 1 row or above line selection wire to apply the 3rd voltage, to selecting 1 row that circuit selects or the row outside 1 row and row corresponding above-mentioned column selection line and above line selection wire to apply above-mentioned the 2nd voltage with said memory cells, thus, select the above-mentioned variable resistor element of the select storage unit of 1 row that circuit selects or 1 row to apply above-mentioned pseudo-read-out voltage to said memory cells

Above-mentioned the 2nd voltage is the magnitude of voltage between above-mentioned the 1st voltage and above-mentioned the 3rd voltage, above-mentioned the 1st voltage is littler than the absolute value of the voltage difference of above-mentioned the 3rd voltage and above-mentioned the 2nd voltage with the absolute value of the voltage difference of above-mentioned the 2nd voltage, during the applying of above-mentioned read-out voltage than long during the applying of above-mentioned pseudo-read-out voltage.

13. the described Nonvolatile semiconductor memory device of claim 10 is characterized in that:

Above-mentioned read-out voltage applies circuit pair and said memory cells and selects 1 corresponding above-mentioned column selection line of 1 row that circuit selects or 1 row or above line selection wire to apply the 1st voltage, to selecting 1 row that circuit selects or the row outside 1 row and row corresponding above-mentioned column selection line and above line selection wire to apply the 2nd voltage with said memory cells, thus, select the above-mentioned variable resistor element of the select storage unit of 1 row that circuit selects or 1 row to apply above-mentioned read-out voltage to said memory cells

Above-mentioned read-out voltage applies circuit pair and said memory cells and selects 1 corresponding above-mentioned column selection line of 1 row that circuit selects or 1 row or above line selection wire to apply above-mentioned the 2nd voltage, to selecting 1 row that circuit selects or the row outside 1 row and row corresponding above-mentioned column selection line and above line selection wire to apply above-mentioned the 1st voltage with said memory cells, thus, select the above-mentioned variable resistor element of the select storage unit of 1 row that circuit selects or 1 row to apply above-mentioned pseudo-read-out voltage to said memory cells.

14. the described Nonvolatile semiconductor memory device of claim 10 is characterized in that:

Above-mentioned read-out voltage applies circuit pair and said memory cells and selects 1 corresponding above-mentioned column selection line of 1 row that circuit selects or 1 row or above line selection wire to apply the 1st voltage, to selecting 1 row that circuit selects or the row outside 1 row and row corresponding above-mentioned column selection line and above line selection wire to apply the 2nd voltage with said memory cells, thus, select the above-mentioned variable resistor element of the select storage unit of 1 row that circuit selects or 1 row to apply above-mentioned read-out voltage to said memory cells

Above-mentioned read-out voltage applies circuit pair and said memory cells and selects 1 above-mentioned column selection line corresponding to 1 row that circuit selects or 1 row or above line to select line to apply the 4th voltage with above-mentioned the 2nd voltage same polarity; To selecting 1 row that circuit selects or the columns and rows outside 1 row corresponding above-mentioned column selection line and above line to select line to apply above-mentioned the 1st voltage with said memory cells; Thus; Select the above-mentioned variable resistor element of the select storage unit of 1 row that circuit selects or 1 row to apply above-mentioned pseudo-read-out voltage to said memory cells

Above-mentioned the 1st voltage is bigger than the absolute value of the voltage difference of above-mentioned the 1st voltage and above-mentioned the 2nd voltage with the absolute value of the voltage difference of above-mentioned the 4th voltage, during the applying of above-mentioned read-out voltage than long during the applying of above-mentioned pseudo-read-out voltage.

15. the described Nonvolatile semiconductor memory device of claim 10 is characterized in that:

In said memory cells is selected during 1 selection till circuit switches to other said memory cells with the selection of above-mentioned select storage unit, exist during the applying of above-mentioned read-out voltage and the applying of above-mentioned pseudo-read-out voltage during, above-mentioned two apply during between to have all above-mentioned column selection line and all above line selection wires be between the precharge phase of same current potential.

16. the described Nonvolatile semiconductor memory device of claim 10 is characterized in that:

In said memory cells is selected during 1 selection till circuit switches to other said memory cells with the selection of above-mentioned select storage unit, above-mentioned read-out voltage applies circuit all above-mentioned column selection lines and all above line selection wires is being applied under the state of the 2nd voltage, to selecting 1 corresponding above-mentioned column selection line of 1 row that circuit selects or 1 row or above line selection wire to apply the 1st voltage with said memory cells, after the 1st time delay, to selecting 1 row that circuit selects or the row outside 1 row and row corresponding above-mentioned column selection line and above line selection wire to apply above-mentioned the 1st voltage with said memory cells, after between the precharge phase that all above-mentioned column selection lines and all above line selection wires has been applied above-mentioned the 1st voltage, to selecting 1 corresponding above-mentioned column selection line of 1 row that circuit selects or 1 row or above line selection wire to apply above-mentioned the 2nd voltage with said memory cells, after the 2nd time delay, to selecting 1 row that circuit selects or the row outside 1 row and row corresponding above-mentioned column selection line and above line selection wire to apply above-mentioned the 2nd voltage with said memory cells

Each of above-mentioned the 1st time delay and above-mentioned the 2nd time delay through during in a side be applying of above-mentioned read-out voltage during, during the opposing party is applying of above-mentioned pseudo-read-out voltage.

17. the described Nonvolatile semiconductor memory device of claim 15 is characterized in that:

Stipulate above-mentioned read-out voltage apply during and the 1st pulse during the total between above-mentioned precharge phase and stipulate above-mentioned pseudo-read-out voltage apply during and a side of the 2nd pulse during the total between above-mentioned precharge phase utilize the opposing party's time delay to generate.

18. the described Nonvolatile semiconductor memory device of claim 16 is characterized in that:

Stipulate above-mentioned read-out voltage apply during and the 1st pulse during the total between above-mentioned precharge phase and stipulate above-mentioned pseudo-read-out voltage apply during and a side of the 2nd pulse during the total between above-mentioned precharge phase utilize the opposing party's time delay to generate.

19. the described Nonvolatile semiconductor memory device of any one in the claim 1～4 is characterized in that:

Said memory cells has above-mentioned variable resistor element and selects transistorized series circuit,

The said memory cells array has many capable selection wires of the direction of following extension and many column selection lines that extend along column direction, above-mentioned each storage unit with delegation makes the transistorized grid of above-mentioned selection be connected with same above line selection wire, above-mentioned each storage unit of same row makes an end of above-mentioned series circuit be connected with same above-mentioned column selection line, above-mentioned each storage unit makes the other end of above-mentioned series circuit be connected with source electrode line

Said memory cells selects circuit to select 1 said memory cells with delegation at least from the said memory cells array,

Above-mentioned read-out voltage applies the above line selection wire that circuit pair is connected with select storage unit that said memory cells selects circuit to select and applies the voltage that makes above-mentioned selection transistor turns, applies above-mentioned read-out voltage and above-mentioned pseudo-read-out voltage between above-mentioned column selection line that is connected with above-mentioned select storage unit and above-mentioned source electrode line respectively.

20. a reading method is to come the storage unit of the variable resistor element of canned data to read the method for above-mentioned information to having the resistance variations utilized, and it is characterized in that, carries out:

The 1st handles, and to apply the read-out voltage of regulation as the above-mentioned variable resistor element of reading the said memory cells of object, judges the size of the electric current that flows through above-mentioned variable resistor element; And

The 2nd handles, and the above-mentioned variable resistor element that has applied the said memory cells of above-mentioned read-out voltage in the above-mentioned the 1st handles is applied opposite polarity pseudo-read-out voltage with above-mentioned read-out voltage.

21. the described reading method of claim 20 is characterized in that:

In the above-mentioned the 1st handles, applied the said memory cells of above-mentioned read-out voltage selecteed during in, carry out the above-mentioned the 1st before and after in time and handle and above-mentioned the 2nd processing.

22. claim 20 or 21 described reading methods is characterized in that:

Above-mentioned variable resistor element is a perovskite type metal oxide.

23. claim 20 or 21 described reading methods is characterized in that:

Above-mentioned variable resistor element is to make resistance value carry out the metal oxide of reversible variation by applying of electric pulse.

24. the described reading method of claim 23 is characterized in that:

Metal oxide as the material of above-mentioned variable resistor element is a transition metal oxide.

25. the described reading method of claim 23 is characterized in that:

Metal oxide as the material of above-mentioned variable resistor element comprises Pr and Mn.

26. a readout device is to come the storage unit of the variable resistor element of canned data to read the device of above-mentioned information to having the resistance variations utilized, and it is characterized in that, comprising:

Decision circuit to apply the read-out voltage of regulation as the above-mentioned variable resistor element of reading the said memory cells of object, is judged the size of the electric current that flows through above-mentioned variable resistor element; And

Pseudo-read-out voltage applies circuit, and the above-mentioned variable resistor element of the said memory cells that applied above-mentioned read-out voltage in the processing of being undertaken by above-mentioned decision circuit is applied opposite polarity pseudo-read-out voltage with above-mentioned read-out voltage.

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