CN1731857B - Signal transformation device - Google Patents
Signal transformation device Download PDFInfo
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- CN1731857B CN1731857B CN2005100911087A CN200510091108A CN1731857B CN 1731857 B CN1731857 B CN 1731857B CN 2005100911087 A CN2005100911087 A CN 2005100911087A CN 200510091108 A CN200510091108 A CN 200510091108A CN 1731857 B CN1731857 B CN 1731857B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/85—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression
- H04N19/87—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving scene cut or scene change detection in combination with video compression
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
- H04N19/146—Data rate or code amount at the encoder output
- H04N19/147—Data rate or code amount at the encoder output according to rate distortion criteria
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Abstract
Matched the transmission rate and phase of an output from an active signal processing unit with the transmission rate and phase of an output from a reserve signal processing unit in a signal conversion apparatus including two kinds of active and reserve signal processing units for applying signal processing of digital compression processing, such as MPEG compression to a video signal. The signal conversion apparatus is provided with: active and reserve storage units which are provided between an active encoder and a switching unit and between a reserve encoder and the switching unit, and write and read video data generated by compressing a video signal, an invalid data storage unit for reading invalid data; and a control unit which reads each of video data at a higher transfer rate than that of writing and performs control to read the invalid data in place of video data stored in the storage units if the video data become less than a predetermined amount.
Description
Technical field
The present invention relates to have the output signal conversion of the chromacoder of 2 above signal processing parts of system with standby purpose, the impact (shock) that more specifically relates to output signal when conversion is lowered, and above-mentioned signal processing part is used for vision signal is carried out the digital compression of MPEG (MovingPicture Experts Group) compression etc. and handles.
Background technology
In the past, the structure of broadcasting equipment was, was improved in order to make reliability, and had now with machine and guest machine, and changed when in now with machine undesirable condition having taken place and now used machine and guest machine.Even if for as the mpeg stream generation systems that utilizes digital broadcasting of an example of chromacoder in the past, just compress the system that is used for digital broadcasting to carrying out MPEG from the vision signal of video camera etc., have existing too with machine and guest machine.And its structure is that machine and guest machine are now used in conversion when in now with machine undesirable condition having taken place.
For mpeg stream generation systems in the past, adopt Fig. 7,8 to describe.Fig. 7 represents the block diagram of mpeg stream generation systems structure in the past.What Fig. 8 represented is, by carry out the time diagram of TS (transport stream) signal that the MPEG compression generates respectively in each encoder of mpeg stream generation systems in the past.In Fig. 8, (a) expression TS1 signal, (b) expression TS2 signal (c) is represented switching signal, and (d) represents the TS output signal of change over switch 23.Be input in the change over switch 23 as the TS1 signal of encoder 21 outputs and the TS2 signal of exporting as encoder 22.Also have, TS1 signal and TS2 signal are to carry out the MPEG compression by 21,22 pairs of same video signal of encoder of same size respectively to generate.But, with regard to mpeg stream generation systems in the past, even each encoder by same size carries out the MPEG compression to same video signal, from the transfer rate of the TS signal of each encoder output also as shown in Figure 8, small difference is arranged (for example, transfer rate as the TS1 signal of encoder 21 output is 15.0Mbps, then is 14.9Mbps as the transfer rate of the TS2 signal of encoder 22 outputs relatively therewith).Its result is, deviation appears in the phase place of TS1 signal and TS2 signal slightly to be exported, and because the deviation of its phase place, though for example the packets of information 3 ' of the packets of information 3 of TS1 signal and TS2 signal is identical data, output time is inconsistent.
Because the packets of information of TS1 signal and the packets of information output time of TS2 signal are inconsistent, thereby it is as described below, when having carried out the conversion of existing usefulness machine and guest machine, the initial code (code in each packets of information front) that the expression packets of information begins can not be exported by some cycles.For example, when encoder 21 is guest machine for now using machine and encoder 22,, then change over switch 23 is operated converting encoder 22 to if in encoder 21, undesirable condition has taken place.At this, because each packets of information of TS1 signal, TS2 signal was exported according to the time shown in Figure 8, thereby for example on the moment ta when the TS1 conversion of signals becomes the TS2 signal, initial code (using 47h (16 systems 47) in native system) can not be exported by some cycles.Therefore, cause being in the initial code that engraves when following and do not have the moment that this then should exist by some cycles output for hypothesis constantly.Because not the existing of initial code, thereby be in the handling interrupt that the digital transmitter 24 at change over switch 23 rear portions will send the resulting last TS signal of modulation grouped data, and carry out the search of initial code once more.Its result is, occurs in to detect the undesirable condition that digital transmitter 24 before the initial code must temporarily stop the transmission of last TS signal and so on.Also have, suppose that initial code presses some cycles and export, then digital transmitter 24 carries out processing that the grouped data behind the initial code is modulated and sent.
For above-mentioned chromacoder in the past, if different existing of transfer rate, phase place changed with machine and guest machine, the equipment such as digital transmitter that then are in the chromacoder rear portion will move the undesirable condition that temporarily stops and so on.In order to prevent this undesirable condition, even if the output cycle of the initial code that the expression packets of information begins changing existing also must keep certain cycle during with machine and guest machine (for example, the situation of Fig. 8 is 204 bytes).In order to keep certain cycle, must accomplish to make from the transfer rate and the phase place of the video data (be to carry out digital compression processed video signal (being to carry out MPEG compression processed video signal) the mpeg stream generation systems, be called video data below) now exported respectively consistent by encoder by encoder with machine and guest machine.
Summary of the invention
Therefore, purpose of the present invention is, consistent by making from the transfer rate and the phase place of the video data now exported respectively with machine and guest machine, remove having changed the existing digital transmitter that is positioned at the signal translating system rear portion during with machine and guest machine and send the undesirable condition that last TS signal temporarily stops and so on.
In order to achieve the above object, the present invention possesses: transfer rate switching mechanism, be arranged at respectively between each encoder and the converter section, and be used for changing the transfer rate of each video data; Phase control mechanism is used for controlling so that the phase place of each transfer rate switching mechanism output is consistent.
Moreover transfer rate switching mechanism possesses: storage part is used for carrying out writing, reading of video data; The invalid data storage part is used for carrying out reading of invalid data; Control part is used for controlling, so that the transfer rate when video data is read is than writing under the fashionable higher situation, institute's video data stored is for less than scheduled volume the time then read invalid data in storage part.
In addition, because storage part has existing usefulness and standby storage part, and possess existing usefulness, standby control part respectively, be used for being existing reading with, standby each storage part control of video data, thereby standby control part is controlled as phase control mechanism by used control part, make from existing with and the phase place of the video data read of standby storage part consistent.
In addition, because video data is made up of a plurality of packets of information with initial code, and the front portion at each control part possesses the test section that is used for detecting initial code respectively, thereby each control part is that unit carries out writing, reading of video data in each storage part with the packets of information, and the gap of packets of information utilize converter section existing usefulness and standby between conversion.
According to the present invention, owing to can make from the phase place of the video data now exported respectively with machine and guest machine consistent, even thereby machine and guest machine are now used in conversion, also the output cycle of packets of information initial code can be remained necessarily, can prevent that therefore the equipment action that is in the chromacoder rear portion from temporarily stopping.
Description of drawings
Fig. 1 is the block diagram of expression as the mpeg stream generation systems structure of an exemplifying embodiment of chromacoder of the present invention.
Fig. 2 is the block diagram of expression as the TS converter section structure of an important document of mpeg stream generation systems of an exemplifying embodiment of chromacoder of the present invention.
Fig. 3 is the block diagram of expression as the TS converter section structure of an important document of mpeg stream generation systems of an exemplifying embodiment of chromacoder of the present invention.
Fig. 4 represents is as before the PCR correcting process in the mpeg stream generation systems of an exemplifying embodiment of chromacoder of the present invention and the time diagram of the TS signal after the PCR correcting process.
What Fig. 5 represented is before changing as the transfer rate of now using machine, guest machine in the mpeg stream generation systems of an exemplifying embodiment of chromacoder of the present invention and the time diagram of the TS signal after the transfer rate conversion.
Fig. 6 represents be as in the mpeg stream generation systems of an exemplifying embodiment of chromacoder of the present invention now with the time diagram of the TS signal before the conversion between machine and the guest machine, after the conversion.
Fig. 7 is the expression conduct block diagram of the mpeg stream generation systems structure of an example of chromacoder in the past.
Fig. 8 represents is time diagram by the TS signal that generates as the mpeg stream generation systems of an example of chromacoder in the past.
Embodiment
Below, for chromacoder, adopt Fig. 1～6 to describe as an exemplifying embodiment of the present invention.Fig. 1 is the block diagram of expression as the mpeg stream generation systems structure of an exemplifying embodiment of chromacoder of the present invention.Fig. 2, the 3rd, expression is as the block diagram of the TS converter section structure of an important document of this exemplifying embodiment mpeg stream generation systems.What Fig. 4 represented is before PCR in this exemplifying embodiment mpeg stream generation systems (the Program Clock Reference) correcting process and the time diagram of the TS signal after handling.What Fig. 5 represented is before now changing with the transfer rate of machine, guest machine in this exemplifying embodiment mpeg stream generation systems and the time diagram of the TS signal after the conversion.Fig. 6 represents is now with the time diagram of the TS signal before machine and the guest machine conversion, after the conversion in this exemplifying embodiment mpeg stream generation systems.
At first, for structure, the action of this exemplifying embodiment mpeg stream generation systems, adopt Fig. 1 to describe.Carrying out TS1 signal, TS2 signal that MPEG compression generated respectively by 11,12 pairs of same video signal of encoder is imported in the TS converter section 13.Also have encoder the 11, the 12nd, the encoder of same size.Because the vision signal MPEG compression processing of being undertaken by encoder 11,12 is one of Digital Signal Processing of mpeg stream, so described as background technology, transfer rate, the phase place of TS1 signal and TS2 signal become inconsistent sometimes.But, as described below, by transfer rate conversion, the phase place adjustment of TS converter section 13 internal conversion portion front portions,, will represent that also the code output cycle that packets of information begins remains necessarily even carry out existing conversion with machine and guest machine.The conversion of now using machine and guest machine is by means of by the user operating portion (not shown) being operated and from the switching signal (not shown) that operating portion is sent out, being undertaken by TD converter section 13.Also have, also can when undesirable conditions take place encoder 11,12, send fault-signal to TD converter section 13 respectively, and carry out the conversion of existing usefulness machine and guest machine by TS converter section 13 detecting from the time now with the fault-signal of the encoder of machine.
Then, for structure, action, adopt Fig. 2,5 to describe as the TS converter section of an important document of this exemplifying embodiment mpeg stream generation systems.Also having, in the following description, will be that the transfer rate of 15.0Mbps and the TS2 signal exported from encoder 12 is the situation of 14.9Mbps for the transfer rate of the TS1 signal of being exported from encoder 11, describe.
From the TS1 signal of encoder 11 output by ASI (Asynchronous SerialInterface) receiver 31a signal aspect is converted from serial to parallel after, send initial code test section 32a, memory 33a and PCR recapiulation 34a to.Initial code test section 32a transmits detection signal to Memory Controller 38a when detecting the packets of information initial code of TS1 signal.Memory Controller 38a is written among the memory 33a 1 packets of information amount (for example, 204 amount of bytes) of TS1 signal video frequency data when sending out detection signal.Here, writing fashionable transfer rate shown in Fig. 5 (a), for example is 15.0Mbps.Memory Controller 38a reads the video data of 1 packets of information amount of TS1 signal after writing of beginning video data passed through certain hour from memory 33a.At this, consistent because the transfer rate when reading is adjusted into the transfer rate of following TS2 signal, so shown in Fig. 5 (b), for example become 15.1Mbps.Also have,, thereby convert higher transfer rate to because it is higher to make the frequency ratio of the readout clock that offers Memory Controller 38a (below, be called CK) write the frequency of CK.From reading 1 packets of information amount of TS1 signal video frequency data,, begin writing of TS1 signal video frequency 1 packets of information amount of data once more through after the certain hour.After this, carrying out this repeatedly writes and reads.
On the other hand, also the TS1 signal with above-mentioned is identical for the TS2 signal of being exported from encoder 12, by ASI (Asynchronous Serial Interface) receiver 31b signal aspect is converted from serial to parallel after, send initial code test section 32b, memory 33b and PCR recapiulation 34b to.Initial code test section 32b transmits detection signal to Memory Controller 38b when detecting the packets of information initial code of TS2 signal.Memory Controller 38b is written among the memory 33b 1 packets of information amount of TS2 signal video frequency data when sending out detection signal.Here, writing fashionable transfer rate shown in Fig. 5 (c), for example is 14.9Mbps.Memory Controller 38b reads 1 packets of information amount of TS2 signal video frequency data after writing of beginning video data passed through certain hour from memory 33b.At this because the transfer rate when reading is consistent with the transfer rate of above-mentioned TS1 signal, so shown in Fig. 5 (d) by carrying out the transfer rate conversion, for example become 15.1Mbps.Also have,, thereby convert higher transfer rate to because it is higher to make the frequency ratio of reading CK that offers Memory Controller 38b write the frequency of CK.After reading of 1 packets of information amount of beginning TS2 signal video frequency data passed through certain hour, begin writing of TS2 signal video frequency 1 packets of information amount of data once more.After this, carrying out this repeatedly writes and reads.
Shown in Fig. 5 (b), (d), TS1 signal, TS2 signal after the transfer rate conversion become identical transfer rate (being 15.1Mbps herein), same-phase.At this,, describe for becoming identical transfer rate, the required action of same-phase.In order to become identical transfer rate, same-phase, must satisfy following (1), (2) simultaneously.
(1) after the transfer rate conversion, the output time in the output time of TS1 signal and the TS2 signal is consistent
(2) after the transfer rate conversion, the transfer rate of the transfer rate of TS1 signal and TS2 signal is consistent
In the starting stage, for example under the state of energized, No. 1 system is for now using machine, and No. 2 systems are guest machine.Behind power connection, at first the synchronizing signal RS that reads is exported to the Memory Controller 38b of No. 2 systems as No. 1 system that now uses machine.If the synchronizing signal RS that reads is input among the Memory Controller 38b, then to the memory 33b of identical No. 2 systems output read output signal R.On the other hand, the Memory Controller 38a of No. 1 system is also to memory 33a output read output signal R.If to memory 33a, 33b output read output signal R, then memory 33a, 33b export grouping (packet) data of TS1 signal, the grouped data of TS2 signal respectively respectively for Memory Controller 38a, 38b.At this, the identical CK that reads is provided for Memory Controller 38a, 38b from oscillator 39.Therefore, in the moment of exporting to Memory Controller 38b by Memory Controller 38a, after the clock pulse of memory 33a, 33b output predetermined number, from Memory Controller 38a, 38b output read output signal R from the synchronizing signal RS that reads.So, the output time of the read output signal R of Memory Controller 38a, 38b is just consistent.And the output time of the output time of grouped data and TS2 signal packets data is consistent in the TS1 signal.After this also identical, because according to input and output time of the synchronizing signal RS that reads, Memory Controller 38a, 38b export read output signal, so the output time of the output time of grouped data and TS2 signal packets data is consistent in the TS1 signal.That is to say, can satisfy above-mentioned (1).
The TS1 signal of exporting respectively from memory 33a, 33b, the transfer rate of TS2 signal decide according to the frequency of reading CK that offers Memory Controller 38a, 38b.The frequency of reading CK is big more, and transfer rate raises.Also have, the frequency setting of reading CK is undertaken by outside SW41.In this exemplifying embodiment, owing to provide the identical CK that reads from oscillator 39 for Memory Controller 38a, 38b, thereby, make it consistent by making the TS1 signal of exporting respectively from memory 33a, 33b, the transfer rate of TS2 signal for example become 15.1Mbps.That is to say, can satisfy above-mentioned (2).Also have, also the transfer rate of TS1 signal, TS2 signal for example can be made as 15.0Mbps.Moreover this exemplifying embodiment is big by making the frequency ratio of reading CK write CK (not shown), has improved transfer rate.For example the TS1 signal of importing respectively to memory 33a, 33b, the transfer rate of TS2 signal are 15.0Mbps, 14.9Mbps, relative therewith, will the 15.1Mbps bigger be made as the TS1 signal of exporting respectively from memory 33a, 33b, the transfer rate of TS2 signal than these values.Like this,, invalid data need be inserted in TS 1 signal, the TS2 signal, in order to avoid be stored in video data exhaustion among memory 33a, the 33b when improving transfer rate and make separately transfer rate consistent.
In this exemplifying embodiment, insert the NULL packets of information as invalid data.To produce when exhausted with interior at the fixed time less than scheduled volume at the video data that is contemplated to because of being stored among memory 33a, the 33b, Memory Controller 38a, 38b do not read the video data that is stored among memory 33a, the 33b.Replace, the NULL packets of information takes place from NULL storage part 35a, 35b.Then, the video data in being stored in memory 33a, 33b reaches scheduled volume when above, and Memory Controller 38a, 38b make stopping of NULL packets of information, and the video data that is stored among memory 33a, the 33b is read.Its result is, to PCR correction portion 36a, when 36b imports respectively TS1 signal, TS2 signal as shown in Figure 5, overlapping NULL packets of information.
Below, revise for PCR, adopt Fig. 2,4 to describe.So-called PCR is meant, be contained in TS1 signal, the TS2 signal time information as video sound packed data benchmark, and as shown in Figure 4, the packets of information that comprises PCR is to each predetermined information bag output.For example, when the data volume that has 42 data volume and 1 packets of information at PCR is 204 bytes, each predetermined information bag is exported packets of information behind the overlapping PCR.But, because TS1 signal, the TS2 signal of conversion behind the transfer rate export from memory 33a, 33b respectively, thus to the input of memory 33a, 33b the time moment with from the output of memory 33a, 33b the time different, therefore need revise PCR.PCR recapiulation 34a, 34b export to PCR correction portion 36a, 36b with inputing to the PCR that comprises in the TS1 signal, TS2 signal of memory 33a, 33b respectively. PCR correction portion 36a, 36b to from PCR recapiulation 34a, 34b the PCR that transmits respectively revise.The value of the PCR that PCR correction portion 36a, 36b import respectively according to the moment of importing TS1 signal, TS2 signal from memory 33a, 33b respectively, from PCR recapiulation 34a, 34b institute and the time of among memory 33a, 33b, storing TS1 signal, TS2 signal respectively, PCR is revised as video data.After the correction of having carried out PCR, TS1 signal, TS2 signal are input in the converter section 37.After one that selects by converter section 37 within TS 1 signal, the TS2 signal, convert signal aspect to serial from parallel by ASI driver 40, export.Also have, in converter section 37, when having imported switching signal, carry out existing conversion with machine and guest machine.
Below, for the change-over time of now using between machine and the guest machine, adopt Fig. 2,6 to describe.As mentioned above, operator (not shown) is operated, given converter section 37 input switching signals from operator by the user.But converter section 37 is not to carry out existing conversion with machine and guest machine in the time of input switching signal.For example, in Fig. 6, when moment tb input switching signal, on this time, export the packets of information 4 of TS1 signal, and export the NULL packets of information of TS2 signal from NULL35b from memory 33a.Thereby, on the time of moment tb, do not carry out existing conversion with machine and guest machine.On the disjunction place time of tc constantly just of the packets of information that moment tb occurs later at first, change.Also have, in disjunction place of the such packets of information of moment tc, read output signal R exports from Memory Controller 38a, 38b.And this read output signal R just is not input among memory 33a, the 33b, also inputs to converter section 37.Thereby, after giving converter section 37 input switching signals, when Memory Controller 38a, 38b are input to the converter section 37, carry out existing conversion with machine and guest machine at read output signal R.Owing on this time, change, thereby can carry out existing in disjunction place of each packets of information with the conversion between machine and the guest machine.
As mentioned above, mpeg stream generation systems according to this exemplifying embodiment, owing to can make transfer rate, the phase place of the TS1 signal exported respectively from each memory and TS2 signal consistent, even thereby conversion now also can will represent that the code output cycle that packets of information begins remains necessarily with machine and guest machine.Thereby, utilize the last TS signal transmission of the digital transmitter that is in mpeg stream generation systems rear portion can temporarily not stop.Also have, in the mpeg stream generation systems of this exemplifying embodiment, although understand the situation that improves transfer rate, but on the contrary when reducing transfer rate, can make TS1 signal, the transfer rate of TS2 signal, the phase place exported respectively from each memory consistent too.Also have, as described below when reducing transfer rate, in the TS1 signal of importing for each memory respectively, TS2 signal, necessarily there is the NULL packets of information, and as shown in Figure 3 NULL is deleted the front portion that the 42a of portion, 42b are arranged at memory 33a, 33b, this NULL deletion portion is used for deleting the NULL packets of information in TS1 signal, the TS2 signal.
Owing to make the amount that is stored in the video data in each memory along with the process of time constantly increases because of reducing transfer rate, thereby the amount of institute's video data stored reaches the memory capacity of each memory sooner or later.And, in memory capacity, do not have to reach memory capacity at once when vacant, and can not stored video data more than this, its result causes the action of mpeg stream generation systems to stop.Therefore, as shown in Figure 3, NULL is deleted the front portion that the 42a of portion, 42b are arranged at memory 33a, 33b, this NULL deletion portion is used for deleting the NULL packets of information that exists in the TS1 signal imported respectively to each memory, the TS2 signal.Its result is, because the such invalid data of NULLL grouped data is stored in each memory, thereby the amount that prevents institute's video data stored as far as possible reaches memory capacity the action of mpeg stream generation systems is stopped.
In this exemplifying embodiment, be that example is illustrated with the mpeg stream generation systems, but be not limited thereto.So long as have 2 chromacoders that more than the system vision signal carried out the signal processing part of digital compression processing with standby purpose, just same, even conversion now also can will represent that the code output cycle that packets of information begins remains necessarily with machine and guest machine.Thereby the transmission of last TS signal that is in the equipment at chromacoder rear portion can temporarily not stop.
Symbol description
11,12: encoder 13:TS conversion section
14: handling part 21,22: encoder
23: change-over switch 24: digital transmitter
31a, 31b:ASI receiver
32a, 32b: the initial code detection 33a of section, 33b: memory
34a, the 34b:PCR reproduction 35a of section, 35b:NULL storage part
36a, 36b:PCR correction portion 37: conversion section
38a, 38b: Memory Controller 39: vibration section
40:ASI driver 41: outside SW
42a, 42b:NULL deletion portion
Claims (5)
1. a chromacoder is used for the different a plurality of transmission signals of transfer rate are changed selection, it is characterized by,
Possess: transfer rate switching mechanism is used for changing the transfer rate of above-mentioned transmission signal; Phase control mechanism is used for controlling so that the phase place of this transfer rate switching mechanism output is consistent;
Above-mentioned transfer rate switching mechanism possesses: storage part is used for carrying out writing, reading of the video data that comprises in the above-mentioned transmission signal; The invalid data storage part is used for carrying out reading of invalid data; Control part is used for controlling, so that the transfer rate when above-mentioned video data is read is than writing under the fashionable high situation, the above-mentioned video data of being stored in above-mentioned storage part is read above-mentioned invalid data and replaced above-mentioned vision signal for less than scheduled volume the time.
2. chromacoder according to claim 1 is characterized by:
Above-mentioned storage part has existing usefulness and standby storage part, above-mentioned existing with and each of standby storage part possess the existing usefulness of reading of controlling above-mentioned video data, standby above-mentioned control part respectively, used control part is controlled standby control part as above-mentioned phase control mechanism, make from existing with and the phase place of the above-mentioned video data read of standby storage part consistent.
3. chromacoder according to claim 1 and 2 is characterized by:
Above-mentioned video data is made up of a plurality of packets of information with initial code, and the front portion at above-mentioned control part possesses the test section that is used for detecting above-mentioned initial code respectively, above-mentioned control part is a unit with above-mentioned packets of information, carry out writing, reading of above-mentioned video data in the above-mentioned storage part, and utilize the existing usefulness of converter section and standby conversion in disjunction place of above-mentioned packets of information.
4. chromacoder according to claim 1 and 2 is characterized by:
In the above-mentioned video data, possesses packets of information with time information, and possesses the time information correction portion, be used for memory time according to above-mentioned video data in the input time of the above-mentioned video data of above-mentioned storage part and above-mentioned storage part revising the time information that is overlapped in the above-mentioned packets of information.
5. chromacoder according to claim 3 is characterized by:
In the above-mentioned video data, possesses packets of information with time information, and possesses the time information correction portion, be used for memory time according to above-mentioned video data in the input time of the above-mentioned video data of above-mentioned storage part and above-mentioned storage part revising the time information that is overlapped in the above-mentioned packets of information.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004230510A JP4463040B2 (en) | 2004-08-06 | 2004-08-06 | Signal converter |
| JP230510/2004 | 2004-08-06 |
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| CN1731857A CN1731857A (en) | 2006-02-08 |
| CN1731857B true CN1731857B (en) | 2010-11-10 |
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| CN2005100911087A Expired - Fee Related CN1731857B (en) | 2004-08-06 | 2005-08-08 | Signal transformation device |
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| JP (1) | JP4463040B2 (en) |
| KR (1) | KR100722088B1 (en) |
| CN (1) | CN1731857B (en) |
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| JP4783724B2 (en) * | 2006-12-28 | 2011-09-28 | 日本放送協会 | TS switch for digital terrestrial broadcasting and method |
| JP5238653B2 (en) * | 2009-09-11 | 2013-07-17 | 株式会社東芝 | Server apparatus, program transmission system, and program transmission method |
| CN108449567B (en) * | 2018-03-23 | 2019-03-19 | 广州市奥威亚电子科技有限公司 | A kind of method and device being used for transmission digital video |
| CN109672923B (en) * | 2018-12-17 | 2021-07-02 | 龙迅半导体（合肥）股份有限公司 | Data processing method and device |
| JP6744038B1 (en) * | 2019-06-03 | 2020-08-19 | Ｎｅｃプラットフォームズ株式会社 | Broadcast signal transmitter, broadcast system seamless switching availability detection method, and broadcast system seamless switching availability detection program |
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| JP4311188B2 (en) * | 2003-12-12 | 2009-08-12 | ソニー株式会社 | Data recording apparatus, data transfer method, data transfer program and recording medium, and data transfer system |
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- 2004-08-06 JP JP2004230510A patent/JP4463040B2/en not_active Expired - Fee Related
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- 2005-08-05 KR KR20050071562A patent/KR100722088B1/en active IP Right Grant
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|---|---|---|---|---|
| CN85107392A (en) * | 1985-10-07 | 1987-04-15 | 日本电气株式会社 | The channel switching means that is used for the digital radio transmitting system |
| CN1036303A (en) * | 1987-11-10 | 1989-10-11 | 日本电气株式会社 | Channel switching system |
| US4984252A (en) * | 1987-11-10 | 1991-01-08 | Nec Corporation | Channel switching system |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100722088B1 (en) | 2007-05-25 |
| KR20060050229A (en) | 2006-05-19 |
| JP4463040B2 (en) | 2010-05-12 |
| CN1731857A (en) | 2006-02-08 |
| JP2006050389A (en) | 2006-02-16 |
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