CN1722175A - An Improved Method and Device for Stencil Shadow Cone Operation - Google Patents

Abstract

The present invention provides a shadow cone algorithm to improve the efficiency of shadow generation for use in a computer graphics system. In one embodiment, a method and apparatus are provided that utilize a combination of compressed and uncompressed stencil buffers, and are paired with compressed and uncompressed depth data buffers. An uncompressed stencil buffer may be used to store stencil shadow cone data for each pixel, and a compressed stencil buffer may be used to store stencil shadow cone data for a group of pixels. The compressed stencil buffer utilizes a high-speed cache to improve computational efficiency.

Description

An Improved Method and Device for Stencil Shadow Cone Operation

technical field

The invention relates to a computer drawing system, in particular to a method and a device for producing shadow effects using shadow cones.

Background technique

The so-called three-dimensional computer graphics is to generate and display three-dimensional objects as two-dimensional images on a flat screen. Three-dimensional objects can be very simple points, lines, triangles or polygons. More complex objects are represented by connected planar polygons, for example, a series of planar triangles assembled into a solid object. And all geometric elements can be described by one or a group of vertices. For example, coordinates (X, Y, Z) define a vertex or an end point of a line or a corner of a polygon.

In order to project a three-dimensional image on a two-dimensional screen, the vertex value needs to go through a series of operations or several programs in the graphics pipeline. A general graphics pipeline is simply a chain of connected processing units or programs, where the output of the previous program is the input to the next program. In a graphics processor, these programs include individual vertex operations, basic combination operations, pixel operations, texture combination operations, bitmap transformation operations, and fragment operations.

In a typical graphical display system, an image database (eg, a command list) may store descriptions of objects in a scene. These objects are described by several small polygons. Similarly, the object surface can be described by several small tiles. Each polygon has a series of vertex coordinates (module coordinates X, Y, Z) and some material surface properties (such as color, material, gloss, etc.), or even the normal vector of each vertex surface. For three-dimensional objects with complex surfaces, polygons must generally be triangles or quadrilaterals, where the latter can be broken down into a pair of triangles.

A transformation engine switches the coordinates of the object according to the viewing angle input by the user. In addition, the user can specify the field of view, image size, or back end of the frustum to include or exclude the background.

Once the view area is selected, a clipping logic circuit eliminates polygons (triangles) outside the view area and clips those polygons that are partially outside and partially inside. The new edges of the clipped polygons are the edges of the view area. These polygon vertices are then sent to the next stage, corresponding to screen coordinates (X, Y), each vertex has a corresponding depth value (Z coordinate). In a typical system, the light source is then calculated with the light source module, and the color values of these polygons are passed to a bitmap converter.

For each polygon, the bitmap converter determines at which pixel to place the polygon and attempts to write the corresponding color and depth (Z-value) to the frame buffer. The bitmap converter compares the polygon's depth value with the depth value of the pixel that may have been written to the frame buffer. If the depth value of the new polygon is smaller, it means that it is located in front of the previously written pixel, so the value at that position in the frame buffer is replaced. This process continues until all polygons have passed through the raster converter. So far, the graphics controller displays the contents of the frame buffer on the display, and displays them row by row according to scan lines.

FIG. 1 is a flow chart of an operation of an existing graphics pipeline. The components in the graphics pipeline can vary from system to system and can be expressed in various ways. A host computer 10 (or a graphics application program interface executed on the computer) generates a command sequence 12, including a series of graphics commands and data, for creating an "environment" on a graphics display. Components in the graphics pipeline operate on the data and instructions in the command sequence 12 to generate images on the display.

A decoder 14 intercepts data from the command line 12 to interpret commands and transmit raw graphics data along the graphics pipeline. Raw drawing data contains position (X, Y, Z and W coordinates), as well as light source and material information. After these original drawing data are read from the command sequence 12 by the decoder 14, they are sent to a vertex converter 16 (vertex shader). The vertex converter 16 executes various conversion programs on the original drawing data. These data must be converted from world coordinates to module view coordinates, projected coordinates, and finally to screen coordinates. The functions in this vertex converter 16 are known in the art. Then the drawing data is sent to the dot matrix converter 18 for dot matrix conversion.

A depth tester 20 then processes each pixel in the raw data, comparing the stored and newly input depth values corresponding to a pixel. The depth value is used to represent the depth value of the pixel position. If the newly input depth value represents a depth closer to the viewer, the stored depth value is replaced, and the associated color information in the graphics buffer 24 is also replaced (processed by the pixel converter 22). On the contrary, if the new depth value is farther, there is no processing. The color information includes whether the pixel is in the shadow, and the method of judging it uses the existing shadow cone algorithm.

Figure 2 is a schematic diagram of the shadow cone algorithm. The shadow cone 34 (shadow volume) defines a shadow space of an obstacle 32 (occluder) under a light source 30 . If a pixel 38 falls within the shadow cone 34, the resulting image appears to be in shadow. The shadow cone algorithm determines whether a pixel 38 , 39 is within the shadow cone 34 , and counts the number of times the ray 35 and the viewer 36 enter point 33 and exit point 37 . If the number of times entering point 33 and leaving point 37 is equal then it is not in the shadow. For example, ray 35 from observer 36 to pixel 38 has one entry point 33 and no exit point 37 . Thus, pixel 38 is in shadow. Likewise, ray 31 from observer 36 enters point 33 once and exits point 37 once before reaching pixel 39, so pixel 39 is not in shadow.

Raytracing can be quite time consuming, especially with multiple blocks and multiple light sources. The stencil shadow cone algorithm simplifies the calculation procedure, and only uses a stencil buffer (stencil buffer) to perform simple input and output operations, also known as the second-level stencil buffer or SL2. The stencil buffer, SL2, stores and executes per-pixel data to generate various functions including stencil shadow cone algorithms. Whether a pixel is in shadow can be determined by performing a depth test (Z-test) on the front and back planes (relative to the viewer or deepest plane) on a shadow cone polygon. For example, if the front plane passes the Z-test, the stencil buffer value is accumulated, and if the back plane passes the Z-test, the stencil buffer value is decremented. So if the final stencil value is zero, the pixel is not in shadow.

Figure 3 is a flowchart for the template shadow cone algorithm. Step 40, initialize and clear the stencil buffer, and step 42, generate a scene with diffuse color. In step 43, data is provided to a color buffer and a depth buffer (also called Z-buffer). In step 44, the depth buffer and color buffer updates are turned off except that the stencil values are left in the depth buffer. In step 46, for each ray, a stencil value is generated for each obstacle, and the front facing polygon of each stencil value is delineated. Step 47, accumulating the stencil buffer value for each pixel on which the polygonal front plane is drawn. In step 48, the same step is performed for each polygonal backplane. In step 49, for each pixel on which the polygonal backplane is drawn, the stencil buffer value is accumulated. These accumulation and subtraction steps are called the template shadow cone procedure. In step 50, objects with non-zero stencil values are positioned in the shadow and drawn accordingly. Step 52, the object with the template value of zero is not in the shadow, so it is drawn with specular color. This step is also known as the specular shading procedure. As shown in FIG. 1 , after the pixel converter 22 calculates the color information, it stores it in the display buffer 24 (framebuffer).

As shown in FIG. 2, the stencil buffer value of the pixel 38 is accumulated once, because the number of times of entering the front plane of the shadow cone polygon at point 33 is one, and the stencil buffer value has not been accumulated because it has not passed through any shadow cone polygon back plane. The stencil buffer value for pixel 38 is then non-zero. Similarly, when pixel 39 enters point 33, the stencil buffer value increases by one, and when it leaves point 37, the stencil buffer value decreases by one. Therefore, it is drawn with the mirror color when drawing. This example only includes a single obstacle and a single light source, but the shadow cone algorithm of this template can be applied to occasions with multiple obstacles and multiple light sources.

FIG. 4 is an existing compressed depth data (Z-data) processing unit, also called ZL1. Using ZL1 to process the depth data of one block or one tile can improve system performance. The depth data of some pixels in the tile exceeds the range of the ZL1 compression format and needs to be processed by another pixel depth data processing unit (also called ZL2).

ZL1 and ZL2 generally represent a first-level depth buffer and a second-level depth buffer. This type of algorithm has various names, such as Hyper Z and Heirarchy Z Buffer. The two-level depth buffer can store higher-level depth information for larger processing units and smallest grains, such as a tile, or a pixel on the screen. One of the benefits of ZL1 is that it reduces the complexity of calculating depth data in the rendering pipeline.

A tile generator 60 generates tile data for a tile composed of a plurality of pixels, such as eight times eight, and sends a request to a ZL1 cache 64 . The tile data is sent to a compressed depth data processing unit ( ZL1 ) 62 . The ZL1 62 also communicates with the ZL1 cache 64. For pixels whose depth data cannot be processed by ZL1 62, it is processed by pixel depth data processing unit (ZL2) 66 with ZL2 cache 68. In this example, the ZL1 62 can reject up to 64 pixels in one cycle, and the pixels that are not rejected are marked with "accept" or "retry" to reduce the traffic of the ZL2 66.

Although ZL1 62 reduces the memory read traffic of ZL2 66, it is not very efficient for solving template operations. When performing stencil operations, ZL1 62 marks all pixels as "retry" to ensure that each stencil operation will not be missed. Rejected pixels will also issue stencil operation requests to the ZL2 66. Therefore, during the template operation, the ZL1 62 must consume a large amount of traffic to filter out the result.

This phenomenon is especially evident when a ZL1 tile (sub-tile) is accepted or rejected after a depth comparison (Z-compare) function. Because even if the sub-tile passes the Z-test, the template calculation is still going on, ZL1 62 must switch the sub-tile from the accept state to the retry state and send it to ZL2 66. At this time, the ZL2 66 is combined with the stencil buffer SL2, so that the ZL2/SL2 processing unit is 32 bits, including a 24-bit depth value and an 8-bit stencil value. In the Accept and Reject states, the entire 32-bit depth/stencil value must be read in full for the 8-bit stencil value. Resulting in extremely poor memory flow efficiency. One solution is to use separate stencil and depth buffers, keeping memory requirements to a minimum. For example, for eight pixels, the memory requirement for a pixel with an 8-bit template value is only 64 bits, resulting in a large waste of memory traffic.

Contents of the invention

An embodiment of the present invention provides a computer graphics device to improve the performance of stencil shadow volume operation. The computer graphics device includes a compressed stencil buffer and a compressed stencil buffer cache. Wherein the stencil buffer contains a compressed stencil shadow cone record corresponding to a group of pixels. The compressed stencil shadow cone record includes a tile reference stencil value. The group of pixels includes a tile, and the tile includes a plurality of sub-tiles, and each sub-tile includes a plurality of blocks. The compressed template shadow cone record further includes a plurality of block reference values, corresponding to each block. The compressed template shadow cone record further includes a plurality of pixel delta values, and each pixel delta value corresponds to a pixel in the tile. The compressed template shadow cone record further includes a plurality of subtile dirty bits, and each subtile dirty bit corresponds to a subtile in the tile. A pixel template value includes one of the sub-tile modification flag bits, the tile reference template value, one of the block reference values, and one of the pixel-level difference values.

Another embodiment of the present invention provides a graphics system including a first stencil buffer for a stencil shadow cone operation of a set of pixels, wherein the set of pixels includes a tile. The first stencil buffer is further used to calculate a stencil for a pixel in the set of pixels. The graphics system also includes a graphics processor for generating a shadow effect, wherein the shadow effect is generated by the template shadow cone operation, and the graphics processor stores a tile template record in the first template buffer. The graphics system further includes a first stencil buffer cache coupled to the first stencil buffer. The graphics system further includes a first depth buffer for storing a tile depth record. The graphics system further includes a second depth buffer for storing a pixel depth record, and a second stencil buffer for storing a pixel stencil record. Wherein the second depth buffer is combined with the second stencil buffer, and the pixel stencil record is combined with the pixel depth record. The drawing system further comprises a plurality of subtiles comprising the tile, and a plurality of blocks comprising one of the subtiles. Wherein the tile template record further includes a tile reference template value, a plurality of block template values, each corresponding to one of these blocks, a plurality of pixel-level difference values, each corresponding to a pixel in the tile, and Multiple sub-tile values, each corresponding to one of the multiple sub-tiles in the tile.

Another embodiment of the present invention provides a drawing method for computing template shadow cones, including the following steps. First, a tile template shadow record, a pixel template shadow record, and a tile triangle value are generated. Finally, a template shadow cone operation is performed using the tile template shadow record and the pixel template shadow record. The pixels include a block, the blocks include a sub-tile, the sub-tiles include a tile, and the tile template shadow record includes template data for each block.

Another embodiment of the present invention provides a shadow generation method for a computer graphics system, comprising the following steps. First, a sub-tile is obtained for compression, and the sub-tile is associated with a compressed depth data buffer. The sub-tile is then optionally flushed to a pixel depth data/stencil buffer, the sub-tile is uncompressed in a compressed stencil buffer. Finally, the stencil shadow cone operation is performed in a compressed stencil buffer. The step of obtaining the sub-tile further detects a state of a sub-tile. The sub-tile status includes "retry", "reject" and "accept".

Another embodiment of the present invention provides a drawing method for a computer graphics system to merge compressed stencil data into a pixel stencil buffer during stencil shadow cone operation, including the following steps. Firstly, it is judged that a sub-tile satisfies a first condition or a second condition, wherein the first condition includes sub-tile underflow, and the second condition includes sub-tile overflow. When one of the first condition or the second condition is met, change the state of a sub-tile from "accept" to "retry". A sub-tile merge mask is then set to validate the compressed stencil data in a compressed stencil buffer for flushing to a pixel stencil buffer. The compressed stencil data is then merged into the pixel stencil buffer, thereby generating a result that is the sum of the compressed stencil data and the stencil data of the pixel stencil buffer. Finally, a sub-tile modification flag bit in the compressed template buffer is reset to zero, and the compressed template value in the compressed template buffer is cleared.

Description of drawings

Figure 1 is a block diagram of an existing drawing pipeline;

Fig. 2 is the two-dimensional representation diagram of existing shadow cone;

Fig. 3 is the block diagram of existing template shadow cone operation;

FIG. 4 is a block diagram of an existing compressed z-buffer;

Fig. 5 is a drawing system of an embodiment of the present invention;

Fig. 6 is the tile format used in the embodiment of the present invention;

Fig. 7 is a compressed template buffer data format according to an embodiment of the present invention;

FIG. 8 is a ZL1 sub-tile state detection logic circuit according to an embodiment of the present invention;

FIG. 9 is an embodiment of the compressed stencil buffer operation of the present invention;

Fig. 10 is the SL1 pretreatment step of the embodiment of the present invention;

Fig. 11 is the SL1 accumulative operation of the embodiment of the present invention;

Fig. 12 is the SL1 cumulative subtraction operation of the embodiment of the present invention;

Fig. 13 is the template shadow cone program merging operation of the embodiment of the present invention;

Fig. 14 is a spherical color merging operation according to an embodiment of the present invention;

FIG. 15 is a compressed stencil buffer merging operation according to an embodiment of the present invention; and

FIG. 16 shows the compressed stencil buffer in the stencil shadow cone operation of the embodiment of the present invention.

Description of reference symbols

10～Computer host 12～Command serial

14~decoder 16~vertex converter

18～dot matrix converter 20～depth tester

22～pixel converter 24～drawing buffer

30～light source 35～light

31～light 32～obstacles

34～Shadow Cone 38～Pixels

39 ~ pixel 33 ~ entry point

37～Leaving Point 60～Tile Generator

62～compressed depth data processing unit ZL1

64 ~ ZL1 cache

66～Pixel depth data processing unit ZL2

68 ~ ZL2 cache

500～computer drawing device 510～graphic processor

511～cache 512～cache

514～high-speed cache 516～logic circuit

520～memory 530～depth buffer

540～stencil buffer 550～single buffer

560～compressed depth buffer ZL1 562～depth data

570 ~ compressed stencil buffer SL1 572 ~ stencil value

610～tiles 620～subtiles

630～blocks 640～pixels

700～data record format 710～8 reference value

720～3 reference values 730～1 triangle value

740 ~ 1 modified flag bit

Detailed ways

FIG. 5 is a basic architecture diagram of an embodiment of the present invention. A computer graphics device 500 includes a graphics processor 510 and a memory 520 . The memory 520 can also be a system or main memory, used together with the graphics processor 510 . Specific addresses in the memory 520 are used as the depth buffer 530 and the stencil buffer 540 . The depth buffer 530 and stencil buffer 540 data structures can also be combined into a single buffer 550 . For example, the data record is 32 bits, of which 24 bits are the depth value and 8 bits are the template value. The single buffer 550 stores a record for each pixel.

There is another specific address in the memory 520 as a compressed depth buffer ZL1 560 for storing depth data (Z-data) 562 of a group of pixels. The set of pixels can be a tile, a sub-tile or multiple tiles. In addition, the memory 520 includes a compressed stencil buffer SL1 570 for storing stencil values 572 in pixels of a tile. The pixels in a tile can be 8 by 8, 8 by 16 or other ratios, depending on the required performance.

In the graphics processor 510, a cache 512 is included as the compressed stencil buffer SL1 570, and a cache 511 is used for the compressed depth buffer ZL1 560, each for storing the compressed depth buffer ZL1 560 and the compressed stencil buffer SL1 570 record. GPU 510 also includes a cache 514 for storing single buffer 550 records. These caches 512, 511 and 514 are also referred to as SL1, Z11 and ZL2/SL2. Graphics processor 510 further includes logic circuitry 516 for controlling compressed depth buffer ZL1 560, compressed stencil buffer SL1 570, depth buffer 530, and stencil buffer 540 during stencil shadow cone operations. The logic circuit 516 may also perform compression of depth and stencil shadow data. The logic circuit 516 can further generate uncompressed template shadow data 542 . In addition, the logic circuitry 516 may optionally merge stencil values 572 and uncompressed stencil shadow data 542 associated with compressed stencil buffer SL1 570 and stencil buffer 540.

FIG. 6 is an embodiment of a tile format. The tile 610 includes 64 pixels 640 arranged in an 8 by 8 pattern. The tile 610 is also divided into four sub-tiles 620, each containing 8 by 2 pixels. The tile 610 can be further divided into 16 blocks 630, each containing 2 by 2 pixels.

FIG. 7 is an embodiment of the data record format for the compressed stencil buffer SL1 570. Stencil values 572 in compressed stencil buffer SL1 570 contain records for each tile 610, corresponding to each tile in compressed depth buffer ZL1 560. The data record format 700 represents an 8 by 8 tile 610 divided into four 8 by 2 sub-tiles 620 . The tile 610 is further divided into sixteen 2 by 2 blocks 630 . The data record format 700 includes an 8-bit reference value 710 for the tile, a 3-bit reference value 720 for the 16 blocks 630, and 1-bit triangular value 730 for every 64 pixels, and 1 bit for modification Flag bits 740 are used for each subtile.

The block data is represented by a 4-bit nibble and a 3-bit carry. Each of the 4 bits represents a pixel delta value of each pixel in the block. The 3-bit carry bit represents the reference value of the block. This data format is based on the fact that for a statistically certain proportion of pixels, the difference in template values between two adjacent pixels is usually not greater than one. Although the template value difference between two adjacent pixels cannot be greater than 1 in SL1, the pixels using the following encoding methods can achieve a dynamic range of -4 to +4.

Table 1 block reference value Pixel level difference = 0 Pixel level difference = 1 000 -4 -3 001 -3 -2 010 -2 -1 011 -1 0 100 0 +1 101 +1 +2 110 +2 +3 111 +3 +4

FIG. 8 is an embodiment of a logic circuit for detecting sub-tile status in ZL1. In step 800 the D_Mask bit value of the sub-tile is checked. The D_Mask is a bit in the ZL1 record, used to indicate whether the sub-tile needs to be drawn. In step 810, if the value of the D_Mask is zero, skip to step 860, and set the status of the sub-tile as rejected. Otherwise, jump to step 820 to check the T_Mask value of the sub-tile. In step 830, if the value of the T_Mask is 0, skip to step 850, and set the state of the sub-tile as accepted. On the contrary, if the value of the T_Mask is 1, skip to step 840, and set the state of the sub-tile to retry. These states are used to determine whether the sub-tile is suitable for SL1 operation.

Fig. 9 is one embodiment of the present invention. Among them, the compressed stencil buffer in the stencil shadow cone operation, SL1 may have many different implementation methods, and the spirit of the present invention is not limited thereto. In step 912, after judging the state of the sub-tile depth data as "retry", "accept" and "reject", it is judged whether the sub-tile needs to be processed by SL1. In step 914, if the sub-tile is a retry, it means that the sub-tile is not suitable for SL1 processing, and the step skips to 930, and SL2 performs pixel or block level processing. On the contrary, if the status is "Reject" or "Accept", it is determined that it is suitable for SL1 processing, and jumps to step 916 to determine whether the sub-tile information can be compressed. The judgment principle is to check whether SL1 is enough to accommodate the sub-tile data. If it cannot be compressed, skip to step 918 and clear the sub-tile template data to SL2. If the sub-tile data can be compressed into SL1 according to the SL1 data record format, in step 941 , a template operation is performed on the sub-tile in SL1.

In step 940, when the template operation is performed on the sub-tile in SL1, an SL1 processor 920 sends an SL1 request to the SL1 cache 922, and puts the cached information of the template record of the sub-tile into the SL1 FIFO 924 in the stack. The SL1 calculator 926 performs accumulation and subtraction operations of the template shadow cone algorithm, and merges the compressed data to the SL2 930. In addition, the SL1 calculator 926 checks the overflow or underfill status of the template data records to avoid data errors.

Figure 10 is an example of a preprocessor for SL1. In step 1010, the subtiles in ZL1 are known to have accepted or rejected status and require SL1 records. In step 1020, a cache hit test is performed on the SL1 cache, and the SL1 entry point is stored in a FIFO stack to compensate for memory access latency. In step 1030, if the result of the cache hit test is a miss, then in step 1040 an SL1 memory request is generated. Step 1050, SL1 enters the stack.

Fig. 11 is an embodiment of accumulation operation in SL1. In step 1110, it is judged according to the format of the template data record whether the tile reference value is at the maximum value. If yes, in step 1120, the SL1 clears the stencil data of the entire tile to SL2 so that the stencil operation can be performed at a pixel level. If not, in step 1140, it is determined whether each tile has an "accepted" status. If each tile is accepted, then in step 1130, the tile reference value is accumulated to complete the accumulation operation procedure. If not all are accepting, then in step 1150, check the overflow status of each block. If the pixels in any block are in the overflow state, the block is in the overflow state. In step 1160, if no pixel in the block overflows, then the sub-tile is accumulated. In step 1170, if the template data of any sub-tile has overflow status, it is cleared to SL2 for template operation. For example, operations at the pixel level may be performed on a block or other logic circuit pixel group.

Consider the accumulation operation of a sub-tile in the compressed template buffer record, the tile reference value is between the minimum and the maximum value, and the tile is cut into four sub-tiles, A, B, C and D. Assume that sub-tile C does not have an accept state because at least one of its 16 blocks is too few, while the other blocks in the tile do not have too few states. Assume further that subtile D does not have an accept state because at least one of its 16 blocks overflows, while no other blocks in the tile overflow. Factor tiles A, B and C do not have overflow blocks, and the block reference values corresponding to these blocks are accumulated. If the factor tile D is not accumulated, the stencil values of all pixels in the sub-tile D are cleared to the pixel stencil buffer.

FIG. 12 is an SL1 accumulation operation of one embodiment of the present invention. In step 1210, it is determined whether the tile reference value is at the minimum value according to the format of the template data record. If the tile reference value is the minimum value, then in step 1220, SL1 clears the template data of the entire tile to SL2. If the tile reference value is not the minimum value, then in step 1240, it is checked whether each sub-tile in the tile has accept status. If the tile is completely accepted, in step 1230, the tile reference value is accumulated to complete the accumulation operation. If the tile is not fully accepted, then skip to step 1250 to check for too little state. If any of the pixels in the block are in the low state, the block is in the low state. If no block is too small, then go to step 1260 to accumulate the sub-tiles. In step 1270, any sub-tiles with too few state blocks are flushed to SL2.

The accumulation operation is considered with the compressed stencil buffer records in the above embodiments. Factor tiles A, B and D do not have any overflow blocks, and the block reference values in all blocks in the sub-tiles are accumulated. The sub-tile C cannot be accumulated because a block reference value is too small, and the stencil values of all pixels in the sub-tile C are cleared to the pixel stencil buffer. If all sub-tiles in the above-mentioned tile have an accepting state, the tile reference value is changed according to the corresponding accumulation and accumulation operations.

As mentioned above, when a sub-tile modification flag is set in SL1, the SL1 data is merged into SL2. The merge operation finds the final distribution of the template values in SL1 and SL2. The merging operation can be performed in the stencil shadow cone program or in the specular shader program. In the shadow cone program of the template, as shown in FIG. 13 , step 1310 is to determine whether the sub-tile is overflowing or too small. In step 1320, if the determination result is true, the sub-tile state is changed to retry. In addition, in step 1330, an SM_Mask is generated for merging data from SL1 and SL2. The SM_Mask is an additional mask output by SL1 to indicate whether SL1 and SL2 are to be merged. The final value, ie SL1+SL2, is written to SL2 in step 1340 . In step 1350, if the data has been merged into SL2, the SL1 sub-tile modification flag bit is reset to zero to represent that the sub-tile has been cleaned, and in step 1360, the sub-tile template value clear. The dynamic merging method reduces the probability of each sub-tile being overfilled and underfilled.

FIG. 14 is an embodiment of a specular shading program, a bit in ZL1 controls the triggering mechanism of the merge operation of SL1 and SL2. Step 1410, start. Step 1420, check whether the SL1 tile modification flag in ZL1 is set, and step 1430, check whether the SL1 sub-tile modification flag is set. If the answers to the above steps are all affirmative, set SM_Mask in step 1440 to notify ZL2 to combine SL1 and SL2. Then in step 1450, SL1 and SL2 are merged before template comparison, and finally in step 1460, the sum of SL1 and SL2 is written into SL2.

The combination of SL1 and S12 is indicated by the setting of the SM_Mask bit. Figure 15 is an example of a general merge procedure. In step 1510, the value of the SM_Mask is read from SL1. In step 1530, if the value of the SM_Mask is zero, skip to step 1520 and nothing happens. Conversely, if the value of SM_Mask is one, then in step 1540, the sum of SL1 and SL2 is generated, and in step 1550 the final value is written into SL2.

FIG. 16 represents an embodiment of compressing the stencil buffer during the operation of the stencil shadow cone of the present invention. In step 1610, a tile template shadow record is generated corresponding to a tile, wherein the tile is further divided into a plurality of sub-tiles, wherein the sub-tile is further divided into a plurality of blocks, including several pixels. In addition, in step 1620, a pixel template shadow record is generated in conjunction with the tile template shadow record to accommodate the template shadow value of each pixel. The pixel template shadow record is necessary in case the sub-tile template data exceeds the capacity of the tile template shadow record. In addition, in step 1630, a tile depth record is generated corresponding to the depth data of the pixels in the shadow record of the tile template. In step 1640, template shadow cone operations are performed using the tile template shadow records as much as possible. If the tile template shadow record cannot accommodate the template shadow operation, the operation is performed at the pixel level using the pixel template shadow record.

The examples provided above have highlighted many features of the present invention. Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. .

Claims (26)

1. a computer graphics unit comprises:

One compression stencil buffer; And

One compression stencil buffer high-speed cache;

Wherein, this compression stencil buffer comprises a compression template shadow awl record of one group of pixel.

2. device as claimed in claim 1, wherein:

This compression template shadow awl record comprises a tile reference template value;

This group pixel comprises a tile;

This tile comprises a plurality of sub-tiles; And

Each sub-tile comprises a plurality of blocks.

3. device as claimed in claim 2, wherein:

This compression template shadow awl record further comprises a plurality of block reference values, and it corresponds respectively to each block; And

The record of this compression template shadow awl further comprises a plurality of pixel triangle values, in this Pixel-level difference to the pixel in should tile.

4. device as claimed in claim 3, wherein:

The record of this compression template shadow awl further comprises a plurality of sub-tiles and revises marker bits, and each sub-tile is revised marker bit to the sub-tile in should tile at this;

One template pixel value comprises:

This a little tile revise marker bit one of them;

This tile reference template value;

These block reference values one of them; And

These Pixel-level differences one of them.

5. a drafting system comprises:

One first stencil buffer is used for a template shadow awl computing of one group of pixel, and wherein this group pixel comprises a tile, and this first stencil buffer further is used for a kind of template computing of a pixel, and this pixel is one of in this group pixel;

One painting processor, in order to produce a hatching effect, wherein, this hatching effect is to produce by this template shadow awl computing;

The logical circuit of one painting processor is in order to store tile template record in this first stencil buffer; And

One first stencil buffer high-speed cache, it is in order to communicate by letter with first stencil buffer.

6. system as claimed in claim 5 further comprises:

One first depth buffer is in order to store tile degree of depth record.

One second depth buffer is in order to store pixel depth record; And

One second stencil buffer is in order to store template pixel record, wherein

This second depth buffer and this second stencil buffer combination, this template pixel record and this pixel depth record combination.

7. system as claimed in claim 6 more comprises:

A plurality of sub-tiles are corresponding to this tile; And

A plurality of blocks, corresponding to this a little tile one of them; Wherein

This tile template record further comprises:

One tile reference template value;

A plurality of block stencil values, respectively corresponding these blocks one of them;

A plurality of Pixel-level differences are respectively to the pixel in should tile; And

A plurality of sub-tile values, each to a plurality of sub-tiles in should tile one of them.

8. system as claimed in claim 7 further comprises dynamic removing logical circuit, and in order to tile template record is optionally cleaned to this second stencil buffer, wherein, this tile template record there is no compression in this first stencil buffer.

9. the method for a template shadow awl computing is used for the counter drafting system, comprises:

Produce tile template shade record;

Produce template pixel shade record;

Produce a tile depth value record; And

Carry out the computing of template shadow awl, wherein this template shadow awl computing utilizes this tile template shade record, and this template shadow awl computing also utilizes this template pixel shade record.

10. method as claimed in claim 9, wherein:

A plurality of pixels are corresponding to a block;

A plurality of blocks are corresponding to a sub-tile;

A plurality of sub-tiles are corresponding to a tile; And

This tile template shade record comprises the template data of each block.

11. method as claimed in claim 10 further comprises:

The record of one tile template shade is optionally cleaned to a template pixel impact damper;

The template data of each sub-tile in the described tile;

The template data of each pixel in this tile; And

One tile reference value.

A 12. drafting system, comprise a template shadow awl arithmetical unit, in order to calculate the template shadow awl of a plurality of pixel groups, wherein these pixel groups comprise one first group of pixel, this first group of pixel comprises a plurality of pixels of one first quantity, these pixel groups also comprise one second group of pixel, and this second group of pixel comprises a plurality of pixels of one second quantity, and this first quantity is greater than this second quantity.

13. system as claimed in claim 12 further comprises a single template shadow awl arithmetical unit, in order to single pixel is done the computing of template shadow awl; Wherein this single pixel is to be selected from this first group of pixel or this second group of pixel.

14. a shadow production method is used for a computer plotting system, comprises:

Try to achieve a sub-tile, be used for compression, this sub-tile is associated with a compression depth data buffer;

Optionally should clean to a pixel depth data/stencil buffer by sub-tile, this sub-tile there is no compression in a compression stencil buffer; And

In a compression stencil buffer, carry out the computing of template shadow awl.

15. method as claimed in claim 14, wherein, this step of trying to achieve sub-tile further comprises the sub-tile state of detection; Wherein this sub-tile state comprises " retry ", " refusal " and " acceptance ".

16. method as claimed in claim 15, wherein:

Be " refusal " if the cleaning step further comprises this sub-tile state, then should clean to this pixel depth data/stencil buffer by sub-tile;

The step that detects this sub-tile state further comprises:

Read one first masking value, wherein, if this first masking value is one, then this sub-tile state is " refusal "; And

Read a secondary shielding value, wherein, if this secondary shielding value is one, then this sub-tile state is " retry "; And

If this secondary shielding value is zero, then this sub-tile state is " acceptance ".

17. method as claimed in claim 16, wherein, this is tried to achieve step and further comprises and judge whether this sub-tile template data is the step of a compressible form.

18. method as claimed in claim 17, wherein, this step of cleaning sub-tile comprises:

When being " refusal ", cleans this sub-tile state this sub-tile; And

When this sub-tile template data is incompressible, clean this sub-tile.

19. method as claimed in claim 18, wherein, this step of carrying out the computing of template shadow awl comprises:

This sub-tile template data of pre-service; At this, and send a requirement to a compression stencil buffer high-speed cache; And the data storing that will compress the stencil buffer high-speed cache is compressed in the stencil buffer in a first in first out.

20. method as claimed in claim 19, wherein, this step of carrying out the computing of template shadow awl further comprises:

A compression template record optionally adds up; Wherein

If a tile reference value is a maximal value, then this compression template record does not add up.

21. method as claimed in claim 20 further comprises:

If each sub-tile state is " acceptance " in the tile, this tile reference value then adds up;

If any one sub-tile state is " refusal " in this tile, then check the whether spill-over of each block in this sub-tile; And

If no any block spill-over in this sub-tile, sub-tile reference value then adds up.

22. method as claimed in claim 21, wherein, this step of carrying out the computing of template shadow awl further comprises the optionally tired compression template record that subtracts; Wherein, if a tile reference value is a minimum value, then this compression template record is not tired subtracts.

23. method as claimed in claim 22 further comprises:

If each sub-tile state is " acceptance " in the tile, then tired this tile reference value that subtracts;

If arbitrary sub-tile state is " refusal " in this tile, check then whether each block is low excessively in this sub-tile; And

If no any block is low excessively in this sub-tile, then tiredly subtract sub-tile reference value.

24. a method that merges compression template data to template pixel impact damper when the computing of template shadow awl is used for computer plotting system, this method comprises:

Judge that whether a sub-tile satisfies a first condition or a second condition, wherein to comprise sub-tile low excessively for this first condition, and this second condition comprises sub-tile spill-over;

When one of them meets when this first condition or second condition, a sub-tile state is changed into " retry " from " acceptance ";

Set a sub-tile and merge shielding, in order to confirm the compression template data in a compression stencil buffer, to clean to a template pixel impact damper;

Merge this compression template data to this template pixel impact damper, produce a result by this, be the template data summation of this compression template data and this template pixel impact damper;

Sub-tile in this compression stencil buffer of resetting is revised marker bit, and making its value is zero; And

Remove the compression stencil value in this compression stencil buffer.

25. method as claimed in claim 24, wherein, this combining step comprises:

From this compression template data, read this sub-tile and merge shielding;

If it is zero that this sub-tile merges shielding, then ignore this compression template data; And

If it is one that this sub-tile merges shielding, then merge this compression template data to this template pixel impact damper.

26. a method that merges compression template data to template pixel impact damper when the computing of minute surface color is used for computer plotting system, comprises:

Reading a tile and revise marker bit, is zero if this tile is revised marker bit, does not then carry out union operation;

Reading a sub-tile and revise marker bit, is zero if this sub-tile is revised marker bit, does not then carry out union operation;

Set a sub-tile and merge shielding,, and cleaned in order to affirmation compression template data;

Merge this compression template data and template pixel data; And

The summation of this compression template data and template pixel data is write this template pixel impact damper.

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