CN1713495A - Driving circuit for DC/DC converter voltage and level transferring method - Google Patents
Driving circuit for DC/DC converter voltage and level transferring method Download PDFInfo
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- CN1713495A CN1713495A CN 200410061842 CN200410061842A CN1713495A CN 1713495 A CN1713495 A CN 1713495A CN 200410061842 CN200410061842 CN 200410061842 CN 200410061842 A CN200410061842 A CN 200410061842A CN 1713495 A CN1713495 A CN 1713495A
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Abstract
The driving circuit consists of an input end used to receive PWM signal, a first output end connecting to main switch and used to output a low side driving signal, a second output end connecting to the active switch and used to output a high end driving signal, a first branch composed of a voltage level transition capacitor and first buffer that are connected between the input end and second output end, and a second branch composed of a delay circuit and second buffer that are connected between the input end and the first output end. When the PWM signal is raised from a low potential to a high potential, the voltage level transition capacitor transfers the PWM signal to first buffer in order to shut down the active switch, and then, after a time delay, triggers the second buffer in order to turn on main switch.
Description
Technical field
The present invention relates to power system, particularly relate to a kind of drive circuit and voltage level transfer method thereof that is used for DC-DC converter.
Background technology
The transducer of one high-end (high-side) and low side (low-side) has been widely used in the driving of the switch brachium pontis (switch bridge) of bridge converter, the feedforward of for example active (active) clamp transducer, semi-bridge convertor and full-bridge converters etc.Fig. 1 is the circuit diagram with traditional active-clamp feedforward transducer of a drive IC, in the figure, low-end switch S1 (main switch) is disposed at the primary side of transformer T, and an active-clamp branch is connected in parallel in the first siding ring of transformer T, this active-clamp branch by a high-end switch (active switch) S2 and a clamping capacitance C11 be connected in series constitute, wherein low-end switch S1 and high-end switch S2 running complimentary to one another to be forming a switch brachium pontis, and a high-end and low side drive IC 1 is in order to drive this switch brachium pontis.
At present, high-side driver and low-end driver usually being integrated on chip piece, Figure 2 shows that a more general design, among the drive IC of this known technology, need two input signal Hin and Lin, input signal Lin is in order to trigger a pwm signal of low-side driver circuitry 3, and another input signal Hin is an opposite signal of this pwm signal, in order to trigger high-end drive circuit 2, the control of this opposite signal by this pwm signal, two high voltage rate switch M1 and M2 can shift in order to the voltage level that reaches high-side driver 1, yet the use of high voltage rate switch M1 and M2 but has several shortcomings; At first, the switch cost of these switches particularly can be very big when high switching frequency, and, switch M1 and M2 are packaged among the driver IC, this can increase technologic complexity, the 3rd, these high voltage rate switches can increase the cost of driver, in addition, for the ease of driving high-end switch S2 and low-end switch S1 smoothly, be necessary to utilize (dead-time) initialization circuit when quiet to produce to have effective two complementary signals when quiet, well-known is that supply of current (source current) and the ability that sinks electric current (sink current) are to weigh the key factor of one drive circuit, among most drive IC, supply of current and the ability that sinks electric current all can be limited, and with the unlatching of the switch module in a large-scale power supply changeover device that slows down and close, and reduce the efficient of this transducer, therefore, be necessary to increase an extra buffer circuit.
In view of the bottleneck that occurs in the above-mentioned known technology, invent out the drive circuit that is used for DC-DC converter of the present invention, it is made of some simple discrete circuits and is integrated on chip piece, this drive circuit provides a high-end cheaply and low-end driver, can overcome the defective in the known technology.It below is brief description of the present invention.
Summary of the invention
First purpose of the present invention is to drive a high-end switch and the low-end switch in the DC-DC converter by a PWM input signal.
Second purpose of the present invention is for passing through a simple circuit to shift the voltage level of high-side driver.
But the 3rd purpose of the present invention is a set-up function when reaching a modulation quiet, to avoid the mutual conducting problem of current potential between high-end and the low-end switch.
The 4th purpose of the present invention is to reach enough supply of current and the ability that sinks electric current, to increase the switch speed of high-end switch and low-end switch.
The 5th purpose of the present invention is for providing the one drive circuit that has simple structure, is used for DC-DC converter, and a kind of driving method cheaply.
The 6th purpose of the present invention is for providing a kind of high-end and low-side driver circuitry that is used for DC-DC converter, and this drive circuit has a voltage level and shifts electric capacity, a time delay circuit, low side driving buffer and a high-side driver buffer.
In order to achieve the above object, the invention provides a kind of drive circuit that is used for a switch brachium pontis of a DC-DC converter, this switch brachium pontis comprises a main switch and an active switch that is connected in series, the complementary running of this active switch and this main switch, and this drive circuit comprises:
One input is in order to receive an input of a pulse-width modulation (PWM) signal;
One first output is connected in this main switch, and this first output is in order to export a low side drive signal;
One second output is connected in this active switch, and this second output is in order to export a high-side driver signal;
One first branch shifts electric capacity and one first buffer by a voltage level and is connected in series between this input and this second output and constitutes; And
One second branch is connected in series between this input and this first output by a delay circuit and one second buffer and constitutes;
Wherein, when this input of this pwm signal when a high potential is reduced to an electronegative potential, this input of this pwm signal promptly is transferred into this second buffer via this delay circuit, in order to close this main switch, and then trigger this first buffer to open this active switch, and when this input of this pwm signal when this electronegative potential rises to this high potential, this voltage level shift that electric capacity promptly transmits this pwm signal this input to this first buffer, in order to closing this active switch, and then after a time of delay, trigger this second buffer to open this main switch.
The above-mentioned drive circuit that is used for a switch brachium pontis of a DC-DC converter, wherein this DC-DC converter is selected from boost one of them of semi-bridge convertor of active-clamp feedforward transducer, an active-clamp flyback converter, an active-clamp feedforward-flyback converter, a boost converter and.
The above-mentioned drive circuit that is used for a switch brachium pontis of a DC-DC converter, wherein this delay circuit is a rising edge delay circuit, comprising:
One switch comprises the emitter terminal that is connected in this input, is connected in the collector terminal of an output of this delay circuit and a base terminal that is connected in a voltage source and ground respectively via one first resistance and one second resistance;
One electric capacity is coupled between this base terminal and this emitter terminal of this switch; And
One diode comprises an anode tap that is connected in this collector terminal and a cathode terminal that is connected in this emitter terminal of this switch.
The above-mentioned drive circuit that is used for a switch brachium pontis of a DC-DC converter, wherein this switch is a PNP transistor.
The above-mentioned drive circuit that is used for a switch brachium pontis of a DC-DC converter, wherein this second buffer comprises:
One NPN transistor; And
One PNP transistor, wherein this NPN transistor and transistorized two emitter terminals of this PNP are connected in this first output, and this NPN transistor and transistorized two base terminals of this PNP are connected in an output of this delay circuit.
The above-mentioned drive circuit that is used for a switch brachium pontis of a DC-DC converter, wherein this first buffer comprises:
Be connected in an end of the one source pole end of this active switch;
One first diode and one second diode, its be one another in series connect and and one be capacitively coupled between a voltage source and this end, form the inhibition circuit that boosts jointly;
One the first transistor, an emitter-base bandgap grading end that comprises a collector terminal of an end that is connected in this electric capacity, is connected in a base terminal of this collector terminal and is connected in a gate terminal of this active switch via a resistance;
One transistor seconds comprises that being connected in this voltage level via a current-limiting resistance shifts a base terminal of electric capacity, a collector terminal of this base terminal that is connected in this first resistance and an emitter terminal that is connected in this end; And
One the 3rd diode and one the 4th diode, it oppositely is connected between this base terminal of this first transistor and this emitter terminal and between this base terminal and this emitter terminal of this transistor seconds respectively, each other.
The above-mentioned drive circuit that is used for a switch brachium pontis of a DC-DC converter, wherein this first transistor and this transistor seconds are NPN transistor.
The above-mentioned drive circuit that is used for a switch brachium pontis of a DC-DC converter, wherein this first buffer comprises:
Be connected in one first end of the one source pole end of this active switch;
One first diode and one second diode, its be one another in series connect and and one first be capacitively coupled between a voltage source and this first end, form the inhibition circuit that boosts jointly;
One the first transistor, a collector terminal that comprises a collector terminal of an end that is connected in this electric capacity, is connected in a base terminal of this emitter terminal and is connected in a gate terminal of this active switch via one the 3rd diode;
Be connected in one second end of a drain electrode end of this active switch;
One the 4th diode and one the 5th diode are connected in series between the negative electrode and this second end of this first diode;
One second electric capacity comprises an end of this base terminal that is connected in this first transistor and the other end that is connected in a cathode terminal of the 4th diode;
One transistor seconds comprises that being connected in this voltage level via a current-limiting resistance shifts a base terminal of electric capacity, a collector terminal of this gate terminal that is connected in this active switch and an emitter terminal that is connected in this first end; And
One the 6th diode, it is connected between this base terminal and this emitter terminal of this transistor seconds.
The above-mentioned drive circuit that is used for a switch brachium pontis of a DC-DC converter, wherein this first transistor is a PNP transistor, and this transistor seconds is a NPN transistor.
The present invention also provides a kind of active hoop DC/DC transducer, comprising:
One transformer;
One main switch is connected in series in the primary side of this transformer;
One active-clamp branch comprises an active switch and a clamping capacitance, the complementary running of this active switch and this main switch, and this clamping capacitance is connected in parallel in the primary side of this transformer; And
One drive circuit comprises:
One input is in order to receive an input of a pulse-width modulation (PWM) signal;
One first output is connected in this main switch, and this first output is in order to export a low side drive signal;
One second output is connected in this active switch, and this second output is in order to export a high-side driver signal;
One first branch shifts electric capacity and one first buffer by a voltage level and is connected in series between this input and this second output and constitutes; And
One second branch is connected in series between this input and this first output by a delay circuit and one second buffer and constitutes;
Wherein, when this input of this pwm signal when a high potential is reduced to an electronegative potential, this input of this pwm signal promptly is transferred into this second buffer via this delay circuit, in order to close this main switch, and then trigger this first buffer to open this active switch, and when this input of this pwm signal when this electronegative potential rises to this high potential, this voltage level shift that electric capacity promptly transmits this pwm signal this input to this first buffer, in order to closing this active switch, and then after a time of delay, trigger this second buffer to open this main switch.
The present invention also provides a kind of voltage level transfer method, the one drive circuit that is used for a switch brachium pontis of a DC-DC converter, this switch brachium pontis comprises a main switch and an active switch that is connected in series, the complementary running of this active switch and this main switch, this drive circuit comprises one first branch and one second branch, this first branch is connected in series between an input and one second output by voltage level transfer electric capacity and one first buffer and constitutes, this second branch is connected in series between this input and one first output by a delay circuit and one second buffer and constitutes, and this voltage level transfer method comprises the following steps:
Receive an input of a pwm signal;
When this input of this pwm signal when a relative high potential is reduced to a relative electronegative potential, this input of this pwm signal is sent to this second buffer via this delay circuit, in order to closing this main switch, and then trigger this first buffer to open this active switch; And
When oneself this relative electronegative potential of this input of this pwm signal rises to this relative high potential, with this input transfer of this pwm signal to this first buffer, in order to closing this active switch, and then after a time of delay, trigger this second buffer to open this main switch.
Above-mentioned voltage level transfer method comprises that also step is as follows:
Receive this input of this pulse-width modulation signal at this input;
Export a low side drive signal at this first output; And
Export a high-side driver signal at this second output.
The present invention is by following accompanying drawing and detailed description, understanding that can be more deep.
Description of drawings
Fig. 1 is the circuit diagram that is applied to a high-end and low side drive IC of active-clamp feedforward DC-DC converter traditionally;
Fig. 2 is the circuit diagram of the common design mode of the high-end and low-end driver of the present invention;
Fig. 3 is the circuit block diagram of a preferred embodiment of the present invention's high-end and low-side driver circuitry of being applied to active-clamp feedforward transducer;
Fig. 4 is the circuit diagram of the present invention's rising edge delay circuit of initialization circuit one embodiment when quiet;
Fig. 5 (A) is the circuit diagram of high-end drive circuit one embodiment of the present invention, and it is in order to drive high-end switch;
Fig. 5 (B) is the circuit diagram of another embodiment of high-end drive circuit of the present invention, and it is in order to drive high-end switch;
Fig. 6 is the integrated circuit figure of a preferred embodiment of the present invention's high-end and low-side driver circuitry of being applied to active-clamp feedforward transducer;
Fig. 7 is the integrated circuit figure of another preferred embodiment of the present invention's high-end and low-side driver circuitry of being applied to active-clamp feedforward transducer;
Fig. 8 is the circuit block diagram of a preferred embodiment of the present invention's high-end and low-side driver circuitry of being applied to an active-clamp flyback converter;
Fig. 9 is the circuit block diagram of a preferred embodiment of the present invention's high-end and low-side driver circuitry of being applied to an active-clamp feedforward-flyback converter;
Figure 10 is the circuit block diagram of a preferred embodiment of the present invention's high-end and low-side driver circuitry of being applied to a boost converter; And
Figure 11 is that the present invention is applied to a circuit block diagram of a preferred embodiment of a high-end and low-side driver circuitry that boosts semi-bridge convertor.
Among the figure:
1 high-side driver
2 high-end drive circuits
3 low-side driver circuitry
The C1 voltage level shifts electric capacity
The C11 clamping capacitance
C10, C11, C21, C31, C32 electric capacity
D1, D2, D10, D31, D32 diode
D33, D34, D36, D37, D38 diode
The Hin input signal
The Lin input signal
L1, Lb inductance
M1, M2 high voltage rate switch
Q1, Q3, Q4, Q5, Q6 transistor
R10, R11, R31, R32, R33, R51 resistance
The S1 low-end switch
The S2 high-end switch
The T transformer
The Vcc voltage source
Embodiment
Drive circuit of the present invention is in order to drive a switch brachium pontis of a DC-DC converter, wherein this DC-DC converter can be active-clamp feedforward transducer, one active-clamp flyback converter, one active-clamp feedforward-flyback converter, one boost converter, or the semi-bridge convertor that boosts, the switch brachium pontis of this DC-DC converter by a main switch (low-end switch) and an active switch (high-end switch) be connected in series constitute, this active switch and this main switch operate with complimentary fashion, below will describe the one drive circuit that is applied to active-clamp feedforward transducer in detailed mode.
Please refer to Fig. 3, it is applied to the circuit block diagram of a preferred embodiment of a high-end and low-side driver circuitry of active-clamp feedforward transducer for the present invention.Among this transducer, low-end switch S1 is connected in series in the primary side of transformer T, and an active-clamp branch is connected in parallel in the primary side of transformer T, this active-clamp branch comprises a high-end switch S2 and a clamping capacitance C11 of mutual series connection, drive circuit 11 has three ports, first port is in order to receive a driving signal input mouth 1 of a pwm signal, second port is a low side drive output mouth 2 that is connected in low-end switch S1, the 3rd port is a high-side driver output port 3 that is connected in high-end switch S2, drive circuit 11 has two branches, a low side that branches between port one and port 2, the series circuit that is constituted by a rising edge delay circuit and a buffer A, another branch then is high-end between port one and port 3, by the series circuit that a voltage level transfer capacitor C 1 and a buffer B are constituted, wherein low-end switch S1 and high-end switch S2 operate with complimentary fashion.
The basic driver principle of drive circuit is as described below:
Suppose that pwm signal is positioned at a high potential, and low-end switch S1 opens and high-end switch is closed, when pwm signal reduces to an electronegative potential, this signal just is transferred into buffer A at once via delay circuit, and low-end switch S1 just is cushioned device A and closes, the output capacitance of the low-end switch S1 electric current that is magnetized charges, and raises fast across the voltage of low-end switch S1, and the signal that this voltage rises is reflected on the buffer B at once and triggers high-side driver to open switch S 2.
When pwm signal becomes high potential, capacitor C 1 promptly transmits this signal to buffer B and at once trigger buffer B to close high-end switch S2, conduct alternately for fear of the current potential between switch S 1 and the S2, pwm signal just is delayed a bit of time of circuit delay and then triggers buffer A to open switch S 1 after off switch S2.
The circuit diagram of the rising edge delay circuit of initialization circuit one embodiment when Fig. 4 is used for drive circuit quiet for the present invention.Port one is an input that is connected in pwm signal, port 4 is connected in a voltage source Vcc, and port 5 is connected in ground, the collector terminal of the output that the PNP transistor comprises the emitter terminal that is connected in pwm signal, be connected in delay circuit and a base terminal that is connected to voltage source and ground via resistance R 10 and resistance R 11, capacitor C 10 is coupled between the base terminal and emitter terminal of transistor Q1, the anode tap of diode D10 is connected in the collector terminal of transistor Q1, and cathode terminal then is connected in the emitter terminal of transistor Q1.
When pwm signal is an electronegative potential, because a positive voltage is coupled across capacitor C 10 and puts between the emitter terminal and base terminal of transistor Q1, transistor Q1 promptly is held in the OFF state, when pwm signal changes into high potential, 10 of capacitor C are via resistance R 10 and R11 discharge, transistor Q1 promptly opens up to the positive voltage of cross-over connection on capacitor C 10 and is discharged to negative voltage, therefore, between the output of delay circuit and input, just can obtain to open one period short time of delay, can be set this time of delay by the capacitance of capacitor C 10 and the resistance value of resistance R 10 and R11, when pwm signal is reduced to electronegative potential, this signal just directly is transmitted via diode D10, does not have any delay feature for the shut-in time.
Fig. 5 (A) is the circuit diagram of high-end drive circuit one embodiment of the present invention, it is made of capacitor C 1 and buffering circuit B, capacitor C 1 can reach the voltage level forwarding function, one end of capacitor C 1 is connected in the PWM input signal, the other end of capacitor C 1 then is connected in buffer circuit B, the port 6 of buffer circuit B is connected in the source terminal of switch S 2, suppressing circuit (boost trap circuit) by boosting of being constituted of the diode D31 that is connected in series and D34 and capacitor C 31 is coupled between voltage source Vcc and the port 6, PNP transistor Q5 comprises a collector terminal of first end that is connected in capacitor C 31, be connected in a base terminal of collector terminal via resistance R 31, an and emitter terminal that is connected in grid (gate) end at high-end beginning, another PNP transistor Q6 comprises a base terminal that is connected in capacitor C 1 via a current-limiting resistance R32, be connected in a collector terminal of the base terminal of transistor Q5, an and emitter terminal that is connected in port 6, diode D32 and D33 are connected anti-parallel to respectively between the base terminal and emitter terminal of transistor Q5 and Q6, these assemblies have formed basic high-end drive circuit, when switch S 2 is positioned at the OFF state, is connected in port one 2 and boosts and suppress resistance R 33 between the diode D31 and just provide a constant bias current to transistor Q6.
When very low and switch S 1 is in the OFF state when the voltage of PWM, one high voltage promptly appears in port 6, it remains in the OFF state by the conducting of diode D33 with transistor Q6, voltage between the grid source electrode of switch S 2 can be set up by transistor Q5, it can be opened switch S 2, when pwm signal goes to high potential from electronegative potential, this signal is promptly via capacitor C 1 and resistance R 32 and be transferred into the base terminal of transistor Q6, transistor Q6 just is unlocked at once, soon the grid capacitance of switch S 2 is promptly via diode D32 and transistor Q6 and discharged, and transistor Q5 and switch S 2 just are closed, when switch S 1 is opened, transistor Q6 remains in the ON state by a bias current, this bias current is from Vcc and in regular turn by diode D31, resistance R 33 and R32, transistor Q6, and switch S 1, base terminal up to transistor Q6, switch S 2 is because its grid voltage is clamped to an electronegative potential, therefore remain in the OFF state, the voltage of capacitor C 1 is via resistance R 32, transistor Q6 and switch S 1 and be discharged to an electronegative potential, in addition, capacitor C 1 and resistance R 32 have constituted the RC vibration absorber of switch S 2.
Fig. 5 (B) is the circuit diagram of another embodiment of high-end drive circuit of the present invention, and it is in order to driving switch S2.With the high-end drive circuit of Fig. 5 (A) by comparison, unique difference is the charging circuit of switch S 2, resistance R 31 and diode D32 are removed, transistor Q5 is then replaced by a PNP transistor, this PNP transistor comprises an emitter terminal that is connected in capacitor C 31 first ends, be connected in a base terminal of emitter terminal via diode D36, an and collector terminal that is connected in the grid of switch S 2, port 7 is the drain electrode end of high-end switch S2, diode D38 and D37 are connected in series between the cathode terminal and port 7 of diode D38, and 32 of capacitor C are connected between the cathode terminal of the base terminal of transistor Q5 and diode D38.
When pwm signal is that high potential and low-end switch S1 are in the ON state, across the voltage of capacitor C 32 be 0 and diode D37 owing to a reverse voltage is in the OFF state, during this period, transistor Q5 is that OFF and transistor Q6 are ON, when pwm signal transfers electronegative potential to, low-end switch S1 is closed, the voltage of port 6 rises, when the voltage of port 6 and port 7 are identical, diode D37 conducting, transistor Q5 is owing to flow through capacitor C 32 and diode D37 of a bias current opens, switch S 2 promptly is unlocked, and is charged to Vcc at the grid voltage between source electrodes of switch S 2 and the voltage of capacitor C 32, and transistor Q5 promptly closes at once, and the grid voltage between source electrodes of switch S 2 remains in Vcc, when pwm signal changes into high potential, switch S 1 promptly is unlocked, and capacitor C 32 is promptly via diode D38 and D36 and be discharged to 0, all as the driver of Fig. 5 (A), it provides zero voltage switching to conduct in switch S 2 in other running.
Fig. 6 is applied to the integrated circuit figure of a preferred embodiment of a high-end and low-side driver circuitry of active-clamp feedforward transducer for the present invention, the circuit of Fig. 6 stems from the circuit of Fig. 2, wherein isolating the time of delay circuit is replaced by the rising edge delay circuit of Fig. 4, the isolation of buffer circuit A is replaced by transistor Q3 and Q4, and the isolation of buffer circuit B is replaced by the circuit of Fig. 5 (A).
Fig. 7 is applied to the integrated circuit figure of another preferred embodiment of a high-end and low-side driver circuitry of active-clamp feedforward transducer for the present invention, with Fig. 6 by comparison, it is by removing transistor Q3, and increase the resistance R 51 of the base stage be connected in parallel in transistor Q4 and emitter terminal and make the drive circuit of Fig. 7 become a circuit of simplifying, in addition, the anode tap of diode D10 is connected in the base terminal of transistor Q4, when pwm signal transfers high potential to, switch S 1 promptly by pwm signal via transistor Q1 to start a time of delay, when pwm signal transfers electronegative potential to, the grid capacitance of switch S 1 is promptly discharged via transistor Q4.
Yet the technical staff who has the knack of this technology can understand easily, and drive circuit of the present invention also can be applicable to the switch brachium pontis topology of other kind of other DC-DC converter.Fig. 8 is applied to the circuit block diagram of a preferred embodiment of a high-end and low-side driver circuitry of an active-clamp flyback converter for the present invention, Fig. 9 is applied to the circuit block diagram of a preferred embodiment of a high-end and low-side driver circuitry of an active-clamp feedforward-flyback converter for the present invention, Figure 10 is applied to the circuit block diagram of a preferred embodiment of a high-end and low-side driver circuitry of a boost converter for the present invention, 1 of Fig. 1 is applied to a circuit block diagram of a preferred embodiment of high-end and a low-side driver circuitry that boosts semi-bridge convertor for the present invention; These variations are not to be used for limiting scope of the invention process, and promptly all remodeling of being done under this invention's idea all belongs in the claim of the present invention.
Claims (12)
1. drive circuit that is used for a switch brachium pontis of a DC-DC converter, this switch brachium pontis comprises a main switch and an active switch that is connected in series, the complementary running of this active switch and this main switch, this drive circuit comprises:
One input is in order to receive an input of a pulse-width modulation signal;
One first output is connected in this main switch, and this first output is in order to export a low side drive signal;
One second output is connected in this active switch, and this second output is in order to export a high-side driver signal;
One first branch shifts electric capacity and one first buffer by a voltage level and is connected in series between this input and this second output and constitutes; And
One second branch is connected in series between this input and this first output by a delay circuit and one second buffer and constitutes;
Wherein, when this input of this pulse-width modulation signal when a high potential is reduced to an electronegative potential, this input of this pulse-width modulation signal promptly is transferred into this second buffer via this delay circuit, in order to close this main switch, and then trigger this first buffer to open this active switch, and when this input of this pulse-width modulation signal when this electronegative potential rises to this high potential, this voltage level shift that electric capacity promptly transmits this pulse-width modulation signal this input to this first buffer, in order to closing this active switch, and then after a time of delay, trigger this second buffer to open this main switch.
2. drive circuit as claimed in claim 1, wherein this DC-DC converter is selected from boost one of them of semi-bridge convertor of active-clamp feedforward transducer, an active-clamp flyback converter, an active-clamp feedforward-flyback converter, a boost converter and.
3. drive circuit as claimed in claim 1, wherein this delay circuit is a rising edge delay circuit, comprising:
One switch comprises the emitter terminal that is connected in this input, is connected in the collector terminal of an output of this delay circuit and a base terminal that is connected in a voltage source and ground respectively via one first resistance and one second resistance;
One electric capacity is coupled between this base terminal and this emitter terminal of this switch; And
One diode comprises an anode tap that is connected in this collector terminal and a cathode terminal that is connected in this emitter terminal of this switch.
4. drive circuit as claimed in claim 3, wherein this switch is a PNP transistor.
5. drive circuit as claimed in claim 1, wherein this second buffer comprises:
One NPN transistor; And
One PNP transistor, wherein this NPN transistor and transistorized two emitter terminals of this PNP are connected in this first output, and this NPN transistor and transistorized two base terminals of this PNP are connected in an output of this delay circuit.
6. drive circuit as claimed in claim 1, wherein this first buffer comprises:
Be connected in an end of the one source pole end of this active switch;
One first diode and one second diode, its be one another in series connect and and one be capacitively coupled between a voltage source and this end, form the inhibition circuit that boosts jointly;
One the first transistor, an emitter-base bandgap grading end that comprises a collector terminal of an end that is connected in this electric capacity, is connected in a base terminal of this collector terminal and is connected in a gate terminal of this active switch via a resistance;
One transistor seconds comprises that being connected in this voltage level via a current-limiting resistance shifts a base terminal of electric capacity, a collector terminal of this base terminal that is connected in this first resistance and an emitter terminal that is connected in this end; And
One the 3rd diode and one the 4th diode, it oppositely is connected between this base terminal of this first transistor and this emitter terminal and between this base terminal and this emitter terminal of this transistor seconds respectively, each other.
7. drive circuit as claimed in claim 6, wherein this first transistor and this transistor seconds are NPN transistor.
8. drive circuit as claimed in claim 1, wherein this first buffer comprises:
Be connected in one first end of the one source pole end of this active switch;
One first diode and one second diode, its be one another in series connect and and one first be capacitively coupled between a voltage source and this first end, form the inhibition circuit that boosts jointly;
One the first transistor, a collector terminal that comprises a collector terminal of an end that is connected in this electric capacity, is connected in a base terminal of this emitter terminal and is connected in a gate terminal of this active switch via one the 3rd diode;
Be connected in one second end of a drain electrode end of this active switch;
One the 4th diode and one the 5th diode are connected in series between the negative electrode and this second end of this first diode;
One second electric capacity comprises an end of this base terminal that is connected in this first transistor and the other end that is connected in a cathode terminal of the 4th diode;
One transistor seconds comprises that being connected in this voltage level via a current-limiting resistance shifts a base terminal of electric capacity, a collector terminal of this gate terminal that is connected in this active switch and an emitter terminal that is connected in this first end; And
One the 6th diode, it is connected between this base terminal and this emitter terminal of this transistor seconds.
9. drive circuit as claimed in claim 8, wherein this first transistor is a PNP transistor, and this transistor seconds is a NPN transistor.
10. active hoop DC/DC transducer comprises:
One transformer;
One main switch is connected in series in the primary side of this transformer;
One active-clamp branch comprises an active switch and a clamping capacitance, the complementary running of this active switch and this main switch, and this clamping capacitance is connected in parallel in the primary side of this transformer; And
One drive circuit comprises:
One input is in order to receive an input of a pulse-width modulation signal;
One first output is connected in this main switch, and this first output is in order to export a low side drive signal;
One second output is connected in this active switch, and this second output is in order to export a high-side driver signal;
One first branch shifts electric capacity and one first buffer by a voltage level and is connected in series between this input and this second output and constitutes; And
One second branch is connected in series between this input and this first output by a delay circuit and one second buffer and constitutes;
Wherein, when this input of this pulse-width modulation signal when a high potential is reduced to an electronegative potential, this input of this pulse-width modulation signal promptly is transferred into this second buffer via this delay circuit, in order to close this main switch, and then trigger this first buffer to open this active switch, and when this input of this pulse-width modulation signal when this electronegative potential rises to this high potential, this voltage level shift that electric capacity promptly transmits this pulse-width modulation signal this input to this first buffer, in order to closing this active switch, and then after a time of delay, trigger this second buffer to open this main switch.
11. voltage level transfer method, the one drive circuit that is used for a switch brachium pontis of a DC-DC converter, this switch brachium pontis comprises a main switch and an active switch that is connected in series, the complementary running of this active switch and this main switch, this drive circuit comprises one first branch and one second branch, this first branch is connected in series between an input and one second output by voltage level transfer electric capacity and one first buffer and constitutes, this second branch is connected in series between this input and one first output by a delay circuit and one second buffer and constitutes, and this voltage level transfer method comprises the following steps:
Receive an input of a pulse-width modulation signal;
When this input of this pulse-width modulation signal when a relative high potential is reduced to a relative electronegative potential, this input of this pulse-width modulation signal is sent to this second buffer via this delay circuit, in order to closing this main switch, and then trigger this first buffer to open this active switch; And
When oneself this relative electronegative potential of this input of this pulse-width modulation signal rises to this relative high potential, with this input transfer of this pulse-width modulation signal to this first buffer, in order to closing this active switch, and then after a time of delay, trigger this second buffer to open this main switch.
12. voltage level transfer method as claimed in claim 11 comprises that also step is as follows:
Receive this input of this pulse-width modulation signal at this input;
Export a low side drive signal at this first output; And
Export a high-side driver signal at this second output.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100618424A CN100384068C (en) | 2004-06-25 | 2004-06-25 | Driving circuit for DC/DC converter voltage and level transferring method |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100618424A CN100384068C (en) | 2004-06-25 | 2004-06-25 | Driving circuit for DC/DC converter voltage and level transferring method |
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| CN1713495A true CN1713495A (en) | 2005-12-28 |
| CN100384068C CN100384068C (en) | 2008-04-23 |
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| CNB2004100618424A Active CN100384068C (en) | 2004-06-25 | 2004-06-25 | Driving circuit for DC/DC converter voltage and level transferring method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101888237A (en) * | 2010-06-29 | 2010-11-17 | 日银Imp微电子有限公司 | Level transfer circuit with anti-interference protection function |
| CN102684458A (en) * | 2012-05-09 | 2012-09-19 | 矽力杰半导体技术(杭州)有限公司 | Driving circuit of power switching tube and switching power circuit employing driving circuit |
| CN103797699A (en) * | 2011-07-01 | 2014-05-14 | 利纳克有限公司 | Power supply with output rectifier |
| CN107017779A (en) * | 2017-05-31 | 2017-08-04 | 青岛大学 | A kind of band pulls down the isolated form DC DC booster converter control methods of active clamp branch road |
| CN107017780A (en) * | 2017-05-31 | 2017-08-04 | 青岛大学 | The isolated form DC DC booster converters and its control method of a kind of band pull-up active clamp branch road |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2795217B2 (en) * | 1995-06-01 | 1998-09-10 | 日本電気株式会社 | Synchronous rectification type converter |
| JP2806320B2 (en) * | 1995-09-13 | 1998-09-30 | 日本電気株式会社 | Synchronous rectification circuit |
| US6069803A (en) * | 1999-02-12 | 2000-05-30 | Astec International Limited | Offset resonance zero volt switching flyback converter |
| JP2001224170A (en) * | 2000-02-09 | 2001-08-17 | Sony Corp | Switching power circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101888237A (en) * | 2010-06-29 | 2010-11-17 | 日银Imp微电子有限公司 | Level transfer circuit with anti-interference protection function |
| CN101888237B (en) * | 2010-06-29 | 2012-05-02 | 日银Imp微电子有限公司 | Level transfer circuit with anti-interference protection function |
| CN103797699A (en) * | 2011-07-01 | 2014-05-14 | 利纳克有限公司 | Power supply with output rectifier |
| CN102684458A (en) * | 2012-05-09 | 2012-09-19 | 矽力杰半导体技术(杭州)有限公司 | Driving circuit of power switching tube and switching power circuit employing driving circuit |
| CN107017779A (en) * | 2017-05-31 | 2017-08-04 | 青岛大学 | A kind of band pulls down the isolated form DC DC booster converter control methods of active clamp branch road |
| CN107017780A (en) * | 2017-05-31 | 2017-08-04 | 青岛大学 | The isolated form DC DC booster converters and its control method of a kind of band pull-up active clamp branch road |
| CN107017780B (en) * | 2017-05-31 | 2019-05-10 | 青岛大学 | A kind of the isolated form DC-DC boost converter and its control method of band pull-up active clamp branch |
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| CN100384068C (en) | 2008-04-23 |
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