CN1713126A - Disk drive system on chip with integrated buffer memory and support for host memory access - Google Patents
Disk drive system on chip with integrated buffer memory and support for host memory access Download PDFInfo
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- CN1713126A CN1713126A CN 200510073062 CN200510073062A CN1713126A CN 1713126 A CN1713126 A CN 1713126A CN 200510073062 CN200510073062 CN 200510073062 CN 200510073062 A CN200510073062 A CN 200510073062A CN 1713126 A CN1713126 A CN 1713126A
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Abstract
A circuit for a storage device that communicates with a host device comprises a first high speed interface. A storage controller communicates with the high speed interface. A buffer communicates with the storage controller. The storage device generates storage buffer data during operation. The storage controller is adapted to selectively store the storage buffer data in at least one of the buffer and/or in the host device via the high speed interface. A bridge chip for enterprise applications couples the circuit to an enterprise device.
Description
Technical field
The present invention relates to hard disk drive, (system on chip, memory buffer SOC) and improvement comprise the business system of HDD system on chip more specifically to increasing the HDD system on chip.
Background technology
Main process equipment often need be stored lot of data such as computing machine, notebook, personal video recorder (PVR), MP3 player, game console, server, set-top box, digital camera and/or other electronic installations.Memory device as hard disk drive (HDD) can be used to satisfy these storage demands.
With reference now to Fig. 1,, shown an exemplary hard disk drive 10 among the figure, this hard disk drive comprises 12 and hard drive assemblies of a hard disk drive (HDD) system on chip (SOC) (HDA) 13.HAD 13 comprises one or more hard drive discs 14, is coated with magnetosphere 15 on these discs.Magnetosphere 15 storage representation binary ones and 0 both positive and negative polarity magnetic field.The Spindle Motor of schematically representing with Reference numeral 16 among the figure makes hard drive disc 14 rotate.Usually Spindle Motor 16 rotates hard drive disc 14 with fixing speed during read/write operation.One or more read/write transmission arm moves with respect to hard drive disc 14, with from hard drive disc 14 reading of data/or data are write hard drive disc 14.
The position of read/write device 20 is near the far-end of read/write arm 18.Read/write device 20 comprises a writing component, such as the inductor that produces magnetic field.Read/write device 20 also comprises the reading component in the magnetic field on the induction disc 14, such as magnetic resistance (MR) element.Preamplifier circuit 22 amplifies analog read/write signal.
When reading of data, the low level signal that preamplifier circuit 22 amplifies from reading component, and a signal that is exaggerated outputs to read/write channel device 24.When write data, produce write current, this write current flows through the writing component of read/write device 20.Write current is switched and just produces the magnetic field with negative or positive electrode.Above-mentioned negative or positive electrode is stored by hard drive disc 14, and is used to represent data.
Hard disk drive system on chip (HDD SOC) 12 typically comprises an impact damper 32, data and/or buffered data that its storage is relevant with the control of hard disk drive, allowing data be collected as bigger data block and to transmit, thereby raise the efficiency.Impact damper 32 can adopt the low delay memory of DRAM, SDRAM or other types.HDD SOC 12 further comprises a processor 34, and it carries out the processing relevant with the operation of HDD 10.
HDD SOC 12 further comprises a hard disk controller 36 (being HDC 36), and it is communicated by letter with main process equipment via I/O (I/O) interface 38.HDC 36 also communicates by letter with main shaft/voice coil motor driver 40 (being main shaft VCM 40) and/or read/write channel device 24.I/O interface 38 can be a serial line interface or parallel interface, such as integrated drive electronics (IDE), AT attachment (ATA) or serial ATA (SATA) interface.Main shaft/VCM driver 40 control Spindle Motors 16, and Spindle Motor 16 rotation discs 14.Main shaft/VCM driver 40 also produces the control signal that is used for to read/write arm 18 location, and voice coil actuator, stepper motor or other suitable drivers are for example used in this location.I/O interface 38 is communicated by letter with I/O interface 44, and I/O interface 44 is associated with main process equipment 46.
With reference now to Fig. 2,, shown an exemplary main process equipment 64 among the figure, it comprises a processor 66, this processor has storer 67, such as buffer memory.Processor 66 is communicated by letter with input/output interface 68 (being I/O interface 68).Volatile memory 69 is also communicated by letter with interface 68 such as random-access memory (ram) 70 and/or other suitable electronic data memories.Graphic process unit 71 and improved the speed and the performance of graphics process such as the such storer 72 of buffer memory.
One or more I/O equipment are communicated by letter with interface 68 with indicating device 74 (such as mouse and/or other suitable devices) such as keyboard 73.Computer architecture 64 can comprise that also display 76, audio output apparatus 77 are such as audio tweeter and/or general other I/O (I/O) equipment of identifying with Reference numeral 78.
In use, HDD is independent of the main process equipment operation.Hard disk drive in locally buffered data to improve performance.This scheme requires hard disk drive to comprise the low RAM that postpones, and such as DRAM, this has increased the cost of hard disk drive.
With reference now to Fig. 3,, shown the desktop HDDSOC 200 of main process equipment such as desktop computer among the figure.HDD SOC 200 comprises processor 204, hard disk controller (HDC) 208, read/write channel device circuit 212, storer 216 (its can be implemented on the chip and/or chip outer) and high-speed interface 220.For instance, high-speed interface 220 can be a kind of serial or parallel interface of communicating by letter with main process equipment 226, such as ATA and/or SATA interface.In this embodiment, as shown in the figure, main shaft/VCM driver and processor 204 integrate.HAD 13 is connected with processor 204 and read/write channel circuit 212.Main process equipment 226 comprises an ATA/SATA interface 228 of communicating by letter with ATA/SATA interface 220.The operation of HDD SOC200 is described similar with the above Fig. 1 of combination.
With reference now to Fig. 4,, shown among the figure that is used for a business equipment 232, such as the HDD SOC 230 of server or other business equipments.HDD SOC 230 comprises a main shaft/VCM/ data processor 234, the operation that its execution is relevant with Spindle Motor, VCM and/or data processing.HDD SOC 230 further comprises an interface/data processor 236, and this processor is carried out and the interface related processing of business equipment.HDD SOC 230 also comprises hard disk controller (HDC) 238, read/write channel circuit 242, storer 246 (it can be implemented on the chip) and high-speed interface 250.For instance, high-speed interface 250 can be a kind of serial or parallel interface, and such as small computer system interface (SCSI), Serial Attached SCSI (SAS) or optical-fibre channel (FC) interface, this interface is communicated by letter with business equipment 232 via high-speed interface 251.
Owing to use the processor and different output terminal interfaces of varying number, manufacturer designs with desktop application for enterprise's application and has made two kinds of different HDD SOC frameworks.Specifically, desktop HDD SOC 200 comprises single processor and the HDD SOC of enterprise 230 comprises two processors.In addition, desktop HDD SOC 200 typically uses ATA and/or SATA interface and enterprise servers typically use SAS and/or FC interface.Independently framework has increased the design total amount and the matrix cost (die cost) of two kinds of equipment.
Summary of the invention
The invention provides a kind of circuit that is used for memory device, comprise first high-speed interface, described memory device is communicated by letter with main process equipment.One memory controller is communicated by letter with described high-speed interface.One impact damper is communicated by letter with described memory controller.Described memory device generates the memory buffer unit data during operation, and described memory controller is suitable for via described high-speed interface the memory buffer unit data optionally being stored in one of described at least impact damper and/or described main process equipment.
Described first high-speed interface comprises AT attachment (ATA) interface of a serial.One processor, one main shaft/VCM driver and a read/write channel circuit are communicated by letter with described memory controller.
The invention provides a kind of hard drive assembly, comprise hard drive disc with magnetic means storage data.One Spindle Motor rotate described hard drive disc and with described main shaft/VCM drive communication.Article one, read/write arm read and write data arrive described hard drive disc, and communicate by letter with described read/write channel circuit.
The invention provides a kind of system, this system comprises described circuit, and further comprises described main process equipment.Described main process equipment comprises second high-speed interface of communicating by letter with described first high-speed interface.Volatile memory stores is from the memory buffer unit data of memory device.
(system on chip SOC) comprises described circuit to a kind of system on chip.
A kind of multi-chip module (MCM) comprises described circuit.
A kind of system that comprises a main process equipment, described main process equipment comprises the volatile memory of a processor, and described processor communication, and first high-speed interface of communicating by letter with one of volatile memory with described processor at least.A memory device comprises second high-speed interface, and second high-speed interface is communicated by letter with described first high-speed interface.A memory controller is communicated by letter with described second high-speed interface.An impact damper is communicated by letter with described memory controller.Described memory device generates the memory buffer unit data during operation.Described memory controller is suitable for via described first and second high-speed interfaces memory buffer unit data optionally being stored in one of described at least impact damper and/or described main process equipment.
The invention provides a kind of bridgt circuit, comprise one first interface, described first interface provides AT attachment (ATA) interface of a serial.One second interface provides one of Serial Attached SCSI (SAS) (SAS) or optical-fibre channel (FC) interface.One processor is connected and data processing with described first and second interface communications and support.Storer and described processor communication.
Described first and second interfaces and described processor are used as integrated circuit and implement.Described integrated circuit further comprises described storer.
The invention provides a kind of system, this system comprises described bridgt circuit, and further comprises a memory device with first interface communication of described bridgt circuit.Described memory device comprises one the 3rd interface, and it provides serial AT attachment (ATA) interface, and with described first interface communication.One memory controller and described the 3rd interface communication.Described memory device generates the memory buffer unit data during operation.Described memory controller is via the described first and the 3rd interface, the memory buffer unit data storage in described bridgt circuit.
The invention provides a kind of circuit that is used for memory device, comprise first interface that serial advanced technology attachment (ATA) interface is provided, described memory device and external device communication.One processor is carried out main shaft/VCM and data processing.One memory controller and described first interface and described processor communication.Described memory device generates the memory buffer unit data during operation.Described memory controller is via second high-speed interface, the memory buffer unit data storage in described external unit.
Storer is communicated by letter with described memory controller.Described memory buffer unit data optionally are stored in one of described storer and/or described external unit.One read/write channel circuit is communicated by letter with described memory controller.
The invention provides a kind of bridging chip, comprise one second interface, it provides serial AT attachment (ATA) interface, and with described first interface communication.One the 3rd interface provides one of Serial Attached SCSI (SAS) (SAS) or optical-fibre channel (FC) interface.
The invention provides a kind of system, this system comprises described circuit, and comprises that further a business equipment, described business equipment comprise the 4th interface with described the 3rd interface communication.Described bridging chip further comprises a processor, itself and described third and fourth interface communication, and carry out and connect and data processing.Described bridging chip and memory communication.Described memory stores is from the memory buffer unit data of described memory device.
According to the following detailed description that provides, other aspects that the present invention uses will become apparent.Represented the preferred embodiments of the present invention though it should be understood that detailed description and specific example, only be for illustrative purposes rather than plan to limit the scope of the invention.
Should illustrate that also the present invention requires No. 60/582259 U.S. Provisional Application No. of submission on June 23rd, 2004.More than Shen Qing disclosure is incorporated herein by reference at this.
Description of drawings
Referring to accompanying drawing, can understand the present invention more fully by following detailed description, wherein:
Fig. 1 is the functional-block diagram according to hard disk drive system on the example chip of prior art;
Fig. 2 is the functional-block diagram according to the example main process equipment of prior art;
Fig. 3 is the functional-block diagram according to the desktop HDD SOC of prior art;
Fig. 4 is the functional-block diagram according to the HDD SOC of enterprise of prior art;
Fig. 5 is the functional-block diagram of the example embodiment of hard drive SOC, and this hard drive SOC comprises an on-chip buffer, and utilizes the volatile memory of main process equipment to be used for extra HDD buffering;
Fig. 6 is a process flow diagram, has illustrated from the volatile memory stores of main process equipment and the step of a kind of illustrative methods of retrieval disk buffer data;
Fig. 7 is the functional-block diagram of the exemplary embodiment of a kind of desktop/SOC of enterprise of implementing in desktop application;
Fig. 8 is the desktop/SOC of enterprise of enforcement in enterprise uses and the illustrative functions block scheme of bridging chip;
Fig. 9 is the more detailed block scheme of the desktop of implementing in desktop application shown in Figure 7/SOC of enterprise;
Figure 10 is a more detailed functional-block diagram of desktop shown in Figure 8/SOC of enterprise and bridging chip;
Figure 11 is the functional-block diagram that has the HDDSOC of FIFO storer and Host Based buffering according to prior art;
Figure 12 A and 12B are the functional-block diagrams of the HDD SOC of low cost/performance HDD SOC according to prior art and superior performance;
Figure 13 A has illustrated the low-cost HDD SOC that uses that is used for according to an embodiment, and it comprises little local storage such as DRAM, and has disabled Host Based pooling feature;
Figure 13 B has illustrated the HDD SOC that superior performance/cost is used that is used for according to another embodiment, and it comprises little local storage such as DRAM, and has the Host Based pooling feature that is activated;
Figure 14 and 15 has illustrated to have HDD SOC and the little local storage MCM such as DRAM; And
Figure 15 has illustrated that a kind of enterprise of the HDD SOC that utilization is identical with Figure 14 uses.
Embodiment
Preferred embodiment described below only is exemplary, and plan restriction the present invention, its application or use by no means.For clarity sake, use identical reference numerals to identify similar elements in the accompanying drawings.Though disclosed herein is SOC, it will be appreciated by those skilled in the art that SOC can be used as multi-chip module and implements, and do not deviate from the present invention.
With reference now to Fig. 5,, wherein show according to system 300 of the present invention, comprise HDD SOC302.HDD SOC 302 comprises impact damper 332, data that this memory stores is related with the control of HDD and/or buffered data, thus allow data be collected as bigger data block and to transmit, to raise the efficiency.Impact damper 332 can utilize the low delay memory of DRAM or other types.HDD SOC 302 further comprises a processor 334, and it carries out the processing relevant with the operation of HDD 300, such as main shaft/VCM control and treatment.
HDD SOC 302 further comprises a hard disk controller (HDC) 336, and it is communicated by letter with main process equipment via high speed I/O (I/O) interface 338.HDC 336 also communicates by letter with spindle/voice coil motor (VCM) driver 340 and/or read/write channel device 324.High-speed i/o interface 338 can be serial ATA (SATA) interface.Main shaft/VCM driver 340 control Spindle Motors 16, Spindle Motor 16 rotation discs 14.Main shaft/VCM driver 340 also produces the control signal that is used to locate read/write arm 18, and this location for example uses voice coil actuator, stepper motor or other suitable drivers to finish.High-speed i/o interface 338 is communicated by letter with high-speed i/o interface 344, and high-speed i/o interface 344 and main process equipment 346 are associated.
In one embodiment, main process equipment 346 comprises an operating system, and this operating system allows the user to give the variable memory block of HDDB 352 allocated size from the volatile memory 350 of main process equipment 346.In another embodiment, volatile memory 350 is distributed automatically, and/or is assigned with memory block fixed-size, that can allow HDDB 352 use.
With reference now to Fig. 6,, the figure illustrates a kind of from volatile memory 350 storages of main process equipment 346 and the method for retrieval hard drive buffer data.The method starts from step 355.In step 356, control has determined whether a request, requires memory buffer unit data in the HDD impact damper.If the result is a "Yes", control proceeds to step 358 so, and has determined whether a request, requires memory buffer unit data in main frame HDDB.If the result of step 358 is a "No", controls so buffer data is stored in the HDD impact damper 332 in the HDD SOC 302.If the result of step 358 is a "Yes", just pass through high- speed interface 338 and 344 in step 364 control so, and buffer data is sent among the main frame HDDB 352, and step 356 is returned in control.
If the result of step 356 is a "No", is controlled at step 366 so and has determined whether a request, the buffer data that requires retrieval to store as the HDD buffer data.If the result of step 366 is a "No", step 354 is returned in control.If the result of step 366 is a "Yes", is controlled at step 370 so and determines whether buffer data is stored among the main frame HDDB 352.If the result of step 370 is a "Yes", just be controlled at step 374 so by high- speed interface 338 and 344, and from main frame HDDB 352 retrieval HDD buffer datas.
As skilled in the art will understand, HDD SOC 302 provides dirigibility, can both be accomplished thereby allow the main process equipment that uses or do not use SATA interface and mainframe memory to carry out the HDD buffering use.
Comprise a HDD SOC and a bridging chip according to a kind of system of the present invention, can in enterprise uses, use.Described HDD SOC also can be used to desktop application.With reference now to Fig. 7 and 8,, desktop/HDD SOC of enterprise 450 can be respectively applied for desktop application 452 and enterprise uses 454, to reduce cost.Desktop/HDD SOC 450 of enterprise communicates by letter with main process equipment 346.Desktop/HDD SOC of enterprise 450 optionally utilizes the volatile memory of main process equipment 346, as HDDB 352 described above.
In Fig. 8, desktop/HDD SOC of enterprise 450 communicates by letter with storer 462 with bridging chip 460 via SATA interface 464.Storer 462 can be DRAM or other low delay memories.Bridging chip 460 is carried out the conversion of SAS/FC to SATA.HDD SOC 450 uses the software protocol of similar ATA, with distributing buffer device storage demand between storer 486 and storer 462.Usually, when exceeding the capacity of the storer 486 related, just use impact damper 462 with HDD SOC 450.Other technology that are fit to can be used to determine the distribution and the use of buffer stores.
In some embodiments, processor can be used to enterprise's application and senior desktop application faster, and can be used to desktop application and enterprise's application cheaply than the processor of low velocity.Identical SOC is used for the ability that desktop and enterprise use, make the overhead provision that is associated with desktop application advantage can with use the general advantages that is associated with enterprise than low capacity.In addition, because identical SOC can be used to this two kinds of application, so in the stock of these application, only need SOC of storage.
With reference now to Fig. 9,, desktop/HDD SOC 450 of enterprise communicates by letter with main process equipment 346.When needs, desktop/HDD SOC of enterprise 450 just optionally utilizes HDDB 352 as buffer memory, as mentioned above.When the extra RAM of needs was used to cushion, desktop/HDD SOC of enterprise 450 was just by high- speed interface 344 and 490, with data transmission to the HDDB 352 of the volatile memory 350 that is arranged in main process equipment 346 or receive data from HDDB 352.As skilled in the art will understand, can use the buffer memory 486 on desktop/HDD SOC450 of enterprise and the HDDB 352 of main process equipment 346, greatly increase the dirigibility of desktop/HDD SOC of enterprise 450.In addition, by further comprising the impact damper 486 on desktop/HDD SOC of enterprise 450, desktop/HDD SOC of enterprise 450 also can be used to not enable in the application of HDDB 352.
With reference now to Figure 10,, shown desktop/HDD SOC of enterprise 450 among the figure.Desktop/HDD SOC of enterprise 450 comprises processor 474, hard disk controller (HDC) 478, read/write channel circuit 482, storer 486 (its can be implemented on the chip and/or chip outer) and high-speed interface 490.Described storer can be low delay memory, such as DRAM or other low delay memories.Storer 486 can comprise the 1-T DRAM storer of embedding.High-speed interface 490 can be the SATA interface (shown in Fig. 7 and 9) of communicating by letter with the main process equipment 424 in the desktop application, or the bridging chip shown in Fig. 8 and 10 460.Bridging chip 460 comprises SAS/FC/ data processor 500 and SATA interface 504.As shown in the figure, storer 462 can be on chip and/or outside the chip.Storer 462 can be low delay memory, such as DRAM or other low delay memories.SAS/FC/ data processor 500 is communicated by letter with business equipment 232 with 251 via interface 506. Interface 506 and 251 can be that SAS/FC interface and business equipment 232 can be servers.
Some main process equipment can't be handled Host Based memory buffer for HDD SOC now.In other words, between old business prototype and new business prototype, there is a transition period.In old business prototype, main process equipment is not supported the driver of Host Based buffering, and HDDSOC and/or MCM have enough memory buffer and support the HDD operation.In new business prototype, HDD SOC and/or MCM have very little FIFO storer, and main frame has the driver of supporting Host Based buffering.Embodiments of the invention can be finished the conversion between new and old business prototype.
With reference now to Figure 11,, the HDD SOC 600 that designs for Host Based buffering generally includes a very little storer 602, and it typically only is used for the FIFO purpose.Storer 602 typically has the capacity less than 1MB, and for example some HDD SOC 600 comprises the storer of about 32kB.Main frame 604 comprises storer 610, and such as the SATA shown in the figure but be not limited to SATA, storer 610 is supported Host Based buffering by high-speed interface 612.As these HDD SOC 600 with when not supporting the main frame 604 of Host Based buffering to use together, owing to do not support that the capacity of storer 602 of high speed operation is little, so system performance significantly reduces.
With reference now to Figure 12 A and 12B,, the HDD SOC640 of low cost/performance is not designed for Host Based buffering, and it typically uses greater than 4MB and less than the storer 642 of 64MB.For example can use the storer of 16MB.The HDD SOC640 of more expensive/performance typically uses the storer 646 more than or equal to 64MB.
With reference now to Figure 13 A and 13B,, comprise storer 652 according to HDD SOC 650 of the present invention, and do not have external interface to be used for extra storer.Storer 652 can be DRAM and the capacity with 16MB.Optionally enable Host Based buffering according to HDD SOC 650 of the present invention.For the application 654 of lower cost/performance, HDD SOC 650 utilizes storer 652, and the Host Based buffering with main frame 658 is then disabled, as shown in FIG. 13A.In the application 660 of higher cost/performance, HDD SOC 650 utilizes storer 652, and Host Based buffering is activated, shown in Figure 13 B.
One of benefit of this scheme is the external pin that can eliminate on the HDD SOC 650 that is used for memory expansion.Therefore can use less matrix and reduce manufacturing cost, this is because solder joint cost for making is higher (particularly for CMOS≤90nm).Solder joint also requires electrostatic discharge (ESD) protection (ESD), and this has also increased manufacturing and design cost.
With reference now to Figure 14 and 15,, for HDD MCM, solder joint can be made forr a short time, and this causes less concern ESD.In addition, a single matrix can be used to HDD MCM does not have the application of local HDD storer with processing, and is used to have the application of local HDD storer.For example, HDD MCM 700 can comprise that HDD SOC 702 and storer 704 are used for desktop application.Identical HDD SOC 700 can be used to enterprise and use in 710, no matter whether uses storer 706.In the case, just HDD SOC 702 uses high-speed interface 712 as SATA, be connected to the storer 714 related, shown in above-mentioned accompanying drawing with bridgt circuit 718.
Be understandable that if desired, HDD SOC 450,460 and 302 can be packaged into multi-chip module.Though embodiments of the invention are described in conjunction with magnetic-memory system, the technician will be understood that the present invention also can be in conjunction with optical storage and/or other read-only datas and/or read/write system use.Those skilled in the art can understand broad principles of the present invention from aforementioned description now and can realize by various forms.Therefore, though the present invention describes in conjunction with the specific examples here, true scope of the present invention should be so not limited, because after research accompanying drawing, instructions and claim, other are revised for the technician conspicuous.
Claims (10)
1. circuit that is used for memory device comprises:
One first high-speed interface;
One memory controller, it is communicated by letter with described high-speed interface; With
One impact damper, it is communicated by letter with described memory controller, wherein said memory device generates during operation and stores relevant buffer data, and wherein said memory controller is by described high-speed interface, the described buffer data relevant with storage optionally is stored at least one described impact damper, and/or transmits and receive the described buffer data relevant with storage.
2. circuit as claimed in claim 1, wherein said first high-speed interface comprises that the serial advanced technology attachment interface is an ata interface.
3. circuit as claimed in claim 1 further comprises:
One processor, it is communicated by letter with described memory controller;
One main shaft/VCM driver, it is communicated by letter with described memory controller; With
One read/write channel circuit, it is communicated by letter with described memory controller.
4. circuit as claimed in claim 3 further comprises a memory module, and this memory module comprises:
One storage media disk, it stores data;
One Spindle Motor, it rotates described storage media disk, and itself and described main shaft/VCM drive communication; With
One read/write arm, it is to described storage media disk read and write data, and it is communicated by letter with described read/write channel circuit.
5. system, it comprises circuit as claimed in claim 1, and further comprises a main process equipment, this main process equipment described memory device is transmitted and receives described with store relevant buffer data.
6. system as claimed in claim 5, wherein said main process equipment comprises:
One second high-speed interface, it is communicated by letter with described first high-speed interface; With
One volatile memory, at least a portion storage of wherein said volatile memory is from the described of the described memory device buffer data relevant with storage.
7. system on chip, it comprises circuit as claimed in claim 1.
8. multi-chip module, it comprises circuit as claimed in claim 1.
9. a system on chip (SOC) comprises circuit as claimed in claim 3.
10. multi-chip module, it comprises circuit as claimed in claim 3.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US58225904P | 2004-06-23 | 2004-06-23 | |
| US60/582,259 | 2004-06-23 | ||
| US10/926,486 | 2004-08-19 |
Related Child Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510079673 Division CN1869911A (en) | 2004-06-23 | 2005-05-27 | System comprising host computer and memory controller |
| CN 200510079675 Division CN1869913A (en) | 2004-06-23 | 2005-05-27 | Memory circuit comprising SATA interface and remote buffer |
| CNB2005100796746A Division CN100483325C (en) | 2004-06-23 | 2005-05-27 | Bridge connecting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1713126A true CN1713126A (en) | 2005-12-28 |
| CN100428129C CN100428129C (en) | 2008-10-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100730626A Expired - Fee Related CN100428129C (en) | 2004-06-23 | 2005-05-27 | Disk drive system on chip with integrated buffer memory and support for host memory access |
| CN 200510079675 Pending CN1869913A (en) | 2004-06-23 | 2005-05-27 | Memory circuit comprising SATA interface and remote buffer |
| CNB2005100796746A Expired - Fee Related CN100483325C (en) | 2004-06-23 | 2005-05-27 | Bridge connecting circuit |
| CN 200510079673 Pending CN1869911A (en) | 2004-06-23 | 2005-05-27 | System comprising host computer and memory controller |
Family Applications After (3)
| Application Number | Title | Priority Date | Filing Date |
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| CN 200510079675 Pending CN1869913A (en) | 2004-06-23 | 2005-05-27 | Memory circuit comprising SATA interface and remote buffer |
| CNB2005100796746A Expired - Fee Related CN100483325C (en) | 2004-06-23 | 2005-05-27 | Bridge connecting circuit |
| CN 200510079673 Pending CN1869911A (en) | 2004-06-23 | 2005-05-27 | System comprising host computer and memory controller |
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| CN (4) | CN100428129C (en) |
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| JP6924026B2 (en) * | 2016-12-19 | 2021-08-25 | シナプティクス インコーポレイテッド | Semiconductor devices, human interface devices and electronic devices |
| TWI668569B (en) * | 2018-03-14 | 2019-08-11 | 群聯電子股份有限公司 | Method for configuring host memory buffer, memory storage apparatus and memory control circuit unit |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE520102C2 (en) * | 1998-05-13 | 2003-05-27 | Axis Ab | Application-specific integrated circuit and transceiver circuit |
| US6871257B2 (en) * | 2002-02-22 | 2005-03-22 | Sandisk Corporation | Pipelined parallel programming operation in a non-volatile memory system |
| JP2003330872A (en) * | 2002-03-04 | 2003-11-21 | Yec:Kk | Hard disc connecting device |
| US20030227703A1 (en) * | 2002-06-06 | 2003-12-11 | Netezza Corporation | Hard disk drive with application-specific components |
| CN2616939Y (en) * | 2003-04-29 | 2004-05-19 | 华硕电脑股份有限公司 | Bridging circuit board |
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2005
- 2005-05-27 CN CNB2005100730626A patent/CN100428129C/en not_active Expired - Fee Related
- 2005-05-27 CN CN 200510079675 patent/CN1869913A/en active Pending
- 2005-05-27 CN CNB2005100796746A patent/CN100483325C/en not_active Expired - Fee Related
- 2005-05-27 CN CN 200510079673 patent/CN1869911A/en active Pending
Also Published As
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| CN1869912A (en) | 2006-11-29 |
| CN1869911A (en) | 2006-11-29 |
| CN100483325C (en) | 2009-04-29 |
| CN100428129C (en) | 2008-10-22 |
| CN1869913A (en) | 2006-11-29 |
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