CN1711674A - Two stage power conversion circuit - Google Patents

Abstract

A power conversion circuit is provided. The circuit includes an isolated board mounted power module operable to convert a nominal input voltage into an intermediate bus voltage; the board mounted power module being unregulated and controlled in an open-loop; and a plurality of tightly regulated point-of-load converters operable to convert the intermediate bus voltage into respective point-of-load voltages to power a respective number of loads.

Description

Two stage power conversion circuit

Cross reference

The application based on respectively on November 11st, 2002, on December 23rd, 2002, on February 14th, 2003 and on June 9th, 2003 submit to (respectively according to IR-2412 PROV, IR-2412 PROVII, IR-2412PROV III and IR-2412 PROV IV) the 60/425th, 422,60/436,316,60/447,635 and 60/477, No. 311 U.S. Provisional Applications, and require their priority.The disclosed content of above-mentioned application is incorporated the application into as a reference.

Invention field

The present invention relates to circuit for power conversion, for example the two stage power conversion circuit that in network and communications applications, uses.

Background information

In the current information age, network and communications applications increase day by day to the serious hope of inromation bandwidth.Occurred the increasing demand of service quality (QoS) is maximized with integrality that guarantees data better and the time (up-time) that system is normally moved along with the increased requirement of bandwidth.To achieve these goals, often use intelligent Route Selection (intelligent routing) management.For example, aspect the allocation of packets Route Selection, data flow is reassembled as little packet, and each little packet is routed to the final destination by independent data path on the way, and in this final destination, packet is reassembled as original data stream at last.Such Route Selection can only realize via intricate processing data packets, and this will need speed NPUs ﹠amp faster and with better function; ASICs.

Growth to the data processing demands has influenced the design that internal hardware designs without doubt, especially carries at plate aspect (on-board) power division field.Because the standard size of communication board (board) remains unchanged relatively, so along with the design in future need be increased to increasing processor on the plate, power distribution system must be realized in the space of more and more reduction.Simultaneously, the increase of number of components always increases power consumption.In order power supply to be installed to less space and to satisfy the power demand that increases, power distribution design should be optimised to guarantee efficient.Design more effective power supply and produce littler loss and so less heat.

Many current networks and communication system are used the power architecture that receives the specified input of 48V from the AC/DC rectification module of integral body.This 48V input is specified input, but various systems will accept the power input in the certain limit on the either side of rated value.For example, the universal telecommunication voltage range is from 36Vin to 75Vin, and ETSI (European Telecommunication Standard input) voltage range is from 36V to 60V.Other system is operation in 48V bus+/-10% through adjusting (regulated).No matter use any power distribution method, input voltage should and have cost-efficient mode as far as possible with the most effective electrical efficiency and distribute to the point of load (point-of-load).

In order to satisfy these harsh more demands, two-stage power conversion is becoming and is being used for the new standard that plate carries power delivery.Traditionally, (isolated) power converter 105a of the isolation of a plurality of being called as " chunk (bricks) " ..., 105n-1,105n are utilized for such as the various low-voltage loads on the circuit board of computer motherboard power are provided, as shown in Figure 1.The periphery output of reduced-current is by via POLs 110a...110n the middle power conversion that one of above-mentioned " chunk " produces being supplied.

Then, make great efforts increasing aspect the simplification and flexibility that plate carries power distribution design, be used to produce intermediate bus voltage through the full transducer of adjusting, then, this intermediate bus voltage is converted into point of load voltage via point of load power converter (POLs).For example, in a kind of scheme, use the independent specified input of isolating converter general-48Vin to convert 3.3 volts intermediate bus voltage to.This intermediate bus voltage is provided directly to the load that needs most power on the plate, to the less load of power demand then via separately POL transducer received power.In another kind of scheme, as shown in Figure 2, specified-48V is converted into the intermediate bus voltage 205 of 12V via the transducer 210 of single isolation.Then, this intermediate bus voltage 205 is via each POLs 215a, and 215b, 215c..., 215n are converted into various point of load voltages.For maximize throughput (throughput) efficient and minimize the cost of arbitrary two-step scheme, each power conversion stage must be by optimization carefully.Yet, to compare with the power distribution design of the transducer that uses a plurality of isolation, the efficiency of throughput of these schemes is lower usually.

Summary of the invention

The objective of the invention is in the power demand growing in satisfying current many application, by being provided at the deficiency that power distribution design that cost and aspect, space have the less assembly of use of efficient overcomes traditional two stage power allocative decision.In order to realize this purpose, exemplary of the present invention has been utilized a kind of like this fact,, when using the POL transducer of closely adjusting (tightly regulated), accurately controls intermediate bus voltage not necessarily with the transducer of isolating that is.On the contrary, by just obtaining effective performance according to the adjustment mode open loop operation transducer of not adjusting (unregulated).

By the DC bus converter of isolating with unadjusted mode open loop operation with 50% duty factor; control required control of above-mentioned power transfer and circuit design and become very simple and efficient, this is because open-loop design does not need the complicated closed-loop control and the excess voltage protection of the power conversion designs of traditional tight adjustment.Therefore, this control circuit can be realized with single IC for both in little space.Use minimized voltage and current stress (stresses) to realize power conversion performance, so just can realize the more effective power MOSFET s (mos field effect transistor) that has than low quality factor (FOMs).And, by allow to use simply, self-driven secondary circuit of synchronous rectification efficiently, fixing 50% duty factor has improved reliability, makes the demand that input and output are filtered reach minimum simultaneously.

In order to be controlled at the simple and novel open loop controlling schemes of introducing herein, two exemplary integrated circuit controllers are provided, one is used for semi-bridge convertor, and another is used for full-bridge converters.(for example can be used within the specific limits according to exemplary half-bridge converter of the present invention, in the scope of 60-160W) the specified input power supply of conversion, and can be in the scope internal conversion rated power input of for example 120-160W according to full-bridge converters of the present invention.Because fixing duty factor, the product of output voltage and specified input voltage and factor K is proportional.For semi-bridge convertor of the present invention, K can for example equal 1/2 turn ratio divided by transformer.Corresponding full-bridge converters of the present invention, K can for example equal 1 turn ratio divided by transformer.Therefore, for output voltage was selected, full-bridge topologies provided greater flexibility.

Brief description of the drawings

Fig. 1 is the block diagram that shows a kind of traditional two-stage power conversion architecture;

Fig. 2 is the block diagram of the traditional two-stage power conversion architecture of demonstration another kind;

Fig. 3 is the block diagram that shows first exemplary power converter bodies architecture of the present invention;

Fig. 4 is the exemplary power change-over circuit that plate carries power model that is used for of the present invention;

The curve chart of Fig. 5 shows the idle time of half-bridge driver IC of the present invention;

Fig. 6 is the block diagram of the half-bridge driver IC among Fig. 4;

The view of Fig. 7 shows the front and back of exemplary power change-over panel of the present invention;

The curve chart of Fig. 8 shows power conversion efficiency and the relation of exporting load current;

Fig. 9 is another exemplary power change-over circuit that plate carries power model that is used for of the present invention;

Figure 10 is the curve chart that shows abrupt change waveform (hiccup waveform);

Figure 11 shows the half-bridge driver IC that is used for allocation plan 4 so that it operates in the method for self-oscillation pattern or synchronous mode.

Describe in detail

Referring now to Fig. 3, wherein as can be seen according to first exemplary half-bridge 2-level power conversion architecture 300 of the present invention.This power conversion architecture 300 comprises that the unadjusted plate with the single isolation of open loop approach operation carries power model (Board Mounted Power Module) (BMP) 305.BMP 305 can operate specified input voltage 320 is converted to intermediate bus voltage 325.Then, intermediate bus voltage 325 is fed to the different point of load (POL) transducer 310a, 310b..., 310n, point of load transducer 310a, 310b..., 310n converts intermediate bus voltage 325 to each point of load voltage 330a, 330b... 330n provides power to be used to load (not shown) different on the plate.

Referring now to Fig. 4, exemplary half-bridge converter circuit 405 of in the BMP of Fig. 3 power model 305, using as can be seen wherein.This half-bridge converter circuit 405 comprises main open-loop inversion circuit (inversion circuit) 410, main biasing circuit 430, secondary rectification and filter circuit 425 and secondary biasing circuit 420.

Main open-loop inversion circuit 410 comprises have end points (CS), (CT), (G), (LO), (Vb), (HO), (Vs) and main half-bridge controller IC (integrated circuit) 415 (Vcc).Diode D1 is connected between the end points (Vb) of Vdd and controller IC 415; Resistance R 1 is connected between the end points (CT) of Vdd and controller IC 415; Capacitor C 1 is connected between the end points (CS), (G) of Vdd and controller IC 415; Capacitor C 2 is connected between the end points (CT) and ground of controller IC 415, and capacitor C 2 also is connected to the end points (CS) of controller IC 415, (G); Capacitor C 3 is connected to the end points (Vb) of controller IC 415, (Vs) between; And end points (Vcc) is connected Vdd.Main open-loop inversion circuit 410 also comprises power MOSFETS M1, M2 (for example, two IRF6603 30V n raceway groove DirectFET (directly welded field-effect transistor) power MOSFETS, it has the gate drive voltage of the bias voltage that for example is clamped to 7.5 volts), power MOSFETS M1, M2 mode with half-bridge configuration between 48 volts of specified inputs 320 and ground is joined to one another at node N1 place, and node N1 also is connected to the end points (Vs) of controller IC 415.MOSFETS M1, the grid of M2 are connected respectively to end points (HO), (LO).Capacitor C 5 that is connected in series and C6 and capacitor C 4 and be in half-bridge MOSFETS M1 between 48 volts of specified inputs 320 and the ground connection, M2 is connected in parallel.Main winding I1 is connected between the end points (Vs) of node N2 and controller IC 415.

For satisfying electric and heat efficiency demand to keep the little comprehensive solution area of coverage (footprint) and to keep simultaneously for the minimum component count, the selection of MOSFET is crucial.Power MOSFETS M1, M2 can comprise MOSFET technology of future generation, and can be configured to the mode of half-bridge configuration work with half-bridge controller IC 415.The DirectFET encapsulation can also be used to realizing low comprehensive conducting state (on-state) impedance from eliminating encapsulation impedance (packaging resistance) in fact with this.And because DirectFET technology is used Plastic Package, therefore when adopting end face cooling (top-side cooling), DirectFET MOSTFETS is very effective.Main biasing circuit 430 comprises two FET encapsulation 435 (for example, IRF7380n channel fet s), and it contains main biasing MOSFETS M3, M4; The resistance R 2 that between 48 volts of specified inputs 320 and MOSFET M3, connects in parallel, R3; The resistance R 4 that between 48 volts of specified inputs 320 and MOSFET M4, connects; The Zener diode D4 that between resistance R 4 and ground, is connected in series, D5; The diode D3 that between node N3 and Vdd, connects; Be connected to the diode D2 of MOSFET M4; And be connected main biasing winding I2 between diode D2 and the ground.In this way, the linear regulator of primary side bias by starting, then the transformer from steady state obtains.

Secondary rectification and filter circuit 425 comprise the magnetic-coupled auxiliary winding I3 with the main winding I1 of main open-loop inversion circuit 410.Auxiliary winding I3 is connected at node N4 place the MOSFETS M5 of coupling mutually, between the M6.Resistance R 5 and capacitor C 7 and diode d6 coupling in parallel mutually, diode d6 is connected with drain electrode end with the source of MOSFET M5 in parallel.Similarly, resistance R 6 and capacitor C 8 are in parallel with diode D7 by the ground that is coupled mutually, and diode D7 then is connected with drain electrode end with the source of MOSFET M6 in parallel.M5, the grid node of M6 passes through resistance R 7 separately, and R8 is connected respectively to node N4.Inductance coil I4 is connected to center tap node N5, and capacitor C 9, and C10, C11 are connected between inductance coil I4 and the node N4 parallel with one anotherly.Secondary rectification and filter circuit 425 also dispose two secondary MOSFETS M7, M8.MOSFETS M7, the grid node of M8 is connected to each other.MOSFETS M7, the source node of M8 is connected respectively to MOSFETS M5, the grid node of M6, and MOSFETS M7, the drain node of M8 is connected respectively to MOSFETS M6, the drain node of M5.The MOSFETs M7 of secondary side, M8 can use (for example) IRF6603 DirectFETMOSFETs to realize, and can dispose with the self-device synchronous rectification topological structure.

Secondary biasing circuit 420 comprises the magnetic-coupled secondary biasing winding I5 with the main biasing winding I2 of main biasing circuit 430.Diode D8, D9 is connected in series mutually between node N4 and N6; Capacitor C 12 is connected to node N7; Biasing winding I5 is connected between capacitor C 12 and the node N4; Resistance R 8 is connected between node N6 and N4 with Zener diode D10; Capacitor C 13 and resistance R 9 are connected in parallel between the grid of M8 at node N4 and MOSFETS M7.In this manner, secondary biasing circuit 420 is designed to allow the output of two bus converters to be connected in parallel, and each bus converter is with the specified input voltage operation of difference.Like this, even if secondary biasing circuit 420 still can continue operation when allowing in 405 two bus converters of half-bridge converter circuit one to break down.

Referring now to Fig. 7, wherein as can be seen according to the front and back of exemplary power plate 705 of the present invention.This power amplifier board can be in the profile of 1/8 transducer BMP to have the 8V output voltage transmission 150W that is higher than 96% efficient.Compare with traditional power converter full adjustment, that plate carries, it has efficient that exceeds 3-5% and the size that is lower than 50%.For the power consumption of minimum printed circuit board (PCB), power amplifier board 705 can have the multi-layer PCB structure, for example 8 layers of PCB structure.Its top layer and the bottom can comprise the copper of (for example) 2oz (ounce), its interior six layers copper that can comprise (for example) 4 ounces.Power amplifier board 705 also can comprise the transformer with flat PQ core (core), and it provides voltage transitions and the isolation between main open-loop inversion circuit 410 and secondary rectification and filter circuit 425.The magnetic core that is used for transformer can be selected according to maximum input voltage and frequency.Can adopt the FR3 material, because it has low consume under high frequency.Very little air gap can be provided in the transformer to reduce master MOSFETs M1, the deadline of M2 under underloaded situation.Little outputting inductance with 160nH of 1 millimeter air gap can be used to pulsation with output and input current and be constrained to and be lower than four amperes.

Half-bridge controller IC 415 can be operated to be used to provide and be used for master driver MOSFETS M1, high side and the low side drive signal of M2 (its have 50% duty factor and the outer member of minimum number).The door driving force of half-bridge controller IC 415 is optimised directly to drive power MOSFETS M1 of new generation, M2 under the situation of additional actuators or buffer.The specified input voltage 320 of high side can be up to for example 100V, even the exemplary circuit of Fig. 4 adopts the specified input voltage of 48V to come executable operations.Therefore, this architecture allows wide specified input voltage range (for example between 24V and 48V), thereby can be used for telecommunications, network and computing application.And primary side bias voltage can be at the range changing of for example 10-15V with further optimized circuit performance.

Pulse width difference between high side and the low side drive signal should be less than predetermined thresholding, for example less than 25ns, and unbalance with the magnetic flux that may need in some applications to prevent to pay close attention to.Switching frequency between high side and the low side drive signal and idle time can change by the value of adjusting resistance R 1 and capacitor C 2, to be used for different application.Switching frequency is determined by following formula:

$f_s=\frac{1}{2R_1{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="A20038010303800231.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}$

External resistance R1 and capacitor C 2 have also determined the idle time between high side and the low side drive signal.Referring now to Fig. 5, therefrom can see capacitor C 2 given the value of the resistance R 1 under the situation of specific capacitance values and the graph of a relation between idle time.Should be longer than master MOSFETSM1 idle time, and the deadline of M2 is to prevent breakdown current.Can estimate by following formula the deadline of main power MOSFETS:

$t_{\mathrm{off}}=\frac{Q_{\mathrm{gd}}+Q_{\mathrm{gs}2}}{I_g}$

Wherein, Qgd is the gate-to-drain electric charge (that is, " Miller (Miller) electric charge ") of MOSFET, and Qgs2 is back thresholding (post-threshold) gate charge, and Ig is a driver current.

In the middle of the process of idle time, secondary MOSFETS M7, the body diode of M8 (bodydiode) conduction.Therefore, should be set to idle time short as much as possible so that the maximization of efficient wants also simultaneously to be master MOSFETS M1 that M2 provides time enough, so that under the operating condition of worst case it is ended.

Referring now to Fig. 6, the more detailed details of the exemplary half-bridge controller IC 415 of Fig. 4 as can be seen wherein.Entire controller IC 415 is in the bias voltage (for example, 10 to 15 volts) that is produced by biasing module 610 operation down.Half-bridge controller IC 415 comprises under-voltage locking (UVLO) module 605,650 that is assigned to Vcc and Vb respectively.Undervoltage lookout function guarantees that all timing signals are maintained in the standard.Oscillator module 615 provide have 50% duty factor as 555 signal S1.Inner soft start module 630 is guaranteed signal S2, S3, and the duty factor of S4 progressively increases from zero to 50%, weakens inrush current with this in the middle of start-up course.High side driver 655 and low side driver 660 can be via MOSFETS 665,670,675,680 at high side and low side driver signals (HO), provide for example one ampere electric current on (LO).Half-bridge controller IC 415 also comprises the current limit function via current source 640,645 and MOSFETS 690,695.

As mentioned above, half-bridge controller IC 415 can be used to control the DC bus converter with the isolation of the non-adjustment of open loop approach operation, the DC bus converter that for example uses in the two-stage on-board power distribution systems of 48V.Half-bridge controller IC 415 is being optimised aspect performance, degree of simplifying and the cost, and entire controller IC 415 can be integrated into single encapsulation (for example single S08 encapsulation).

Referring now to Fig. 9, wherein be used for the exemplary full-bridge converter circuit of using at the BMP of Fig. 3 power model 305 900 as can be seen.Full-bridge converter circuit 900 comprises main open-loop inversion circuit 910, main biasing circuit 915 and secondary rectification and filter circuit 425.

Main open-loop inversion circuit 910 comprises have end points (CS), (D), (CT), (G1), (LO 1), (Vcc), (VB1), (HO1), (VS1), (G2), (LO2), (VS2), (HO2) and main full-bridge controller IC 905 (VB2).Diode D1 is connected between the end points (VB1) of Vcc and controller IC 905; Diode D2 is connected between the end points (VB2) of Vcc and controller IC 905; Resistance R 1 is connected between the end points (CT) of Vcc and controller IC 905; Capacitor C 1 is connected between the end points (G1) of Vcc and controller IC 905; Capacitor C 2 is connected between the end points (CT) and ground of controller IC 905; Capacitor C 15 be connected the end points (Vb1) of controller IC 905 and (VS1) between; End points (Vcc) is connected to Vcc; Capacitor C 17 and C18 are connected in parallel mutually between 48 volts of specified inputs 320 and the ground; Capacitor C 16 be connected the end points (VS2) of controller IC 905 and (VB2) between.Main open-loop inversion circuit 905 also comprises power MOSFETS M9, M10, M11 and M12 (for example, four IRF6603 30V n raceway groove DirectFET power MOSFETSs).MOSFET M9, M10 and M11, M12 are connected to each other in the mode that the node N9 between 48 volts of specified inputs 320 and ground and N10 sentence full bridge configuration respectively.Node N9 also is connected to the end points (VS1) of controller IC 905, and node N10 also is connected to the end points (VS2) of controller IC 905.MOSFETSM9, M10, M11, the grid of M12 are connected respectively to end points (HO1), (LO1), (HO2) and (LO2).Main winding I7 is connected between node N9 and the N10.

Main biasing circuit 915 comprises: main biasing MOSFETS M15, M16; The resistance R 16 that between 48 volts of specified inputs 320 and MOSFET M15, is connected in parallel, R17; The resistance R 18 that between 48 volts of specified inputs 320 and MOSFET M4, connects; The Zener diode D13 that is connected in series that between resistance R 18 and ground, connects, D14; Be connected to the diode D15 of MOSFET M16; Be connected the main biasing winding 19 between diode D15 and the ground; The resistance R 14 and the capacitor C 22 that between the end points (CS) of controller IC 905 and ground, are connected in parallel mutually; The resistance R 15 and the R13 that are connected in series at the end points (CS) and the node N1 place between the ground of controller IC 905; The resistance R 19 that connects at the end points (CS) of controller IC 905 and (rm); Be connected the diode D16 that is connected in series between node N11 and the ground, D17; Be connected the diode D18 that is connected in series between node N11 and the ground, D19; And the coil I10 that between diode in series D16, D17 and D18, D19, connects.

Secondary rectification and filter circuit 920 comprise the magnetic-coupled auxiliary winding I11 with the main winding I7 of main open-loop inversion circuit 910.Auxiliary winding I11 is connected at node N12 place the MOSFETSM17 of coupling mutually, between the M18.By resistance R 11, R10 is connected to node N12 respectively for MOSFETS M17, the grid node of M18.Inductance coil I8 is connected to center tap node N13, and capacitor C 19, C20 and C21 are connected in parallel mutually between inductance coil I8 and node N12.Secondary rectification and filter circuit 425 also dispose two secondary MOSFETS M13, M14.MOSFETS M13, the grid node of M14 is connected to each other.Zener diode D20 and capacitor C 23 are connected in parallel mutually between the grid node of M14 and the node N12 at MOSFETS M13.Resistance R 12 is connected MOSFETS M13, between the grid node and coil I8 of M14.MOSFETS M13, the source node of M14 is connected respectively to MOSFETS M17, the grid node of M18, MOSFETS M13, the drain node of M14 is connected respectively to MOSFETS M18, the drain node of M17.Secondary side MOSFETs M13, M14 can adopt for example IRF6603 DirectFET MOSFETs realization, and is disposed with the self-device synchronous rectification topological structure.

The full-bridge controller is similar to the half-bridge controller 415 among Fig. 4 with driver IC 905, but has improved current limit function pattern and soft start capacity flexibly.This current limit function has abrupt change (hiccup) pattern, and the abrupt change cycle can be by electric capacity from external control in this pattern.Primary side current is come sensing with the current transformer with high turn ratio (for example turn ratio is 150 to 1).Sensed to the AC current information be subjected to rectification, and then after RC filtering, be provided to the current sense pin (CS) of driver IC 905 as input.

Because sort controller IC 905 is designed to full-bridge circuit, so it provides four gate drive signals to be used for MOSFETS M9, M10, M11 and M12 respectively.This controller is alternately with each branch of duty factor conducting of 50%.The difference of the turn-on cycle between above-mentioned two branches should be less than (for example) 25ns to prevent the unbalance of magnetic flux.Conducting and timeing closing difference between two MOSFETS also should be less than 25ns.

Referring now to Figure 10, wherein showing during the abrupt change pattern at the electric current limit setting is that 21A, current loading are set at the output voltage waveform under the specified input voltage situation of 22A and 48 volts.As shown in figure 10, controller IC 905 is attempted in predetermined period the above-mentioned transducer of conducting once.For example, above-mentioned predetermined period can be configured to (for example) 500ms by the value of adjusting capacitor C 14.

Half-bridge controller IC 415 and full-bridge controller IC 905 all are designed to allow in running frequency (ride frequency) scope and are easy to realize external sync.For this reason, need to remove timing resistor R1, and timing capacitor C2 is connected between IC 415,905 and the external synchronization source, as shown in figure 11.In the self-oscillation pattern, the electric current by external definition resistance R 1 charges to timing capacitor C2.In case the voltage at (CT) of arbitrary IC 415 and 915 end points place is higher than predetermined thresholding, for example be higher than half of IC supply voltage vcc or Vdd, then the inner drive of controller IC 415,905 begins timing capacitor C2 is discharged.After the voltage that end points (CT) is located is lower than predetermined threshold, for example be 1/5th of supply voltage vcc or Vdd, controller IC 405,915 is closed above-mentioned inner drive, and stop discharge to timing capacitor C2, so that begin once more to capacitor C 2 chargings by the electric current of resistance R 1.

In the synchronous mode of operation, external capacitive C2 is coupled to (CT) end points with the rising edge of external synchronization source.As long as the voltage located of end points (CT) is higher than predetermined threshold, half of IC supply voltage for example, then the inner drive of controller 415,905 begins voltage discharge that end points (CT) is located.At the voltage of end points (Ct) during less than predetermined threshold, for example 1/5th of IC 415,905 supply voltages, then IC 405,915 closes above-mentioned driver, and stops timing capacitor C2 is discharged.When negative edge was applied in, the voltage that internal body diodes is located end points (CT) resetted and the voltage of external definition capacitor C 2 is remained on zero volt.After externally the voltage of timing capacitor C2 reached zero, capacitor C 2 had been carried out the preparation of tackling next external positive pulse.In this synchronous mode, the internal driving that only located by end points (CT) idle time and the capacitance of external definition capacitor C 2 decide.

In the self-oscillation pattern, timing resistor R1 can not be too little, thereby in order to limit maximum frequency of operation.Usually, timing resistor R1 should be higher than predetermined value, for example 2K Ω.The resistance value of resistance R 1 is low more, is used for IC415, and (sink current) is high more for the absorption current of 905 internal discharge driver.Because timing resistor R1 is removed in synchronous mode, so can obtain higher frequency of operation.Maximum frequency of operation in the synchronous mode is decided by the power consumption that drives external primary MOSFETS.

Claims (20)

1. circuit for power conversion comprises:

The plate of controlled isolation does not carry power model, and it can be operated converting specified input voltage to intermediate bus voltage, and the plate of described isolation carries power model and is controlled in the mode of open loop; And

The point of load transducer that a plurality of quilts are closely adjusted, it can be operated and be used for converting described intermediate bus voltage to each point of load voltage, thereby provides power for each load.

2. circuit for power conversion as claimed in claim 1, wherein, described plate carries power model and comprises: mutual magnetic-coupled main open-loop inversion circuit, main biasing circuit, secondary synchronous rectification and filter circuit and secondary biasing circuit, described synchronous rectification and filter circuit produce described intermediate bus voltage.

3. circuit for power conversion as claimed in claim 2, wherein, described main open-loop inversion circuit comprises half-bridge controller IC and a pair of MOSFET that is connected in the half-bridge configuration mode, and it is right that described controller IC can be operated alternately to control described MOSFET according to 50% duty factor.

4. circuit for power conversion as claimed in claim 3, wherein, described main open-loop inversion circuit comprises timing resistor and timing capacitor, the idle time of described controller IC and switching frequency are adjusted according to the value of described timing resistor and timing capacitor.

5. circuit for power conversion as claimed in claim 4, wherein, described switching frequency passes through formula: $f_s=\frac{1}{2R_1{C}_2}$ Determine that wherein, fs is described switching frequency, R1 is the value of described timing resistor, and C2 is the value of described timing capacitor.

6. circuit for power conversion as claimed in claim 3, wherein, described MOSFET is to comprising DirectFET.

7. circuit for power conversion as claimed in claim 3, wherein, described half-bridge controller IC can be with at least two kinds of mode operations, and a kind of in the described pattern is the self-oscillation pattern, and another in the described pattern is synchronous mode.

8. circuit for power conversion as claimed in claim 2, wherein, described main open-loop inversion circuit comprises full-bridge controller IC and two couples of MOSFET that are connected in the full bridge configuration mode, and described controller IC can be operated alternately to control described two couples of MOSFET according to 50% duty factor.

9. circuit for power conversion as claimed in claim 8, wherein, described main open-loop inversion circuit comprises timing resistor and timing capacitor, the idle time of described full-bridge controller IC and switching frequency are adjusted according to the value of described timing resistor and timing capacitor.

10. circuit for power conversion as claimed in claim 9, wherein, described switching frequency passes through formula: $f_s=\frac{1}{2R_1{C}_2}$ Determine that wherein, fs is described switching frequency, R1 is the value of described timing resistor, and C2 is the value of described timing capacitor.

11. circuit for power conversion as claimed in claim 8, wherein, described two couples of MOSFET comprise DirectFET.

12. half-bridge power change-over circuit as claimed in claim 8, wherein, described full-bridge controller IC can be with at least two kinds of mode operations, and a kind of in the described pattern is the self-oscillation pattern, and another in the described pattern is synchronous mode.

13. a half-bridge controller IC that uses with circuit for power conversion, described circuit for power conversion comprises: not controlled plate of isolation carries power model, and it can be operated to convert specified input voltage to intermediate bus voltage; Described plate carries power model and is controlled in the mode of open loop; And the point of load transducer closely adjusted of a plurality of quilts, it can be operated and be used for converting described intermediate bus voltage to each point of load voltage, thus for each load provides power, described half-bridge controller IC comprises:

Biasing circuit is used to produce bias voltage to operate described half-bridge controller IC;

Undervoltage lockout circuit, it can operate the voltage with the power supply pin of monitoring described half-bridge controller IC;

Pierce circuit is used to provide the timing signal with 50% duty factor;

Soft starting circuit, the described duty factor that is used to guarantee described timing signal rise to 50% duty factor from 0 step by step, thereby weaken inrush current in the middle of start-up course; And

High side and low side driver are used to provide the MOSFET drive signal to control according to the interconnected a pair of MOSFET of half-bridge configuration mode, and described half-bridge controller IC is alternately controlled described MOSFET according to 50% duty factor.

14. half-bridge controller IC as claimed in claim 13, wherein, described MOSFET comprises a pair of DirectFET.

15. a circuit for power conversion comprises:

The plate of controlled isolation does not carry power model, it can be operated to convert specified input voltage to intermediate bus voltage, the plate of described isolation carries power model and is controlled in the mode of open loop, the plate of described not controlled isolation carries power model and comprises the half-bridge controller IC, described half-bridge controller IC comprises: biasing circuit is used to produce bias voltage to operate described half-bridge controller IC; Undervoltage lockout circuit, it can operate the voltage with the power supply pin of monitoring described half-bridge controller IC; Pierce circuit is used to provide the timing signal with 50% duty factor; Soft starting circuit, the described duty factor that is used to guarantee described timing signal rise to 50% duty factor from 0 step by step, thereby weaken inrush current in the middle of start-up course; And high side and low side driver, be used to provide the MOSFET drive signal to control according to the interconnected a pair of MOSFET of half-bridge configuration mode, described half-bridge controller IC is alternately controlled described MOSFET according to 50% duty factor; And

The point of load transducer that a plurality of quilts are closely adjusted, it can be operated and be used for converting described intermediate bus voltage to each point of load voltage, thereby provides power for each load.

16. circuit for power conversion as claimed in claim 15, wherein, described plate carries power model and comprises: main open-loop inversion circuit, main biasing circuit, secondary rectification and filter circuit and secondary biasing circuit, described main open-loop inversion circuit magnetic coupling is to described secondary rectification and filter circuit, described main biasing circuit magnetic coupling is to described secondary biasing circuit, and described secondary rectification and filter circuit produce described intermediate bus voltage.

17. circuit for power conversion as claimed in claim 16, wherein, described main open-loop inversion circuit comprises timing resistor and timing capacitor, and the idle time of described controller IC and switching frequency are adjusted according to the value of described timing resistor and timing capacitor.

18. circuit for power conversion as claimed in claim 17, wherein, described switching frequency passes through formula: $f_s=\frac{1}{2R_1{C}_2}$ Determine that wherein, fs is described switching frequency, R1 is the value of described timing resistor, and C2 is the value of described timing capacitor.

19. circuit for power conversion as claimed in claim 16, wherein, described MOSFET is to comprising DirectFET.

20. circuit for power conversion as claimed in claim 16, wherein, described half-bridge controller IC can be with at least two kinds of mode operations, and a kind of in the described pattern is the self-oscillation pattern, and another in the described pattern is synchronous mode.

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