CN1710975A - Apparatus and method for reducing wireless communication terminal consumption - Google Patents
Apparatus and method for reducing wireless communication terminal consumption Download PDFInfo
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- CN1710975A CN1710975A CNA2005100260207A CN200510026020A CN1710975A CN 1710975 A CN1710975 A CN 1710975A CN A2005100260207 A CNA2005100260207 A CN A2005100260207A CN 200510026020 A CN200510026020 A CN 200510026020A CN 1710975 A CN1710975 A CN 1710975A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
When system operation reaches a rated frequency, the disclosed method turns off the power supply system of open loop DVS, and turns on the power supply system of closed loop AVS. When system operates under a rated frequency, i.e. if working load is not too large, then DVS and AVS together supply power. Equipment for applying the method includes parts: system processor, power source control unit, power source management unit, clock management unit, and timer. The power source control unit includes hardware executive controller, closed-loop controller, manager for outputting power source, clock manager, and frequency meter. The invention solves disadvantages existed when DVS technique or AVS technique operates solely so as to lower power consumption of system.
Description
[technical field]
The present invention relates to the power management techniques field of wireless communication terminal, particularly a kind of apparatus and method that reduce wireless communication terminal consumption.
[background technology]
In recent years, wireless telecommunications are flourish, and service is set up thereupon and provided to various wirelessmobile communication system.Yet user's mobile terminal apparatus one is to being development trend with compact.Under the restriction of limited bulk and weight, power problems is one of wireless communication apparatus greatest problem always.With GSM mobile handset, the battery of a 3.6V/1000mAh consumes 300mAh in conversation, standby consumes under the assumed condition of 10mAh, can standby converse 200 minutes in 100 hours.If add that with PDA WLAN (802.11b) carries out mobile network's service, at battery electric quantity 1250mAh, resting state power consumption 100mAh uses under the state of WLAN online power consumption 400mAh, can standby use 3 hours in 10 hours.If consider that mobile terminal apparatus can use the different radio interface to come the access heterogeneous network, no matter be that single hand-held device is equipped with multiple radio access interface, or portable terminal has the multi-mode wireless system wafer to be designed, and the multimode service is provided, and power problems will be more serious.
Traditional design to portable mobile termianl product reduction power consumption has many methods, lists the wherein drawback of some method down:
1, in order to reduce power consumption, dormancy or standby mode are turned off the clock of all circuit outside the processor specific part usually.Because the power consumption of CMOS is directly proportional with the signal change frequency, the clock of turning off processor can greatly reduce power consumption.Even but system is operated under such operator scheme, also the leakage current loss may be arranged still.The Clock gating method is based on a kind of technology that the method for designing that designs the predictability analysis provides low power dissipation design, can reduce the clock power consumption effectively, but, therefore in a particular design, seek suitable gate to liking a complicated problems owing in a typical design, existing a large amount of triggers.
2, if will be by the emulation of instruction set in microprocessor and the microprocessor being measured every instruction power consumption, thereby optimize instruction set and reduce system consumption, then the shortcoming of this method is to know that the error of the details of processor and power consumption that estimates by this method and actual value is 1%-10%.
3, in order to prolong the stream time of battery as far as possible, nearly all processor has all used low core voltage and power saving dormancy mode of operation, makes CPU only consume a spot of electric energy under the little situation of workload.On the other hand, in order to improve the service efficiency of battery, use a large amount of DC/DC supply convertors to obtain high efficient.For further reducing power consumption, the DC/DC transducer can be operated in pulse frequency modulated (PFM) pattern or PWM burst mode usually, and this mode of operation usually can produce audio-frequency noise.
4, the flush bonding processor developer realizes low-power consumption by using a large amount of low-power consumption idle mode and sleep pattern.Now, flush bonding processor will be carried out becoming increasingly complex of task, thereby needs higher performance level.Consequently, the new processor design begins to adopt advanced day by day framework technology, as branch prediction and supposition computing, to reach high-performance.Yet these technology also can enlarge markedly the power consumption of processor.
Consider to reduce the composition that power consumption must at first be learnt about power consumption.
(1) dynamic power consumption
P
sw＝aCV
dd 2f
Dynamic power consumption is to be caused by the electric capacity in the circuit.If C is the electric capacity of cmos circuit, capacitance is the PMOS pipe voltage required from 0 state to the H state and the ratio of electric weight.With an inverter is example, when this voltage is Vdd, is CVdd2 from 0 to H state variation (input) energy needed.Wherein the energy of half is stored among the electric capacity, and second half energy spread is among PMOS.For output, it to 0 process, does not need the charging of Vdd from H, but in the drop-down process of NMOS, can fall second half energy consumption of capacitance stores.If CMOS changes once when each clock changes, then the power that is consumed is exactly CBdd2f, but be not that all CMOS electric capacity all can once be changed (except clock buffer) among each clock saltus step process, so will add a probability factor a at last.Circuit activity factor a representative be, in average time, among the node, within each clock cycle, the probability that this node changed.The power consumption expression formula that finally obtains is: Psw=aCVdd2f.
(2) internal short-circuit power consumption
In the cmos circuit,, at this moment will open simultaneously to NMOS between the ground and PMOS, produce short circuit current at Vdd if condition Vtn＜Vin＜Vdd-|Vtp| (wherein Vtn is the threshold voltage of NMOS, and Vtp is the threshold voltage of PMOS) sets up.In the rising of its output of time ratio that the input of door rises or descends or fall time fast in, the short circuit current phenomenon can be more obvious.In order to reduce average short circuit current, should keep input and output on same edge as far as possible.
In general, the internal short-circuit current power dissipation can not surpass 10% of dynamic power consumption.And if on a node, in the time of Vdd＜Vtn+|Vtp|, short circuit current can be eliminated.
(3) static leakage power consumption
Static leakage falls be diode when oppositely powering up, the leaky that occurs in the transistor.In metal-oxide-semiconductor, mainly refer to injection effect and subphylum limit effect from substrate.These are relevant with technology, and the power consumption that electric leakage is caused is very little, are not the emphasis of considering.
Main power consumption type in the table 1CMOS integrated circuit
| Type formula ratio dynamic power consumption (switching power) Psw=aCVdd
2F 70%～90% internal short-circuit power consumption (internal short-circuit Pint= |
By the improvement of design technology technology, Pint and Pleak can be reduced to negligible degree, thereby Psw also just becomes the principal element of power consumption.Back institute work consumption is optimized major part and is carried out around this formula.Therefore improve the power consumption that each component among the formula Psw=aCVdd2f helps the deflate whole system.Simultaneously thus formula as seen, voltage Vdd is maximum to the contribution of dynamic power.
PowerWise closed-loop adaptation voltage-regulation (AVS) technology of dynamic electric voltage adjustment (DVS) technology of TI and NS is to reduce by two kinds of methods of the dynamic power consumption of system by regulation voltage.
See also Fig. 1, PowerWise closed-loop adaptation voltage-regulation (AVS) technology of NS makes portable equipment dynamically adjust performance and power consumption, battery can be prolonged 25% to 400% service time.AVS dynamically is adjusted to voltage the required floor level of specific operation by a feedback mechanism, adopts rated voltage in high performance mode, then reduces voltage in the low performance pattern, realizes the reduction of power consumption.
See also Fig. 2 again, dynamic electric voltage adjustment (DVS) technology of TI connects into open cycle system with processor and power supply changeover device, dynamically regulates its supply power voltage and frequency by buses such as I2C, to improve power utilization efficient.When allowing to be operated in when being lower than highest frequency, frequency reduces with the decline of voltage.In the DVS system, the supply power voltage value of every kind of operating frequency all is all chip technologies and the required worst-case value of variations in temperature.When system during in the frequency work that reduces, power consumption also significantly descends, because two of F in the power equation and V2 all reduce.
Yet two kinds of technology of DVS and AVS all respectively have it to improve part not to the utmost.
Wherein, the shortcoming of DVS technology maximum is that the DVS method does not have energy-saving effect to constant voltage when system works during at highest frequency.It only is being operated in highest frequency when following, just can be by providing a pair of voltage/frequency to reaching the purpose that reduces power consumption.
The generation of AVS technology is to a great extent just in order to remedy this defective of DVS technology, but it also has the some shortcomings part.According to its operation principle, the performance that needs HPM to come monitoring chip is changeed the information of being handled it by APC then, determines whether need regulation voltage with this, and this process itself is a power consumption process, and a large amount of wait decision-making times has been reduced its treatment effeciency.
[summary of the invention]
The technical problem to be solved in the present invention is to provide a kind of apparatus and method that reduce wireless communication terminal consumption, solves utilization DVS technology and the existing above-mentioned defective of AVS technology separately, has reduced the power consumption of system significantly.
For solving the problems of the technologies described above, the present invention is achieved in that
A kind of method that reduces wireless communication terminal consumption is characterized in that: when system works arrives rated frequency, turn-off open loop DVS electric power system, powered by closed loop AVS; When below rated frequency, working, then can power jointly when promptly operating load is little by DVS and AVS.
Described closed loop AVS detects the voltage margin from ASIC, and adjusts voltage, and making all has minimum operate power on all running frequencies.
When obtaining the suitableeest voltage of system works, described closed loop AVS system is transferred to open loop DVS system with this point compacting, and directly transfer order DVS system also uses this suitableeest voltage.
In the described open loop DVS system, each voltage/frequency pair set of determining all is to write in the system in the mode of hard coded.
The software-driven that customizes in the described system can be imported into the voltage that closed loop AVS system is measured by a special interface, before changing clock frequency, checks stable voltage states (VDD_OK) by timer.
A kind of device of using said method, comprise system processor, power control unit, Power Management Unit, Clock Managing Unit, timer, wherein, power control unit comprises hardware implementation controller, closed loop controller, power supply output management device, timer manager, frequency meter.
Hardware implementation controller in this power control unit comes the timing performance of supervisory control system processor, and the closed loop mechanism of variable voltage system control loop is provided.
This power control unit is handled the information from the hardware implementation controller, and whether decision needs regulation voltage, and the voltage-regulation instruction is given Power Management Unit by the power supply output management device.
[description of drawings]
Fig. 1 is a closed loop AVS apparatus structure block diagram.
Among the figure:
1-system processor (System Processor);
(Advanced Power Controller is called for short: APC) the 2-power control unit;
(Hardware Performance Monitor is called for short: HPM) 21-hardware implementation controller;
22-closed loop controller (Control Loop Processing);
23-power supply output management device (PWI Master);
24-timer manager (Clock Management);
25-frequency meter (Frequency Table);
(Power Management Unit is called for short: PMU) the 3-Power Management Unit.
Fig. 2 is an open loop DVS apparatus structure block diagram.
4-system processor (System Processor);
5-timer (VDD_OK Timer);
6-Clock Managing Unit (Clock Management Unit);
7-follows power supply supply unit (Companion Power Supply Regulator).
Fig. 3 is the structured flowchart of apparatus of the present invention.
10-system processor (System Processor);
(Advanced Power Controller is called for short: APC) the 20-power control unit;
(Hardware Performance Monitor is called for short: HPM) 201-hardware implementation controller;
202-closed loop controller (Control Loop Processing);
203-power supply output management device (PWI Master);
204-timer manager (Clock Management);
205-frequency meter (Frequency Table);
(Power Management Unit is called for short: PMU) the 30-Power Management Unit;
40-Clock Managing Unit (Clock Management Unit);
50-timer (VDD_OK Timer).
[embodiment]
If therefore can in design, use DVS or AVS can make the fixed voltage system obtain obvious energy-saving effect.When the operating frequency of frequency adjustable joint system was lower than maximum rated frequency, DVS can provide the electricity saving and energy saving function.Then performance electricity saving and energy saving effect in fixed frequency system and variable/scalable frequency system of AVS.
When system worked under the scalable frequency, DVS and AVS reached the target that reduces the fixed voltage system power dissipation jointly.AVS can both provide the added advantage that reduces power consumption when all working frequency.If therefore DVS and two kinds of technology of AVS are used in combination and will be very effective energy-conservation means.
A kind of method that reduces wireless communication terminal consumption mainly is to utilize DVS and AVS technology to mutually combine to reduce wireless communication terminal consumption.When system works arrives rated frequency, turn-off open loop DVS electric power system, power by closed loop AVS; When below rated frequency, working, then can power jointly when promptly operating load is little by DVS and AVS.
According to as above method, the invention provides a kind of device that reduces wireless communication terminal consumption, as shown in Figure 3: it comprises system processor 10, power control unit 20, Power Management Unit 30, Clock Managing Unit 40, timer 50, wherein, power control unit 20 comprises hardware implementation controller 201, closed loop controller 202, power supply output management device 203, timer manager 204, frequency meter 205.
Come the timing performance of supervisory control system processor 10 by the hardware implementation controller 201 that is embedded in the closed loop AVS system voltage adjusting territory, and the closed loop mechanism of variable voltage system control loop is provided.Because hardware implementation controller 201 is positioned on the identical chip with the computing system of its monitoring, thereby can provide chip technology compensation and temperature-compensating.The information that Power Management Unit 30 is handled from hardware implementation controller 201, whether decision needs regulation voltage.The voltage-regulation instruction is given Power Management Unit 30 by power supply output management device 203.
Owing to adopt the chip technology of low speed sequential, the ASIC design can be worked under maximum temperature.Typical working temperature and typical chip performance have voltage margin (headroom).The AVS system can detect this surplus, and adjusts voltage, and making all has minimum operate power on all running frequencies.
When obtaining the most suitable voltage of chip this moment, the AVS system is being transferred to the DVS system with this point compacting, and directly transfer order DVS system also uses this voltage.In the DVS system, each voltage/frequency pair set of determining all is to write in the chip in the mode of hard coded.The software-driven that customizes on the chip can be imported into by the voltage of a special interface with the AVS system measurement, before changing clock frequency, must check stable voltage states (VDD_OK) by a timer or other method.
The method of voltage adjustment that this combination had both utilized the AVS system simplification; No longer need the frequency/voltage table, but can monitor kernel inside and outside technology and temperature variations more accurately, and can utilize the DVS open loop to take voltage, frequency that form is powered again by the advantage that standard interface and outside energy management unit (FMU) communicate, then when voltage reduces, frequency also significantly reduces, and then makes power consumption reduce the characteristics that amplitude increases.
A power comparison sheet that uses fixed voltage, DVS technology and AVS technology respectively is provided below:
Measuring condition is 0.13 micron typical chip, room temperature.
Table 2 power comparison sheet
| Frequency (MHz) | Power consumption (standardization) | ||
| ??Fixed?Voltage | ??DVS | ??AVS | |
| ??96 | ??100.0 | ??100.0 | ??51.2 |
| ??72 | ??72.4 | ??72.4 | ??28.6 |
| ??48 | ??50.5 | ??26.4 | ??15.8 |
| ??24 | ??24.3 | ??12.7 | ??8.5 |
| ??12 | ??11.7 | ??6.6 | ??4.8 |
| ??6 | ??6.9 | ??4.6 | ??2.8 |
From this comparison sheet as can be seen, when frequency when 48MHz is following, using the DVS technology than using the used power consumption of fixed voltage has a bigger reduction, but uses the power consumption of AVS technology to reduce at most on the overall performance.
But simultaneously, through measuring the clock delay that uses the AVS technology greater than DVS technology, comparison sheet as follows:
Measuring condition is 0.13 micron typical chip, room temperature.
Table 3 time delay comparison sheet
| Frequency (MHz) | Postpone (s) | |
| ??DVS | ??AVS | |
| ??96 | ??0.0001 | ??0.0004 |
| ??72 | ??0.0023 | ??0.0028 |
| ??48 | ??0.0035 | ??0.0040 |
| ??24 | ??0.0040 | ??0.0048 |
| ??12 | ??0.0052 | ??0.0059 |
| ??6 | ??0.0063 | ??0.0070 |
Through experiment, find after the power consumption after relatively three kinds of technology are used, more than the highest frequency 64MHz of DVS, use the AVS technology fully; And below the frequency, use AVS in conjunction with the DVS technology at this.Though under each fixed frequency scope, the power consumption of AVS is littler than the power consumption of both combinations like this, its total average power consumption then is greater than both in conjunction with power consumption, therefore proves two kinds of technology combinations, can well reach to subtract the consumption purpose.
Table 4DVS, AVS and DVS/AVS are in conjunction with three kinds of technology power comparison sheets
| Frequency (MHz) | Power consumption (standardization) | ||
| ?DVS | ?AVS | AVS is in conjunction with DVS | |
| 96 | ?100.00 | ?51.20 | ?51.2 |
| 72 | ?72.40 | ?28.62 | ?28.6 |
| 64 | ?32.58 | ?18.55 | ?18.61 |
| 32 | ?18.50 | ?10.20 | ?10.25 |
| 16 | ?7.25 | ?6.66 | ?6.67 |
| 8 | ?5.00 | ?4.04 | ?4.02 |
| Average power consumption | ?61.25 | ?29.94 | ?29.81 |
Being preferred embodiment of the present invention only in sum, is not to be used for limiting practical range of the present invention.Be that all equivalences of doing according to the content of the present patent application claim change and modification, all should be technology category of the present invention.
Claims (8)
1, a kind of method that reduces wireless communication terminal consumption is characterized in that: when system works arrives rated frequency, turn-off open loop DVS electric power system, powered by closed loop AVS; When below rated frequency, working, then can power jointly when promptly operating load is little by DVS and AVS.
2, the method for minimizing wireless communication terminal consumption according to claim 1 is characterized in that: described closed loop AVS detects the voltage margin from ASIC, and adjusts voltage, and making all has minimum operate power on all running frequencies.
3, the method for minimizing wireless communication terminal consumption according to claim 1, it is characterized in that: when obtaining the suitableeest voltage of system works, described closed loop AVS system is transferred to open loop DVS system with this point compacting, and directly transfer order DVS system also uses this suitableeest voltage.
4, the method for minimizing wireless communication terminal consumption according to claim 3 is characterized in that: in described open loop DVS system, each voltage/frequency pair set of determining all is to write in the system in the mode of hard coded.
5, the method for minimizing wireless communication terminal consumption according to claim 4, it is characterized in that: the software-driven that customizes in the described system can be imported into the voltage that closed loop AVS system is measured by a special interface, before changing clock frequency, check stable voltage states (VDD_OK) by timer.
6, a kind of application device of method according to claim 1, comprise system processor (10), power control unit (20), Power Management Unit (30), Clock Managing Unit (40), timer (50), wherein, power control unit (20) comprises hardware implementation controller (201), closed loop controller (202), power supply output management device (203), timer manager (204), frequency meter (205).
7, the device of minimizing wireless communication terminal consumption according to claim 6, it is characterized in that: the hardware implementation controller (201) in this power control unit (20) comes the timing performance of supervisory control system processor (10), and the closed loop mechanism of variable voltage system control loop is provided.
8, the device of minimizing wireless communication terminal consumption according to claim 7, it is characterized in that: this power control unit (20) is handled the information from hardware implementation controller (201), whether decision needs regulation voltage, and the voltage-regulation instruction is given Power Management Unit (30) by power supply output management device (203).
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104903816A (en) * | 2013-01-08 | 2015-09-09 | 高通股份有限公司 | Method for performing adaptive voltage scaling (AVS) and integrated circuit configured to perform AVS |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104903816A (en) * | 2013-01-08 | 2015-09-09 | 高通股份有限公司 | Method for performing adaptive voltage scaling (AVS) and integrated circuit configured to perform AVS |
| CN104903816B (en) * | 2013-01-08 | 2019-04-26 | 高通股份有限公司 | For executing the method for adaptive voltage scaling (AVS) and being configured to execute the integrated circuit of AVS |
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Open date: 20051221 |