CN1708903A

CN1708903A - System for reducing leakage in integrated circuits

Info

Publication number: CN1708903A
Application number: CN 200380102092
Authority: CN
Inventors: G·A·乌格哈拉
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2002-10-29
Filing date: 2003-10-29
Publication date: 2005-12-14
Anticipated expiration: 2023-10-29
Also published as: CN100372232C

Abstract

A system for reducing current leakage in an integrated circuit. The system includes a first circuit component and a second circuit component in a path between a high voltage state and a low voltage state, such as ground. A feedback mechanism selectively provides feedback from an output of the second circuit component to an input of the first circuit component to selectively cutoff the path at the first circuit when the path is not cutoff at the second circuit. In a more specific embodiment, feedback mechanism preserves data in the integrated circuit via a multiplexer that selectively enables the feedback when the integrated circuit is in sleep mode. The first and second circuit components are High Voltage Threshold (HVT) CMOS inverters. The feedback path is chosen so that when the feedback path is activated, leakage paths through the CMOS inverters are cutoff.

Description

Reduce the system of leakage in integrated circuits

Background of invention

Related application

The application requires in No. 60/422367 U.S. Provisional Application No. of submission on October 29th, 2002.

Invention field

The present invention relates to integrated circuit.The invention particularly relates to the system that is used to prevent or reduce synchronous digital hierarchy internal leakage during park mode.

Description of related art

Integrated circuit is used in the higher application of various requirement, such as personal computer, cell phone, wrist-watch and finite state machine.This kind application requirements high performance integrated circuit that minimum current is leaked under free time or park mode.Electric current leaks particularly individual problem in moving application, and described mobile application is wished to have than long battery life in these are used such as cell phone, laptop computer and personal digital assistant.

These are used and often use the synchronous digital hierarchy of realizing by integrated circuit.Synchronous digital hierarchy uses synchronised clock correctly circuit operation is sorted.The power consumption of synchronous digital hierarchy and performance depend on power consumption and form the performance of assembly that described assembly is such as latch.Latch is ubiquitous in many modern synchronous systems.Therefore, expect to have the high-speed latches of minimum current leakage and minimum related power consumption.

In order to address the leakage concern, use high voltage threshold values transistor (HVT) usually.The voltage that HVT has relatively high expectations at the transistor gate place is with turn-on transistor, and making has path by transistor.When HVT is in off status, seldom or do not have electric current to pass through transistor.Therefore, HVT has minimum current to leak.Yet the unlatching of HVT is relatively slow.Therefore, mainly use the latch of HVT that excellent leakage characteristics is arranged, but generally slower, this has reduced the performance of whole synchronous digital hierarchy.

Consider in order to solve performance, use low-voltage threshold values (LVT) transistor usually.LVT opens very fast, and needs minimum gate voltage.Yet LVT is general, and leakage is more serious.Therefore, use the latch of LVT and related system to leak more serious usually.

Exist compromise between low leakage and high-performance.Generally, high-performance latch demonstrates high electric current leakage under park mode.The low performance latch shows low the leakage under park mode.

In order to obtain acceptable energy and low the leakage, the engineer has researched and developed a kind of hybrid latch, and it uses the HVT of selectivity placement and the combination of LVT.Unfortunately, in order to obtain acceptable energy and leakage characteristics, these hybrid latch require the synchronised clock dormancy at electronegative potential (sleep low), make clock very low when latch is in park mode, or require the synchronised clock dormancy at high potential (sleep high), make that clock is a high potential when latch is in park mode.

If the design of hybrid latch makes the clock dormancy at high potential, then HVT generally is positioned at the LVT of data path by before the door by door.The latch that produces has longer setting-up time and the short transfer delay of not expecting.Setting-up time is the time delays between the triggering edge of stable and synchronised clock of input.Transfer delay is the time slot between the triggering edge of clock and latch output stable.Transfer delay is commonly called clock Q is delayed time when the d type flip flop latch (time-delay trigger or DQ trigger are otherwise known as) when described, and Q represents latch output.

Long establishing time is to be caused by door by slower HVT.Control LVT must wait for that by the clock signal of door input arrives LVT by door by slower HVT by door, and this causes long establishing time.The minimum transition time-delay is caused by door by quick LVT, and this has minimized LVT by the time-delay between door and latch output.

If the design of hybrid latch makes the clock dormancy at electronegative potential, then LVT generally is positioned at data path HVT by before the door by door.The longer transfer delay that the latch that produces has shorter establishing time and do not expect.Short establishing time be since fast LVT by door.Longer transfer delay is caused by door by slower HVT.

Generally, existence is compromise between establishing time and transfer delay.General hybrid latch require clock or dormancy in high potential or dormancy at electronegative potential, this causes long establishing time or long transfer delay respectively.In addition, require clock or dormancy to limit these latchs at electronegative potential and do not requiring that latch selects the applicability of dormancy in the application of high potential and/or electronegative potential in high potential or dormancy.

Therefore, need the leakage of a kind of system's energy minimization integrated circuit under park mode in the field, and do not jeopardize performance.Also have a kind of demand in addition to relevant high-performance latch, this latch optionally dormancy at high potential or electronegative potential; Have minimum setting-up time and transfer delay; And leak at park mode minimization electric current.

The present invention's general introduction

Needs in the field are satisfied by the system that reduces electric current leakage in the integrated circuit of the present invention.In explanation embodiment, the invention system is applicable to complementary metal oxide semiconductors (CMOS) (CMOS) latch.Described system is included in first circuit unit in the path and second circuit assembly between relative high voltage and relatively low voltage.A kind of mechanism optionally provides the feedback that outputs to first circuit unit input from the second circuit assembly, the path that optionally cuts off the first circuit place when not cutting off the path at the second circuit place.

In specific embodiment more, this mechanism also comprises the mechanism that is used for preserving data in integrated circuit.The mechanism that is used for preservation data in integrated circuit comprises a multiplexer, and it optionally enables feedback when integrated circuit is in park mode.Multiplexer is the 2-1 multiplexer, having displacement input as the control input and have the scanning input and the feedback input.

First and second circuit units are CMOS inverters.The selection of feedback path makes when the activation feedback path, and the high state that occurs in the 2nd CMOS inverter input causes the high state in a CMOS inverter input.Similarly, the low state in the 2nd CMOS inverter input causes the low state in a CMOS inverter input.This is used for cutting off the leakage paths by the CMOS inverter when enabling feedback, such as during following the latch park mode.In explanation embodiment, integrated circuit is principal and subordinate's d type flip flop.

Novel designs of the present invention is to realize by the feedback that outputs to the input of first circuit unit from the second circuit assembly when associated latches or other circuit are in park mode.This has minimized the leakage when park mode, and does not jeopardize the performance of following latch.When latch is in park mode, minimizes leakage under the park mode and got rid of conventional at low leakage and high-performance and compromise between setting-up time and transfer delay by will feed back to master unit from half latch data strategicly.The present invention realized low leakage latches and do not jeopardized performance, and realized short setting-up time and do not jeopardize transfer delay, and vice versa.In addition, clock can or dormancy in high potential or dormancy at electronegative potential, leak or performance characteristics and do not jeopardize.This has increased to add has the present invention to reduce multifunctionality, performance and the leakage characteristics of latch of the system of leakage.

Brief description of drawings

Fig. 1 is the conventional latch of the necessary dormancy of requirement clock at electronegative potential.

Fig. 2 is the latch sequential chart that Fig. 1 of longer transfer delay is described.

Fig. 3 is the system diagram that the minimizing of constructed according to the principles of the present invention is leaked.

Fig. 4 is the high-performance according to principle of the present invention, low leakage latches figure, and this latch can effectively be worked at high potential or when low in the clock dormancy, and has added the system that is used to reduce leakage of Fig. 3.

Fig. 5 is the latch sequential chart of Fig. 4 of short setting-up time of explanation and transfer delay.

Fig. 6 is the latch first alternative figure that comprises Fig. 4 of complex gate realization.

Fig. 7 is the latch second alternative figure that is applicable to the Fig. 4 that uses with diphasic clock.

The present invention describes

Though the present invention describes with reference to the explanation embodiment of application-specific at this, is appreciated that to the invention is not restricted to this.Those of ordinary skill in the field and can visit at this and provide the people of principle can recognize within the scope of the present invention or additional modifications, application and embodiment in the present invention has the field of important use.

The discussion of following conventional principal and subordinate's d type flip flop latch is used for convenient understanding of the present invention.

Fig. 1 is the conventional principal and subordinate d type flip flop latch 10 of the necessary dormancy of requirement clock at electronegative potential.For clear, be omitted from figure such as each known tip assemblies of the power supply utmost point, substrate etc., yet the technical staff of the visit principle of the invention can know and realizes which assembly and how to realize that these assemblies are to satisfy the needs of given application in the field.

Latch 10 comprises and 14 master units of connecting 12 from the unit.Master unit 12 has five inputs, comprises input (SIN) 16, data input (D) 18, displacement input (SHIFT) 20, dormancy input (SLP) 22 and clock input (CLK) 24 of scanning input.Master unit 12 offers from the unit 14 with master unit output 28.14 also receive through the clock signal 26 of anti-phase (inverted) as input and provide data outputs (Q) 30 and scanning output 32 from the unit.

Master unit 12 comprises the first transistor row 34 and transistor seconds row 36, and they are as the selectivity gated inverter, as will be discussed in more detail.The first transistor row 34 comprise first high pressure threshold values (HVT) NMOS (N NMOS N-channel MOS N) transistor T 1, second low-voltage threshold values (LVT) the nmos pass transistor T2, the 3rd LVT PMOS (P-channel metal-oxide-semiconductor) transistor T 3 and the 4th HVT PMOS transistor T 4 from top to bottom.The connection of transistor T 1-T4 makes the 4th PMOS transistor T 4 source electrodes be connected to high-voltage state (Vdd), and this generally provides (not shown) by the dc voltage source electrode.The drain electrode of PMOS transistor T 4 (drain) is connected to the source electrode of the 3rd PMOS transistor T 3.The drain electrode of the 3rd PMOS is connected to the drain electrode of the second nmos pass transistor T2.The source electrode of the second nmos pass transistor T2 is connected to the drain electrode of the first nmos pass transistor T1.The source electrode of the first transistor nmos pass transistor T1 is connected to low-voltage state, such as ground connection.Therefore, if the connection of the first transistor row 34 makes transistor T 1-T4 all for opening, then electric current can flow to low-voltage state from high-voltage state, i.e. source electrode from the source electrode of the 4th PMOS transistor T 4 to the first nmos pass transistor T1.

Transistor seconds row 36 comprise the 5th PMOS transistor T 5, the 6th PMOS transistor T 6, the 7th nmos pass transistor T7, the 8th nmos pass transistor T8 from top to bottom.The source electrode of the 5th PMOS transistor T 5 is connected to high-voltage state Vdd, and drain electrode is connected to the source electrode of the 6th PMOS transistor T 6.The drain electrode of the 6th PMOS transistor T 6 is connected to the drain electrode of the 7th nmos pass transistor T7.The source electrode of the 7th nmos pass transistor T7 is connected to the drain electrode of the 8th nmos pass transistor T8.The all crystals pipe T5-T8 of secondary series 36 is a hvt transistor, and it generally is characterized as low the leakage but the relatively slow opening time.

The displacement of master unit 12 input 20 and dormancy input 22 are imported into or (OR) door 38.The output of OR door 38 is connected to the input of a HVT inverter I1; Arrive the grid of the 4th HVT PMOS transistor T 4 of the first transistor row 34; To transistor seconds row 36 interior the 8th nmos pass transistor grids.The output of the first inverter I1 is connected to the grid of a HVT nmos pass transistor T1 and the grid of the 5th HVT PMOS transistor T 5.

Data input 18 is connected to the door of the 2nd LVT nmos pass transistor T2 and the door of the 3rd LVT PMOS transistor T 3.The input 16 of scanning input is connected to the door of the 6th HVT PMOS transistor T 6 and the door of the 7th HVT nmos pass transistor T7.

The drain electrode of the second nmos pass transistor T2, the 3rd PMOS transistor T 3, the 6th PMOS transistor T 6 and the 7th nmos pass transistor T7 is connected at common node 40.Common node 40 is connected to the input of initial LVT by door 42.

The 3rd column of transistors 44 comprises the 11 HVT PMOS transistor T the 11, the 12 HVTPMOS transistor T the 12, the 13 HVT nmos pass transistor T13 and the 14 HVT nmos pass transistor T14 from top to bottom.The drain electrode of the transistor T 11-T14 of the 3rd column of transistors 44 is connected with source electrode with the drain electrode that source electrode is similar to the transistor T 5-T8 of transistor seconds row 36.The source electrode of the 11 PMOS transistor T 11 is connected to Vdd, and the source electrode of the 14 nmos pass transistor T14 is connected to low-voltage state, such as ground connection.Therefore, if transistor T 11-T14 is in unlatching, then electric current can be relatively freely flows to the ground (or other low-voltage states) at the source electrode place of T14 from the Vdd at the source electrode of T11.

The door of the 12 HVT PMOS transistor T 12 is connected to initially by the LVT NMOS part of door 42 and the anti-phase back clock signal 26 that provides by the 2nd HVT inverter 12.The 13 HVT nmos pass transistor T13 door is connected to the initial LVT PMOS part of passing through door 42 also to clock signal 24 by the output of the 3rd inverter I3, and the described inverter I3 and the second inverter I2 are connected in series.

VLT is connected to the input of the 4th inverter I4 and the drain electrode of the 12 HVT PMOS transistor 12 and the 13 HVT nmos pass transistor T13 by door 42 outputs.When initial during by door 42 conductings, the output by door 42 is connected to common node 40.

The door of the 11 HVT PMOS transistor T 11 and the 14 HVT nmos pass transistor T14 is connected to the output of the 4th inverter I4 and passes through the input of door 46 to the 2nd HVT.The output of the 2nd HVT by door 46 be connected to the 3rd HVT by door 48 first terminal and be connected to the 5th HVT inverter I5 and the input of the 6th LVT inverter I6.The output of the 6th LVT inverter I6 is input to the 7th LVT inverter I7.Q output 30 is represented in the output of the 7th LVT inverter I7.The 6th LVT inverter I6 and the 7th LVT inverter I7 be ground connection or be connected to low-voltage state by afterbody HVT nmos pass transistor T20 optionally.Therefore, have fully high voltage status on the grid of one-level HVT nmos pass transistor T20 in the end, then I6 and I7 only operate as inverter.The door of afterbody HVT nmos pass transistor T20 is connected to the output of the first inverter I1 in the master unit 12.Therefore, Q output 30 is imported in be shifted input 20 or dormancy and is activated when 22 neither ones are high, promptly is activated when two

inputs

20,22 are when hanging down.This has guaranteed that the first inverter I1 is output as height, and this has opened HVT nmos pass transistor T20, has enabled inverter I6 and I7.Afterbody HVT nmos pass transistor T20 helps to reduce when latch 10 is in park mode and leaks.

Threeway move into one's husband's household upon marriage 48 NMOS partly be connected to second by door the PMOS part and the inversion clock signal 26 that provides by the 2nd HVT inverter I2 is provided.Similarly, move into one's husband's household upon marriage 48 PMOS of threeway partly is connected to the second NMOS part by door 46, and the clock signal 24 that provides by the 3rd HVT inverter I3 output is provided the latter.

The output of the 5th HVT inverter T5 is connected to the input of the 8th HVT inverter I8 and the input of the 9th HVT inverter I9.The output of I9 is represented half latch data (IQ) and is connected to move into one's husband's household upon marriage 48 second terminal of threeway.Half latch data (IQ) generally mates the Q output 30 of latch 10.Scanning output (SOUT) 32 represented in the output of the 8th HVT inverter I8.

In operation, latch 10 is limited in dormancy when clock signal 24 is electronegative potential.Suppose latch 10 not dormancy (make dormancy (sleep)=0) or be not shifted (make displacement (shift)=0).Then OR door 38 is output as electronegative potential.The transistor T 1 of the first transistor row 34 and T4 are for opening.Therefore, first rowed transistor 34 is activated as inverter with anti-phase to data input signal 18 and provide the result at common node 40 places.

The transistor T 5 of transistor seconds row 36 and T8 are for closing.Therefore, forbidding is by the inverter of the selective enabling of transistor seconds row 36 realizations.Therefore, scanning input data 16 are not by anti-phase and be transferred to common node 40.

Input data (D) 18 is through anti-phase and be provided at common node 40 places.When clock signal 24 was electronegative potential, initial was to open by door 42.The anti-phase input data at common node 40 places are then by also anti-phase once more by the 4th HVT inverter I4 by door 42.The output corresponding data of the 4th inverter I4 input 18, this input are latched by latch 10 and are represented that master unit exports 28.

When the clock conversion of signals when the high state, first closes by door 42, it has latched data in output place of the 4th inverter I4.In addition, the 2nd HVT opens by door 46, and the 3rd HVT closes by door 48.The data that produce are anti-phase and appear at Q and export 30 places by high speed LVT inverter I6 and I7 then.Anti-phase twice and appear at scanning output 32 places of identical data by HVT inverter I5 and I8.Also anti-phase twice and appear at output place of the 9th inverter I9 as half latch data of identical data by HVT inverter I5 and I9.

The operating characteristics of d type flip flop 10 is described by following transfer function:

Form 1

Original state Q (t-1)	Input D (t-1) 01
Original state Q (t-1)	Input D (t-1) 01	??0	??0????????1 ? ??0????????1
??1		??0
??1		New state Q (t)

There is similar transfer function for scanning input 16 and scanning output 32.Yet 16 of the inputs of scanning input are latched during for high potential in displacement or

dormancy input

20,22.

The clock signal 24 necessary dormancy of latch 10 are at high potential.When clock signal 24 dormancy during at electronegative potential, when the dormancy input 22 to OR door 38 was high potential (1), clock signal 24 was electronegative potential (0).And thereby OR door 38 be output as height.When clock signal 24 was electronegative potential, the 3rd HVT inverter I3 was output as low, and the 2nd HVT inverter I2 is output as height.This makes initial by door 42 conductings; Second closes by door 46; Threeway 48 conductings of moving into one's husband's household upon marriage; And make the 12 PMOS transistor T 12 and the 13 nmos pass transistor T13 of the 3rd rowed transistor 44 close.

When latch 10 dormancy during at electronegative potential (clock signal 24 dormancy are at electronegative potential), there are various leakage paths (being shown in dotted line), comprise first leakage paths 50 from the Vdd of source electrode place of the 11 PMOS transistor T 11; Its 12 PMOS transistor T 12 by closing; Get back to initial LVT by door 42; Arrive ground by the 2nd LVT nmos pass transistor T2 and the first hvt transistor T1 then, described transistor T 1 is for closing.This leakage paths 50 is by two hvt transistors of closing, i.e. T12 and T1, therefore when latch 10 is in park mode (the clock dormancy is at electronegative potential) to pass through the leakage of leakage paths 50 lower.

Have second leakage paths 52 from the Vdd of the 4th HVT PMOS transistor T 4 source electrodes, described transistor T 4 is for closing; This path is by the 3rd LVT PMOS transistor T 3, by the initial door 42 that passes through; Arrive ground by the 13 hvt transistor 13 and the 14 HVT nmos pass transistor T14 then, described transistor T 13 is for closing.The LVT transistor that second leakage paths is flowed through two and closed, promptly therefore T4 and T13 leak lower.

May there be the 3rd leakage paths 54 from the Vdd of the 4th HVT inverter I4; Pass through door 46 by the 2nd HVT that closes; Move into one's husband's household upon marriage 48 by threeway; Arrive ground by the 9th HVT inverter I9 then.The 4th leakage paths 56 flows out from the Vdd of the 9th HVT inverter I9; Pass through door 48 by the 3rd HVT; Pass through door 46 by the HVT that closes; And pass through the 4th HVT inverter I4 to ground.Therefore, the hvt transistor that all leakage paths 50-56 flow through and close, thus minimized leakage.

In the latch 10 of Fig. 1, the necessary dormancy of clock is at electronegative potential, because the initial door 42 that passes through is by the realization of LVT transistor.If clock signal 24 dormancy at high potential, then can cause by initial by door 42 unacceptable leakages.For example, can there be leakage paths from the source electrode Vdd of the 5th HVT PMOS transistor T 5; Pass through door 42 by the LVT that closes; And pass through the 4th HVT inverter I4 to ground.Unique transistor of closing will be the LVT transistor of initial LVT by door 42 in leakage paths.Because the LVT transistor leakage is more, then can cause the leakage of not expecting.May exist by initial additional leakage paths by door 42.

When clock signal 24 during at high potential latch design 10 be limited in dormancy, and when second being that HVT is that LVT passes through door by door 42 initially during by door by door 46.This configuration causes comparatively faster setting-up time because fast LVT by door 42 to import 18 and import in 28 the data path from the data of unit.Yet, because the 2nd HVT opens more slowly by door 46 response inversion clock signals 26, from there are long transfer delaies in 14 input 28 to the Q output 30 of latch 10 from the unit.

In other designs, clock signal 24 must dormancy at high potential, and initially must be embodied as HVT by door, and second must be embodied as LVT by door by door 46 by door 42.Other design features are long setting-up time and relative short transfer delay.

Unfortunately, must dormancy apply the design constraint of not expecting to the system that comprises the latch design that is similar to latch 10 to clock signal 24 in the requirement of high potential or electronegative potential.In addition, requirement is corresponding transfer delay or the establishing time performance parameter of jeopardizing of inverse time second by door 46 to being LVT or HVT by door by door 42 initially.

Fig. 2 is latch 10 sequential Figure 60 of Fig. 1, and longer transfer delay (t is described _d) 70.With reference to figure 1 and Fig. 2, when clock signal 24 was transferred to high state at the place, rising edge of clock pulse 64, the 2nd HVT was by door 46 conductings.In order to latch the high state as data pulse 66 expressions, the pulse 66 of data-signal 18 must keep one subscription settings time of high potential (t in clock signal 24 before clock pulse 64 places are converted to high state _Su) 62.In order to guarantee reliable operation, require minimum setup time.The minimum setup time of the latch 10 of Fig. 1 is because LV is shorter relatively by door 42 fast.Transfer to high state at clock pulse 64 places and export 30 places at Q and the relative longer transfer delay (t of 66 existence of data pulse occurs in clock signal 24 _d) 68.

Clock pulse 64 must have certain minimum clock pulse width 72 to guarantee reliable operation.In data path, use slow HVT to require relatively long clock pulse 72 by door 46.For example, if clock pulse 64 is too short, then slow HVT may not conducting by door 46.Similarly latch (not shown) (wherein clock must dormancy at high potential) can require relatively long setting-up time, short transfer delay and the clock-pulse width of relative broad.

Fig. 3 is 80 figure of system that leak according to the minimizing that the principle of the invention makes up.System 80 goes for various circuit, and wherein said circuit has more than an inverter by its leakage paths of may flowing through.For example, system 80 goes for improving the leakage and the performance characteristics of conventional latch, such as the latch 10 of Fig. 1.

System 80 comprises 2-1 multiplexer (MUX) 82, controller 84, adjunct circuit 88, the first low leakage inverter 92, intervenes circuit (intervening circuitry) 94, the second low leakage inverter 96, additional intervention circuit 98 and the 3rd low leakage inverter 100.MUX82 slave controller 84 receives control input (SHIFT) 20.The one MUX input 86 is from adjunct circuit 88.Adjunct circuit 88 can provide input (SIN) 86 to be scanned the input latch (see figure 1).Perhaps, MUX input 86 can come self-controller 84.The 2nd MUX input (IQ) 90 is from the output of the 3rd low leakage inverter 100.The input of the 3rd low leakage inverter 100 is from adjunct circuit 88, and this can represent the afterbody (see Fig. 1 14) from latch.The output of the 3rd low leakage inverter 100 is also connected to the additional circuit 98 of intervening.Additional intervention circuit 98 is also connected to the output of the second low leakage inverter 96.The input of the second low leakage inverter 96 is connected to intervenes circuit 94, and it also is connected to the output of the first low leakage inverter 92.The input of the first low leakage inverter is connected to the output of MUX82.

The second low leakage inverter 96 is the HVT CMOS inverters from a HVT PMOS transistor T 20 and the 2nd HVT nmos pass transistor T22 structure.Similarly, the 3rd low leakage inverter 96 is the HVT CMOS inverters from the 3rd HVTPMOS transistor T 24 and the 4th HVT nmos pass transistor T26 structure.The first low leakage inverter 92 possibility corresponding selection gated inverter are such as the selectivity gated inverter that is realized by the secondary series transistor 36 of Fig. 1.

In operation, there are two operator schemes in the system that reduces leakage 80, and this is set by MUX82 by controller 84.In first operator scheme, forbidding MUX82.Perhaps, MUX input 86 is chosen as the output of MUX82, and forbidding is from the feedback 90 of the output of the 3rd low leakage inverter 100.Under this pattern, intervene

circuit

94,98; Inverter 92,96,100; And adjunct circuit 88 can be operated as partly not the latching IQ feedback 90 of expectation.First pattern may the interior activity pattern of corresponding latch.

Second pattern is low leakage mode, and it may the interior park mode of corresponding latch.In this pattern, forbid MUX input 86, and the 2nd MUX input 90 expressions are chosen as the output of MUX82 from the feedback of the output of the 3rd low leakage inverter 100.

In this specific embodiment, existing from the Vdd of a HVT PMOS transistor T 20 source electrodes of the second low leakage inverter 96 first may leakage paths 102, by additional the 4th HVT nmos pass transistor T26 of circuit 98 and the 3rd low leakage inverter 100 that intervenes to ground.May there be the second possibility leakage paths 104 from the 3rd Vdd that hangs down the 3rd HVT PMOS transistor T 24 source electrodes of leakage inverter 100, arrives ground by additional the 2nd HVT nmos pass transistor T22 that intervenes the circuit 98 and the second low leakage inverter 96.The first possibility leakage paths 102 and the second possibility leakage paths 104 are similar to corresponding the 4th leakage paths 56 and the 3rd leakage paths 54 of Fig. 1.The feedback 90 of enabling by controller 84 and MUX82 has guaranteed that leakage paths 102-104 is closed when system 80 is in low leakage mode.

For example, if to the high potential that is input as of the 3rd low leakage inverter 100, PMOS transistor T 24 is for closing, and NMOS T26 is conducting.Therefore, pass through NMOS T26 to the path on ground for opening, this has guaranteed that the 3rd low leakage inverter 100 is output as electronegative potential.Low-potential state passes through MUX82 through feeding back 90; Anti-phase by the first low leakage inverter 92, become high potential state; And by intervening circuit 94, appear at the input of the second low leakage inverter 96 as high potential state then.This high potential state has guaranteed that NMOST22 is conducting, and PMOS T20 is for closing.Therefore, first leakage paths 102 from Vdd to ground is cut off by a HVT PMOS transistor T 20.Second leakage paths from Vdd to ground is cut off by the 3rd HVT PMOS transistor T 24.Equally, when system 80 is in low leakage mode, if in the input of the 3rd low leakage inverter 100 low-potential state takes place, then can low-potential state take place in the input of the second low leakage inverter 96.Therefore,

inverter

96 and 100 HVT nmos pass transistor T22 and T26 correspondingly can be closed.Therefore, the leakage paths from Vdd to ground 102,104 can be cut off.

When the configuration of system made and is in low leakage mode in system 80, the high potential state that takes place in the 3rd low leakage inverter 100 inputs can cause in the input of the second low leakage inverter 96 high potential state taking place.Those of skill in the art are appreciated that feeding back 90 can directly remove from the input of the 3rd low leakage inverter 100 and the first low leakage inverter 92, and can omit and intervene circuit 94, and do not depart from the scope of the invention.Other guarantee that when system 80 is in low leakage mode or park mode the device by feeding back 90 cut-out leakage paths 102 and 104 also can be used not departing under the scope of the invention situation.For example, come the MUX control input of self-controller 84 to replace, and can omit controller 84 with the input that is function clock signal.In addition, MUX82 can be omitted in certain design.For example, MUX82 can replace with controller or other logics, and described logic optionally offers necessary feedback second when being in low leakage mode in system 80 and hangs down leakage inverter 96.In addition, system 80 can be used for the circuit except latch, and they have two or more inverters, may have leakage paths during leaking such as not expecting during the park mode by these inverters.

Fig. 4 is high-performance, low leakage latches 110 figure that make up according to the principle of the invention, and it can be in clock dormancy valid function during at high potential or electronegative potential, and it comprises and is used to reduce the system 80 that Fig. 3 leaks.The high performance nature of latch 10 has been enabled the use of more effective clock signal 24 ', inversion clock signal 26 ', principal and subordinate's output signal 28 ' and data-signal 18 '.Clock signal 24 ' has higher frequency and narrower pulse duration.Data-signal 18 ' also has narrower pulse duration, and this influences the principal and subordinate and exports 28 ' and output signal 30 ', will go through as following.

The structure of the low leakage latches 110 of high-performance is similar to the structure of the latch 10 of Fig. 1, except the latch 110 of Fig. 4 comprises additional logic 12 and comprises MUX82 in the master unit 12 '.In addition, slow the 2nd HVT of Fig. 1 replaces by door 114 by door 46 usefulness high speed LVT.The second low leakage inverter 96 of the 4th inverter I4 corresponding diagram 3.The 3rd low leakage inverter 100 of the 9th inverter I9 corresponding diagram 3.In addition, the output 90 of the 9th HVT inverter I9 feeds back to the input of MUX 82.

Additional logic 112 comprises NAND door 122, and its receives efficient clock signal 24 ' and sleep signal 22 as input, and output is offered and (AND) door 116 and additional inverter 118.AND door 116 receives additional input from the output of OR door 38.The output of AND door 116 is connected to the door of the 8th HVT nmos pass transistor T8.The output of additional inverter 118 is input to additional OR door 120.Additional OR door 120 receives second input from the output of a HVT inverter I1, and output is offered 5 of the 5th HVT PMOS transistor Ts.

The additional intervention circuit 98 that passes through

door

114 and 48 corresponding diagram 3 of Fig. 4.The 3rd column of transistors 44 and LVT are by the intervention circuit 94 of door 42 corresponding diagram 3.Transistor seconds row 36 are as the initial HVT inverter 92 of selectivity gated inverter and corresponding diagram 3.The adjunct circuit 88 of remaining circuit corresponding diagram 3.The output of MUX 82 is connected to transistor seconds row 36, and the input 16 that is similar to the scanning input of Fig. 1 is connected to the mode of transistor seconds row 36.

In operation, when latch 110 was in park mode, half latch data of corresponding feedback 90 was from 14 ' feeding back to MUX82 from the unit.The pattern of latch 110 (such as clock signal 24 ' dormancy at high potential or electronegative potential) can determine by dormancy input 22 and displacement input 20 automatically, and this is controlled by the controller such as the controller 84 of Fig. 3.By optionally controlling dormancy and

displacement input

20,22, when clock signal 24 ' when being high or low, latch 110 can be automatically enabled to dormancy.This is different from conventional latch, and they have rigid line to connect, and when synchronizing clock signals 24 ' is connected to dormancy during for high potential, or is connected to dormancy during for electronegative potential when synchronizing clock signals 24 '.

Feedback 90 is transferred to the output of MUX82.The inverter T6 of transistor seconds row 36 and Y7 are anti-phase to data in output place of MUX82 then.Be sent to the input of the second low leakage inverter 96 then through anti-phase feedback data.This has guaranteed that (I4, I9) 96,100 leakage paths is cut off by a hvt transistor in the inverter 96,100 by low leakage inverter under park mode.Therefore, second of Fig. 1 can be replaced by door 114 with the high speed LVT of Fig. 4 by door 46, because no longer be a problem by second leakage by door 46.Therefore, latch 110 low leakage, quick setting-up time, the quick clock-pulse width that shifts time-delay and minimum requirement owing to the high-speed door 42,114 in the data path has.

Additional logic 112 guaranteed when clock signal 24 ' dormancy during at high potential, and the end transistor T5 of transistor seconds row 36 and T8 be for closing, and when the 24 ' dormancy of clock signal during at electronegative potential end transistor T5 and T8 be conducting.This has for example guaranteed when clock signal 24 ' dormancy during at high potential, anyly be cut off by HVT nmos pass transistor T8 to the leakage on ground from low leakage inverter 96 Vdd of place, described leakage is passed through the 42, the 7th a HVT nmos pass transistor T7 and the 8th HVT nmos pass transistor T8 by a LVT of transistor seconds row 36.In addition, cut off the leakage of the Vdd at any next self-closing the 5th HVT PMOS transistor T 5 source electrode places, described leakage is arrived ground that hang down leakage inverter 96 places by the 6th a HVT PMOS transistor T 6 and a LVT by door 42.

When clock signal 24 ' dormancy during, do not need from half latch feedback 90, because the 3rd HVT closes automatically by door 48 at high potential.This has blocked leakage paths 102 and 104.Therefore, the blockade that the leakage paths 102,104 by low leakage inverter 96,100 does not require at inverter 96,100 places is because they are blocked by door 48 places at the 3rd HVT.

When clock signal 24 ' dormancy during at high potential, transistor seconds row 36 are the fact of high potential for closing owing to additional logic 112 and clock signal 24 ' and sleep signal 22.Therefore, the selectivity gated inverter of forbidding transistor seconds row 36 realizations.Therefore, optionally forbid from half latch feedback 90.

When clock signal 24 ' dormancy during, cut off the leakage paths (not shown) of the Vdd of any transistor T 5 from transistor seconds row 36 to ground at electronegative potential.In this case, cut-out or T6 or T7.If T6 is for closing, then block leakage paths from the Vdd place of transistor T 5 by the hvt transistor T7 that closes.If T6 is conducting, T7 is for closing, and then leakage paths keeps closing, because node 40 is isolated with ground.The nmos pass transistor T22 that node 40 is closed by the transistor T 7 of closing, T13, T1, T13 and low leakage inverter 96 isolates (see figure 3) with ground.

When clock signal 24 ' dormancy during at electronegative potential, hvt transistor T12 in the 3rd column of transistors 44 and T13 are for closing.Therefore, anyly be cut off by HBT transistor T 12, the T13 that closes by the leakage paths of door 42 by the 3rd column of transistors 44 and a HVT.

When clock dormancy during at high potential or electronegative potential, the end transistor T1 of the first transistor row 34 and T4 are for closing.Therefore, cut off the leakage paths of any source electrode from T4, and when the clock dormancy or be high potential or during, cuts off any by the leakage paths of T1 to ground for electronegative potential.And when clock dormancy during at high potential or electronegative potential, according to the system 80 of Fig. 3, the leakage paths by

low leakage inverter

96 and 100 is owing to be cut off to half latch feedback 90 of MUX82.

Therefore, all leakage paths in the latch 110 are cut off during at high potential and when clock signal 24 ' sleeps in clock signal 24 ' dormancy.In addition, latch 110 uses the high speed in the data path to pass through door 42,114, and this has improved the performance of latch 110 greatly.Therefore, latch 110 is high-performance latch, and it leaks during in high potential or sleeps lower in clock signal 24 ' dormancy.

Those of skill in the art are appreciated that can carry out various modifications to latch 110 does not depart from scope of the present invention with the needs that satisfy given application.For example, the 5th HVT inverter I5 and the 8th HVT inverter I8 can substitute with the LVT inverter.In this case, additional afterbody transistor (not shown), such as being used for from the transistor T 20 of LVT inverter I6, I7, can be with the leakage during inverter I5, I8 are included to guarantee to minimize park mode.In addition, the scanning of latch 110 input and scanning output function can be omitted not departing under the scope of the invention situation.

In this specific embodiment, MUX82 realizes by

door

126 and 128 by additional MUX inverter 124 and additional HVT.Can use other MUX realizations and not depart from scope of the present invention.Those of skill in the art are appreciated that MUX 82 realizes that details is that application is specific, and different MUX realizes may being used to satisfy needs of different applications.And MUX82 can be omitted or use other equipment replacements, such as controller, and does not depart from scope of the present invention.

Fig. 5 is latch 10 sequential Figure 60 ' of Fig. 4, relatively short setting-up time 62 ' is described, shifts time-delay 68 ' and clock-pulse width 72 '.The latch 110 of Fig. 4 can adapt to the clock signal 24 ' of higher frequency of narrower clock pulse 64 ' and the more valid data input and output signal 18 ', 30 ' that has narrower data pulse 66 '.Therefore, corresponding sequential Figure 60 of comparison diagram 2 and Fig. 5 and 60 ', high-speed latches 114 performances of Fig. 4 are better than the latch 10 of Fig. 1 greatly.

Fig. 6 is latch 110 first alternatives 130 of Fig. 4, and described latch 110 lacks MUX82 but uses part to gather the integrated MUX that realizes by additional hvt transistor 132." integrated by MUX and master unit 12 that transistor 132 is realized.Transistor seconds row 36 are suitable for additional hvt transistor 132, and described additional hvt transistor 132 comprises the 40 PMOM transistor T the 40, the 41 PMOS transistor T the 41, the 42 PMOS transistor T the 42, the 43 nmos pass transistor T43, the 44 nmos pass transistor T44 and the 45 nmos pass transistor T45 from top to bottom.The source electrode of the 40 transistor T 40 is connected to the high-voltage state of expression Vdd, and drain electrode is connected to the source electrode of the 5th transistor T 5 and the source electrode of transistor T 41.PMOS transistor T 40-T42 is connected to drain-to-source, and nmos pass transistor T43-T45 be connected to drain-to-source.Yet the drain electrode of the 42 PMOS transistor T 42 is connected to the drain electrode of the 43 nmos pass transistor T43.The drain electrode of the 45 nmos pass transistor T45 is connected to the source electrode of transistor T 44 and T8.

The connection of additional logic 112 makes the output 116 of AND door be connected to the door of the 45 PMOS transistor T 45.The output of OR door 120 is connected to the door of the 40 PMOS transistor T 40.Half latch data feedback 90 is connected to the door of transistor T 41 and T44.The input 16 of scanning input is connected to the door of transistor T 5 and T8.Displacement input 20 is connected to the door of transistor T 7 and T42.Shift signal 20 passes through MUX inverter 124 by anti-phase, and is input to the door of transistor T 6 and T43.

The class of operation of latch 130 is similar to the operation of Fig. 4 latch 110, except the function of the MUX 82 of the latch 110 of Fig. 4 by column of transistors 36 and 132 and the MUX inverter 124 of the latch 130 of Fig. 6 realize.When latch 130 was in park mode, half latch feedback 90 guaranteed to be cut off by inverter (I4) 96 and (I9) 100 leakage paths.Therefore, can be implemented as high speed LVT by

door

42 and 114 and do not jeopardize leakage characteristics by door.

It should be noted that SIN signal 16 and SOUT signal 32 to be omitted and do not depart from scope of the present invention.The integrated MUX that latch 130 uses realizes simpler relatively, because share many transistor sources and drain electrode.

Fig. 7 is latch 110 second alternatives 140 that are applicable to Fig. 4 of diphasic clock 142.The latch 140 of Fig. 7 is similar to the latch 110 of Fig. 4, and the clock signal 24 ' and the anti-phase back clock signal 26 ' that are different from Fig. 4 except the clock signal 144 that has two outs of phase are used to optionally open by door 42,114 and 48.

Feedback 90 novelty is used the leakage that has reduced in the latch 140, and no matter what use is single-phase or diphasic clock, also no matter use which multiplexing scheme with Control and Feedback 90 optionally.

Therefore, the present invention describes at this specific embodiment with reference to application-specific.The personnel of the those of ordinary skill in the field and the visit principle of the invention can recognize modification, application and embodiment additional in the scope of the invention.

Therefore appended claims is intended to cover any and all this kind application, modification and embodiment in the scope of the invention.

Claims

1. one kind is used to reduce the system that electric current leaks in the circuit, it is characterized in that comprising:

The circuit that in described integrated circuit, easily leaks; And

Be used for optionally blocking described path to remove or to reduce device by the leakage in described path by the feedback in the described integrated circuit.

2. the system as claimed in claim 1 is characterized in that the described device that is used for selective blockade comprises;

First circuit unit in the described path, described path are between relative high voltage and the relatively low voltage; Second circuit assembly in the described path, and be used for optionally providing the feedback that outputs to the input of described first circuit unit from described second circuit assembly, optionally cut off described path when not being cut off at the described first circuit place at described second circuit place in described path.

3. system as claimed in claim 2 is characterized in that describedly being used for optionally providing the device of feedback also to comprise the device that is used for preserving data in described circuit.

4. system as claimed in claim 3 is characterized in that the described device of preserving data in described circuit comprises the device of optionally enabling described feedback when described circuit is in park mode.

5. system as claimed in claim 4 is characterized in that the described device that is used for optionally enabling described feedback comprises multiplexer.

6. system as claimed in claim 5 is characterized in that described multiplexer is the 2-1 multiplexer, and described multiplexer has displacement input as the control input, and the input with scanning input as an input and described feedback as second input.

7. system as claimed in claim 5 it is characterized in that described first circuit unit is first complementary metal oxide semiconductors (CMOS) (CMOS) inverter, and described second circuit assembly is the 2nd CMOS inverter.

8. system as claimed in claim 7, the selection that it is characterized in that described feedback path makes when activating described feedback path, occur in high state that the input of described the 2nd CMOS inverter takes place and cause high state, and the low state that occurs in described the 2nd CMOS inverter input causes the low state in a described CMOS inverter input in a described CMOS inverter input.

9. system as claimed in claim 7 is characterized in that described circuit is principal and subordinate's latch.

10. system as claimed in claim 9, it is characterized in that when described latch dormancy and when the synchronizing clock signals of described latch when being high, additional logic is cut off the master unit of described latch by high voltage threshold values (HVT) transistor, and described hvt transistor is positioned at the selectivity gated inverter of described master unit.

11. system as claimed in claim 10, it is characterized in that also comprising device, and wherein said additional logic is placed on certain position to block any remaining leakage paths that does not block when described clock signal dormancy described feedback of selective disabling during at high potential.

12. system as claimed in claim 11, it is characterized in that also comprising the device that is used for blocking described path by described clock signal, and when described clock signal dormancy during at high potential one HVT by door between described first circuit unit and described second assembly.

13. a high-performance, low leakage latches is characterized in that comprising:

Clock signal;

Comprise transistorized circuit, described transistorized arrangement makes data optionally transfer to the output of described circuit from the input of described circuit in response to described clock signal; And

When described circuit is in park mode, in described circuit, use feedback to block the device that passes through described transistorized leakage paths by one or more described transistors.

14. latch as claimed in claim 13, it is characterized in that described circuit comprises LVT and hvt transistor, and the wherein said device that is used for use feedback in described circuit comprises when described circuit is in park mode, blocks the device of the leakage paths that passes through hvt transistor in described circuit by one or more described hvt transistors.

15. latch as claimed in claim 14 is characterized in that when described latch is in operator scheme described LVT transistor is arranged to setting-up time and the transfer delay to minimize described latch.

16. latch as claimed in claim 15 is characterized in that the described device that is used to block leakage comprises the device of closing described one or more hvt transistors when described circuit is in park mode.

17. latch as claimed in claim 16 is characterized in that described circuit comprises master unit and from the unit, described feedback occur in from described from the unit to described master unit.

18. latch as claimed in claim 17 is characterized in that described feedback represents half latch data that comes from the unit from described.

19. latch as claimed in claim 18 is characterized in that also comprising shift signal, when described circuit is in park mode in described shift signal indication.

20., it is characterized in that described latch is lacking HVT by door in the described data path that is input to described output, and comprise that in described data path two LVT are by door as the latch of claim 15.

21. latch as claimed in claim 20 is characterized in that described LVT by in one in the door master unit that is included in described latch, the 2nd LVT by door be included in described latch in the unit.

22. latch as claimed in claim 21 is characterized in that all leakage paths of described latch flow out (flow through off) hvt transistor when described latch is in park mode.

23. latch as claimed in claim 22 is characterized in that also comprising being used for the device that makes described latch dormancy automatically when being high or low when the described clock signal of described latch.

24. system as claimed in claim 23, it is characterized in that described latch is in the dormancy when being high of described clock signal, additional logic is cut off leakage paths in the described master unit by hvt transistor, and described hvt transistor is positioned at the inverter of described master unit selectivity gate.

25. system as claimed in claim 24 is characterized in that also comprising the device of optionally forbidding described feedback when described clock signal dormancy during at high potential, and being placed to block any remaining leakage paths that is not blocked of wherein said additional logic.

26. latch as claimed in claim 23 is characterized in that the described device of enabling automatically comprises the multiplexer of communicating by letter with controller, described controller is used for optionally controlling described feedback.

27. latch as claimed in claim 26 is characterized in that described multiplexer and described master unit are integrated.

28. latch as claimed in claim 23 is characterized in that described synchronizing clock signals comprises two synchronizing clock signals that have out of phase.

29. a high-performance, low leakage latches is characterized in that comprising:

The circuit that comprises LVT and hvt transistor, described transistor is arranged to the output that makes data optionally transfer to described circuit from the input of described circuit in response to described clock signal, there is LVT to pass through door in the data path of described circuit between the input and output of described circuit, but lacks HVT by door; And

When described circuit is in park mode, in described circuit, use feedback by optionally close described one or more hvt transistor in response to described feedback to block device through one or more described hvt transistors by the transistorized leakage paths of described LVT.

30. one is used to reduce the method that electric current leaks in the circuit, it is characterized in that may further comprise the steps;

First circuit unit is placed in the path between relative high voltage and relatively low voltage;

The second circuit assembly is positioned in the described path; And

Optionally provide feedback from the input of described first circuit unit of outputing to of described second circuit assembly when described second circuit is cut off, optionally not to be breaking at the described path at the described first circuit place in described path.