CN1704889A - Data distribution method for improving data access speed - Google Patents
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Abstract
A data distribution method for increasing data acc velocity is used in increasing the data acc speed of a host to a mobile storage device, which includes a control module transmitting data with the host by the communication protocol, a storage module for storing data including at least two slices of storage dielectrics. Said method includes the following steps: 1, letting said control module receive data read/write instructions from the host and get the fan address of the data the instruction referring to 2, carrying out data read/write operation of the add fan zone and even fan zone to the corresponding storage dielectric at the same time if the number of the current transmitted fan zones is larger than 1, 2, selecting corresponding storage dielectric for the read/write operation based on the add or even of the fan zone address.
Description
Technical field
The present invention relates to storage control technology, relate in particular to the data distributing method that improves data access speed.
Background technology
Along with popularizing of PC, various digital products and people's work life relation are close day by day, the processing of thing followed mass data and carry and just become urgent problem, thereby various movable storage devices emerge in an endless stream, and semiconductor memory apparatus is little because of volume, capacity is big, zero access, easy to carry, stable performance, advantage such as not fragile and obtained the application of more and more popularizing.
Present semiconductor memory apparatus is made of control module and storage medium, host computer system is carried out data read-write operation by this control module to storage medium, can communicate by various Data Transport Protocols between this control module and the host computer system, this Content of Communication comprises the transmission instruction and carries out data transmission, control module is carried out corresponding data manipulation according to this instruction to storage medium after receiving instruction and data again, because the read write attribute that storage medium is intrinsic, data rate between host computer system and the control module is much larger than the read-write operation speed of control module to storage medium, so control module just becomes the bottleneck that carries out data transmission between host computer system and the storage medium to the read-write operation speed of storage medium.
For example, widespread use at present carry out data transmission with usb protocol, with the movable storage device of flash media (FLASHMemory) as storage medium, after USB2.0 releases, speed between the control module of host computer system and this memory device can reach 480Mbps, and because the restriction of the intrinsic read write attribute of flash media, can only reach 160Mbps (PLSCONFM) to the data manipulation speed of 8bit flash media is the highest, and the control module of present above-mentioned movable storage device adopts single pass method for flash media, can only read and write a slice flash media at every turn, if monolithic 8bit flash media, the high transmission speed in laboratory is: read data 80Mbps, writing rate 64Mbps; If monolithic 16bit flash media, the high transmission speed in laboratory is: read data 160Mbps, writing rate 128Mbps, control module under the obvious this control model to the data access speed of flash media far below the data rate between host computer system and the control module, fail to make full use of the high data transmission rate between host computer system and the control module, and then limited data rate between host computer system and the storage medium.
Therefore, how to provide a kind of data distributing method that improves data access speed to become problem demanding prompt solution.
Summary of the invention
The objective of the invention is on the prior art basis,, provide a kind of data distributing method that improves data access speed at the deficiency of prior art application.
The data distributing method that the present invention improves data access speed can be achieved through the following technical solutions:
A kind of data distributing method that improves data access speed, described method is used to improve the data access speed of main frame to flash memory device, described flash memory device comprises the control module that can carry out data transmission by communication protocol and main frame, be used for storing the memory module of data, comprise at least two storage mediums in the described memory module, described method comprises the steps:
1) makes described control module from the host receiving data read/write command, and obtain the sevtor address of described order indication data;
2) if the current number of sectors that needs transmission greater than 1, then simultaneously and is respectively carried out odd number of sectors and the read/write operation of even number sectors of data to the storage medium of correspondence;
3), then select corresponding storage medium to carry out the data read/write operation according to the parity of described sevtor address if described number of sectors is 1.
Described method further comprises according to described sevtor address calculates corresponding LBA (Logical Block Addressing), and obtains the corresponding physical block address by logical comparison table.
Described method comprises that further the storage medium that described physical block address is sent into described correspondence carries out the data read/write operation.
Described two storage mediums can a shared logical comparison table, also can use logical comparison table separately.
Described control module is connected with a slice storage medium by data line D0-D7, control line CE1, control line ALE, CLE, RB, RE, WE, be connected control line ALE, the CLE of described two shared described control modules of storage medium, RB, RE, WE by data line D8-D15, control line CE2, control line ALE, CLE, RB, RE, WE with another sheet storage medium.
Described storage medium can be but be not limited to flash media (FLASH Memory), SDRAM, DRAM, EPPROM, ferromagnetic random access memory/ferroelectric memory (FRAM), magnetic random access memory (MRAM), ultrahigh density storage chip (MILLIPEDE).
Described communication protocol comprises but is not limited to usb protocol, the Zigbee agreement, the IEEE1394 agreement, Bluetooth protocol, the serial ATA agreement, the IDE agreement, the SCSI agreement, the HiperLAN agreement, the IrDA infrared protocol, the HomeRF agreement, IEEE802.11x, IEEE802.11a, 802.11b, 802.11d, 802.11.g, 802.15,802.16,802.3 agreement, the RS232 agreement, the RS485 agreement, the USB_OTG agreement, the UWB agreement, the GPIO agreement, the UART agreement, the CF agreement, the SM agreement, the MMC agreement, the SD agreement, the MS agreement, the MD agreement, the X-D agreement, the PCMCIA agreement, GSM, GPRS, CDMA, 2.5G and/or 3G agreement.
The method that the present invention improves data access speed also can be achieved through the following technical solutions:
A kind of data distributing method that improves data access speed, described method is used to improve the data access speed of main frame to flash memory device, described flash memory device comprises the control module that can carry out data transmission by communication protocol and main frame, be used for storing the memory module of data, comprise at least two storage mediums in the described memory module, described method comprises the steps:
1) described control module is from the host receiving data read/write command, and obtains the sevtor address of described order indication data;
2) simultaneously and respectively the storage medium of correspondence is carried out the data read/write operation of the odd bytes and the even bytes of described sector, or described sector is divided into preceding 256 bytes and back 256 bytes simultaneously and respectively the storage medium of correspondence is carried out the data read/write operation.
The offset address of each sectors of data in the described method in piece (Block) is the multiple of (256+8).
Described control module is connected with a slice storage medium by data line D0-D7, control line CE, ALE, CLE, RB, RE, WE, be connected control line CE, the ALE of described two shared described control modules of storage medium, CLE, RB, RE, WE by data line D8-D15, control line CE, ALE, CLE, RB, RE, WE with another sheet storage medium.
Described storage medium can be but be not limited to flash media (FLASH Memory), SDRAM, DRAM, EPPROM, ferromagnetic random access memory/ferroelectric memory (FRAM), magnetic random access memory (MRAM), ultrahigh density storage chip (MILLIPEDE).
Described communication protocol comprises but is not limited to usb protocol, the Zigbee agreement, the IEEE1394 agreement, Bluetooth protocol, the serial ATA agreement, the IDE agreement, the SCSI agreement, the HiperLAN agreement, the IrDA infrared protocol, the HomeRF agreement, IEEE802.11x, IEEE802.11a, 802.11b, 802.11d, 802.11.g, 802.15,802.16,802.3 agreement, the RS232 agreement, the RS485 agreement, the USB_OTG agreement, the UWB agreement, the GPIO agreement, the UART agreement, the CF agreement, the SM agreement, the MMC agreement, the SD agreement, the MS agreement, the MD agreement, the X-D agreement, the PCMCIA agreement, GSM, GPRS, CDMA, 2.5G and/or 3G agreement.
The present invention is logical can to carry out data access operation to storage medium simultaneously, and then improves data access speed greatly.
Description of drawings
Fig. 1 is the data allocations synoptic diagram of first embodiment of the invention.
Fig. 2 is the write data process flow diagram of first embodiment of the invention.
Fig. 3 is the read data flow process figure of first embodiment of the invention.
Fig. 4 is the data allocations synoptic diagram of another embodiment of the present invention.
Fig. 5 is the write data process flow diagram of another embodiment of the present invention.
Fig. 6 is the read data flow process figure of another embodiment of the present invention.
Embodiment
The data distributing method that the present invention improves data access speed is applicable to the data transmission and the storing process of flash memory device.
See also Fig. 1, Fig. 1 is the data allocations synoptic diagram of first embodiment of the present invention's data distributing method of improving data access speed, as shown in Figure 1, flash memory device comprises control module 20 and memory module 30, comprise DMA, ECC unit and other necessary device (the common personage of all industries of described device all knows, repeats no more) in the described control module 20.
One end of described control module 20 can carry out data transmission by communication protocol with main frame, and described communication protocol comprises but is not limited to usb protocol, the Zigbee agreement, the IEEE1394 agreement, Bluetooth protocol, the serial ATA agreement, the IDE agreement, the SCSI agreement, the HiperLAN agreement, the IrDA infrared protocol, the HomeRF agreement, IEEE802.11x, IEEE802.11a, 802.11b, 802.11d, 802.11.g, 802.15,802.16,802.3 agreement, the RS232 agreement, the RS485 agreement, the USB_OTG agreement, the UWB agreement, the GPIO agreement, the UART agreement, the CF agreement, the SM agreement, the MMC agreement, the SD agreement, the MS agreement, the MD agreement, the X-D agreement, the PCMCIA agreement, GSM, GPRS, CDMA, 2.5G and/or 3G agreement.
The other end of described control module 20 is connected with memory module 30, and described memory module 30 adoptable storage mediums can be but be not limited to flash media (FLASH Memory), SDRAM, DRAM, EPPROM, ferromagnetic random access memory/ferroelectric memory (FRAM), magnetic random access memory (MRAM), ultrahigh density storage chip (MILLIPEDE).The storage medium that memory module 30 adopts in the present embodiment is two flash memory (Flash) FLASH1 and FLASH2, as shown in the figure, logical sector address is that the sector storage of even number is in FLASH1, logical sector address is that the sector storage of odd number is in FLASH2, the distribution of the sevtor address among FLASH1 shown in the figure and the FLASH2 all is distributed as example with the sevtor address in the piece (B1ock), and wherein N refers to an open ended maximum sector of piece (512 byte) number.Described control module 20 is connected with FLASH1 by data line D0-D7, control line CE1, control line ALE, CLE, RB, RE, WE, be connected with FLASH2 by data line D8-D15, control line CE2, control line ALE, CLE, RB, RE, WE, just control line ALE, CLE, RB, RE, the WE of the shared described control module 40 of FLASH1 and FLASH2.
In the present embodiment: from the data of main frame input is that timesharing enters control module 20, and the data transmission procedure of this structure has two kinds of situations:
1) when packet (packet is that sector is a unit with 1 sector) during greater than 2 sector, after control module 20 will wait two sector to accept, respectively corresponding sector is sent to FLASH1 and FLASH2 respectively simultaneously, because two FLASH operate simultaneously, can allow two FLASH shared control signals ALE like this, CLE, RE, WE, RB so can save control signal.
2) when packet has only a sector, this moment, can only to be a slice FLASH transmit data, can only choose wherein that a slice FLASH operates, so the sheet of these two FLASH choosing (CE) control signal can not be shared.
See also Fig. 2, Fig. 2 is the flow process of the first embodiment write data.
Below the data of present embodiment are write flow process illustrated:
At first, by step 201 beginning, control module 20 receives write order from main frame;
Enter step 203 then, obtain LBA (Logical Block Addressing) according to writing the initial sector address:
Described LBA (Logical Block Addressing)=logical sector address/(the sector number of 2* logical block);
Enter step 205 then, find described LBA (Logical Block Addressing) corresponding physical block address by logical comparison table, described logical comparison table has two kinds to build method, can make each sheet FLASH set up the table of comparisons of oneself, also can two shared tables of FLASH, during the but shared table of comparisons, if there are some BLOCK of a slice FLASH to break, then a slice FLASH corresponding physical BLOCK also will be marked as bad piece in addition;
Enter step 206, judge that current to need the number of sectors of transmission be less than 1, promptly in the packet contained sector number whether less than 1;
If not, promptly contained sector number is not less than 1 in the packet, and just contained sector number then entered step 208 more than or equal to 2 o'clock in the packet, prepared two sectors of data and was transferred to simultaneously among two FLAH for DMA; Then enter step 210, send program command and corresponding physical address is delivered to corresponding FLASH; Enter step 212 then, open described DMA and make odd number of sectors and even number sector also write FLASH1 and FLASH2 simultaneously respectively; Return step 206 then, whether sector number contained in the judgment data bag is less than 1;
If promptly contained sector number then enters step 207 less than 1 in the packet, judging currently needs whether the number of sectors of transmission is 0, and promptly whether contained sector number is 0 in the packet;
If promptly contained sector number is 0 in the packet, then enters step 215 process ends;
If not, promptly the sector number in the packet is 1, then judges the parity of the current sevtor address that will transmit;
If the current sevtor address that will transmit is an odd number, then enter step 213, described sectors of data is write FLASH2; Enter step 215 process ends then.
If the current sevtor address that will transmit is to be even number, then enter step 211, described sectors of data is write FLASH1; Enter step 215 process ends then.
See also Fig. 3, Fig. 3 is the flow process of the first embodiment read data.
Flow process to the read data of present embodiment is illustrated below:
This flow process is by step 301 beginning, and control module 20 receives the order of read data from main frame;
Enter step 303 then, obtain LBA (Logical Block Addressing) according to writing the initial sector address:
Described LBA (Logical Block Addressing)=logical sector address/(the sector number of 2* logical block);
And find described LBA (Logical Block Addressing) corresponding physical block address by logical comparison table, described logical comparison table has two kinds to build method, can make each sheet FLASH set up the table of comparisons of oneself, also can two shared tables of FLASH, during the but shared table of comparisons, if there are some BLOCK of a slice FLASH to break, then a slice FLASH corresponding physical BLOCK also will be marked as bad piece in addition;
Enter step 305 then, judge that whether the current number of sectors of transmission that needs is less than 1;
If not, the promptly current number of sectors that needs transmission then enters step 306 greater than 1, and DMA also reads odd number of sectors and even number sectors of data from FLASH1 and FLASH2 respectively simultaneously; Return step 305 then, judge that whether the current number of sectors of transmission that needs is less than 1;
If the promptly current number of sectors that needs transmission then enters step 307 and judges whether the current number of sectors that will transmit is 0 less than 1;
If the promptly current sector number that needs to transmit is 0, then enters step 311 process ends;
If not, the promptly current sector number that needs to transmit is not 0 (being 1), then enters step 308, judges the parity of the current sevtor address that will transmit;
If the current sevtor address that will transmit is an odd number, then enter step 310, read described sectors of data from FLASH2; Enter step 311 process ends then.
If the current sevtor address that will transmit is to be even number, then enter step 309, read described sectors of data from FLASH1; Enter step 311 process ends then.
See also Fig. 4, Fig. 4 is the data allocations synoptic diagram of another embodiment of the present invention.
As shown in Figure 4, flash memory device comprises control module 40 and memory module 50, comprises DMA, ECC unit and other necessary device (the common personage of all industries of described device all knows, repeats no more) in the described control module 40.
One end of described control module 40 can carry out data transmission by communication protocol with main frame, and described communication protocol comprises but is not limited to usb protocol, the Zigbee agreement, the IEEE1394 agreement, Bluetooth protocol, the serial ATA agreement, the IDE agreement, the SCSI agreement, the HiperLAN agreement, the IrDA infrared protocol, the HomeRF agreement, IEEE802.11x, IEEE802.11a, 802.11b, 802.11d, 802.11.g, 802.15,802.16,802.3 agreement, the RS232 agreement, the RS485 agreement, the USB_OTG agreement, the UWB agreement, the GPIO agreement, the UART agreement, the CF agreement, the SM agreement, the MMC agreement, the SD agreement, the MS agreement, the MD agreement, the X-D agreement, the PCMCIA agreement, GSM, GPRS, CDMA, 2.5G and/or 3G agreement.
The other end of described control module 40 is connected with memory module 50, and described memory module 50 adoptable storage mediums can be but be not limited to flash media (FLASH Memory), SDRAM, DRAM, EPPROM, ferromagnetic random access memory/ferroelectric memory (FRAM), magnetic random access memory (MRAM), ultrahigh density storage chip (MILLIPEDE).
The storage medium that memory module 50 adopts in the present embodiment is two flash memory (Flash) FLASH1 and FLASH2, described control module 40 is connected with FLASH1 by data line D0-D7, control line CE, ALE, CLE, RB, RE, WE, be connected with FLASH2 by data line D8-D15, control line CE, ALE, CLE, RB, RE, WE, just control line CE, ALE, CLE, RB, RE, the WE of the shared described control module 40 of FLASH1 and FLASH2.
In the present embodiment,, therefore when a sectors of data bag arrives, just can send in two FLASH in the past, not have the situation of a certain moment operation a slice FLASH like this because a sectors of data is separately to exist among two FLASH.Therefore all control signals of FLASH can be shared fully.The data of 512 bytes are being divided into each 256 when being sent to two FLASH, two kinds of point-scores can arranged: 1) 512 bytes are being divided into preceding 256 bytes and back 256 bytes are sent to two FLASH respectively.2) 512 bytes are divided into odd bytes and even bytes and are sent to two FLASH respectively.Because a sectors of data splits into two halves, therefore its offset address in piece (BLOCK) lining becomes original half, be that the skew of each sectors of data in BLOCK is the multiple of (256+8), as shown in the figure, wherein the distribution of the sevtor address among FLASH1 and the FLASH2 all is distributed as example with the sevtor address in the piece (Block), and wherein N refers to an open ended maximum sector of piece (512 byte) number.This data distributing method make when transmission speed can be not a sector because of transmits data packets can not be simultaneously transmission and influenced in the FLASH.
See also Fig. 5, write flow process and receive write order from main frame by step 501;
Enter step 503 then, obtain LBA (Logical Block Addressing) according to writing the initial sector address:
Described LBA (Logical Block Addressing)=logical sector address/(the sector number of 2* logical block);
And find described LBA (Logical Block Addressing) corresponding physical block address by logical comparison table, described logical comparison table has two kinds to build method, can make each sheet FLASH set up the table of comparisons of oneself, also can two shared tables of FLASH, during the but shared table of comparisons, if there are some BLOCK of a slice FLASH to break, then a slice FLASH corresponding physical BLOCK also will be marked as bad piece in addition;
Enter step 505 then, judge whether the current number of sectors that needs to transmit is 0;
If zero, then enter step 511 process ends.
If the current number of sectors that needs to transmit is not 0, then enter step 507, prepare a sectors of data and be transferred to simultaneously among two FLASH for DMA;
Enter step 509 then, open DMA the odd bytes of current sector and the data of even bytes are also write respectively among FLASH1 and the FLASH2 simultaneously; Perhaps, 512 bytes of current sector are divided into preceding 256 bytes and back 256 bytes are sent to FLASH1 and FLASH2 respectively;
Return step 505 then, judge whether the current number of sectors that needs to transmit is 0.
See also Fig. 6, the read data flow process receives read command by step 601 from main frame;
Enter step 603 then, obtain LBA (Logical Block Addressing) according to writing the initial sector address:
Described LBA (Logical Block Addressing)=logical sector address/(the sector number of 2* logical block);
And find described LBA (Logical Block Addressing) corresponding physical block address by logical comparison table, described logical comparison table has two kinds to build method, can make each sheet FLASH set up the table of comparisons of oneself, also can two shared tables of FLASH, during the but shared table of comparisons, if there are some BLOCK of a slice FLASH to break, then a slice FLASH corresponding physical BLOCK also will be marked as bad piece in addition;
Enter step 605 then, judge whether the current number of sectors that needs to transmit is 0;
If zero, then enter step 611 process ends.
If the current number of sectors that needs to transmit is not 0, then enter step 607, prepare a sectors of data and read from two FLASH for DMA;
Enter step 609 then, open DMA and also from FLASH1 and FLASH2, read the odd bytes of current sector and the data of even bytes simultaneously respectively; Perhaps, read preceding 256 bytes and back 256 of current sector from FLASH1 and FLASH2 respectively;
Return step 605 then, judge whether the current number of sectors that needs to transmit is 0.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (12)
1. data distributing method that improves data access speed, described method is used to improve the data access speed of main frame to flash memory device, described flash memory device comprises the control module that can carry out data transmission by communication protocol and main frame, be used for storing the memory module of data, comprise at least two storage mediums in the described memory module, described method comprises the steps:
1) makes described control module from the host receiving data read/write command, and obtain the sevtor address of described order indication data;
2) if the current number of sectors that needs transmission greater than 1, then simultaneously and is respectively carried out odd number of sectors and the read/write operation of even number sectors of data to the storage medium of correspondence;
3), then select corresponding storage medium to carry out the data read/write operation according to the parity of described sevtor address if described number of sectors is 1.
2. the data distributing method of raising data access speed according to claim 1 is characterized in that: described method further comprises according to described sevtor address calculates corresponding LBA (Logical Block Addressing), and obtains the corresponding physical block address by logical comparison table.
3. the data distributing method of raising data access speed according to claim 2 is characterized in that: described method comprises that further the storage medium that described physical block address is sent into described correspondence carries out the data read/write operation.
4. the data distributing method of raising data access speed according to claim 2 is characterized in that: described two storage mediums can a shared logical comparison table, also can use logical comparison table separately.
5. the data distributing method of raising data access speed according to claim 1, it is characterized in that: described control module is connected with a slice storage medium by data line D0-D7, control line CE1, control line ALE, CLE, RB, RE, WE, be connected control line ALE, the CLE of described two shared described control modules of storage medium, RB, RE, WE by data line D8-D15, control line CE2, control line ALE, CLE, RB, RE, WE with another sheet storage medium.
6. the data distributing method of raising data access speed according to claim 1 is characterized in that: described storage medium can be but be not limited to flash media (FLASH Memory), SDRAM, DRAM, EPPROM, ferromagnetic random access memory/ferroelectric memory (FRAM), magnetic random access memory (MRAM), ultrahigh density storage chip (MILLIPEDE).
7. the data distributing method of raising data access speed according to claim 1 is characterized in that: described communication protocol comprises but is not limited to usb protocol, the Zigbee agreement, the IEEE1394 agreement, Bluetooth protocol, the serial ATA agreement, the IDE agreement, the SCSI agreement, the HiperLAN agreement, the IrDA infrared protocol, the HomeRF agreement, IEEE802.11x, IEEE802.11a, 802.11b, 802.11d, 802.11.g, 802.15,802.16,802.3 agreement, the RS232 agreement, the RS485 agreement, the USB_OTG agreement, the UWB agreement, the GPIO agreement, the UART agreement, the CF agreement, the SM agreement, the MMC agreement, the SD agreement, the MS agreement, the MD agreement, the X-D agreement, the PCMCIA agreement, GSM, GPRS, CDMA, 2.5G and/or 3G agreement.
8. data distributing method that improves data access speed, described method is used to improve the data access speed of main frame to flash memory device, described flash memory device comprises the control module that can carry out data transmission by communication protocol and main frame, be used for storing the memory module of data, comprise at least two storage mediums in the described memory module, described method comprises the steps:
1) described control module is from the host receiving data read/write command, and obtains the sevtor address of described order indication data;
2) simultaneously and respectively the storage medium of correspondence is carried out the data read/write operation of the odd bytes and the even bytes of described sector, or described sector is divided into preceding 256 bytes and back 256 bytes simultaneously and respectively the storage medium of correspondence is carried out the data read/write operation.
9. the data distributing method of raising data access speed according to claim 8 is characterized in that: the offset address of each sectors of data in piece (Block) is the multiple of (256+8).
10. the data distributing method of raising data access speed according to claim 8, it is characterized in that: described control module is connected with a slice storage medium by data line D0-D7, control line CE, ALE, CLE, RB, RE, WE, be connected control line CE, the ALE of described two shared described control modules of storage medium, CLE, RB, RE, WE by data line D8-D15, control line CE, ALE, CLE, RB, RE, WE with another sheet storage medium.
11. the data distributing method of raising data access speed according to claim 8 is characterized in that: described storage medium can be but be not limited to flash media (FLASH Memory), SDRAM, DRAM, EPPROM, ferromagnetic random access memory/ferroelectric memory (FRAM), magnetic random access memory (MRAM), ultrahigh density storage chip (MILLIPEDE).
12. the data distributing method of raising data access speed according to claim 8 is characterized in that: described communication protocol comprises but is not limited to usb protocol, the Zigbee agreement, the IEEE1394 agreement, Bluetooth protocol, the serial ATA agreement, the IDE agreement, the SCSI agreement, the HiperLAN agreement, the IrDA infrared protocol, the HomeRF agreement, IEEE802.11x, IEEE802.11a, 802.11b, 802.11d, 802.11.g, 802.15,802.16,802.3 agreement, the RS232 agreement, the RS485 agreement, the USB_OTG agreement, the UWB agreement, the GPIO agreement, the UART agreement, the CF agreement, the SM agreement, the MMC agreement, the SD agreement, the MS agreement, the MD agreement, the X-D agreement, the PCMCIA agreement, GSM, GPRS, CDMA, 2.5G and/or 3G agreement.
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| WO2009121291A1 (en) * | 2008-03-31 | 2009-10-08 | 深圳市朗科科技股份有限公司 | Storage device and storage method |
| CN101930798A (en) * | 2009-06-25 | 2010-12-29 | 联发科技股份有限公司 | The method of flash memory device, storage arrangement and control flash memory device |
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| CN1549134A (en) * | 2003-05-19 | 2004-11-24 | 群联电子股份有限公司 | Alternative execution new control method for raising processing speed of plastic fast flash storage |
| CN100433195C (en) * | 2003-12-31 | 2008-11-12 | 深圳市朗科科技股份有限公司 | Flash memory medium data writing method |
| CN100346282C (en) * | 2004-03-31 | 2007-10-31 | 深圳市朗科科技有限公司 | Mobile storage device increasing data access speed and method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009121291A1 (en) * | 2008-03-31 | 2009-10-08 | 深圳市朗科科技股份有限公司 | Storage device and storage method |
| CN101930798A (en) * | 2009-06-25 | 2010-12-29 | 联发科技股份有限公司 | The method of flash memory device, storage arrangement and control flash memory device |
| CN101930798B (en) * | 2009-06-25 | 2014-04-16 | 联发科技股份有限公司 | Flash memory device, memory device and method for controlling flash memory device |
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| Publication number | Publication date |
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| CN100410864C (en) | 2008-08-13 |
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