CN1697075B - Input buffer of low flucturation of input signal - Google Patents
Input buffer of low flucturation of input signal Download PDFInfo
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- CN1697075B CN1697075B CN 200410043574 CN200410043574A CN1697075B CN 1697075 B CN1697075 B CN 1697075B CN 200410043574 CN200410043574 CN 200410043574 CN 200410043574 A CN200410043574 A CN 200410043574A CN 1697075 B CN1697075 B CN 1697075B
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- 230000003139 buffering effect Effects 0.000 claims description 27
- 229910044991 metal oxide Inorganic materials 0.000 claims description 15
- 150000004706 metal oxides Chemical class 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000013078 crystal Substances 0.000 claims description 3
- 230000004044 response Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 102100036466 Delta-like protein 3 Human genes 0.000 description 4
- 101710112748 Delta-like protein 3 Proteins 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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Abstract
An input buffer of low input signal fluctuation consists of a buffer input unit for receiving an input signal (SIGNAL_IN), a large capacitance channel controller CHC between PMOS bias node and power voltage Vss, as well as a buffer output unit for generating an output signal (SIGNAL_OUT1). It is featured as achieving purpose of earthing line noise removal by controlling power voltage Vss from linked bias VB11 to the input device.
Description
Technical field
The present invention is meant a kind of input buffer of low input-signal fluctuation especially normally relevant for an interface circuit.
Background technology
The present invention is applied on the input circuit of storage device, also be suggested in existing a large amount of solution before, as: United States Patent (USP) power numbers 5,978,310 (Bae et al) have described a kind of a kind of input buffer that is used for DRAM (Dynamic Random Access Memory) (DRAM) storage device, and it can remove the noise that comes from (identification of receiver code translator is used) column address wave filter.This device has a data fan-out capability that can be delayed a schedule time, and can produce the control signal of an output.Also having simultaneously a device exports according to the buffering that this control signal produces the noiselessness input.
United States Patent (USP) power number 6,002,618 (Komarek et al) have disclosed an a kind of N channel metal-oxide semiconductor (NMOS) input sink circuit that is used for ROM (read-only memory).It comprises the feedback loop of a control hysteresis, be useful on a subordinate phase and the additional output of receiver, transformation noise from internal memory inside is segregate, and can not feedback removes to influence the voltage levvl of transistor-transistor logic (circuit) TTL in acceptor circuit.It is minimized that the wide and long field effect transistor FET of size is used to receiver is changed the process variations amount of level.
An input buffer reacts on before the ground wire noise, still needs a kind of mechanical hook-up, and specific electric capacity can be used to reduce a this noise of storage input circuit.
Summary of the invention
Fundamental purpose of the present invention is that the input buffering receiver for a specific storage device provides a kind of efficient circuit design technique, to filter its ground wire noise.
Further purpose of the present invention provides a kind of method that reduces signal fluctuation in input buffer.This method is a jumbo electric capacity that adheres on the bias voltage node of the p channel metal oxide semiconductor of input buffering receiver (PMOS).
These purposes are finished by the input buffering receiver, and it comprises: in order to receive the impact damper importation of an input signal SIGNAL_IN; Bias voltage node and a supply voltage V in a P channel metal-oxide semiconductor (PMOS)
SSBetween a high capacitance channel controller CHC, in order to produce the impact damper output of an output signal SIGNAL_OUT1.
In addition, in the input buffering receiver, the gate voltage signal V of transistor P11 and transistor P12
B11Connected load supply voltage V
SS, this will cause output signal SIGNAL_OUT1 that the reaction time is faster arranged.
By following every detailed description to a preferred embodiment of the present invention, aforesaid and other purpose, each side and advantage all will be understood than being easier to.
Description of drawings
Fig. 1 is the input buffering acceptor circuit figure according to prior art.
Fig. 2 is an input buffering receiver preferred embodiment circuit diagram of the present invention.
Fig. 3 A is the definition time vector plot that fluctuation promotes in the input buffering receiver of the present invention.
Fig. 3 B is the definition time vector plot that fluctuation falls after rise in the input buffering receiver of the present invention.
Fig. 4 A is the present invention reduces fluctuation with electric capacity channel controller CHC a equivalent circuit diagram.
Fig. 4 B is the present invention reduces fluctuation with electric capacity channel controller CHC a work synoptic diagram.
＜icon set piece number number reference 〉
100,101 ... impact damper importation 200,201 ... the impact damper output
N1, N2, N11, N12 ... N channel metal-oxide semiconductor
V
SSSupply voltage P1, P2, P11, P12 ... P channel metal-oxide semiconductor
V
DDSupply voltage V
B1, V
B11Signal
I1, I11 ... reverser CHC ... the electric capacity channel controller
Embodiment
Fig. 1 is the input buffering acceptor circuit figure according to prior art, and this input buffering receiver comprises: be used for the impact damper importation 100 of receiving inputted signal SIGNAL_IN, and be used for producing the impact damper output 200 of output signal SIGNAL_OUT.
Impact damper importation 100 includes: transistor N1, the N2 of two N channel metal-oxide semiconductor (NMOS), and at this, a lower supply voltage V
SSBe applied in the source node of this transistor N1, N2, and transistor P1, the P2 of two P channel metal-oxide semiconductor (PMOS), at this, a higher supply voltage V
DDBe applied in its source node, and a signal V
B1Be connected to the gate node of transistor P1, P2, in the prior art, a reference voltage V
REFBe applied in the gate of transistor N1, input signal SIGNAL_IN is connected to the gate of transistor N2, and signal V
B1Be applied in the drain of transistor N1 and transistor P1, similarly be applicable to the bias voltage node of the P channel metal-oxide semiconductor of transistor P1 and electric crystal P2.This input signal SIGNAL_IN is a kind of signal of low swing; Impact damper output 200 is made up of a common node of transistor N2 drain and transistor P2 drain, and it is suitable as the input to a reverser I1, and the output of reverser I1 is output signal SIGNAL_OUT.
Fig. 2 is an input buffering receiver preferred embodiment circuit diagram of the present invention, shown in this figure, the present invention includes: an impact damper importation 101 and an impact damper output 201, this buffering importation 101 includes: the transistor N11 of two N channel metal-oxide semiconductor and transistor N12, at this, a lower supply voltage V
SSBe applied in the source node of transistor N11 and transistor N12, the transistor P11 of two P channel metal-oxide semiconductor and transistor P12, at this, a higher supply voltage V
DDBe applied in source node, with a signal V
B11Be connected in the gate node of transistor P11 and transistor P12, with a reference voltage V
REFBe connected in the gate of this transistor N11, input signal SIGNAL_IN is applied in the gate of transistor N12, and signal V
B11Be connected in the drain of transistor N11 and transistor P11.In the present invention, big electric capacity channel controller CHC is at the bias voltage node signal V of PMOS metal-oxide semiconductor (MOS)
B11With supply voltage V
SSBetween, impact damper output 201 is made up of a common node of the drain of the drain of electric crystal N12 and transistor P12, and it is suitable as the input to a reverser I11, and the output of reverser I11 is output signal SIGNAL_OUT1 of the present invention.
High capacitance channel controller CHC is that the stray capacitance with input buffering acceptor device transistor N11, P11 and P12 is in series, the V of P channel metal-oxide semiconductor bias voltage node because its big connection ratio, this high capacitance channel controller CHC have doubled to charge basically
B11Gate voltage, and for the voltage source V of transistor N11 and transistor N12
SS, then allow output signal SIGNAL_OUT1 signal that ratio response time is faster arranged.
Fig. 3 A, Fig. 3 B are the definition time vector plots that fluctuation promotes, falls after rise in the input buffering receiver of the present invention, by this two figure input signal SIGNAL_IN of the present invention as can be known, voltage source V
SS, and the time control method of operation of output signal SIGNAL_OUT1, SIGNAL_IN is defined as V when input signal
1H=V
REF+ 350mv and V
1L=V
REF-350mv, supply voltage V
SSBe 200mv.When input signal SIGNAL_IN increased, output signal SIGNAL_OUT1 defined by the DELTA1 or the DELTA2 that postpone, and during input signal SIGNAL_IN decline, and then the DELTA3 or the DELTA4 that are delayed of this output signal SIGNAL_OUT1 defines.As supply voltage V
SSDuring=200mv, this DELTA1 is defined as from the rising edge of input signal SIGNAL_IN to the delay of the rising edge of output signal SIGNAL_OUT, as transistor N12 experience supply voltage V
SSNoise, and when faintly opening, it is the delay on the output signal SIGNAL_OUT1, as voltage source V
SSDuring=0v, DELTA2 is defined as from the rising edge of input signal SIGNAL_IN to the delay of the rising edge of output signal SIGNAL_OUT1, when transistor N12 does not experience supply voltage V
SSNoise, and when opening consumingly, it is the delay on the output signal SIGNAL_OUT1, and as voltage source V
SSDuring=0v, DELTA3 is defined as from the drop edge of SIGNAL_IN to the delay of the drop edge of output signal SIGNAL_OUT1, when transistor N12 does not experience supply voltage V
SSNoise, and faintly pent the time, it is the delay on the output signal SIGNAL_OUT1.As supply voltage V
SSDuring=200mv, DELTA4 is defined as from the drop edge of input signal SIGNAL_IN to the delay of the drop edge of output signal SIGNAL_OUT1, as transistor N12 experience supply voltage V
SSNoise, and when being opened intensely, it is the delay on the output signal SIGNAL_OUT1; According to above-mentioned definition, DELTA2 or DELTA4 are less than DELTA1 or DELTA3, when input signal SIGNAL_IN rises, it is different that fluctuation between DELTA1 or DELTA2 promotes JITTER_RISE, and when input signal SIGNAL_IN descended, it was different that the fluctuation between DELTA3 or DELTA4 falls JITTER_FALL after rise.Electric capacity channel controller CHC mainly utilizes the device that transistor P12 and transistor N12 are arranged with being in the present invention, and the fluctuation that almost exists simultaneously or do not exist in the ground wire noise promotes JITTER_RISE and fluctuation falls JITTER_FALL after rise to reduce.
Fig. 4 A is the present invention reduces fluctuation with electric capacity channel controller CHC a equivalent circuit diagram, by its with reference to Fig. 4 B reduce the work synoptic diagram of fluctuation with electric capacity channel controller CHC, this electric capacity channel controller CHC connects ratio double the to charge bias voltage node signal V of two PMOS metal-oxide semiconductor with high capacity as can be known
B11, come from the supply voltage V of input buffering receiver
SS, this will cause output signal SIGNAL_OUT1 signal that one response time was faster arranged.
The above only is a preferred embodiment of the present invention, is not to be used for limiting scope of the invention process.Be that all equalizations of being done according to claim scope of the present invention change and modification, be all claim of the present invention and contain.
Claims (9)
1. the input buffering receiver of low input-signal fluctuation, it is characterized in that: it comprises:
One for receiving inputted signal SIGNAL_IN impact damper importation, comprises: a first transistor N11 has the one source pole node and is connected to supply voltage V
SS, a gate node is connected to a reference voltage V
REFAnd one the drain node be connected to a bias voltage node signal V
B11One transistor seconds P11 has a drain node, is connected to the drain node of the first transistor N11, and a gate is connected to bias voltage node signal V
B11, one source pole is connected to a supply voltage V
DDOne the 3rd transistor P12 has a drain node, is connected to the drain node of following the 4th transistor N12, and a gate node is connected to bias voltage node signal V
B11, the one source pole node is connected to a supply voltage V
DDOne the 4th transistor N12 has the one source pole node and is connected to supply voltage V
SS, a gate node is connected to input signal SIGNAL_IN, and an input drain node that is connected to the impact damper output;
One electric capacity, it is at described bias voltage node and described supply voltage V
SSBetween;
One in order to produce output signal SIGNAL_OUT1 impact damper output, and comprise: one is connected to the reverser I11 of the 3rd transistor P12 drain and the 4th transistor N12 drain.
2. the input buffering receiver of low input-signal fluctuation as claimed in claim 1, it is characterized in that: wherein this first transistor N11 and the 4th transistor N12 all are the transistors of NMOS metal-oxide semiconductor, and transistor seconds P11 and the 3rd transistor P12 are the transistors of PMOS metal-oxide semiconductor.
3. the input buffering receiver of low input-signal fluctuation as claimed in claim 1, it is characterized in that: wherein this electric capacity is at first electric crystal N11 of impact damper importation and the source electrode of the 4th transistor N12, and is connected between the gate of the transistor seconds P11 of impact damper importation.
4. the input buffering receiver of low input-signal fluctuation as claimed in claim 1, it is characterized in that: wherein the gate of this transistor seconds P11 is connected to its drain.
5. the input buffering receiver of low input-signal fluctuation as claimed in claim 1, it is characterized in that: wherein the gate of this transistor seconds P11 is connected to the drain of the first transistor N11.
6. the input buffering receiver of low input-signal fluctuation as claimed in claim 1, it is characterized in that: wherein the gate of this transistor seconds P11 is connected to the gate of the 3rd transistor P12.
7. the input buffering receiver of low input-signal fluctuation as claimed in claim 1 is characterized in that: wherein the 3rd transistor P12 and the 4th transistor N12 while is excited.
8. the input buffering receiver of low input-signal fluctuation as claimed in claim 1, it is characterized in that: wherein this electric capacity is used to double to control the described bias voltage node of input buffering receiver, to the voltage source V of input buffering receiver
SS
9. the input buffering receiver of low input-signal as claimed in claim 1 fluctuation is characterized in that: wherein this electric capacity causes output signal SIGNAL_OUT1 signal that one response time was faster arranged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410043574 CN1697075B (en) | 2004-05-14 | 2004-05-14 | Input buffer of low flucturation of input signal |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410043574 CN1697075B (en) | 2004-05-14 | 2004-05-14 | Input buffer of low flucturation of input signal |
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| CN1697075A CN1697075A (en) | 2005-11-16 |
| CN1697075B true CN1697075B (en) | 2011-04-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200410043574 Active CN1697075B (en) | 2004-05-14 | 2004-05-14 | Input buffer of low flucturation of input signal |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5729165A (en) * | 1996-04-04 | 1998-03-17 | National Science Council | 1.5v full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage deep-submicron CMOS VLSI |
| US6002618A (en) * | 1994-08-15 | 1999-12-14 | Creative Integrated Systems | NMOS input receiver circuit |
| CN1239576A (en) * | 1997-07-18 | 1999-12-22 | 罗姆股份有限公司 | Memory with processing function |
| US6242973B1 (en) * | 1998-09-01 | 2001-06-05 | Hyundai Electronics Industries Co., Ltd. | Bootstrapped CMOS driver |
| US20040085137A1 (en) * | 2002-08-27 | 2004-05-06 | Furst Claus Erdmann | Preamplifier for two terminal electret condenser microphones |
-
2004
- 2004-05-14 CN CN 200410043574 patent/CN1697075B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6002618A (en) * | 1994-08-15 | 1999-12-14 | Creative Integrated Systems | NMOS input receiver circuit |
| US5729165A (en) * | 1996-04-04 | 1998-03-17 | National Science Council | 1.5v full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage deep-submicron CMOS VLSI |
| CN1239576A (en) * | 1997-07-18 | 1999-12-22 | 罗姆股份有限公司 | Memory with processing function |
| US6242973B1 (en) * | 1998-09-01 | 2001-06-05 | Hyundai Electronics Industries Co., Ltd. | Bootstrapped CMOS driver |
| US20040085137A1 (en) * | 2002-08-27 | 2004-05-06 | Furst Claus Erdmann | Preamplifier for two terminal electret condenser microphones |
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|---|---|
| CN1697075A (en) | 2005-11-16 |
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