CN1691324A - Electrostatic discharge protecting device - Google Patents
Electrostatic discharge protecting device Download PDFInfo
- Publication number
- CN1691324A CN1691324A CN 200410042024 CN200410042024A CN1691324A CN 1691324 A CN1691324 A CN 1691324A CN 200410042024 CN200410042024 CN 200410042024 CN 200410042024 A CN200410042024 A CN 200410042024A CN 1691324 A CN1691324 A CN 1691324A
- Authority
- CN
- China
- Prior art keywords
- switch
- electrostatic discharge
- protective equipment
- discharge protective
- gate terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 32
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 21
- 230000001681 protective effect Effects 0.000 claims description 80
- 230000003068 static effect Effects 0.000 claims description 73
- 238000005516 engineering process Methods 0.000 claims description 36
- 238000012360 testing method Methods 0.000 claims description 26
- 238000002360 preparation method Methods 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 9
- 229910021332 silicide Inorganic materials 0.000 abstract description 27
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 230000004224 protection Effects 0.000 description 36
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 26
- 238000010586 diagram Methods 0.000 description 12
- 239000000758 substrate Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 239000011469 building brick Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 238000007599 discharging Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000006378 damage Effects 0.000 description 4
- 230000001808 coupling effect Effects 0.000 description 3
- 230000008485 antagonism Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005421 electrostatic potential Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 206010003497 Asphyxia Diseases 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000001012 protector Effects 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 235000013599 spices Nutrition 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
An electrostatic discharge protecting apparatus for multi power sources, comprising: a first switch which is metal oxide semiconductor transistor; a detecting circuit connects the first switch and internal circuit; when electrostatic discharge happens, the protecting apparatus will discharge when the first switch is on and under the standing current while not under the breakdown situation. Using metal oxide semiconductor component, lock detecting circuit and metal oxide semiconductor transistor apparatus which goes through self aligning metal siliconize preparing art, the switch controlling the electrostatic discharge path turn on when the electrostatic discharge happens and make the internal circuit work at certain action current and don't need the transistor's drain with silicides spacing block to enhance the protecting ability of electrostatic discharge.
Description
Technical field
The present invention relates to a kind of electrostatic discharge protective equipment; particularly relate to a kind of device that uses metal-oxide semiconductor assembly, bolt-lock testing circuit and self-aligned metal silication preparation technology, can reach when discharge of electricity takes place and still can keep the electrostatic discharge protective equipment that internal circuit remains on certain running electric current.
Background technology
When electronic building brick operates, static discharge effect (Electro-Static Discharge, ESD) be to cause most electronic building brick or electronic system to be subjected to excessively electrically stress (Electrical Overstress, EOS) principal element of Po Huaiing, especially more and more accurate in assembly preparation technology, size is more and more little, the static discharge effect punctures assembly easily, can cause a kind of to a kind of nonvolatil breaking-ups of formation such as semiconductor subassembly and computer systems, and influence the circuit function of integrated circuit, make that electronic product work is undesired.The generation of static discharge, mostly be because human factor forms, be difficult to the static discharge situation of avoiding human factor like this to cause, reason be electronic building brick or system make, produce, assemble, test, deposit or handling process in, static can be accumulated in human body, instrument or store equipment, even electronic building brick itself also has the accumulation of static, under certain conditions, human body and equipment contact or electronic building brick between contact, will form the discharge path of a static discharge, make electronic building brick or system suffer uncertain destruction.
Be the infringement of asking effective anti-blocking static discharge current that electronic building brick is caused; promptly by ESD protection circuit so that ESD current drain path to be provided; the maximum electrostatic discharging current that general electrostatic protection assembly can bear; the secondary breakdown point D that should be equivalent to this assembly; secondary breakdown district B shown in Fig. 1 voltage-current characteristic figure and secondary breakdown point D; if electric current has arrived this secondary breakdown district B, then can cause nonvolatil destruction to assembly.At present general protective circuit assembly uses as contrary diode partially; two-carrier transistor (Bipolar); metal-oxide semiconductor (MOS) assembly and silicon controlled rectifier (Silicon-Controlled Rectifier; SCR) etc.; in these protection circuits; be to utilize assembly to be operated in it once to collapse (first breakdown) district and discharge static discharge current mostly; once collapse district A shown in Fig. 1 volt-ampere characteristic curve; assembly is when arriving once collapse district A through a collapse point C; this electrostatic protection device promptly operates on counter-rotating collapse district (snap breakdown) E in the icon; the electrostatic protection assembly can not damage, and because of assembly ground connection (zero potential) formation one ESD current drain path.
General electrostatic protection apparatus is at human body discharge mode (Human-body Model; HBM) or machine discharge mode (Machine Model; MM); static enters in the internal circuit via integrated circuit pin position (Pin) via the human body or the machine in the external world; so general electrostatic discharge protective circuit all is set directly at inputing or outputing by the weld pad (Bonding pad), to discharge static discharge current nearby of internal circuit.And assembly charge mode (Charged-Device Model, CDM) electrostatic charge is stored in the substrate (Substrate) of assembly suspension joint earlier, when the ground connection of a certain pin position, therefore these electrostatic charges just obtain a discharge path and discharge out by the pin position of ground connection.The static discharge phenomenon of this kind assembly charge mode; the as easy as rolling off a log input grid (gate) that causes is punched; even if the input grid has had the use of electrostatic discharge protective circuit, but the assembly charge mode static discharge current that still can't conducting under a lot of situations produces with discharging moment.
Seeing also known technology Fig. 2, is the schematic diagram of an electrostatic discharge protective circuit 20 shown in the figure.Electrostatic discharge protective circuit 20 includes a main ESD (Electrostatic Discharge) clamp circuit 22; an ESD (Electrostatic Discharge) clamp circuit 24; one resistance 26; this resistance 26 is earlier with in parallel with main ESD (Electrostatic Discharge) clamp circuit 22 again after inferior ESD (Electrostatic Discharge) clamp circuits 24 are connected; protection internal circuit 21 was unlikely to because the CMOS transistor 28 (PMOS of the static discharge current that the static discharge voltage 23 that is subjected to importing in the external world is produced 25 infringement input stages since this ESD protection circuit 20 was positioned at input weld pad 29 sides; NMOS); wherein static discharge current is represented by dotted lines, for electrostatic discharge protective circuit 20 is directed to earth terminal 27.
When the static discharge of human body discharge mode or machine discharge mode occurs in the pin position of input weld pad 29, come from the grid that extraneous high potential electrostatic potential 23 is transmitted to the CMOS transistor 28 of input stage, because of the major function of this time ESD (Electrostatic Discharge) clamp circuit 24 is the electrostatic potential input 23 that strangulation is too high, damaged by too high static discharge voltage with the gate terminal that prevents CMOS transistor 28.But general inferior ESD (Electrostatic Discharge) clamp circuit 24 all is to utilize N type metal-oxide semiconductor (NMOS) assembly of short channel (Short-channel) to realize, generally all hold and can't stand great static discharge current 25, therefore need add resistance 26 and main ESD (Electrostatic Discharge) clamp circuit 22 again, with avoid excessive static discharge current to flow through inferior ESD (Electrostatic Discharge) clamp circuit 24 that short channel NMOS assembly formed.The main ESD (Electrostatic Discharge) clamp circuit 22 of static discharge current 25 main dependences discharges, and forms main ESD (Electrostatic Discharge) clamp circuit 22 so need the guard assembly of higher electric current ability to bear.But this class component generally all has higher conducting voltage or slower conducting speed, therefore needs the auxiliary grid that can protect CMOS transistor 28 effectively of time ESD (Electrostatic Discharge) clamp circuit 24 again.Yet; the ESD protection circuit 20 of this known technology can equivalence becomes the bigger resistance and the combination of electric capacity; operate on the counter-rotating collapse district E after A is distinguished in once collapse shown in Figure 1; and will have bigger RC time constant to postpone relatively to input term signal, and be not suitable for the application of high-frequency signal and current-mode input signal.
Along with advanced technologies as drain electrode light dope (Light Doped Drain; LDD) and silicide diffusion (Silicide diffusion) preparation technology's use; though on the integrated level of integrated circuit and arithmetic speed, promote to some extent, relatively sacrificed the static discharge antagonism of integrated circuit (no matter be internal circuit or be applied in ESD protection circuit).
In order to overcome the problem of bringing the static discharge antagonism to descend because of the LDD structure, just develop on the preparation technology and static discharge implantation preparation technology (ESD-Implant Process), its notion is in same complementary metal oxide semiconductors (CMOS) (CMOS) preparation technology, make two kinds of different NMOS assemblies, a kind of is to the NMOS assembly of internal circuit with LDD structure, and another kind is to the use of I/O level but the NMOS assembly that does not have the LDD structure.To be incorporated in these two kinds of modular constructions among the same preparation technology, just need in original preparation technology, add one deck static discharge again and implant the light shield of usefulness, add some extra preparation technology's treatment steps, just can in same preparation technology, make different N MOS assembly.In addition, owing to use the NMOS assembly of static discharge implantation preparation technology institute output different with the NMOS assembly of LDD structure, so need extra processing and design to extract the SPICE parameter that this static discharge is implanted preparation technology NMOS assembly, be beneficial to the carrying out of circuit simulation and design work.
As for the silicide diffusion technology, its main purpose with the service speed of lifting MOS assembly, and then makes the CMOS technology can accomplish the application of higher frequency reducing the MOS assembly in the stray resistance of connecting of drain electrode (drain) with source terminal.But it is also all very little by its stray resistance, make when static discharge takes place, static discharge current can be transmitted to the LDD structure of MOS assembly at an easy rate, and the destruction of causing the MOS assembly, even use again the MOS assembly of large scale length-width ratio (W/L) to work as the resistivity that output stage also can't promote its static discharge effectively.To this, in order to promote the electro-static discharge protective ability of output stage, on preparation technology, develop the fabricating technology that silicide diffusion spacing block (Silicide Diffusion Blocking), give removal the disilicide layer of part in the output stage MOS assembly, so do and to make the MOS assembly have higher source electrode and drain resistance, and can promote the protective capacities of MOS assembly effectively static discharge.
Above-mentioned known technology sees also Fig. 3 A and Fig. 3 B, and Fig. 3 A and Fig. 3 B are respectively the schematic layout pattern whether MOS assembly drain electrode has silicide spacing block (Silicide block) to be provided with.Fig. 3 A is not for there being the layout that the silicide spacing block is set, include source contact 32a up and down, the metal level 31a of 32b, 31b, many silicon gates (Poly gate) 34 of metering function are arranged therebetween, and there are a plurality of drain contacts 33 centre, and Fig. 3 B that improves at Fig. 3 A then is the setting that the silicide spacing block is arranged, and because the restriction on the layout makes that the distance (Spacing) between drain electrode 33 and source electrode 32a, 32b must reach the degree that this silicide spacing block 35 can be set.Although silicide spacing block 35 is to be used for increasing the resistance of 34 of drain contact 33 and many silicon gates and effect that current limliting can be arranged, make this kind MOS assembly can strengthen to some extent for the resistance of static discharge, but also because the increase of distance between drain contact 33 and source contact 32a, 32b, the layout of whole M OS assembly also will occupy bigger area (space), relatively will influence the number of the MOS assembly that can produce on the single wafer.In addition, with regard to the viewpoint of input, the increase of resistance postpones the related RC time constant of input signal that makes to increase, and is unsuitable for the high-frequency signal or the input of current signal pattern.
See also the schematic diagram that ESD protection circuit that Fig. 4 U.S. Pat 2002/1030390 disclosed is used for protecting internal circuit.Wherein electrostatic discharge protective circuit 40 all is electrically connected with 44 with at least two power lines 43 with internal circuit 42, wherein power line 43 and 44 a preferable power supply line and the zero potential power lines of being respectively.
The ESD protection circuit 410 that ESD protection circuit 40 includes a power line 43 and 44 is comprised of phase inverter 412 and the RC delay circuit 413 of a CMOS, so that the static discharge current that static discharge voltage is derived can follow along inclined to one side diode pair (D1 and D2 or D3 and D4) or operate in the substrate triggering metal oxide semiconductor transistor (Substrate-triggered MOS) 417 of ESD protection circuit 410 between the power line of once collapse district A shown in Figure 1 (or counter-rotating collapse (Snapback Breakdown) district E) and can obtain an electrostatic discharging path. CMOS inverter 412 is to be used for triggering substrate to trigger metal oxide semiconductor transistor 417, and the grid of substrate triggering metal oxide semiconductor transistor 417 is connected with power line 44 by a resistance R 2, be used for when no static discharge takes place, keep this substrate to trigger metal oxide semiconductor transistor 417 and remain on closing state.This ESD protection circuit is to be set directly between input weld pad 45 and the internal circuit 42, is used to provide the discharge path of static discharge current.Junction rectifier respectively can equivalence become a capacitor C 1 to C4 to D1 to D4, and C1 is to connect with C4 with C3 with C2, and the capacitance of whole equivalence can increase and descend along with the quantity that is provided with of junction rectifier.
In ESD protection circuit shown in Figure 4 40, no matter be that substrate triggers the setting that MOS assembly (capacitor C in the RC delay circuit 413 can be realized by a MOS assembly) in metal oxide semiconductor transistor 417, CMOS inverter 412 and the RC delay circuit 413 all must have the drain silicide spacing block 35 that Fig. 3 B led to.When the drain electrode of MOS assembly has being provided with of silicide spacing block, can improve resistance really, but the equivalent input resistance value that thereupon rises will influence the application of this kind MOS assembly in the high frequency field to static discharge.In addition, the occupied area of the MOS assembly that the occupied area of this kind MOS assembly does not have the silicide spacing block to be provided with than general technology yet is for big, will cause MOS assembly on the single wafer that the decline of number is set relatively.
In view of known electrostatic discharge protection circuit cause structural area too big with the shortcoming that signal delay is arranged; the present invention promptly proposes one need not use the silicide spacing block, and still can keep the electrostatic discharge protective equipment that internal circuit remains on certain running electric current when static discharge takes place.
Summary of the invention
It is big to the objective of the invention is to solve known electrostatic discharge protective equipment footprint area; be unsuitable for the high-frequency signal or the shortcomings such as input of current signal pattern; and provide a kind of protector of static discharge; it still can be kept internal circuit and remain on certain running electric current when static discharge takes place, and improves the protective capacities to static discharge effectively.
In order to achieve the above object; the invention provides a kind of electrostatic discharge protective equipment; by using the devices such as transistor of metal-oxide semiconductor assembly, testing circuit and self-aligned silication technique for metal; make and when static discharge takes place, still can keep under the running electric current that internal circuit remains on certain static discharge; and do not need to use the silicide spacing block to strengthen the electrostatic discharge (ESD) protection ability, stablize operational effectiveness and the purpose that reduces electrostatic defending assembly area and reach in this transistor drain (drain).
This device includes a testing circuit, includes an electric capacity, a second switch at least, and is electrically connected to the internal circuit of desire protection; With one first switch, be implemented in N type metal-oxide semiconductor (NMOS) with a self-aligned silication technique for metal, the gate terminal of this first switch connects this testing circuit; Thus, device reaches when static discharge takes place, stabling current discharge down when this electrostatic discharge protective equipment operates on the opening of this first switch, but not operate under the collapse characteristic of assembly.
That is to say, the invention provides a kind of electrostatic discharge protective equipment, be used between a plurality of power supplys, wherein this device comprises: one first switch is a metal oxide semiconductor transistor; And a testing circuit, electrically connect this first switch and an internal circuit; When static discharge took place, this electrostatic discharge protective equipment discharged under the stabling current when the opening of this first switch, was not under the collapse characteristic of assembly and discharge.
According to design of the present invention, this first switch is a self-aligned metal silication preparation technology (Self-Aligned Silicidation, the N type metal-oxide semiconductor of salicide) making.
According to design of the present invention, this electrostatic discharge protective equipment cross-over connection is between these a plurality of power supplys.
According to design of the present invention, this testing circuit connects the gate terminal of this first switch.
According to design of the present invention, this first switch electrically connects this internal circuit.
According to design of the present invention, can a plurality of first switches in parallel on this first switch.
A kind of electrostatic discharge protective equipment is provided according to a further aspect in the invention, has been used for that this device comprises at least between a plurality of power supplys: a testing circuit comprises an electric capacity, a second switch, and is electrically connected to an internal circuit; And one first switch, be the N type metal oxide semiconductor transistor made from a self-aligned metal silication preparation technology (NMOS), the gate terminal of this first switch connects this testing circuit; When static discharge took place, stabling current discharge down when this electrostatic discharge protective equipment operates on the opening of this first switch non-ly operated on assembly collapse characteristic and discharges.
According to design of the present invention, this electrostatic discharge protective equipment cross-over connection is between these a plurality of power supplys.
According to design of the present invention, the drain electrode end of this second switch of this testing circuit connects the gate terminal of this first switch.
According to design of the present invention, this electric capacity is connected between the drain electrode end of gate terminal, second switch of this power supply and this first switch.
According to design of the present invention, this first switch electrically connects this internal circuit.
According to design of the present invention, a plurality of first switches in parallel on this first switch.
A kind of electrostatic discharge protective equipment is provided according to a further aspect in the invention, has been used between a plurality of power supplys, this device comprises: one first switch is a metal oxide semiconductor transistor; One second switch, the drain electrode end of this second switch connects the gate terminal of this first switch; One electric capacity connects the gate terminal of this first switch and the drain electrode end of this second switch; And an internal circuit, electrically connect this first switch and this second switch; When static discharge takes place, stabling current discharge down when this electrostatic discharge protective equipment operates on the opening of this first switch, non-operating under the assembly collapse characteristic discharged, and the gate terminal current potential of this second switch determines the keying state of this first switch.
According to design of the present invention, this first switch is a N type metal oxide semiconductor transistor made from the self-aligned silication technique for metal.
According to design of the present invention, this electrostatic discharge protective equipment cross-over connection is between these a plurality of power supplys.
According to design of the present invention, a plurality of first switches in parallel on this first switch.
A kind of electrostatic discharge protective equipment is provided according to a further aspect in the invention, be used between a plurality of power supplys, when static discharge takes place, this electrostatic discharge protective equipment is stabling current discharge down when the opening of this first switch, discharge under the non-collapse characteristic that operates on assembly, this device comprises: one first switch is the N type metal oxide semiconductor transistor made from a self-aligned metal silication preparation technology; One second switch, the drain electrode end of this second switch connects the gate terminal of this first switch, to control the keying state of this first switch; One electric capacity connects the gate terminal of this first switch and the drain electrode end of this second switch; And an internal circuit, electrically connect this first switch and this second switch.
According to design of the present invention, this electrostatic discharge protective equipment cross-over connection is between these a plurality of power supplys.
According to design of the present invention, a plurality of first switches in parallel on this first switch.
Electrostatic discharge protective equipment of the present invention; can be under the situation of not using the silicide spacing block; use the technology of self-aligned metal silication program to keep internal circuit and remain on certain running electric current, reach that layout area is little, protective capacities big, reduce ghost effect and the purpose of improving the high frequency running.
Description of drawings
Fig. 1 is known voltage-current characteristic figure;
Fig. 2 is the electrostatic discharge protective circuit schematic diagram of known technology;
Fig. 3 A and Fig. 3 B are the schematic layout pattern that the silicide spacing block of known technology MOS assembly drain electrode is provided with;
Fig. 4 is the ESD protection circuit protection internal circuit schematic diagram of known technology;
Fig. 5 A is an electrostatic discharge protective equipment schematic diagram of the present invention;
Fig. 5 B is electrostatic discharge protective equipment running performance plot of the present invention;
Fig. 6 is the electrostatic discharge protective equipment first embodiment schematic diagram of the present invention;
Fig. 7 is the electrostatic discharge protective equipment second embodiment schematic diagram of the present invention;
Fig. 8 is electrostatic discharge protective equipment the 3rd an embodiment schematic diagram of the present invention.
Wherein, description of reference numerals is as follows:
A once collapses the district; B secondary breakdown district; Collapse point of C; D one secondary breakdown point;
E one protective device operating space; 20 1 electrostatic discharge protective circuits; 21 1 internal circuits;
22 1 main ESD (Electrostatic Discharge) clamp circuits; 23 1 voltages; 24 ESD (Electrostatic Discharge) clamp circuits;
25 1 electric currents; 26 1 resistance; 27 1 earth terminals;
28 1 CMOS transistors; 29 1 input weld pads;
31a one metal level; 31b one metal level; 32a one source pole contact; 32b one source pole contact;
33 1 drain contacts; Silicon gate more than 34 1; 35 1 silicide spacing blocks;
40 1 electrostatic discharge protective circuits; 42 1 internal circuits; 43 1 power lines; 44 1 power lines;
45 1 input weld pads; 410 1 ESD protection circuits; 412 1 CMOS inverters;
413 1 RC delay circuits; 417 1 substrates trigger metal oxide semiconductor transistor;
R1 one resistance; R2 one resistance; C1 one electric capacity; C2 one electric capacity; C3 one electric capacity;
C4 one electric capacity; D1 one diode; D2 one diode; D3 one diode;
D4 one diode; M1 one first switch; M2 one second switch; M3 1 the 3rd switch;
VDD one first power supply; C one electric capacity; VSS one second source; 50 internal circuits;
52 1 testing circuits; Io one stabling current; R one resistance; M one transistor;
A M ' transistor; M " transistor; 80 1 internal circuits; 82 1 testing circuits.
Embodiment
Utilize a RC delay circuit to live with respect to known technology above the static discharge bolt-lock of a quota magnitude of voltage; wait for discharge within a certain period of time; and be used for increasing the resistance between drain electrode and many silicon gates and the effect of current limliting can be arranged with the silicide spacing block; make this kind MOS assembly can strengthen (seeing also Fig. 3 B) to some extent for the resistance of static discharge; the present invention is by using cross-over connection in the metal-oxide semiconductor assembly (MOS) of a plurality of power supplys; bolt-lock testing circuit (latch; detected turned-on circuit) with the device such as metal oxide semiconductor transistor of self-aligned silication technique for metal (Salicide); make the internal circuit that when static discharge takes place, still can keep desire protection of the present invention remain on the electrostatic discharge protective equipment of certain running electric current, do not need to use the silicide spacing block to strengthen the electrostatic discharge (ESD) protection ability in this transistor drain (drain).
See also Fig. 5 A electrostatic discharge protective equipment schematic diagram of the present invention; be illustrated as a cross-over connection two power supply (VDD; VSS) electrostatic discharge protective equipment between; wherein the switch of Control current keying (on/off) is all specifically with metal-oxide semiconductor (MOS) (NMOS; PMOS) implement; between the first power vd D and second source VSS, be provided with when one first switch M1 takes place as static discharge and the conducting electric current arranged to set up the switch of discharge path effect; a plurality of switch of the present invention is to realize (NMOS) with N type metal-oxide semiconductor; and the preparation technology of all right self-aligned metal silication of first switch makes; need not comprise the silicide spacing block; other has a testing circuit 52 to connect the gate terminal (gate) of the first switch M1; at any time control the static discharge situation, its grid connects internal circuit 50.
Device as Fig. 5 A; do not have under the normal operation of static discharge situation generation; the first switch M1 is for closing (off) state; when static discharge takes place; because of capacitance coupling effect in the testing circuit 52 produces high potential the first switch M1 is opened; the electrostatic induced current that produces through the first power vd D then is directed to second source VSS ground connection thus, forms a discharge path and reaches purpose to internal circuit 50 electrostatic discharge (ESD) protections.Because of the grid of internal circuit 50 with testing circuit 52 is connected, can monitor the discharge situation of static discharge at any time, promptly control the gate terminal P current potential of the first switch M1 by testing circuit 52, open (on) time with control, when electric current is higher than an electrostatic current upper limit (threshold), even the first switch M1 opens, the discharge of wait electrostatic current, if be lower than this upper limit, what be about to closes, and is not the collapse characteristic (as the counter-rotating collapse district E of Fig. 1) that operates on assembly.Present embodiment is monitored the static discharge situation because use with the testing circuit 52 of internal circuit 50; practice need not use the silicide spacing block to strengthen protective capability; only need transistor (the Self-Aligned Silicidation of self-aligned silication technique for metal; Salicide), reduce circuit parasitic effect and the effect that reduces the assembly area to reach.
Above-mentioned come the first switch M1 done by testing circuit 52 open and close control; change the keying state along with the static discharge situation; it is not the collapse characteristic of using static discharge protection component; even in high-tension static discharge state; integrated circuit is operated under the stable discharging electric current I o situation as Fig. 5 B running performance plot, and device of the present invention is promptly with the opening stable discharging of this first switch M1.
See also Fig. 6 first embodiment of the invention schematic diagram again, be illustrated as the electrostatic discharge protective circuit between cross-over connection first power vd D and second source VSS.When the normal operation pattern that no static discharge situation takes place; the first switch M1 is a closed condition; and connect the drain electrode end P of second switch M2 this moment; promptly the gate terminal P of the first switch M1 is electronegative potential (low); and cross-over connection two power supplys (VDD is arranged in addition; VSS) capacitor C and second switch; the transistor (not being shown in this figure) that the first switch M1 also connects control internal circuit 50 channels also is closed condition; expression and un-activation electrostatic discharge (ESD) protection pattern; and this moment; the voltage that internal circuit 50 is connected in second switch M2 gate terminal Q is high potential (high); second switch M2 is opening (on); channel is monitored the static discharge state with second switch M2 at any time thus, and the opening of this second switch M2 can also avoid the first power vd D that the first switch M1 is produced noise (noise) and influences its keying state and electrostatic discharge (ESD) protection usefulness.
If in the first power vd D to generation Electrostatic Discharge phenomenon between second source VSS, the capacitor C of this device promptly produces coupling effect, the gate terminal P that makes the first switch M1 is a high potential, allow the first switch M1 be opening, the drain electrode end P that is second switch M2 is a high potential, because internal circuit 50 detects static discharge simultaneously, making the gate terminal Q of the second switch M2 of connection is electronegative potential, and is closed condition.This moment, electrostatic discharge protective equipment of the present invention promptly provided one first power vd D discharge path to second source VSS, with the second source VSS that electrostatic current is directed to ground connection, finished the purpose of electrostatic discharge (ESD) protection.Because the grid of second switch M2 connects internal circuit 50, and make second switch M2 control the leakage current situation of static discharge at any time, so can control the current potential of the first switch M1 gate terminal P thus, and then control opening time of the first switch M1, up to the current value that is discharged to a certain setting, make and in a limited area, need not use the silicide spacing block and can increase electrostatic discharge capacity, pass through internal circuit 50 to prevent super-high-current.
Fig. 7 is the electrostatic discharge protective equipment second embodiment schematic diagram of the present invention.Present embodiment comprises the first switch M1 as the static discharge switch, its gate terminal connects the grid of one the 3rd switch M3 in the internal circuit, under the normal operation pattern that no static discharge takes place, its gate terminal P is an electronegative potential, and the first switch M1 and the 3rd switch M3 are closed condition; If the static discharge situation takes place; because of the capacitor C coupling effect; the gate terminal P that causes the first switch M1 is a high potential; the first switch M1 is opened; electrostatic current promptly thus discharge path be directed to earth terminal; this moment internal circuit the 3rd switch M3 also to answer gate terminal P be that high potential is opened; the gate terminal Q that makes second switch M2 is an electronegative potential; at this moment; second switch M2 is a closed condition, finishes the 3rd switch M3 drain electrode end Q when electrostatic current more drives to banish; just the gate terminal Q of second switch M2 becomes high potential; second switch M2 is opened, make its drain electrode end P, just the gate terminal P of the first switch M1 is an electronegative potential; the first switch M1 is closed, and finish the purpose of this electrostatic discharge (ESD) protection internal circuit.
Fig. 8 is electrostatic discharge protective equipment the 3rd an embodiment schematic diagram of the present invention.May be implemented in various circuit form by above-mentioned ESD protection circuit; as can be with (the VDD between two power supplys of a plurality of ESD protection circuits in the circuit; VSS) combination in parallel; as in the icon with a plurality of transistor M; M '; M " parallel with one another on the switch that forms; by static discharge state in internal circuit 80 and testing circuit 82 supervisory circuits; open each transistor switch more one by one; set up a plurality of discharge paths; and control the transistorized opening time, can increase whole electrostatic discharge (ESD) protection ability.
Other has embodiment electrostatic discharge protective equipment of the present invention can be applied to the protective device of power supply; also can be applicable in the output/input system (I/O system); each input is done the protection of static discharge; enter as unexpected big electric current, the area that all can reach thus with limited assembly reaches dynamical electrostatic discharge (ESD) protection ability.
In sum; the present invention improves known technology to use the silicide spacing block to increase the defective of electro-static discharge protective ability; by using metal-oxide semiconductor assembly (MOS); the device of (Salicide) under bolt-lock testing circuit (latch-detected turned-on circuit) and the self-aligned silication technique for metal; make under the situation of not using the silicide spacing block; use the technology of self-aligned metal silication program to keep the electrostatic discharge protective equipment that internal circuit remains on certain running electric current, it is little to reach layout area; protective capacities is big; reduce ghost effect and the purpose of improving the high frequency running.
The above; only be the detailed description and the accompanying drawing of preferred specific embodiment of the present invention; all embodiment by the variation similar of the present invention's spirit with it; all should be contained in the category of the present invention; anyly be familiar with this operator in the field of the invention, can think easily and variation or modify and all should be encompassed among protection scope of the present invention.
Claims (19)
1. an electrostatic discharge protective equipment is used between a plurality of power supplys, and wherein this device comprises:
One first switch is a metal oxide semiconductor transistor; And
One testing circuit electrically connects this first switch and an internal circuit;
When static discharge took place, this electrostatic discharge protective equipment discharged under the stabling current when the opening of this first switch, was not under the collapse characteristic of assembly and discharge.
2. electrostatic discharge protective equipment as claimed in claim 1 is characterized in that this first switch is the N type metal-oxide semiconductor that a self-aligned metal silication preparation technology makes.
3. electrostatic discharge protective equipment as claimed in claim 1 is characterized in that this electrostatic discharge protective equipment cross-over connection is between these a plurality of power supplys.
4. electrostatic discharge protective equipment as claimed in claim 1 is characterized in that this testing circuit connects the gate terminal of this first switch.
5. electrostatic discharge protective equipment as claimed in claim 1 is characterized in that this first switch electrically connects this internal circuit.
6. electrostatic discharge protective equipment as claimed in claim 1, it is characterized in that can a plurality of first switches in parallel on this first switch.
7. an electrostatic discharge protective equipment is used between a plurality of power supplys, and wherein this device comprises:
One testing circuit comprises an electric capacity, a second switch, and is electrically connected to an internal circuit; And
One first switch is the N type metal oxide semiconductor transistor made from a self-aligned metal silication preparation technology, and the gate terminal of this first switch connects this testing circuit;
When static discharge took place, stabling current discharge down when this electrostatic discharge protective equipment operates on the opening of this first switch non-ly operated on assembly collapse characteristic and discharges.
8. electrostatic discharge protective equipment as claimed in claim 7 is characterized in that this electrostatic discharge protective equipment cross-over connection is between these a plurality of power supplys.
9. electrostatic discharge protective equipment as claimed in claim 7 is characterized in that the drain electrode end of this second switch of this testing circuit connects the gate terminal of this first switch.
10. electrostatic discharge protective equipment as claimed in claim 7 is characterized in that this electric capacity is connected between the drain electrode end of the gate terminal of this power supply and this first switch, second switch.
11. electrostatic discharge protective equipment as claimed in claim 7 is characterized in that this first switch electrically connects this internal circuit.
12. electrostatic discharge protective equipment as claimed in claim 7 is characterized in that a plurality of first switches in parallel on this first switch.
13. an electrostatic discharge protective equipment is used between a plurality of power supplys, wherein this device comprises:
One first switch is a metal oxide semiconductor transistor;
One second switch, the drain electrode end of this second switch connects the gate terminal of this first switch;
One electric capacity connects the gate terminal of this first switch and the drain electrode end of this second switch; And
One internal circuit electrically connects this first switch and this second switch;
When static discharge takes place, stabling current discharge down when this electrostatic discharge protective equipment operates on the opening of this first switch, non-operating under the assembly collapse characteristic discharged, and the gate terminal current potential of this second switch determines the keying state of this first switch.
14. electrostatic discharge protective equipment as claimed in claim 13 is characterized in that this first switch is a N type metal oxide semiconductor transistor made from the self-aligned silication technique for metal.
15. electrostatic discharge protective equipment as claimed in claim 13 is characterized in that this electrostatic discharge protective equipment cross-over connection is between these a plurality of power supplys.
16. electrostatic discharge protective equipment as claimed in claim 13 is characterized in that a plurality of first switches in parallel on this first switch.
17. an electrostatic discharge protective equipment is used between a plurality of power supplys, when static discharge took place, this electrostatic discharge protective equipment is stabling current discharge down when the opening of this first switch, discharged under the non-collapse characteristic that operates on assembly, and this device comprises:
One first switch is the N type metal oxide semiconductor transistor made from a self-aligned metal silication preparation technology;
One second switch, the drain electrode end of this second switch connects the gate terminal of this first switch, to control the keying state of this first switch;
One electric capacity connects the gate terminal of this first switch and the drain electrode end of this second switch; And
One internal circuit electrically connects this first switch and this second switch.
18. electrostatic discharge protective equipment as claimed in claim 17 is characterized in that this electrostatic discharge protective equipment cross-over connection is between these a plurality of power supplys.
19. electrostatic discharge protective equipment as claimed in claim 17 is characterized in that a plurality of first switches in parallel on this first switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200410042024XA CN100490144C (en) | 2004-04-29 | 2004-04-29 | Electrostatic discharge protecting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200410042024XA CN100490144C (en) | 2004-04-29 | 2004-04-29 | Electrostatic discharge protecting device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1691324A true CN1691324A (en) | 2005-11-02 |
| CN100490144C CN100490144C (en) | 2009-05-20 |
Family
ID=35346613
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200410042024XA Expired - Lifetime CN100490144C (en) | 2004-04-29 | 2004-04-29 | Electrostatic discharge protecting device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100490144C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101145792B (en) * | 2006-09-11 | 2010-12-08 | 联发科技股份有限公司 | Electronic device with correction function and method for correcting electronic device |
| CN108847176A (en) * | 2018-07-13 | 2018-11-20 | 京东方科技集团股份有限公司 | A kind of array substrate, display panel and display device |
-
2004
- 2004-04-29 CN CNB200410042024XA patent/CN100490144C/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101145792B (en) * | 2006-09-11 | 2010-12-08 | 联发科技股份有限公司 | Electronic device with correction function and method for correcting electronic device |
| CN108847176A (en) * | 2018-07-13 | 2018-11-20 | 京东方科技集团股份有限公司 | A kind of array substrate, display panel and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100490144C (en) | 2009-05-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8044466B2 (en) | ESD protection device in high voltage and manufacturing method for the same | |
| US6498357B2 (en) | Lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process | |
| US8455315B2 (en) | Symmetric blocking transient voltage suppressor (TVS) using bipolar transistor base snatch | |
| CN100342535C (en) | Turn-on-efficient bipolar structures with deep N-well for on-chip ESD protection | |
| CN102214655B (en) | Integrated circuit and method for reduced trigger voltage ofstacked ESD protection circuit | |
| US20080224220A1 (en) | Electrostatic Discharge Protection Device | |
| CN1360347A (en) | Electrostatic discharge protecting circuit | |
| CN1402358A (en) | Electrostatic discharge protection element structure with high base trigger effect, and use circuit thereof | |
| CN1808716A (en) | Electrostatic discharge protective unit with low voltage triggered bipolar transistor | |
| US20070241407A1 (en) | Electrostatic discharge protection device and method of fabricating the same | |
| US20110133247A1 (en) | Zener-Triggered SCR-Based Electrostatic Discharge Protection Devices For CDM And HBM Stress Conditions | |
| US7532446B2 (en) | Protection circuit for electro static discharge | |
| KR100971431B1 (en) | Electro-static Discharge Protection Device | |
| CN109712971B (en) | Semiconductor electrostatic discharge protection element | |
| CN2743976Y (en) | Electrostatic discharging protection circuit | |
| CN1283003C (en) | Electrostatic discharge protection circuit | |
| CN100338770C (en) | Electrostatic discharge protecting circuit | |
| CN1691324A (en) | Electrostatic discharge protecting device | |
| EP2130276B1 (en) | Structure and circuit technique for uniform triggering of multifinger semiconductor devices with tunable trigger voltage | |
| CN1157789C (en) | Static discharge buffer device | |
| CN101271891B (en) | Electrostatic discharge protecting equipment and manufacturing method thereof | |
| CN220895509U (en) | Special transistor structure and electrostatic protection circuit for display driving output channel | |
| CN102148246B (en) | Electrostatic discharge (ESD) protection circuit | |
| CN1719607A (en) | Electrostatic discharge protector | |
| Ker et al. | ESD protection circuits with novel MOS-bounded diode structures |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20090520 |
|
| CX01 | Expiry of patent term |