CN1690899B

CN1690899B - Controller

Info

Publication number: CN1690899B
Application number: CN200510065958XA
Authority: CN
Inventors: 芦田和英
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 2004-04-19
Filing date: 2005-04-19
Publication date: 2012-07-18
Anticipated expiration: 2025-04-19
Also published as: JP2005332370A; CN1690899A

Abstract

The control unit comprises a plurality of control program memory 191 to 19n for storing the control program continuously addressed to the instructions continuously executed in such a dispersive manner that the instructions to be executed continuously can be read out in parallel, a program memory control means 31 for preemptively reading the instructions following the instructions under execution by outputting addresses in a control program order to a plurality of control program memory 191 to 19n and a computation means 30 for executing the instructions read out by the program memory control means 31.

Description

Control device

Technical field

The present invention relates to be controlled at the control device on the set-point to the process values of controlling object.

Background technology

Control device for example be used to comprise the assembling work of paper mill and automobile industry the FA field, comprise the chemical plant the PA field, comprise the various industrial systems such as public system of water-wastewater system.

Figure 17 is the block diagram of existing control device one example of expression.

Input/output module 1 is exported the data from control device 2 inputs to controlling object 3.Input/output module 1 is exported the control data 1a from controlling object 3 inputs to control device 2 in addition.

Control program executive circuit 4 as control device 2 for example uses microprocessor, CPU etc.

Control program executive circuit 4 is read the processing command of putting down in writing the control program 5a successively from control program storer 5, reads control data 1a via input/output module 1 and I/O interface 6, reads the control data 7a that is stored in the control data storer 7.

Control program executive circuit 4 is carried out the processing for control data 1a and control data 7a according to the processing command of control program 5a.

Then, control program executive circuit 4 outputs to input/output module 1 to the data of expression result via I/O interface 6 according to control program 5a, perhaps in the data write control data storer 7 of expression result.

In view of the above, carry out the control and treatment of control device 2.Control device 2 is imported various commands from monitor 8 via communication interface 9.

In addition, in control device 2,, can also possess program executing circuit 10, program storage 11, data-carrier store 12 except control program executive circuit 4, control program storer 5, I/O interface 6, control data storer 7.Between the each several part in control device 2 via bus 13 input/output routines and data.

Example as control device 2 has programming controller etc.

In recent years; Proposed to come the technology multiplexed or in certain device, a plurality of control device are installed to make it share processing etc. control device through a plurality of control device are installed in certain device; So that the technology of control and treatment high speed (for example, the flat 11-196457 communique of special hope).

In existing control device 2; Even control program executive circuit 4 high speeds; Read the action of control program 5a and control data 7a from control program storer 5 and control data storer 7 and also want spended time, this reading speed becomes restriction, and the high speed of control and treatment is difficult.

In addition, when the frequency of the oscillator that has when a plurality of control device is incomplete same, in multiplexed a plurality of control device, make the parallel execution of same control program, be difficult between a plurality of control device, obtain synchronously.In addition, also be difficult to make the timing of control beginning consistent.

Summary of the invention

According to the present invention, a kind of control device is provided, it is characterized in that comprising: a plurality of control program storeies; Program storage comprises: the Controlling Source program exists branch and interflow, to the prime of the processing command that after branch location, disposed, disposed the judgement that the gives order that authority is judged and carried out to the execution authority of carrying out this processing command in processing; And program compiler; Arrange from said branch location with continuous state and to begin the judgement order and the processing command that are disposed the side's circuit till the position, said interflow; Thereafter; Arrange from said branch location with continuous state and to begin the judgement order and the processing command that are disposed the opposing party's circuit till the position, said interflow; With said Controlling Source program transformation for to have given the control program of continuous address for the order of continuous execution; This order of carrying out is continuously disperseed to be stored in said a plurality of control program storer,, carry out the program executing circuit of said program compiler so that can it be read according to execution sequence and according to different memory unit concurrently; And the control program executive circuit, comprising: the control program memorizer control circuit, to the said continuous address of output, said a plurality of control program memory order ground, read the order order afterwards of carrying out object in advance; And arithmetic unit, carry out the order of reading by said program storage control assembly.

In the control device of the embodiment of the invention, a plurality of control program storeies are stored the control program that the processing command of continuous execution has been given continuous address dispersedly, and making to walk abreast takes out the processing command of carrying out continuously.The program storage control assembly is pressed control program order OPADD for a plurality of control program storeies, reads the later processing command of processing command of carrying out object in advance.Arithmetic unit is carried out the processing command of being read by the program storage control assembly.

Description of drawings

Following brief description accompanying drawing.

Fig. 1 is the block diagram of control device one example of expression example 1 of the present invention.

Fig. 2 is the block diagram of an example of expression control program executive circuit structure.

Fig. 3 is the figure of expression based on compiling result one example of the Controlling Source program of program compiler.

Fig. 4 is the figure of example of the command execution state of expression example 1.

Fig. 5 is the figure of the example of the existing command execution state of expression.

Fig. 6 be the expression control data allocation result first the example figure.

Fig. 7 is the figure of expression based on allocation result second example of the control data of program compiler.

Fig. 8 is the figure of expression for the example of the Access status of the control data of example 1.

Fig. 9 is the timing chart of action timing one example of expression control program storer, control data storer, cache memory.

Figure 10 is the block diagram of output action one example of the direct output variable of expression.

Figure 11 is the timing chart of action timing one example of expression control data storer.

Figure 12 is the figure of the control program that uses one example in the control device of expression example 2 of the present invention.

Figure 13 is the block diagram of control device one example of expression example 2.

Figure 14 is the block diagram of detailed structure one example of the communication interface in the control device of expression example 3 of the present invention.

Figure 15 is that expression comprises the figure that transmits process of commands one example.

Figure 16 is the circuit diagram of buffer one example of expression example 4 of the present invention.

Embodiment

Example of the present invention is described with reference to the accompanying drawings.And, in above-mentioned Figure 17 and following each figure, give identical symbol and omit its explanation for identical part.

(example 1)

In this example, explain from the control program storer and read control program at a high speed, and read control data at a high speed from the control data storer, thus the control device of ability high speed executive control program.

Fig. 1 is the block diagram of an example of this example of expression.

Control device 14 has program executing circuit 15, program storage 16, data-carrier store 17.

In addition, control device 14 comprises: control program executive circuit 18; Irrelevant with the action of other storage cell, the control program storer 191～19n of a plurality of units that can visit with different address bus and different commands; Irrelevant with the action of other storage cell, the control data storer 201～20m of a plurality of units that can visit with different address bus and different commands.

Control device 14 possesses a plurality of buffer 211～21ns corresponding with each control program storer 191～19n; The a plurality of buffer 221～22ms corresponding with each control data storer 201～20m.Between the each several part in control device 14, via system bus 26 input/output routines and data.

Controlling Source program 23 and program compiler 24 that program storage 16 storages are recorded and narrated by higher level lanquage.

Program executing circuit 15 access program storeies 16; The variation of using program compiler 24 to carry out to Controlling Source program 23; Record the control program obtained of compiling result among a plurality of control program storer 191～19n, and a plurality of control data storer 201～20m are carried out the distribution of the control data that uses in the control program that the compiling results obtain.

Fig. 2 is the block diagram of structure one example of expression control program executive circuit 18.

In addition, control program executive circuit 18 visits a plurality of control data storer 201～20m via buffer 211～22m respectively.

Control program executive circuit 18 possesses I/O interface 27, communication interface 28, system bus interface 29, computing circuit 30, control program memorizer control circuit 31, buffer 32, cache memory control circuit 33, cache memory 34, control data memorizer control circuit 35, buffer 36.

I/O interface 27 is same with I/O interface 6 and the communication interface 9 of said Figure 17 with communication interface 28, but is built in the control program executive circuit 18, so can the high speed inputoutput data.

System bus interface 29, is exported to computing circuit 30 from other partial data in the control device 14 via system bus 26 inputs.In addition, system bus interface 29 inputs are from the data of computing circuit 30, via system bus 26 other part outputs in control device 14.

Computing circuit 30 uses control data memorizer control circuit 31 to read the program code that is stored among each control program storer 191～19n via buffer 211～21n, buffer 32 respectively.

In addition, computing circuit 30 is read control data when being judged as the control data of reading object by cache memory control circuit 33 when being stored in the cache memory 34 from cache memory 34.

In addition; Computing circuit 30 uses control data memorizer control circuit 35 to read the control data that is stored among each control data storer 201～20m via buffer 221～22m, buffer 36 respectively when being judged as the control data of reading object by cache memory control circuit 33 when not being stored in the cache memory 34.

In addition, computing circuit 30 uses control data memorizer control circuit 35 to write control data among each control data storer 201～20m via buffer 221～22m, buffer 36.

Then, computing circuit 30 is carried out and is handled according to program code of reading and control data.

In this example, the parallel control program storer 191～19n that is provided with distributes continuous address by 24 pairs of continuous program codes of program compiler, and continuous program code is recorded in respectively in the Different control data-carrier store.

Therefore, computing circuit 30 can be read program code at a high speed, according to the order high-speed execution code of address.

In addition; In this example, store the control data that uses in certain program component unit (is said Program Organization Unit (POU) among the IEC 61131-3 at this said program component unit) in the zone of any given range among control data storer 201～20m into through program compiler 24.And the control data in should the zone stores in the cache memory 34 together.

Therefore, computing circuit 30 can be read control data from cache memory 34 with high probability, can improve the hit rate of cache memory 34, can read control data at a high speed.

In addition, in this example, parallel be provided with control data storer 201～20m, through program compiler 24, can with to other control datas read or write state is irrespectively read or write control data.

Therefore, computing circuit 30 can with certain control data read or write state is irrespectively carried out reading or writing of other control datas, can make the visit high speed of paired domination number certificate.

Explanation is based on the action of reading of the control program of the control device 14 of this example and control data below.

In this example, a plurality of control program storer 191～19n are connected on the control program executive circuit 18 through buffer 211～21n.Buffer 211～21n is of the back; Obtain from the address of control program memorizer control circuit 31 outputs; Order according to from 31 outputs of control program memorizer control circuit reads into the control program storer; The ability output command can irrespectively be visited control program storer arbitrarily with the action of other control program storer.

Control program memorizer control circuit 31 starts each control program storer 191～19n successively.

Fig. 3 is the figure of expression based on compiling result one example of the Controlling Source program 23 of program compiler 24.It should be noted that, in Fig. 3, the situation when illustration Controlling Source program 23 is SFC (SequentialFunction Chart) program.

It should be noted that in Fig. 3, possessing 4 control program storer 191～194 o'clock (during 4 storehouse memorizers) with control device 14 is that example describes.

Program compiler 24 generates the control program 25 that the continuous processing command of carrying out (program code) can be read continuously to 23 compilings of Controlling Source program.

Then, program compiler 24 stores control program 25 in a plurality of control program storeies 191～194 into, thereby can read the program code that can carry out continuously continuously with different memory unit.

In this example, when recording certain program code of control program 25 in the control program storer 191, in order to shorten the access time, record the program code of then carrying out among any of other control program storeies 192～194.

It should be noted that; Program compiler 24 partly is compiled as row to component or executed in parallel when Controlling Source program 23 existence condition branches, control; Make and be branched off into the part of not carrying out and can't help computing circuit 30 and carry out; Thereby do not make branch operation not, reading the address and can not becoming discontinuously of the control program of component stored control program 25 in a plurality of control program storeies 191～194 into.

Be that program compiler 24 compiles, thereby, realize the processing of recording and narrating by Controlling Source program 23 only by sequence of addresses executive routine code.

Controlling Source program 23 possesses order Sa1～Sa4.In the control program that possesses order Sa1～Sa4 23, after the execution of order Sa1, handle branch, fill order Sa2 or order Sa3.After any side's in order Sa2 and order Sa3 the execution, handle the interflow, fill order Sa4.

Controlling Source program 23 comprises: be configured in the prime of respectively ordering Sa2～Sa4; The judgement order Ta1～Ta4 of " the execution authority of the order Sa2～Sa4 of level has or not after judging; have right of execution in limited time when being judged as, and makes the order Sa2～Sa4 of back level become the state with execution authority ".Promptly judge the order Sa2～Sa4 of order Ta1～Ta4, carry out the judgement of authority and carry out giving of authority about the back level.Judge that ordering Ta1～Ta4 to have sometimes judges whether that relaying is judged the function of the execution result that the prime order of order Ta1～Ta4 obtains by each between the prime order of judging order Ta1～Ta4 and back grade order.

When having branch between the order Sa2 of in front order Sa1 and back, the Sa3, configuration determination order Ta1, Ta2 between the order Sa2 after branching portion and the branch, Sa3.

When having the interflow between in front order Sa2, Sa3 and the order Sa4 at the back, configuration determination order Ta3, Ta4 between the order Sa2 before the interflow, Sa3 and the interflow portion.

Controlling Source program 23 is transformed to the control program 25 of the order of order Sa1 → judgement order Ta1 → order Sa2 → judgement order Ta3 → judgement order Ta2 → order Sa3 → judgement order Ta4 → order Sa4 by program compiler 24.

In this control program 25; When in handling, having branch with the interflow; Judgement order that from the side's that is branched off into the interflow circuit, comprises and order are continuously; Under judgement order that from the opposing party's of being branched off into the interflow circuit, comprises and order continuum of states, arrange each and judge order and order then.

In control program 25, order Sa1～Sa4 is transformed to order " STEP " respectively by program compiler 24.If more specifically explanation then orders Sa1 to be transformed to order (instruction word: operand) " STEP:Sa1 ".Order Sa2 is transformed to order " STEP:Sa2 ".Order Sa3 is transformed to order " STEP:Sa3 ".Order Sa4 is transformed to order " STEP:Sa4 ".

In addition; In control program 25, judge that order Ta1～Ta4 is transformed to judgement respectively by program compiler 24 and whether the order " CONDITION " of carrying out authority is arranged, in the order of back grade, exist right of execution to carry out the order of authority " TRANSITION " in limited time in the order of back level.If more specifically explanation judges that then order Ta1 is transformed to order (instruction word: operand) " CONDITION:Ta1 " and " TRANSITION:Sa1, Sa2 ".Judge that order Ta3 is transformed to order " CONDITION:Ta3 " and order " TRANSITION:Sa2, Sa4 ".Judge that order Ta2 is transformed to order " CONDITION:Ta2 " and order " TRANSITION:Sa1, Sa3 ".Judge that order Ta4 is transformed to order " CONDITION:Ta4 " and order " TRANSITION:Sa3, Sa4 ".

To order (instruction word: operand) give address " 1 "～" 12 " according to execution sequence.

In this example, the order of order adjacency is stored in the Different control program storage 191～194 in order to read in advance.Through like this demanded storage of order adjacency in Different control program storage 191～194, can walk abreast and carry out the reading of order of order adjacency, can prevent the generation of the confusion of pipeline control.

At this, specify the executing state of the control program 25 of this example.

Fig. 4 is the figure of example of executing state of the order of this example of expression.It should be noted that in Fig. 4, having 4 control program storer 191～194 o'clock (during 4 storehouse memorizers) with control device 14 is that example describes.

In this example, read stage, operand by order by order Ta1～Ta4 to read 4 stages such as stage, command execution stage, write phase be that example describes when constituting with judging with each order Sa2～Sa4, but this stage can be more than 2.In addition, in this example,, be that example describes when carrying out the order Sa3 after the branch, but opposite not carry out the order Sa2 after the branch, carry out the order Sa2 after the branch, when not carrying out the order Sa3 after the branch, also be same.

In this example; Control program executive circuit 18 is according to pipeline control, orders Ta3 → judgement to order Ta2 → order Sa3 → judgement to order that Ta4 → order Sa4's call over control program 25 from control program storer 191～194 according to order Sa1 → judgements order Ta1 → order Sa2 → judgements.

If with the order unit's explanation after the compiling; Then control program executive circuit 18 is according to pipeline control, calls over control program 25 from control program storer 191～194 according to " STEP " of the order Sa4 of " TRANSITION " → address number " 12 " of the order Ta4 of " CONDITION " → address number " 11 " of the order Ta4 of " STEP " → address number " 10 " of the order Sa3 of " TRANSITION " → address number " 9 " of the order Ta2 of " CONDITION " → address number " 8 " of the order Ta2 of " TRANSITION " → address number " 7 " of the order Ta3 of " CONDITION " → address number " 6 " of the order Ta3 of " STEP " → address number " 5 " of the order Sa2 of " TRANSITION " → address number " 4 " of the order Ta1 of " CONDITION " → address number " 3 " of the order Ta1 of " STEP " → address number " 2 " of the order Sa1 of address number " 1 ".

Explanation is for the pipeline control of control program 25 below.

At first, carry out for the order of " STEP:Sa1 " of address number " 1 " read the stage, operand is read stage, command execution stage, write phase.

After reading the execution in stage for the order of " STEP:Sa1 " of address number " 1 ", carry out for the order of " CONDITION:Ta1 " of address number " 2 " read the stage, operand is read stage, command execution stage, write phase.

For the command execution of " CONDITION:Ta1 " of address number " 2 " in the stage,, judge " whether order Sa2 has the execution authority " according to the execution result of obtaining in the stage in command execution for " STEP:Sa1 " of address number " 1 ".In the present example, in the command execution stage for " CONDITION:Ta1 " of address number " 2 ", be judged as " order Sa2 does not carry out authority ".

After reading the execution in stage for the order of " CONDITION:Ta1 " of address number " 2 ", carry out for the order of " TRANSITION:Sa1, the Sa2 " of address number " 3 " read the stage, operand is read the stage.But just now for the command execution of " CONDITION:Ta1 " of address number " 2 " in the stage; Be judged as " order Sa2 does not carry out authority ", so do not carry out command execution stage and write phase for " TRANSITION:Sa1, the Sa2 " of address number " 3 "." STEP:Sa2 " of result address numbering " 4 " becomes the state with execution authority.

After execution for command execution stage of " TRANSITION:Sa1, the Sa2 " of address number " 3 ", carry out for the order of " STEP:Sa2 " of address number " 4 " read the stage, operand is read the stage.But " STEP:Sa2 " of address number " 4 " do not have the shape of carrying out authority, so do not carry out command execution stage and the write phase for " STEP:Sa2 " of address number " 4 ".

After reading the stage for the order of " STEP:Sa2 " of address number " 4 ", carry out for the order of " CONDITION:Ta3 " of address number " 5 " read the stage, operand is read stage, command execution stage, write phase.For the command execution of " CONDITION:Ta3 " of address number " 5 " in the stage; Do not carry out the command execution stage, so be judged as command execution stage, the write phase of not carrying out for " TRANSITION:Sa2, the Sa4 " of the address number of following " 6 " for " STEP:Sa2 " of address number " 4 ".

After reading the execution in stage for the order of " CONDITION:Ta3 " of address number " 5 ", carry out for the order of " TRANSITION:Sa2, the Sa4 " of address number " 6 " read the stage, operand is read the stage.But,, do not carry out command execution stage, write phase for " TRANSITION:Sa2, the Sa4 " of address number " 6 " according to the judgement in " CONDITION:Ta3 " of just now address number " 5 ".

After reading the execution in stage for the order of " TRANSITION:Sa2, the Sa4 " of address number " 6 ", carry out for the order of " CONDITION:Ta2 " of address number " 7 " read the stage, operand is read stage, command execution stage, write phase.

For the command execution of " CONDITION:Ta2 " of address number " 7 " in the stage,, judge " whether order Sa3 has the execution authority " according to the execution result of obtaining in the stage in command execution for " STEP:Sa1 " of address number " 1 ".In the present example, in the command execution stage for " CONDITION:Ta2 " of address number " 7 ", be judged as " order Sa3 has the execution authority ".

After reading the execution in stage for the order of " CONDITION:Ta2 " of address number " 7 ", carry out for the order of " TRANSITION:Sa1, the Sa3 " of address number " 8 " read the stage, operand is read the stage.At this; Just now for the command execution of " CONDITION:Ta2 " of address number " 7 " in the stage; Be judged as " order Sa3 has the execution authority "; So pass through the command execution stage for " TRANSITION:Sa1, the Sa3 " of address number " 8 ", order Sa3 becomes the state with execution authority.

After reading the execution in stage for the order of " TRANSITION:Sa1, the Sa3 " of address number " 8 "; Execution for the order of " STEP:Sa3 " of address number " 9 " read the stage, operand is read the stage; Because order Sa3 has the state of carrying out authority, so carry out command execution stage, the write phase for " STEP:Sa3 " of address number " 9 ".It should be noted that the result who uses the command execution for " STEP:Sa1 " of address number " 1 " to obtain in the stage for the command execution stage of " STEP:Sa3 " of address number " 9 " handles.

After reading the execution in stage for the order of " STEP:Sa3 " of address number " 9 ", carry out for the order of " CONDITION:Ta4 " of address number " 10 " read the stage, operand is read stage, command execution stage, write phase.

For the command execution of " CONDITION:Ta4 " of address number " 10 " in the stage, the execution result according to obtaining in the stage in the command execution for " STEP:Sa3 " of address number " 9 " judges whether " order Sa4 has the execution authority ".In this example, in the stage, be judged as " order Sa4 has the execution authority " for the command execution of " CONDITION:Ta4 " of address number " 10 ".

After reading the execution in stage for the order of " CONDITION:Ta4 " of address number " 10 "; Execution for the order of " TRANSITION:Sa3, the Sa4 " of the address number of following " 11 " read the stage, operand is read stage, command execution stage, write phase; Because just now for the command execution of " CONDITION:Ta4 " of address number " 10 " in the stage; Be judged as " order Sa4 has the execution authority "; So through the command execution stage for " TRANSITION:Sa3, the Sa4 " of the address number of following " 11 ", order Sa4 becomes and has the state of carrying out authority.

After reading the execution in stage for the order of " TRANSITION:Sa3, the Sa4 " of address number " 11 "; Execution for the order of " STEP:Sa4 " of address number " 12 " read the stage, operand is read the stage; Because Sa4 has the state of carrying out authority, so carry out command execution stage, the write phase for " STEP:Sa4 " of address number " 12 ".It should be noted that, use the result who obtains in the stage in command execution to handle for the command execution stage of " STEP:Sa4 " of address number " 12 " for " STEP:Sa3 " of address number " 9 ".

Through handling by Fig. 4 that kind, pipeline control continues in this example, based on order Sa1～Sa4 with judge between each order of order Ta1～Ta4, repeats the processing stage of making on one side, carries out processing on one side, can carry out efficiently and processing rapidly.

And Fig. 5 is illustrated in the executing state of the existing control program when having branch in the processing.

When in handling, having branch in the past, transfer instruction word " JON " and unconditional branch instruction word " JUMP " when the condition that in control program, comprises is set up.When existence condition is set up, in the part of transfer instruction word " JON " and unconditional branch instruction word " JUMP ", be difficult to read the next instruction word in advance, carry out, confusion reigned in pipeline control, pipeline control continue the difficulty that becomes.Branch is increase more, and transfer instruction word " JON " and unconditional branch instruction word " JUMP " increased more when condition was set up, and efficiently and rapidly handling of control program becomes difficult.

Fig. 6 be the expression control data allocation result first the example figure.It should be noted that; In Fig. 6; Illustration Controlling Source program is recorded and narrated by LD (Ladder Diagram) language, the situation when being recorded in the control data storer 51 about the control data of control data variables A 1～A6 of using in the Controlling Source program, B7, A8～A10, B11.

The control data that uses among certain program component unit MS01 in the region allocation control program of any given range in 24 pairs of control program storeies 51 of program compiler.

Control data about control data variables A 1～A6, A8～A10 is the input data.Control data about B7, B11 is an output data.

Program compiler 24 is carried out the distribution of control data, thereby the memory block that the control data that uses among the program component unit MS01 is distributed is become below the memory capacity of cache memory 34.And, in the execution of program component unit MS01, store the control data that uses among the program component unit MS01 in the cache memory 34 into.

Through adopting the storage mode of Fig. 6, in the execution of program component unit MS01, can improve the hit rate of control data for cache memory 34, the result can make the execution speed high speed of program component unit MS01.

Fig. 7 is the figure of expression based on second example of the control data allocation result of program compiler 24.It should be noted that in Fig. 7, Controlling Source program 52 is recorded and narrated by the LD language, illustration is recorded in the situation in the control data storer 201,202 about the control data of control data variables A 1～A6 of using in the Controlling Source program 52, B7, A8～A10, B11.Promptly in Fig. 7, having 2 control data storeies with control device 14 201,202 o'clock was that example illustrates.

The appearance of the control data variable when carrying out Controlling Source program 52 is A1～A6, B7, A8～A10, B11 in proper order.Control data variables A 1～A6, B7, A8～A10, B11 give Different control data-carrier store 201,202 according to order assignment occurring.As shown in Figure 7, through alternately storing the control data of appearance order adjacency into respectively in the control data storer 201,202, can efficiently carry out reading or writing from the control data of control data storer 201,202.In addition; When the content of the control data storer that uses a side; Through in advance the content stores of the opposing party's control data storer in cache memory 34; Can store the control data that then will use in the cache memory 34 in advance, can improve the hit rate of cache memory.

Program compiler 24 is stored in control data among a plurality of control data storer 201～20m, thus can with other control data read or the control data of continuous use is irrespectively independently read or write to write state.

In this example; When first control data is recorded in the control data storer 201; Second control data that then uses be in order independently to read or to write outside first control data, is recorded among any of other control program storeies 202～20m.

It should be noted that, can make up the storage mode of control data of storage mode and said Fig. 7 of the control data of said Fig. 6.The control data variables A 1～A6, B7, A8～A10, the B11 that for example use among the program component unit MS01 about said Fig. 6, the control data variable storage of use order adjacency in Different control data-carrier store 201,202.I.e. storage control data variables A 1, A3, A5, B7, A9, B11 in control data storer 201, storage control data variables A 2, A4, A6, A8, A10 in control data storer 202.And, storage control data variables A 1, A3, A5, B7, A9, B11 near the given area control data storer 201, storage control data variables A 2, A4, A6, A8, A10 near the given area control data storer 202.And, the control data variables A 1～A6, B7, A8～A10, the B11 that use among the cache memory 34 ability storage and uniform program component unit MS01.

In view of the above, can improve the hit rate of the executory cache memory of program component unit MS01.In addition, can with from parallel the reading of control data variables A 2, A4, A6, A8, A10 of carrying out of reading of the control data variables A 1 of control data storer 201, A3, A5, B7, A9, B11 from control data storer 202.Can also walk abreast and carry out the reading or writing of control data variables A 2, A4, A6, A8, A10 between the reading or write of control data variables A 1, A3, A5, B7, A9, B11, cache memory 34 and the control data storer 202 between cache memory 34 and the control data storer 201.Therefore, can make the execution speed high speed of program component unit MS01.

Specify the Access status of the control data of this example at this.

Fig. 8 is the figure for the example of the Access status of control data of this example of expression.It should be noted that in Fig. 8, (during 2 storehouse memorizers) are that example is represented to possess 2 control data storeies with control device 14 at 201,202 o'clock.

According to each order of pipeline control executive control program 25, in this example, each order of control program 25 is carried out in order.In control program 25, be stored in the Different control data-carrier store (storehouse memorizer) 201,202 by the control data of the command access of execution sequence adjacency.In view of the above, the first row access of ability is by the control data of the command access of execution sequence adjacency.

As stated, in this example, can prevent the generation of the confusion of pipeline control.In this example, be not stored in the identical control data storer by the control data of the command access of execution sequence adjacency, can maintain high level to the concurrent access of control data.

Fig. 9 is the timing chart of an action example regularly of expression control program storer 191～194, control data storer 201,202, cache memory 34.

In Fig. 9; Control device 14 has 4 control program storeies 191～194; To possess 2 control data storeies 201,202 o'clock was that example illustrates, but when possessing other control program storeies 193～19n and other control data storeies 203～20m, also was same.

Fig. 9 is illustrated in the said control device illustrated in figures 1 and 2 14 in addition, has shown that the reading of control data variables A 8 of the Controlling Source program 52 of carrying out said Fig. 6 program component unit MS01 or Fig. 7 handled timing chart before, omits processing thereafter.

It is effective to be illustrated in when descending the address for the sense command of control program storer 191～194, release when rising.

Control program memorizer control circuit 31 is as shown in Figure 9, to a plurality of control program storeies 191～194 address and sense command is provided in order, can be according to sequence of addresses read routine code (order).In control program storer 191～194, has buffer 211～214, so can distinguish independent execution from the reading of program code of control program storer 191～194.

Even be the control program memorizer control circuit 31 any read routine code from control program storer 191～194, also can read other program codes from other control program storeies.

As stated, but can be compiled as the state of carrying out by sequence of addresses to Controlling Source program 52.Program compiler 24 is of Fig. 3, through carrying out branch or executed in parallel is compiled as the program that simple sequence is carried out, thereby generates control program, and the address of access control program storer 191～194 o'clock can not become discontinuous.

In view of the above, even in Controlling Source program 52, have branch condition, according to sequence of addresses read routine code, computing circuit 30 can be carried out each order that constitutes the processing that comprises conditional branching according to pipeline control by control program memorizer control circuit 31.

But; When because the execution of interrupt routine and the switching of task etc.; Be difficult to make the address consecutive hours of the program code of reading; Control program memorizer control circuit 31 is controlled, thereby to required control program storer OPADD and sense command, makes till the program code outputs by the time such as execution of computing circuit 30.

From reading and write also from independent execution the outside the reading of the program code of control program storer 191,192 of the control data of control data storer 201,202.

In Fig. 9, control data variables A 1, A3, A5, B7, A9, B11 are stored in the given area of control data storer 201.Control data variables A 2, A4, A6, A8, A10 are stored in the given area of control data storer 202.

When any one for control data variables A 1, A3, A5, B7, A9, B11; When the generation cache memory misses, store control data variables A 1, A3, A5, B7, A9, the B11 that (can be stored in the zone in the cache memory 34) in the given area of control data storer 201 into cache memory 34.Then, carry out paired domination number reading or writing for cache memory 34 according to variables A 1, A3, A5, B7, A9, B11.

Equally; When any one for control data variables A 2, A4, A6, A8, A10; When the generation cache memory misses, store control data variables A 2, A4, A6, A8, A10 in the given area of control data storer 202 into cache memory 34.Then, carry out paired domination number reading or writing for cache memory 34 according to variables A 2, A4, A6, A8, A10.

For example, as control data variable B7, write control data in the cache memory 34 from cache memory 34 write control data storeies 201 (write-back).

In the pipe stage of Fig. 9, read or write the control data of object for each order record.

In the pipe stage of Fig. 9, when because cache memory misses, and that can not handle necessary control data variable reads or write fashionable, the execution of order becomes waiting status.

It should be noted that, produce control data sense command and control data write command in same timing.In the control data write command, when cache memory taking place equally miss, wait for reading of control program sometimes with the control data sense command.

The control data of the control device 14 of this example of explanation reads first example with write activity below.

Computing circuit 30 is exported the address of the control data of reading object and sense command to cache memory control circuit 33.

Cache memory control circuit 33 judges whether the control data of reading object is stored in the cache memory 34.

When the control data of reading object was stored in the cache memory 34, cache memory control circuit 33 was read the control data of object and is exported to computing circuit 30 from cache memory 34.

And when the control data of reading object is not stored in the cache memory 34, address from the control data of object to 35 outputs of control data memorizer control circuit and sense command that cache memory control circuit 33 is read.

If the address and the sense command of the control data of object are read in 35 input and output of control data memorizer control circuit; Just read the set of the control data that uses in the program component unit under the control data of reading object; Store in the cache memory 34, and export the control data of reading object to computing circuit 30.

In this example, between computing circuit 30 and control data storer 201～20m, be provided with cache memory 34.34 visits for control data of cache memory are effective.

In order to use cache memory 34 effectively, as stated, when program compiler 24 is distributed control data at paired domination number according to storer 201～20m, distribute to the zone in the given range to the control data that comprises in certain program component unit.In view of the above, in the execution of the program code of certain program component unit, improve from the read-around number of cache memory 34 ratio (hit rate) for whole control data access times, can be to read the control data variable at a high speed.

In addition, in the control data variable, there is the variable that is called direct output variable.Write control data in the direct output variable outside the unified input and output (scanning input and output) of control device 14, constantly output in the input/output module 1 writing.

Figure 10 be the expression direct output variable output action one the example block diagram.

When the control data variable that writes object is direct output variable; Computing circuit 30 is to cache memory 34 these information of output; Not only to cache memory 34 write control datas, the input/output module 1 to reality writes (transcription action) simultaneously.In view of the above, the control data that writes object is directly exported to input/output module 1 via I/O interface 27.

Below, second example with write activity of reading based on the control data of the control device 14 of this example is described.

Control device 14 is in order to control a plurality of control data storer 201～20m, possess buffer 221～22m and the control data memorizer control circuit 35 that is used for control data.

In each control data storer 201～20m, be provided with special-purpose buffer 221～22m.Therefore, control data memorizer control circuit 35 can independently be carried out and read action and write activity according to sense command or write command.

Figure 11 is the timing chart of an action example regularly of expression control data storer 201,202.It should be noted that, when possessing other control data storeies 203～20m, also be same.

As stated, in order to effectively utilize a plurality of control data storeies, consider access order, distribute to control data storer 201,202 about the control data of control data variable.

For example in the said control program of being recorded and narrated by the LD language shown in Figure 6, the access order of control program is by the numeral of the variable name of operand.In this example, the control data of connected reference is distributed to Different control data-carrier store 201,202 according to access order.

Coil order is to be write fashionablely when resembling, and makes the control data storer that uses in next order for ordering other different control data storeies of control data storer of use with coil.About not being other orders that write of coil order, also be same.

In view of the above, for example during according to storer 201 write control datas, can read control data from control data storer 202 at paired domination number.

In this example of above explanation, according to the order of address, read to sequence the program code of continuous execution, carry out.

In addition, use control program storer 191～19n and control program memorizer control circuit 31, can read the program code that then will carry out in advance.

In view of the above, can high speed executive control program 25.Special when control device 14 is Programmable Logic Controller, usually carry out the control program 25 that uses in this control device 14, so the action of the control device 14 of this example is effective by sequence of addresses.

In this example, when control program storer 191～19n ratio calculating circuit 30 desired memory access speed are also slow, also can high speed executive control program 25.

In addition, in this example, the control data storage and uniform that belongs to certain program component unit is in cache memory 34, so can improve the hit rate of cache memory 34, ability high speed access control data can high speed executive control program 25.In addition also can be corresponding to direct output.

In addition; In this example; The control data that uses continuously is stored among Different control data-carrier store 201～20m, so can prevent to carry out reading or writing of control data from identical control data storer the writing and reading of this external enwergy executed in parallel control data.

In view of the above, ability high speed access control data can high speed executive control program 25.

Promptly in this example, can be from storer high-speed reading data or program, in view of the above can the high speed executive control program.

(example 2)

In this example, the variation of the control device of said example 1 is described.

Figure 12 is the figure of an example of the control program that uses in the control device of this example of expression.

Figure 13 is the block diagram of control device one example of this example of expression.It should be noted that, in Figure 13, about with said Fig. 1,2 identical parts, omit.

In this example, in order to improve reliability, make the identical control program 37 of a plurality of control device 381～38k executed in parallel for the control of controlling object 3, comparator results is selected correct result.Beginning configuration synchronization order at each program component unit of control program 37.Control device 381～38k is same structure.

In the control device 381, replace the control program executive circuit 18 and control program 25 of said control device 14, use control program executive circuit 39 and control program 37.Control device 381 possesses AND operational part 40 in order to obtain synchronously with other control systems 382～38k, and in control program executive circuit 39, possesses AND operational part 41.

It should be noted that AND

operational part

40,41 can be unified.

If the computing circuit that possesses in the control program executive circuit 39 42 is carried out synch command, just export synchronous requirement to other control systems 382～38k.In the output that requires synchronously, use communication interface 28.

The synchronous requirement of control device 381 input other control systems 382～38k.AND operational part 40 is imported the synchronous requirement of these control device 381 outputs and each logic product signal that requires synchronously of importing from other control systems 382～38k with AND operational part 41 to computing circuit 42.

Computing circuit 42 is according to the logic product signal, detects whether the finishing synchronously of each control device 381～38k (whether the logic product signal is effective status).

When not the finishing synchronously of each control device 381～38k, computing circuit 42 makes the execution standby of next program code to same EOS.

And when with EOS, computing circuit 42 is carried out next program code.

In this example of above explanation,, easily realize the executed in parallel of control device 381～38k through the synch command that each the program component unit that is configured in control program 37 begins.

(example 3)

In this example, specify the communication interface 28 of said example 1.It should be noted that, about the communication interface 28 of the control device 381～38k of said example 2, also be same.

Figure 14 be the expression communication interface 28 detailed structure one the example block diagram.

Figure 15 is the figure that expression comprises an example of the control program that transmits order in addition.

Communication interface 28 is built in the control program executive circuit 14.

Computing circuit 30 directly the delivery status register 28a that possessed of accessing communication interface 28, transmit data buffer 28b.

Computing circuit 30 was ordered 43 o'clock in the transmission of carrying out through the transmission of the network shown in said 15 data; When the transmission data buffer 28b to communication interface 28 writes specified data, command status register 28a is write kind, the transmission starting indication of transmission.

In addition; Computing circuit 30 is when carrying out the transmission order of passing through network reception data; The outside communication interface of access control program executive circuit 14 not, and the inner communication interface 28 of access control program executive circuit 14 is carried out the affirmation of delivery status, the reception of data.

Through being installed to communication interface 28 control program executive circuit 14 inside, can directly visit its inner buffer 28b, register 28a from computing circuit 30, thereby can high speed processing transmit data, carry out at a high speed and transmit order.

(example 4)

In this example, the control device that in various buffers, has lock function (hold function) is described.

Figure 16 be the expression this example buffer one the example circuit diagram.In Figure 16, represent 1 the lock and the example of structure of buffer.

Buffer 44 can use as data buffer, Address Register, command buffer.

Buffer 44 is applicable to transmission data buffer 28b in buffer 211～21n of explaining in said each example, 221～22m, 32,36, the communication interface 28, the buffer in the I/O interface 27, the buffer equal controller 14 in the system bus interface 29, the various buffers in 381～38k.

It should be noted that, in this example, although clear data buffer and situation about using as latch data, but also be same when using as the command buffer of the Address Register of latch lock address, breech lock order.

Buffer 44 possesses AND circuit 45, shift register 46, the lock data are read with buffer 47, AND circuit 48, OR circuit 49, on-off circuit 50.

When selecting the output of new data, select signal as the input of High signal, when selecting the output of lock data, import as the Low signal.Promptly this selection signal works as the output command of lock data.

AND circuit 45 input new datas and selection signal, when selecting signal to be the High signal, the output new data.

Shift register 46 is saved in the lock data to the new data of input as the lock data and reads with in the buffer 47.

And shift register 46 is when each input latch-up signal, reads to export with buffer 47 from the lock data and respectively locks data.It should be noted that the output order of lock data can be the order of preservation or opposite order.

48 inputs of AND circuit are from the lock data and the paraphase result who selects signal of shift register 46, and the selection signal paraphase of Low signal, when becoming the High signal, data are locked in output.

OR circuit 49 output is from the new data of AND circuit 45 with from any side of the lock data of AND circuit 48.

On-off circuit 50 is from AND circuit 45 input new datas and any side who locks the data.If on-off circuit 50 input buffer enable signals are just exported new data and any side who locks in the data in addition.

In this example, can be the output of new data according to selecting signal to select, still lock the output of data.Buffer 44 is when using as two-way buffer, and the circuit same with said Figure 16 is connected in parallel on reverse direction.

In this example, when generation in the execution of control program 25,37 is wrong arbitrarily, stop visit, select the data of reading breech lock in the buffer 44.

Through possessing function by time series latch data in address and data buffer, can confirm the data of visit when mistake takes place, the reason that the ability profiling error takes place finds out that easily executive control program is the reason of the mistake of generation.

It should be noted that in said each example, if can realize same action, then each inscape can Free Transform, both can change configuration, also can independent assortment, cut apart.

The application is based on No.2004-123330 of Japanese patent application formerly that proposed on April 19th, 2004 and the No.2005-108797 that proposed on April 5th, 2005, and requires its right of priority, through with reference to and its full content is incorporated into this.

Claims

1. control device is characterized in that comprising:

A plurality of control program storeies (191～19n);

Program storage (16); Comprise: Controlling Source program (23); In processing, there are branch and interflow, to the prime of the processing command that after branch location, disposed, disposed the judgement that the gives order that authority is judged and carried out to the execution authority of carrying out this processing command; And program compiler (24); Arrange from said branch location with continuous state and to begin the judgement order and the processing command that are disposed the side's circuit till the position, said interflow; Thereafter; Arrange from said branch location with continuous state and to begin the judgement order and the processing command that are disposed the opposing party's circuit till the position, said interflow, said Controlling Source program transformation for to have given the control program of continuous address for the order of continuous execution, is stored in this order of carrying out continuously dispersion in said a plurality of control program storer; So that can it be read according to execution sequence and according to different memory unit concurrently

Carry out the program executing circuit (15) of said program compiler; And

Control program executive circuit (18) comprising: control program memorizer control circuit (31), to the said continuous address of output, said a plurality of control program memory order ground, read the order order afterwards of carrying out object in advance; And arithmetic unit (30), carry out the order of reading by said program storage control assembly.

2. control device according to claim 1 is characterized in that also comprising:

Buffer (211～21n), be arranged between said a plurality of control program storer and the said control program executive circuit.

3. control device according to claim 1 is characterized in that also comprising:

A plurality of control data storeies (201～20m), a plurality of data of access are carried out in the order of the said continuous execution of memory by using,

Said control program executive circuit will utilize the order of execution sequence adjacency to come the control data of access to be stored in respectively in the Different control data-carrier store.

4. control device according to claim 1 is characterized in that also comprising:

Cache memory (34) is used for storing the control data that the part of said control program is used;

Control data storer (201) is stored in the control data that uses in the part of said control program within the capacity of said cache memory;

Cache memory control assembly (33); When having taken place to utilize said arithmetic unit to read control data; Judge whether the control data of reading object is stored in the said cache memory; When the said control data of reading object is stored in the said cache memory, read the said control data of reading object from said cache memory.

5. control device according to claim 1 is characterized in that;

Said a plurality of control program storer disperses the said control program of storage, makes to be extended under the state of a plurality of word lengths in the program command word length, can parallel read-out or write,

Also comprise:

Data-carrier store control assembly (35) for employed control data in the part of said control program, is carried out and to be read or to write processing for said a plurality of control data storeies.

6. control device according to claim 1 is characterized in that:

Said control program is in commission hoped to obtain in the synchronous part and is included synch command,

Also comprise:

The other control systems of the said control program of detection execution (whether 382～38k) carried out the parts (40) of said synch command,

Said arithmetic unit when in said other control device, carrying out said synch command, advances the processing of said control program, carries out said control program synchronously with said other control systems.